KR102419864B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device includes: a substrate including a first active region, a second active region, and a first field insulating layer in direct contact between the first active region and the second active region; and a first gate electrode structure crossing the first active region, the second active region, and the first field insulating layer on the substrate, wherein the first gate electrode structure is in direct contact with each other. a gate electrode and a first n-type gate electrode, wherein the first p-type gate electrode includes a first work function control layer on the first active region and the first field insulating layer, and a first work function control layer on the first work function control layer a first upper gate electrode, wherein the first n-type gate electrode includes a second work function control layer on the second active region and the first field insulating layer, and a second upper gate electrode on the second work function control layer wherein the first work function regulating film and the second work function regulating film are in direct contact with each other and are the same material film, and the thickness of the first work function regulating film is different from the thickness of the second work function regulating film, and the first The overlapping width of the p-type gate electrode and the first field insulating layer is different from the overlapping width of the first n-type gate electrode and the first field insulating layer.

Description

semiconductor device

The present invention relates to a semiconductor device.

Recently, with the rapid spread of information media, the functions of semiconductor devices are also developing rapidly. In the case of recent semiconductor products, high integration is required for low cost and high quality in order to secure competitiveness. For high integration, semiconductor devices are being scaled down.

Research is being conducted to speed up the operation speed of semiconductor devices and increase the degree of integration. A semiconductor device includes discrete devices such as a MOS transistor. As the semiconductor device is integrated, the gate of the MOS transistor is gradually reduced, and the lower channel region of the gate is also getting narrower.

The critical size of the gate region of a transistor greatly affects the electrical characteristics of the transistor. That is, when the width of the gate region becomes narrow as the semiconductor device is highly integrated, the distance between the source and drain regions formed with the gate region therebetween also becomes narrower.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of improving the threshold voltage of a transistor.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the semiconductor device of the present invention for solving the above problems is a first active region, a second active region, and a first field insulating film in direct contact between the first active region and the second active region. a substrate comprising; and a first gate electrode structure crossing the first active region, the second active region, and the first field insulating layer on the substrate, wherein the first gate electrode structure is in direct contact with each other. a gate electrode and a first n-type gate electrode, wherein the first p-type gate electrode includes a first work function control layer on the first active region and the first field insulating layer, and a first work function control layer on the first work function control layer a first upper gate electrode, wherein the first n-type gate electrode includes a second work function control layer on the second active region and the first field insulating layer, and a second upper gate electrode on the second work function control layer wherein the first work function regulating film and the second work function regulating film are in direct contact with each other and are the same material film, and the thickness of the first work function regulating film is different from the thickness of the second work function regulating film, and the first The overlapping width of the p-type gate electrode and the first field insulating layer is different from the overlapping width of the first n-type gate electrode and the first field insulating layer.

In some embodiments of the present invention, a thickness of the first work function control layer is greater than a thickness of the second work function control layer.

In some embodiments, an overlapping width of the first p-type gate electrode and the first field insulating layer is greater than an overlapping width of the first n-type gate electrode and the first field insulating layer.

In some embodiments of the present invention, the first active region includes a channel region of a p-type transistor, the second active region includes a channel region of an n-type transistor, and the first p-type gate electrode and the second active region 1 The contact surface of the n-type gate electrode is closer to the channel region of the n-type transistor than the channel region of the p-type transistor.

In some embodiments, an overlapping width of the first p-type gate electrode and the first field insulating layer is smaller than an overlapping width of the first n-type gate electrode and the first field insulating layer.

In some embodiments of the present invention, the first active region includes a channel region of a p-type transistor, the second active region includes a channel region of an n-type transistor, and the first p-type gate electrode and the second active region 1 The contact surface of the n-type gate electrode is closer to the channel region of the p-type transistor than the channel region of the n-type transistor.

In some embodiments of the present invention, the first active region and the second active region are included in an SRAM region.

In some embodiments of the present invention, the first active region is a region in which a pull-up transistor of the SRAM is formed, and the second active region is a region in which a pull-down transistor or a pass transistor of the SRAM is formed.

In some embodiments of the present invention, the substrate includes a first region and a second region having different functions, wherein the first active region and the second active region are formed in the first region, and the second region the substrate of the region comprises a third active region, a fourth active region, and a second field insulating film in direct contact between the third active region and the fourth active region, on the substrate, the third active region a second gate electrode structure crossing a region, the fourth active region, and the second field insulating layer, wherein the second gate electrode structure includes a second p-type gate electrode and a second n-type gate electrode in direct contact with each other wherein the second p-type gate electrode is formed on the third active region and the second field insulating layer, and the second n-type gate electrode is formed on the fourth active region and the second field insulating layer. do.

In some embodiments of the present invention, a contact surface of the second p-type gate electrode and the second n-type gate electrode is closer to the fourth active region than the third active region.

In some embodiments, the overlapping width of the second p-type gate electrode and the second field insulating layer is substantially the same as the overlapping width of the second n-type gate electrode and the second field insulating layer.

In some embodiments of the present invention, a contact surface of the second p-type gate electrode and the second n-type gate electrode is closer to the third active region than the fourth active region.

In some embodiments of the present disclosure, the second p-type gate electrode includes a third work function control layer on the third active region and the second field insulating layer, and the second n-type gate electrode includes the fourth active region and a fourth work function regulating film on the second field insulating film, wherein the third work function regulating film and the fourth work function regulating film are in direct contact and are the same material film, and the thickness of the third work function regulating film is the It is thicker than the thickness of the fourth work function control layer.

In some embodiments of the present disclosure, the second p-type gate electrode includes a first etch stop layer on the third active region and the second field insulating layer, and a first etch stop layer on the first etch stop layer in contact with the first etch stop layer a third work function regulating layer, and a first interposed layer on the third work function regulating layer and in contact with the third work function regulating layer, wherein the second n-type gate electrode includes the fourth active region and the second a second etch stop layer on the field insulating layer; and a second insert layer on the second etch stop layer and in contact with the second etch stop layer.

In some embodiments of the present invention, the first etch stop layer and the second etch stop layer are the same material layer and are in direct contact with each other, and the thickness of the first etch stop layer and the thickness of the second etch stop layer are substantially the same, and , The first interposing layer and the second interposing layer are the same material layer, and are in direct contact with each other, and the thickness of the first interposing layer and the thickness of the second interposing layer are substantially the same.

In some embodiments of the present invention, the first region is an SRAM region, and the second region is a logic region.

In some embodiments of the present invention, each of the first work function control layer and the second work function control layer is a TiN layer.

In some embodiments of the present disclosure, a gate insulating layer intersecting the first active region, the second active region, and the first field insulating layer is further included between the substrate and the first gate electrode structure, and the first The gate electrode structure further includes a lower TiN layer extending along the gate insulating layer on the gate insulating layer, and an etch stop layer on the lower TiN layer, wherein the first work function control layer and the second work function control layer are respectively The etch stop layer is in contact with the etch stop layer.

In some embodiments of the present invention, the etch stop layer includes TaN.

In some embodiments of the present disclosure, a gate insulating layer intersecting the first active region, the second active region, and the first field insulating layer is further included between the substrate and the first gate electrode structure, and the first The work function control layer and the second work function control layer contact the gate insulating layer, respectively.

In some embodiments of the present disclosure, an interlayer insulating layer including a trench crossing the first active region, the first field insulating layer, and the second active region is further included on the substrate, wherein the first work function is adjusted The film and the second work function control film extend along side surfaces and bottom surfaces of the trench.

In some embodiments of the present invention, a top surface of the first gate electrode structure is disposed on the same plane as a top surface of the interlayer insulating layer.

In some embodiments of the present disclosure, the first gate electrode structure may further include a capping pattern filling a portion of the trench and filling the trench on the first gate electrode structure, and a top surface of the capping pattern is the interlayer insulating layer. lie on the same plane as the top surface of

In some embodiments of the present disclosure, the first upper gate electrode includes a first interposing layer on the first work function regulating layer, and the second upper gate electrode includes a second interposing layer on the second work function regulating layer. and the first interposing layer and the second interposing layer are the same material layer, and are in direct contact with each other, and the thickness of the first insertion layer and the thickness of the second insertion layer are substantially the same.

In some embodiments of the present invention, the first intercalation layer and the second intercalation layer include TiAl.

In some embodiments of the present invention, the first active region and the second active region are a first fin-shaped pattern and a second fin-shaped pattern, respectively.

Another aspect of the semiconductor device of the present invention for solving the above problems is a first fin-shaped pattern and a second fin-shaped pattern adjacent to each other; a first field insulating layer between the first fin-shaped pattern and the second fin-shaped pattern and covering a portion of the first fin-shaped pattern and the second fin-shaped pattern; a first gate electrode structure intersecting the first fin-shaped pattern, the first field insulating layer, and the second fin-shaped pattern, wherein the first gate electrode structure includes a first p-type gate electrode in direct contact with each other and a first n-th gate electrode structure a type gate electrode, wherein the first p-type gate electrode includes a first work function control layer on the first fin pattern and the first field insulating layer, and a first upper gate electrode on the first work function control layer and the first n-type gate electrode includes a second work function regulating film on the second fin-shaped pattern and the first field insulating film, and a second upper gate electrode on the second work function regulating film, and the first The work function control layer and the second work function control layer are in direct contact with each other and are the same material layer, the thickness of the first work function control layer is thicker than the thickness of the second work function control layer, and the first p-type gate electrode and the The overlapping width of the first field insulating layer is greater than the overlapping width of the first n-type gate electrode and the first field insulating layer.

In some embodiments of the present invention, a contact surface between the first p-type gate electrode and the first n-type gate electrode is closer to the second fin-shaped pattern than the first fin-shaped pattern.

In some embodiments of the present disclosure, the first work function regulating film and the second work function regulating film are successively formed along the profile of the first fin-shaped pattern, the upper surface of the first field insulating film, and the profile of the second fin-shaped pattern. is extended

In some embodiments of the present invention, a gate insulating layer extending along the profile of the first fin-shaped pattern, the upper surface of the first field insulating layer, and the profile of the second fin-shaped pattern is further included under the first gate electrode structure, , the first gate electrode structure further includes a TiN layer extending along the gate insulating layer on the gate insulating layer, and a TaN layer on the TiN layer, wherein the first work function control layer and the second work function control layer include respectively on the TaN film and in contact with the TaN film.

In some embodiments of the present invention, a gate insulating layer extending along the profile of the first fin-shaped pattern, the upper surface of the first field insulating layer, and the profile of the second fin-shaped pattern is further included under the first gate electrode structure, , the first work function control layer and the second work function control layer contact the gate insulating layer, respectively.

In some embodiments of the present invention, a third fin-shaped pattern and a fourth fin-shaped pattern adjacent to each other, and between the third fin-shaped pattern and the fourth fin-shaped pattern, a portion of the third fin-shaped pattern and the fourth fin-shaped pattern is formed a second field insulating layer covering the second field insulating layer; and a second gate electrode structure crossing the third fin-shaped pattern, the second field insulating layer, and the fourth fin-shaped pattern on the gate insulating layer, wherein the second gate electrode structure includes: a second p-type gate electrode and a second n-type gate electrode in direct contact with each other, wherein a contact surface of the second p-type gate electrode and the second n-type gate electrode is larger than the third fin pattern close to

In some embodiments of the present invention, the first fin-shaped pattern and the second fin-shaped pattern are formed in an SRAM region, and the third fin-shaped pattern and the fourth fin-shaped pattern are formed in a logic region.

In some embodiments of the present invention, between the first fin-shaped pattern and the second fin-shaped pattern, the fin-shaped pattern protruding above the top surface of the field insulating layer is not formed.

Another aspect of the semiconductor device of the present invention for solving the above problems is a substrate including a first active region, a second active region, and a field insulating film in direct contact between the first active region and the second active region ; an interlayer insulating layer on the substrate, the interlayer insulating layer including a trench crossing the first active region, the field insulating layer, and the second active region; a gate insulating layer extending along sidewalls and bottom surfaces of the trench; and a gate electrode structure on the gate insulating layer, filling the trench, and crossing the first active region, the second active region, and the field insulating layer, wherein the gate electrode structure is in direct contact with each other. and an n-type gate electrode, wherein the p-type gate electrode extends over the first active region and the field insulating layer, the n-type gate electrode extends over the second active region and the field insulating layer, and The p-type gate electrode includes a first TiN layer extending along the gate insulating layer and a first upper gate electrode on the first TiN layer, the n-type gate electrode extending along the gate insulating layer and the first TiN layer a second TiN film in direct contact with the film and a second upper gate electrode on the second TiN film, wherein a thickness of the first upper gate electrode on the field insulating film is equal to that of the second upper gate electrode on the field insulating film is smaller than a thickness of , and the overlapping width of the first TiN layer and the field insulating layer is different from the overlapping width of the second TiN layer and the field insulating layer.

In some embodiments of the present invention, a thickness of the first TiN layer is greater than a thickness of the second TiN layer.

In some embodiments of the present invention, an overlapping width of the first TiN layer and the field insulating layer is greater than an overlapping width of the second TiN layer and the field insulating layer.

In some embodiments of the present invention, an overlapping width of the first TiN layer and the field insulating layer is smaller than an overlapping width of the second TiN layer and the field insulating layer.

In some embodiments of the present invention, the first active region is a pull-up transistor formation region of an SRAM, and the second active region is a pull-down transistor formation region of an SRAM.

In some embodiments of the present invention, the first active region and the second active region are a first fin-shaped pattern and a second fin-shaped pattern, respectively.

Other specific details of the invention are included in the detailed description and drawings.

1 is a plan view illustrating a semiconductor device according to some embodiments of the present invention.
2A and 2B are cross-sectional views taken along line A - A of FIG. 1 .
3A and 3B are cross-sectional views taken along lines B - B and C - C of FIG. 1 .
4 and 5 are diagrams for explaining a semiconductor device according to some embodiments of the present invention.
6 is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
7 is a view for explaining a semiconductor device according to some embodiments of the present invention.
8 is a plan view illustrating a semiconductor device according to some embodiments of the present invention.
9 is a cross-sectional view taken along line A - A of FIG. 8 .
10A is a diagram for explaining a semiconductor device according to some embodiments of the present invention.
10B is a diagram for describing a semiconductor device according to some embodiments of the present invention.
11 is a plan view illustrating a semiconductor device according to some embodiments of the present invention.
12 is a cross-sectional view taken along line A - A of FIG. 11 .
13 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
14 is a plan view illustrating a semiconductor device according to some embodiments of the present invention.
15 is a cross-sectional view taken along line A - A of FIG. 14 .
16 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
17 is a plan view illustrating a semiconductor device according to some embodiments of the present invention.
18 is a cross-sectional view taken along lines A - A and D - D of FIG. 17 .
19 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
20 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
21 is a plan view illustrating a semiconductor device according to some embodiments of the present invention.
22 is a plan view illustrating a semiconductor device according to some embodiments of the present invention.
23 is a plan view illustrating a semiconductor device according to some embodiments of the present invention.
24 is a cross-sectional view taken along lines A - A and D - D of FIG. 23 .
25 is a diagram for describing a semiconductor device according to some embodiments of the present invention.
26 is a plan view for explaining a semiconductor device according to some embodiments of the present invention.
27 is a cross-sectional view taken along lines A - A and D - D of FIG. 26 .
28 is a block diagram of an SoC system including a semiconductor device according to embodiments of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Relative sizes of layers and regions in the drawings may be exaggerated for clarity of explanation. Like reference numerals refer to like elements throughout.

When an element is referred to as “connected to” or “coupled to” with another element, it means that it is directly connected or coupled to another element, or with the other element intervening. including all cases. On the other hand, when one element is referred to as “directly connected to” or “directly coupled to” with another element, it indicates that another element is not interposed therebetween. Like reference numerals refer to like elements throughout. “And/or” includes each and every combination of one or more of the recited items.

Reference to an element or layer “on” or “on” another element or layer includes not only directly on the other element or layer, but also with intervening other layers or other elements. include all On the other hand, reference to an element "directly on" or "directly on" indicates that no intervening element or layer is interposed.

Although first, second, etc. are used to describe various elements, components, and/or sections, it should be understood that these elements, components, and/or sections are not limited by these terms. These terms are only used to distinguish one element, component, or sections from another. Accordingly, it goes without saying that the first element, the first element, or the first section mentioned below may be the second element, the second element, or the second section within the spirit of the present invention.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural, unless specifically stated otherwise in the phrase. As used herein, “comprises” and/or “comprising” refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded.

Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used with the meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless clearly defined in particular.

In the drawings of semiconductor devices according to some embodiments of the present invention, a fin-type transistor (FinFET) including a channel region having a fin-shaped pattern is illustrated, but the present invention is not limited thereto. Of course, the semiconductor device according to some embodiments of the present invention may include a tunneling transistor (FET), a transistor including a nanowire, a transistor including a nanosheet, or a three-dimensional (3D) transistor. . In addition, the semiconductor device according to some embodiments of the present invention may include a bipolar junction transistor, a lateral double diffusion transistor (LDMOS), or the like.

Hereinafter, semiconductor devices according to some embodiments of the present invention will be described with reference to FIGS. 1 to 3 .

1 is a plan view illustrating a semiconductor device according to some embodiments of the present invention. 2A and 2B are cross-sectional views taken along line A - A of FIG. 1 . 3A and 3B are cross-sectional views taken along lines B - B and C - C of FIG. 1 .

For reference, for convenience of description, FIG. 1 schematically illustrates only the first active region 10 , the second active region 20 , and the first gate electrode structure 50 .

1 to 3B , a semiconductor device according to some embodiments of the present invention includes a substrate 100 including a first active region 10 , a second active region 20 , and a first field insulating layer 105 . and a first gate electrode structure 50 crossing the first active region 10 , the second active region 20 , and the first field insulating layer 105 .

The substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate, or another material such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide or It may include, but is not limited to, gallium antimonide.

In the following description, for convenience of description, the substrate 100 will be described as a substrate including silicon.

The first active region 10 and the second active region 20 may be defined by the first field insulating layer 105 . Although the first active region 10 and the second active region 20 are spatially separated, they are adjacent to each other.

The first active region 10 and the second active region 20 may have a rectangular shape elongated in the first direction X1, but are not limited thereto. The first active region 10 and the second active region 20 may be adjacent to each other in the long side direction and may be arranged in parallel.

The first active region 10 is a region in which a PMOS is formed, and the second active region 20 is a region in which an NMOS is formed. For example, the first active region 10 is a region in which a pull-up transistor of the SRAM is formed, and the second active region 30 is a region in which a pull-down transistor or a pass transistor of the SRAM is formed. It may be an area to be used, but is not limited thereto.

That is, the regions to which the gate voltage is applied by one gate electrode structure and where the PMOS and NMOS adjacent to each other are formed may be the first active region 10 and the second active region 20 .

In the semiconductor device according to some embodiments of the present invention, the first active region 10 and the second active region 20 will be described as being formed in the SRAM region.

The first field insulating layer 105 may be formed to surround the first active region 10 and the second active region 20 . However, in the semiconductor device according to some embodiments of the present invention, the first field insulating layer 105 will be described as meaning a portion positioned between the first active region 10 and the second active region 20 .

The first field insulating layer 105 may be disposed between the first active region 10 and the second active region 20 , and may directly contact the first active region 10 and the second active region 20 .

That is, when the first field insulating layer 105 directly contacts the first active region 10 and the second active region 20 , there is another active region between the first active region 10 and the second active region 20 . This means that it is not intervening.

The first field insulating layer 105 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.

In addition, the first field insulating layer 105 includes at least one field formed between the first active region 10 and the first field insulating layer 105 , and the second active region 20 and the first field insulating layer 105 . It may further include a liner film.

When the first field insulating layer 105 further includes a field liner layer, the field liner layer may include at least one of polysilicon, amorphous silicon, silicon oxynitride, silicon nitride, and silicon oxide.

A width of the first field insulating layer 105 positioned between the first active region 10 and the second active region 20 may be the first width W1 . Also, the first field insulating layer 105 includes a first center line CL1 positioned at the same distance from the first active region 10 and the second active region 20 .

That is, the distance from the first center line CL1 to the first active region 10 and the distance from the first center line CL1 to the second active region 20 are equal to each other, and the It may be half of the width W1. The first center line CL1 of the first field insulating layer 105 may be arranged in parallel with the first active region 10 and the second active region 20 .

The first gate electrode structure 50 may be formed on the substrate 100 . The first gate electrode structure 50 may cross the first active region 10 , the second active region 20 , and the first field insulating layer 105 . The first gate electrode structure 50 may extend long in the second direction Y1 .

The first gate electrode structure 50 includes a first gate electrode 120 and a second gate electrode 220 . The first gate electrode 120 and the second gate electrode 220 are in contact with each other, specifically, in direct contact with each other.

The first gate electrode 120 is a p-type metallic gate electrode, and may be formed on the first active region 10 and the first field insulating layer 105 . The second gate electrode 220 is an n-type metallic gate electrode, and may be formed on the second active region 20 and the first field insulating layer 105 .

A first transistor 10p is formed in a region where the first active region 10 and the first gate electrode structure 50 intersect, and the second active region 20 and the first gate electrode structure 50 intersect each other. A second transistor 10n may be formed in the region. The first transistor 10p may be a p-type transistor, and the second transistor 10n may be an n-type transistor.

That is, the first transistor 10p and the second transistor 10n of different conductivity types may share the first gate electrode structure 50 .

Since the first gate electrode 120 extends on the first field insulating layer 105 , it overlaps a portion of the first field insulating layer 105 as well as the first active region 10 .

Since the second gate electrode 220 is in direct contact with the first gate electrode 120 , the second gate electrode 220 includes a second gate electrode 220 that does not overlap not only the second active region 20 but also the first gate electrode 120 . It may overlap the rest of the first field insulating layer 105 .

The first gate electrode structure 50 includes a first contact surface MI1 where the first gate electrode 120 and the second gate electrode 220 contact each other. The first contact surface MI1 contacting the first gate electrode 120 and the second gate electrode 220 is disposed on the first field insulating layer 105 .

The first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 may not coincide with the first center line CL1 of the first field insulating layer 105 . In other words, the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 may be closer to the second active region 20 than to the first active region 10 , and It may be closer to the first active region 10 than to the active region 20 .

In the semiconductor device according to some exemplary embodiments described with reference to FIG. 1 , the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is the first active region 10 . It may be located closer to the second active region 20 .

In FIG. 1 , since the first active region 10 , the first center line CL1 , the first contact surface MI1 , and the second active region 20 are arranged in this order, the second gate electrode 220 is formed in the first field It does not overlap the first center line CL1 of the insulating layer 105 . That is, the first contact surface MI1 is positioned between the second active region 20 and the first center line CL1 of the first field insulating layer 105 .

The first active region 10 includes a channel region of a p-type transistor, and the second active region 20 includes a channel region of an n-type transistor. In this case, since the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is located closer to the second active region 20 than to the first active region 10 , the first The contact surface MI1 is closer to the channel region of the n-type transistor than the channel region of the p-type transistor.

In other words, among the first gate electrodes 120 , the width of the first gate electrode 120 extending onto the first field insulating layer 105 is the first overlapping width W11 . That is, the width of the first gate electrode 120 from the first contact surface MI1 to the boundary of the first active region 10 is the first overlapping width W11 .

Among the second gate electrodes 220 , the width of the second gate electrode 220 extending on the first field insulating layer 105 is the second overlapping width W12 . That is, the width of the second gate electrode 220 from the first contact surface MI1 to the boundary of the second active region 20 is the second overlapping width W12 .

Since the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 does not coincide with the first center line CL1 of the first field insulating layer 105 , the first overlap width W11 . is different from the second overlapping width W12.

In the semiconductor device according to some exemplary embodiments described with reference to FIG. 1 , the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is the first active region 10 . Since it is located closer to the second active region 20 , the first overlapping width W11 is greater than the second overlapping width W12 .

The width W11 of the first gate electrode 120 overlapping the first field insulating layer 105 is greater than the width W12 of the second gate electrode 220 overlapping the first field insulating layer 105 .

In addition, since the first gate electrode 120 and the second gate electrode 220 are in direct contact with each other, the width W11 of the first gate electrode 120 overlapping the first field insulating layer 105 and the first field The sum of the width W12 of the second gate electrode 220 overlapping the insulating layer 105 may be equal to the width W1 of the first field insulating layer 105 .

The structures of the first gate electrode 120 and the second gate electrode 220 will be described in detail below.

The interlayer insulating layer 190 may be formed on the substrate 100 . The interlayer insulating layer 190 may include a first trench 50t.

The first trench 50t may cross the first active region 10 , the first field insulating layer 105 , and the second active region 20 . That is, the first trench 50t may intersect the first active region 10 and the second active region 20 . The first trench 50t may extend long in the second direction Y1 .

The interlayer insulating layer 190 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The low-dielectric constant material is, for example, Flowable Oxide (FOX), Torene SilaZene (TOSZ), Undoped Silica Glass (USG), Borosiliica Glass (BSG), PhosphoSilica Glass (PSG), BoroPhosphoSilica Glass (BPSG), Plasma Enhanced Tetra (PETEOS). Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material or a combination thereof, but is not limited thereto.

The first spacers 55 may be formed on the substrate 100 . The first spacer 55 may define a first trench 50t. The first spacer 55 may be formed on a sidewall of the first gate electrode structure 50 .

The first gate electrode structure 50 elongates in the second direction Y1 . Accordingly, the first gate electrode structure 50 includes a long side extending in the second direction Y1 and a short side extending in the first direction X1 .

2A to 3B , the first spacer 55 is shown to be formed on both the sidewall including the long side of the first gate electrode structure 50 and the sidewall including the short side of the first gate electrode structure 50 . However, it is not limited thereto.

2A to 3B , the first spacer 55 is formed on the sidewall including the long side of the first gate electrode structure 50 , but includes the short side of the first gate electrode structure 50 . It may not be formed on the sidewall.

Alternatively, the thickness of the first spacer 55 formed on the sidewall including the long side of the first gate electrode structure 50 is the thickness of the first spacer 55 formed on the sidewall including the short side of the first gate electrode structure 50 . ) may be different from the thickness of

The first spacer 55 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon oxycarbonitride (SiOCN), and combinations thereof.

Although the first spacer 55 is illustrated as a single layer, it is only for convenience of description and is not limited thereto. When the first spacer 55 is a plurality of layers, at least one of the layers included in the first spacer 55 may include a low-k material such as silicon oxycarbonitride (SiOCN).

Also, when the first spacer 55 is a plurality of layers, at least one layer included in the first spacer 55 may have an L-shape.

In some cases, the first spacer 55 may serve as a guide for forming a self-aligned contact. Accordingly, the first spacer 55 may include a material having an etch selectivity with respect to the interlayer insulating layer 190 .

The first gate insulating layer 130 and the second gate insulating layer 230 may be formed on the substrate 100 . The first gate insulating layer 130 may be formed on the first active region 10 and the first field insulating layer 105 . The second gate insulating layer 230 may be formed on the second active region 20 and the first field insulating layer 105 .

The first gate insulating layer 130 and the second gate insulating layer 230 may extend along sidewalls and bottom surfaces of the first trench 50t. The first and second gate insulating layers 130 and 230 extending along the bottom surface of the first trench 50t form the first active region 10 , the first field insulating layer 105 , and the second active region 20 . can cross

The first gate insulating layer 130 and the second gate insulating layer 230 may be divided by the first contact surface MI1 of the first gate electrode structure 50 . The first gate insulating layer 130 and the second gate insulating layer 230 are formed at the same level. Here, the term “same level” means that they are formed by the same manufacturing process.

Each of the first gate insulating layer 130 and the second gate insulating layer 230 may include a high-k insulating layer. The high dielectric constant insulating film is, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium may include one or more of strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. have.

In addition, although the high-k insulating layer has been described with the focus on oxide, the high-k insulating layer is different from the above-described metallic material nitride (eg, hafnium nitride) or oxynitride (eg, hafnium oxynitride). ), but is not limited thereto.

Unlike FIGS. 2A and 3A , in FIGS. 2B and 3B , between the first gate insulating layer 130 and the first active region 10 and between the second gate insulating layer 230 and the second active region 20 , A first interfacial layer 131 and a second interfacial layer 231 may be formed, respectively.

Depending on the formation method, the first and second interfacial layers 131 and 231 may be formed only on the first active region 10 and the second active region 20 , or on the sidewall of the first trench 50t and It may be formed along the bottom surface (ie, the top surface of the first field insulating layer 105 and the sidewall of the first spacer 55 ).

Depending on the type of the substrate 100 or the type of the first and second gate insulating layers 130 and 230 , the first and second interface layers 131 and 231 may include different materials. When the substrate 100 is a silicon substrate, the first and second interface layers 131 and 231 may include, for example, silicon oxide.

In FIGS. 2B and 3B , top surfaces of the first and second interface layers 131 and 231 are illustrated as being on the same plane as the top surfaces of the first field insulating layer 105 , but this is only for convenience of description, and the present invention is limited thereto. it's not going to be

The first gate electrode structure 50 may be formed on the first gate insulating layer 130 and the second gate insulating layer 230 . The first gate insulating layer 130 and the second gate insulating layer 230 may be formed between the first gate electrode structure 50 and the substrate 100 . The first gate insulating layer 130 and the second gate insulating layer 230 may be formed under the first gate electrode structure 50 .

The first gate electrode structure 50 may fill the first trench 50t. A top surface of the first gate electrode structure 50 may be coplanar with a top surface of the first spacer 55 and a top surface of the interlayer insulating layer 190 .

The first gate electrode 120 includes a first lower conductive layer 125 sequentially formed on the first gate insulating layer 130 , a first etch stop layer 124 , a first work function control layer 121 , It may include a first insertion layer 122 and a first peeling layer 123 .

The second gate electrode 220 includes a second lower conductive layer 225 sequentially formed on the second gate insulating layer 230 , a second etch stop layer 224 , a second work function control layer 221 , and It may include a second insertion layer 222 and a second peeling layer 223 .

The first lower conductive layer 125 and the second lower conductive layer 225 may be formed on the first and second gate insulating layers 130 and 230 . The first lower conductive layer 125 may be in contact with the first gate insulating layer 130 , and the second lower conductive layer 225 may be in contact with the second gate insulating layer 230 .

The first lower conductive layer 125 may be formed on the first active region 10 and the first field insulating layer 105 . The second lower conductive layer 225 may be formed on the second active region 20 and the first field insulating layer 105 .

The first lower conductive layer 125 and the second lower conductive layer 225 may extend along sidewalls and bottom surfaces of the first trench 50t. The first lower conductive layer 125 may extend along the profile of the first gate insulating layer 130 , and the second lower conductive layer 225 may extend along the profile of the second gate insulating layer 230 .

The first lower conductive layer 125 and the second lower conductive layer 225 may be divided by the first contact surface MI1 of the first gate electrode structure 50 .

The first lower conductive layer 125 and the second lower conductive layer 225 may include the same material. The first lower conductive layer 125 and the second lower conductive layer 225 may include, for example, TiN.

The first etch stop layer 124 and the second etch stop layer 224 may be formed on the first and second lower conductive layers 125 and 225 . The first etch stop layer 124 may be formed on the first active region 10 and the first field insulating layer 105 . The second etch stop layer 224 may be formed on the second active region 20 and the first field insulating layer 105 .

The first etch stop layer 124 and the second etch stop layer 224 may extend along sidewalls and bottom surfaces of the first trench 50t. The first etch stop layer 124 may extend along the profile of the first lower conductive layer 125 , and the second etch stop layer 224 may extend along the profile of the second lower conductive layer 225 .

The first etch stop layer 124 and the second etch stop layer 224 may be divided by the first contact surface MI1 of the first gate electrode structure 50 . The first etch stop layer 124 and the second etch stop layer 224 may be formed at the same level. The thickness of the first etch stop layer 124 on the first active region 10 may be substantially the same as that of the second etch stop layer 224 on the second active region 20 , but is not limited thereto.

The first etch stop layer 124 and the second etch stop layer 224 may include the same material. The first etch stop layer 124 and the second etch stop layer 224 may include, for example, TaN.

The first work function control layer 121 and the second work function control layer 221 may be formed on the first and second etch stop layers 124 and 224 . The first work function control layer 121 may contact the first etch stop layer 124 , and the second work function control layer 221 may contact the second etch stop layer 224 .

The first work function control layer 121 may be formed on the first active region 10 and the first field insulating layer 105 . The second work function control layer 221 may be formed on the second active region 20 and the first field insulating layer 105 . The first work function control layer 121 and the second work function control layer 221 may directly contact each other.

The first work function control layer 121 and the second work function control layer 221 may extend along sidewalls and bottom surfaces of the first trench 50t. The first work function control layer 121 extends along the profiles of the first gate insulating layer 130 and the first etch stop layer 124 , and the second work function control layer 221 includes the second gate insulating layer 230 and It may extend along the profile of the second etch stop layer 224 .

The first work function control layer 121 and the second work function control layer 221 may include the same material. More specifically, the first work function control layer 121 and the second work function control layer 221 may be the same material layer. The first work function control layer 121 and the second work function control layer 221 may include, for example, TiN.

A thickness t11 of the first work function control layer 121 may be different from a thickness t21 of the second work function control layer 221 . For example, the thickness t11 of the first work function control layer 121 may be greater than the thickness t21 of the second work function control layer 221 .

That is, the thickness t11 of the first work function control layer 121 included in the p-type gate electrode may be greater than the thickness t21 of the second work function control layer 221 included in the n-type gate electrode. For example, the thickness t11 of the first work function control layer 121 is the thickness on the first active region 10 , and the thickness t21 of the second work function control layer 221 is the second active region It may be the thickness of the phase (20), but is not limited thereto.

The first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is defined between the first work function control layer 121 and the second work function control layer 221 having different thicknesses. do. That is, the first gate electrode along the normal line of the substrate 100 with the boundary between the first work function control layer 121 and the second work function control layer 221 extending on the first field insulating layer 105 . When the structure 50 is cut, it becomes the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 .

Since the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is defined as a boundary between the first work function control layer 121 and the second work function control layer 221 , The overlapping width W11 of the first work function control layer 121 and the first field insulating layer 105 is the same as the overlapping width W12 of the second work function control layer 221 and the first field insulating layer 105 . different.

1 to 2B , the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is located closer to the second active region 20 than the first active region 10 . Therefore, the overlapping width W11 of the first work function control layer 121 and the first field insulating layer 105 is the overlapping width W12 of the second work function control layer 221 and the first field insulating layer 105 . ) is greater than

In addition, since the first active region 10 , the first center line CL1 , the first contact surface MI1 , and the second active region 20 are arranged in this order, the second work function control layer 221 is formed in the first field It does not overlap the first center line CL1 of the insulating layer 105 .

The first intercalation layer 122 and the second interposing layer 222 may be formed on the first and second work function control layers 121 and 221 . The first insertion layer 122 and the second insertion layer 222 may directly contact each other.

The first insertion layer 122 may be formed on the first active region 10 and the first field insulating layer 105 . The second insertion layer 222 may be formed on the second active region 20 and the first field insulating layer 105 .

The first insertion layer 122 and the second insertion layer 222 may extend along sidewalls and bottom surfaces of the first trench 50t. The first intercalation layer 122 and the second interlayer layer 222 may extend along the profiles of the first and second work function control layers 121 and 221 in direct contact with each other.

The first insertion layer 122 and the second insertion layer 222 may be divided by the first contact surface MI1 of the first gate electrode structure 50 . The first insertion layer 122 and the second insertion layer 222 may be formed at the same level.

A thickness t12 of the first insertion layer 122 may be substantially the same as a thickness t22 of the second insertion layer 222 . For example, the thickness t12 of the first insertion layer 122 is the thickness on the first active region 10 , and the thickness t22 of the second insertion layer 222 is on the second active region 20 . may be, but is not limited thereto.

The first insertion layer 122 and the second insertion layer 222 may include the same material. The first etch stop layer 124 and the second etch stop layer 224 may include, for example, one of Ti, TiAl, TiAlN, TiAlC, and TiAlCN.

In the semiconductor device according to some embodiments of the present invention, the first interposed layer 122 and the second interposed layer 222 will be described as a layer including TiAl.

The first filling layer 123 and the second filling layer 223 may be formed on the first and second insertion layers 122 and 222 . The first peeling layer 123 and the second peeling layer 223 may directly contact each other.

The first filling layer 123 may be formed on the first active region 10 and the first field insulating layer 105 . The second filling layer 223 may be formed on the second active region 20 and the first field insulating layer 105 .

The first filling layer 123 and the second filling layer 223 may be divided by the first contact surface MI1 of the first gate electrode structure 50 . The first filling layer 123 and the second filling layer 223 may be formed at the same level.

The first filling layer 123 and the second filling layer 223 may include the same material. The first and second peeling layers 123 and 223 may include, for example, at least one of W, Al, Co, Cu, Ru, Ni, Pt, Ni-Pt, and TiN.

The first insertion layer 122 and the first filling layer 123 on the first work function control layer 121 may be a first upper gate electrode, and the second insertion layer ( ) on the second work function control layer 221 . 222 and the second filling layer 223 may be a second upper gate electrode.

The thickness h1 of the first upper gate electrodes 122 and 123 is the distance from the top surface of the interlayer insulating layer 190 to the first work function control layer 121 on the bottom surface of the first trench 50t, and the second The thickness h2 of the upper gate electrodes 222 and 223 may be a distance from the top surface of the interlayer insulating layer 190 to the second work function control layer 221 on the bottom surface of the first trench 50t.

In this case, on the first field insulating layer 105 , the thickness h1 of the first upper gate electrodes 122 and 123 may be different from the thickness h2 of the second upper gate electrodes 222 and 223 . For example, the thickness h1 of the first upper gate electrodes 122 and 123 may be smaller than the thickness h2 of the second upper gate electrodes 222 and 223 .

The first source/drain 150 may be formed on both sides of the first gate electrode 120 , and the second source/drain 250 may be formed on both sides of the second gate electrode 220 .

The first source/drain 150 and the second source/drain 250 are illustrated as including an epitaxial layer formed in the substrate 100 , but are not limited thereto. The first source/drain 150 and the second source/drain 250 may be impurity regions formed by implanting impurities into the substrate 100 .

In addition, the first source/drain 150 and the second source/drain 250 may be raised sources/drains including upper surfaces protruding above the upper surface of the substrate 100 .

4 and 5 are diagrams for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, the points different from those described with reference to FIGS. 1 to 3B will be mainly described.

For reference, FIG. 4 is a cross-sectional view taken along line A - A of FIG. 1 , and FIG. 5 is a cross-sectional view taken along line B - B and C - C of FIG. 1 .

4 and 5 , in the semiconductor device according to some embodiments of the present disclosure, the first work function control layer 121 is in contact with the first gate insulating layer 130 , and the second work function control layer 221 is in contact with the second work function control layer 221 . ) may be in contact with the second gate insulating layer 230 .

The first gate electrode 120 may include a first work function control layer 121 sequentially formed on the first gate insulating layer 130 , a first insertion layer 122 , and a first filling layer 123 . can

The second gate electrode 220 may include a second work function control layer 221 , a second insertion layer 222 , and a second filling layer 223 sequentially formed on the second gate insulating layer 230 . can

A conductive layer may not be interposed between the first gate insulating layer 130 and the first work function control layer 121 . Similarly, a conductive layer may not be interposed between the second gate insulating layer 230 and the second work function control layer 221 .

6 is a diagram for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, the points different from those described with reference to FIGS. 1 to 3B will be mainly described.

For reference, FIG. 6 is a cross-sectional view taken along line A - A of FIG. 1 .

Referring to FIG. 6 , the semiconductor device according to some exemplary embodiments may further include a capping pattern 60 .

The first gate electrode structure 50 may partially fill the first trench 50t. The top surface of the first gate electrode structure 50 may be closer to the top surface of the substrate 100 than the top surface of the interlayer insulating layer 190 .

The capping pattern 60 may be formed on the first gate electrode structure 50 . In other words, the capping pattern 160 may be formed on the first upper gate electrodes 122 and 123 . The capping pattern 60 may fill a portion of the first trench 50t remaining after the first gate electrode structure 50 is filled.

Since the capping pattern 60 is formed by filling a portion of the first trench 50t, the upper surface of the capping pattern 60 may be disposed on the same plane as the upper surface of the first spacer 55 and the upper surface of the interlayer insulating layer 190. have.

Since the capping pattern 60 may serve as a guide for forming a self-aligned contact, it may include a material having an etch selectivity with respect to the interlayer insulating layer 190 .

The capping pattern 60 is, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbon dioxide oxynitride (SiOCN), and combinations thereof. may include.

Unlike the drawings, the first gate insulating layer 130 may extend between the first spacer 55 and the capping pattern 60 . That is, a portion of the first gate insulating layer 130 may extend between the inner wall of the first spacer 55 facing each other and the capping pattern 60 .

Similarly, the second gate insulating layer 230 may extend between the first spacer 55 and the capping pattern 60 .

7 is a view for explaining a semiconductor device according to some embodiments of the present invention. For convenience of description, the points different from those described with reference to FIGS. 1 to 3B will be mainly described.

Referring to FIG. 7 , in the semiconductor device according to some embodiments of the present disclosure, the first gate insulating layer 130 and the second gate insulating layer 230 are interposed between the first gate electrode structure 50 and the first spacer 55 . It may not include an extended part.

In addition, in the first gate electrode 120 , the first lower conductive layer 125 , the first etch stop layer 124 , the first work function control layer 121 , and the first insertion layer 122 are formed of a first A portion extending along the inner wall of the spacer 55 may not be included.

Similarly, in the second gate electrode 220 , the second lower conductive layer 225 , the second etch stop layer 224 , the second work function control layer 221 , and the second insertion layer 222 include the first A portion extending along the inner wall of the spacer 55 may not be included.

8 is a plan view illustrating a semiconductor device according to some embodiments of the present invention. 9 is a cross-sectional view taken along line A - A of FIG. 8 . For convenience of description, the points different from those described with reference to FIGS. 1 to 3B will be mainly described.

For reference, since FIG. 9 may be substantially the same as FIG. 2 except for the fin-shaped pattern, overlapping matters will be omitted or briefly described. That is, the first fin-shaped pattern 110 may correspond to the first active region 10 , and the second fin-shaped pattern 210 may correspond to the second active region 20 .

Also, in FIG. 8 , a cross-sectional view taken along the first fin-shaped pattern 110 and the second fin-shaped pattern 210 may be substantially the same as that of FIG. 3A , except for the fin-shaped pattern.

In addition, for convenience of description, FIG. 8 schematically illustrates only the first fin-shaped pattern 210 , the second fin-shaped pattern 210 , and the first gate electrode structure 50 .

8 and 9 , a semiconductor device according to some embodiments of the present invention includes a first fin-shaped pattern 110 , a second fin-shaped pattern 210 adjacent to the first fin-shaped pattern 110 , and a first The first field insulating film 105 between the fin-shaped pattern 110 and the second fin-shaped pattern 210 , and the first fin-shaped pattern 110 , the first field insulating film 105 and the second fin-shaped pattern 210 intersect each other. A first gate electrode structure 50 is included.

The first fin-shaped pattern 110 and the second fin-shaped pattern 210 may protrude from the substrate 100 . The first fin-shaped pattern 110 and the second fin-shaped pattern 210 may each extend in the first direction X1 .

The first fin-shaped pattern 110 is a region in which a PMOS is formed, and the second fin-shaped pattern 210 is a region in which an NMOS is formed. For example, the first fin-shaped pattern 110 and the second fin-shaped pattern 210 may be formed in the SRAM region.

The first fin-shaped pattern 110 and the second fin-shaped pattern 210 may be a part of the substrate 100 , and may include an epitaxial layer grown from the substrate 100 .

Each of the first fin-shaped pattern 110 and the second fin-shaped pattern 210 may include, for example, silicon or germanium, which is an elemental semiconductor material. In addition, each of the first fin-shaped pattern 110 and the second fin-shaped pattern 210 may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. .

Specifically, using the group IV-IV compound semiconductor as an example, each of the first fin-shaped pattern 110 and the second fin-shaped pattern 210 may include carbon (C), silicon (Si), germanium (Ge), and tin (Sn). It may be a binary compound, a ternary compound, or a compound in which a group IV element is doped therewith, including at least two or more of them.

Taking the group III-V compound semiconductor as an example, each of the first fin-shaped pattern 110 and the second fin-shaped pattern 210 includes at least one of aluminum (Al), gallium (Ga), and indium (In) as a group III element; The group V element may be one of a binary compound, a ternary compound, or a quaternary compound formed by combining one of phosphorus (P), arsenic (As), and antimonium (Sb).

In the semiconductor device according to some embodiments of the present invention, each of the first fin-shaped pattern 110 and the second fin-shaped pattern 210 will be described as a silicon fin-shaped pattern.

Since the first field insulating layer 105 covers a part of the sidewall of the first fin-shaped pattern 110 and a part of the sidewall of the second fin-shaped pattern 210 , the first fin-shaped pattern 110 and the second fin-shaped pattern 210 . ) may protrude above the top surface of the first field insulating layer 105 formed on the substrate 100 .

The first fin-shaped pattern 110 and the second fin-shaped pattern 210 may be defined by the first field insulating layer 105 . The first fin-shaped pattern 110 and the second fin-shaped pattern 210 are spaced apart from each other, but are adjacent to each other.

The first field insulating layer 105 may be disposed between the first fin-shaped pattern 110 and the second fin-shaped pattern 210 , and may directly contact the first fin-shaped pattern 110 and the second fin-shaped pattern 210 .

When the first field insulating layer 105 is in direct contact with the first fin-shaped pattern 110 and the second fin-shaped pattern 210, the first field insulating layer ( 105) means that the pin-shaped pattern protruding above the upper surface is not interposed.

9 , the first field insulating layer 105 is disposed between the first fin-shaped pattern 110 and the first field insulating layer 105 , and between the second fin-shaped pattern 210 and the first field insulating layer 105 . At least one field liner layer formed may be further included.

A distance from the first center line CL1 to the first fin-shaped pattern 110 may be the same as a distance from the first center line CL1 to the second fin-shaped pattern 210 .

The first gate electrode structure 50 may cross the first fin-shaped pattern 110 , the second fin-shaped pattern 210 , and the first field insulating layer 105 . The first gate electrode structure 50 may extend long in the second direction Y1 .

The first gate electrode 120 may be formed on the first fin-shaped pattern 110 and the first field insulating layer 105 . The second gate electrode 220 may be formed on the second fin-shaped pattern 210 and the first field insulating layer 105 .

The first transistor 10p formed in a region where the first fin-type pattern 110 and the first gate electrode structure 50 intersect may be a p-type fin-type transistor. The second transistor 10n formed in a region where the second fin-type pattern 210 and the first gate electrode structure 50 intersect may be an n-type fin-type transistor.

The first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 may be closer to the second fin-shaped pattern 210 than to the first fin-shaped pattern 110, or the second fin-shaped pattern ( It may be closer to the first fin-shaped pattern 110 than 210 .

In the semiconductor device according to some exemplary embodiments described with reference to FIG. 8 , the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is the first fin-shaped pattern 110 . It may be located closer to the second fin-shaped pattern 210 .

Accordingly, the width W11 of the first gate electrode 120 overlapping the first field insulating layer 105 is greater than the width W12 of the second gate electrode 220 overlapping the first field insulating layer 105 . .

The first trench 50t defined by the first spacer 55 may cross the first fin-shaped pattern 110 , the first field insulating layer 105 , and the second fin-shaped pattern 210 . That is, the first trench 50t may cross the first fin-shaped pattern 110 and the second fin-shaped pattern 210 .

The first gate insulating layer 130 may be formed on the first field insulating layer 105 and the first fin-shaped pattern 110 . The first gate insulating layer 130 may be formed along the top surface of the first field insulating layer 105 and the profile of the first fin-shaped pattern 110 .

The second gate insulating layer 230 may be formed on the first field insulating layer 105 and the second fin-shaped pattern 210 . The second gate insulating layer 230 may be formed along the top surface of the first field insulating layer 105 and the profile of the second fin-shaped pattern 210 .

The first and second gate insulating layers 130 and 230 extending along the bottom surface of the first trench 50t have the profile of the first fin-shaped pattern 110 , the top surface of the first field insulating layer 105 , and the second fin-shaped pattern. It may be formed along the profile of 210 .

The first gate electrode structure 50 may be formed on the first and second gate insulating layers 130 and 230 .

The first gate electrode 120 is formed on the first gate insulating layer 130 and may cross the first fin-shaped pattern 110 . The second gate electrode 220 may be formed on the second gate insulating layer 230 and intersect the second fin-shaped pattern 210 .

Each of the first lower conductive layer 125 , the first etch stop layer 124 , the first work function control layer 121 , and the first interlayer layer 122 has a profile of the first gate insulating layer 130 . Thus, it can be formed.

In other words, each of the first lower conductive layer 125 , the first etch stop layer 124 , the first work function control layer 121 , and the first insertion layer 122 includes the first fin-shaped pattern 110 . ) and the top surface of the first field insulating layer 105 .

Each of the second lower conductive layer 225 , the second etch stop layer 224 , the second work function control layer 221 , and the second interlayer layer 222 has a profile of the second gate insulating layer 230 . Thus, it can be formed.

Each of the second lower conductive layer 225 , the second etch stop layer 224 , the second work function control layer 221 , and the second interlayer layer 222 has a profile of the second fin-shaped pattern 210 and It may extend along the top surface of the first field insulating layer 105 .

The first and second work function control layers 121 and 221 extending along the bottom surface of the first trench 50t include the profile of the first fin-shaped pattern 110 , the top surface of the first field insulating layer 105 , and the second work function control layer 121 . It may extend continuously along the profile of the fin-shaped pattern 210 .

9 , a thickness t11 of the first work function control layer 121 may be greater than a thickness t21 of the second work function control layer 221 . However, the thickness t12 of the first insertion layer 122 may be substantially the same as the thickness t22 of the second insertion layer 222 .

The thickness h1 of the first upper gate electrodes 122 and 123 from the upper surface of the interlayer insulating film 190 to the first work function adjusting film 121 is the second work function adjusting film from the upper surface of the interlayer insulating film 190 . It may be smaller than the thickness h2 of the second upper gate electrodes 222 and 223 up to 221 .

10A is a diagram for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, the points different from those described with reference to FIGS. 8 and 9 will be mainly described.

For reference, FIG. 10A is a cross-sectional view taken along line A - A of FIG. 8 .

Referring to FIG. 10A , in the semiconductor device according to some embodiments of the present invention, the first gate electrode 120 includes a first work function control layer 121 sequentially formed on the first gate insulating layer 130 , and a second It may include a first insertion layer 122 and a first peeling layer 123 .

In addition, the second gate electrode 220 includes a second work function control layer 221 , a second insertion layer 222 , and a second filling layer 223 sequentially formed on the second gate insulating layer 230 . may include

In this case, the first work function control layer 121 may contact the first gate insulating layer 130 , and the second work function control layer 221 may contact the second gate insulating layer 230 .

10B is a diagram for describing a semiconductor device according to some embodiments of the present invention. For convenience of description, the points different from those described with reference to FIG. 10A will be mainly described.

Referring to FIG. 10B , in the semiconductor device according to some embodiments of the present disclosure, the width W3 of the first fin-shaped pattern 110 may be different from the width W4 of the second fin-shaped pattern 210 .

For example, the width W3 of the first fin-shaped pattern 110 may be greater than the width W4 of the second fin-shaped pattern 210 .

Here, the width of the fin-shaped pattern may mean the width of the fin-shaped pattern at a portion meeting the top surface of the first field insulating layer 105 . For example, when the number of processes for adjusting the shape of the first fin-shaped pattern 110 is different from the number of processes for adjusting the shape of the second fin-shaped pattern 210 , the first fin-shaped pattern 110 is A width may be different from a width of the second fin-shaped pattern 210 .

Accordingly, unlike illustrated in FIG. 10B , the width W3 of the first fin-shaped pattern 110 may be smaller than the width W4 of the second fin-shaped pattern 210 .

11 is a plan view illustrating a semiconductor device according to some embodiments of the present invention. 12 is a cross-sectional view taken along line A - A of FIG. 11 . For convenience of description, the points different from those described with reference to FIGS. 1 to 3B will be mainly described.

Also, in FIG. 11 , a cross-sectional view taken along the first active region 10 and the second active region 20 may be substantially the same as that of FIG. 3A .

11 and 12 , in the semiconductor device according to some embodiments of the present invention, the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is the second active region ( 20), it may be located closer to the first active region 10 .

Since the first active region 10 , the first contact surface MI1 , the first center line CL1 , and the second active region 20 are arranged in this order, the first gate electrode 120 is formed by the first field insulating layer 105 . does not overlap with the first center line CL1 of That is, the first contact surface MI1 is positioned between the first active region 10 and the first center line CL1 of the first field insulating layer 105 .

The first active region 10 includes a channel region of a p-type transistor, and the second active region 20 includes a channel region of an n-type transistor. At this time, since the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is located closer to the first active region 10 than to the second active region 20 , the first The contact surface MI1 is closer to the channel region of the p-type transistor than the channel region of the n-type transistor.

The first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is located closer to the first active region 10 than the second active region 20 . Accordingly, the width W11 of the first gate electrode 120 overlapping the first field insulating layer 105 is smaller than the width W12 of the second gate electrode 220 overlapping the first field insulating layer 105 . .

The first gate electrode 120 includes a first lower conductive layer 125 sequentially formed on the first gate insulating layer 130 , a first etch stop layer 124 , a first work function control layer 121 , It may include a first insertion layer 122 and a first peeling layer 123 .

The second gate electrode 220 includes a second lower conductive layer 225 sequentially formed on the second gate insulating layer 230 , a second etch stop layer 224 , a second work function control layer 221 , and It may include a second insertion layer 222 and a second peeling layer 223 .

At this time, since the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is located closer to the first active region 10 than to the second active region 20 , the first The overlapping width W11 of the work function control layer 121 and the first field insulating layer 105 is smaller than the overlapping width W12 of the second work function control layer 221 and the first field insulating layer 105 .

In addition, since the first active region 10 , the first contact surface MI1 , the first center line CL1 , and the second active region 20 are arranged in the order, the first work function control layer 121 is formed in the first field It does not overlap the first center line CL1 of the insulating layer 105 .

13 is a diagram for describing a semiconductor device according to some embodiments of the present invention. For convenience of explanation, the points different from those described with reference to FIGS. 11 and 12 will be mainly described.

For reference, FIG. 13 is a cross-sectional view taken along line A - A of FIG. 11 .

Referring to FIG. 13 , in the semiconductor device according to some embodiments of the present invention, the first work function control layer 121 is in contact with the first gate insulating layer 130 , and the second work function control layer 221 is the second work function control layer 221 . 2 may be in contact with the gate insulating layer 230 .

14 is a plan view illustrating a semiconductor device according to some embodiments of the present invention. 15 is a cross-sectional view taken along line A - A of FIG. 14 .

For convenience of description, the points different from those described with reference to FIGS. 11 and 12 will be mainly described.

In addition, since the contents of the first fin-shaped pattern 110 and the second fin-shaped pattern 210 are substantially the same as those described with reference to FIGS. 8 and 9 , they will be briefly described or omitted.

14 and 15 , the semiconductor device according to some embodiments of the present invention may include a first fin-shaped pattern 110 and a second fin-shaped pattern 210 adjacent to the first fin-shaped pattern 110 . have.

The first contact surface MI1 of the first gate electrode structure 50 crossing the first fin-shaped pattern 110 and the second fin-shaped pattern 210 is at the first fin-shaped pattern 110 rather than the second fin-shaped pattern 210 . can be close

The overlapping width W11 of the first gate electrode 120 formed on the first fin-shaped pattern 110 and the first field insulating layer 105 is the second gate electrode 220 formed on the second fin-shaped pattern 210 . and the width W12 at which the first field insulating layer 105 overlaps.

Since the first contact surface MI1 of the first gate electrode structure 50 is defined at a boundary between the first work function control layer 121 and the second work function control layer 221 , the The overlapping width W11 of the first work function control layer 121 formed along the profile and the first field insulating layer 105 is the second work function control layer 221 formed along the profile of the second fin-shaped pattern 210 . and the width W12 at which the first field insulating layer 105 overlaps.

16 is a diagram for describing a semiconductor device according to some embodiments of the present invention. For convenience of description, the points different from those described with reference to FIGS. 14 and 15 will be mainly described.

For reference, FIG. 16 is a cross-sectional view taken along line A - A of FIG. 14 .

Referring to FIG. 16 , in the semiconductor device according to some embodiments of the present disclosure, the first gate electrode 120 adjusts the first work function in contact with the first gate insulating layer 130 on the first gate insulating layer 130 . It may include a film 121 , a first intercalation film 122 on the first work function adjusting film 121 , and a first peeling film 123 on the first interposing film 122 .

In addition, the second gate electrode 220 includes a second work function control layer 221 on the second gate insulating layer 230 in contact with the second gate insulating layer 230 , and a second work function control layer 221 on the second work function control layer 221 . It may include a second insertion layer 222 and a second peeling layer 223 on the second insertion layer 222 .

17 is a plan view illustrating a semiconductor device according to some embodiments of the present invention. 18 is a cross-sectional view taken along lines A - A and D - D of FIG. 17 .

The first active region 10 , the second active region 20 , and the first gate electrode structure 50 illustrated in the first region I of FIGS. 17 and 18 are the same as those described with reference to FIGS. 1 to 2B . Since they are substantially the same, the contents shown in the second region II will be mainly described in FIGS. 17 and 18 .

17 and 18 , a semiconductor device according to some embodiments of the present invention includes a substrate 100 including a first region (I) and a second region (II), and a substrate formed in the first region (I). It may include a first gate electrode structure 50 and a second gate electrode structure 70 formed in the second region II.

The substrate 100 includes a first active region 10 , a second active region 20 , a third active region 30 , a fourth active region 40 , a first field insulating layer 105 , and a second field insulating layer ( 106) may be included.

The first region I and the second region II may be regions in which devices having different functions are formed. For example, the first region I may be an SRAM region, and the second region II may be a logic region or an I/O region.

The substrate 100 of the first region I may include a first active region 10 , a second active region 20 , and a first field insulating layer 105 .

The substrate 100 of the second region II may include a third active region 30 , a fourth active region 40 , and a second field insulating layer 106 .

The third active region 30 and the fourth active region 40 may be defined by the second field insulating layer 106 . Although the third active region 30 and the fourth active region 40 are spatially separated, they are adjacent to each other.

The third active region 30 and the fourth active region 40 may have a rectangular shape elongated in the third direction X2, but are not limited thereto. The third active region 30 and the fourth active region 40 may be adjacent to each other in the long side direction and may be arranged in parallel.

The third active region 30 is a region in which a PMOS is formed, and the fourth active region 40 is a region in which an NMOS is formed.

The second field insulating layer 106 may be formed to surround the third active region 30 and the fourth active region 40 . However, in the semiconductor device according to some embodiments of the present invention, the second field insulating layer 106 will be described as meaning a portion positioned between the third active region 30 and the fourth active region 40 .

The second field insulating layer 106 may be disposed between the third active region 30 and the fourth active region 40 , and may directly contact the third active region 30 and the fourth active region 40 .

That is, the second field insulating layer 106 is in direct contact with the third active region 30 and the fourth active region 40 between the second field insulating layer 106 and the third active region 30 and the second This means that no other active region is interposed between the field insulating layer 106 and the fourth active region 40 .

The second field insulating layer 106 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.

In addition, the second field insulating layer 106 includes at least one field formed between the third active region 30 and the second field insulating layer 106 , and the fourth active region 40 and the second field insulating layer 106 . It may further include a liner film.

A width of the second field insulating layer 106 positioned between the third active region 30 and the fourth active region 40 may be the second width W2 . In addition, the second field insulating layer 106 includes a second center line CL2 positioned at the same distance from the third active region 30 and the fourth active region 40 .

That is, the distance from the second center line CL2 to the third active region 30 and the distance from the second center line CL2 to the fourth active region 40 are equal to each other, and the It may be half of the width W2. The second center line CL2 of the second field insulating layer 106 may be arranged in parallel with the third active region 30 and the fourth active region 40 .

The first gate electrode structure 50 may be formed on the substrate 100 of the first region I.

The second gate electrode structure 70 may be formed on the substrate 100 in the second region II. The second gate electrode structure 70 may cross the third active region 30 , the fourth active region 40 , and the second field insulating layer 106 . The second gate electrode structure 70 may extend long in the fourth direction Y2 .

The second gate electrode structure 70 includes a third gate electrode 320 and a fourth gate electrode 420 . The third gate electrode 320 and the fourth gate electrode 420 directly contact each other.

The third gate electrode 320 is a p-type metallic gate electrode and may be formed on the third active region 30 and the second field insulating layer 106 . The fourth gate electrode 420 is an n-type metallic gate electrode and may be formed on the fourth active region 40 and the second field insulating layer 106 .

A third transistor 20p is formed in a region where the third active region 30 and the second gate electrode structure 70 intersect, and the fourth active region 40 and the second gate electrode structure 70 intersect each other. A fourth transistor 20n may be formed in the region. The third transistor 20p may be a p-type transistor, and the fourth transistor 20n may be an n-type transistor.

Since the third gate electrode 320 extends on the second field insulating layer 106 , it overlaps a portion of the second field insulating layer 106 as well as the third active region 30 .

Since the fourth gate electrode 420 is in direct contact with the third gate electrode 320 , the fourth gate electrode 420 has a third gate electrode 320 that does not overlap not only the fourth active region 40 , but also the third gate electrode 320 . 2 It may overlap the rest of the field insulating layer 106 .

The second gate electrode structure 70 includes a second contact surface MI2 where the third gate electrode 320 and the fourth gate electrode 420 contact each other. The second contact surface MI2 where the third gate electrode 320 and the fourth gate electrode 420 contact is disposed on the second field insulating layer 106 .

In FIG. 17 , the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 may not coincide with the first center line CL1 of the first field insulating layer 105 . Also, the second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 may not coincide with the second center line CL2 of the second field insulating layer 106 .

The first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 may be located closer to the second active region 20 than the first active region 10 . The second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 may be located closer to the fourth active region 40 than the third active region 30 .

The second gate electrode 220 does not overlap the first center line CL1 of the first field insulating layer 105 . The fourth gate electrode 420 does not overlap the first center line CL2 of the second field insulating layer 106 .

The third active region 30 includes a channel region of a p-type transistor, and the fourth active region 40 includes a channel region of an n-type transistor. In this case, since the second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 is located closer to the fourth active region 40 than the third active region 30 , the second The contact surface MI2 is closer to the channel region of the n-type transistor than the channel region of the p-type transistor.

In other words, among the third gate electrodes 320 , the width of the third gate electrode 320 extending on the second field insulating layer 106 is the third overlapping width W21 . That is, the width of the third gate electrode 320 from the second contact surface MI2 to the boundary of the third active region 30 is the third overlapping width W21 .

Among the fourth gate electrodes 420 , the width of the fourth gate electrode 420 extending on the second field insulating layer 106 is the fourth overlapping width W22 . That is, the width of the fourth gate electrode 420 from the second contact surface MI2 to the boundary of the fourth active region 40 is the fourth overlap width W42 .

In FIG. 17 , the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is located closer to the second active region 20 than to the first active region 10 , so The first overlapping width W11 is greater than the second overlapping width W12. In addition, since the second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 is located closer to the fourth active region 40 than the third active region 30 , the third overlap The width W21 is greater than the fourth overlapping width W22.

The width W11 of the first gate electrode 120 overlapping the first field insulating layer 105 is greater than the width W12 of the second gate electrode 220 overlapping the first field insulating layer 105 . The width W21 of the third gate electrode 320 overlapping the second field insulating layer 106 is greater than the width W22 of the fourth gate electrode 420 overlapping the second field insulating layer 106 .

The structures of the third gate electrode 320 and the fourth gate electrode 420 will be described in detail below.

The interlayer insulating layer 190 may include a first trench 50t formed in the first region I and a second trench 70t included in the second region II.

The second trench 70t may cross the third active region 30 , the second field insulating layer 106 , and the fourth active region 40 . That is, the second trench 70t may intersect the third active region 30 and the fourth active region 40 . The second trench 70t may extend long in the fourth direction Y2 .

The first spacers 55 formed in the first region I may define a first trench 50t. The second spacers 75 formed in the second region II may define a second trench 70t. The second spacer 70t may be formed on the substrate 100 . The second spacer 75 may be formed on a sidewall of the second gate electrode structure 70 .

The second gate electrode structure 70 elongates in the fourth direction Y2 . Accordingly, the second gate electrode structure 70 includes a long side extending in the fourth direction Y2 and a short side extending in the third direction X2 .

Although the second spacer 75 is illustrated as being formed on both the sidewall including the long side of the second gate electrode structure 70 and the sidewall including the short side of the second gate electrode structure 70 , the present invention is not limited thereto. .

Since the description of the second spacer 75 may be substantially the same as that of the first spacer 55 , the description thereof will be omitted.

The third gate insulating layer 330 and the fourth gate insulating layer 430 may be formed on the substrate 100 . The third gate insulating layer 330 may be formed on the third active region 30 and the second field insulating layer 106 . The fourth gate insulating layer 430 may be formed on the fourth active region 40 and the second field insulating layer 106 .

The third gate insulating layer 330 and the fourth gate insulating layer 430 may extend along sidewalls and bottom surfaces of the second trench 70t. The third and fourth gate insulating layers 330 and 430 extending along the bottom surface of the second trench 70t form the third active region 30 , the second field insulating layer 106 , and the fourth active region 40 . can cross

The third gate insulating layer 330 and the fourth gate insulating layer 430 may be divided by the second contact surface MI2 of the second gate electrode structure 70 . The first to fourth gate insulating layers 130 , 230 , 330 , and 440 may be formed at the same level.

The third gate insulating layer 330 and the fourth gate insulating layer 430 may each include a high-k insulating layer.

The second gate electrode structure 70 may be formed on the third gate insulating layer 330 and the fourth gate insulating layer 430 . The third gate insulating layer 330 and the fourth gate insulating layer 430 may be formed between the second gate electrode structure 70 and the substrate 100 . The third gate insulating layer 330 and the fourth gate insulating layer 430 may be formed under the second gate electrode structure 70 .

The second gate electrode structure 70 may fill the second trench 70t. A top surface of the second gate electrode structure 70 may be coplanar with a top surface of the second spacer 75 and a top surface of the interlayer insulating layer 190 .

The third gate electrode 320 includes a third lower conductive layer 325 sequentially formed on the third gate insulating layer 330 , a third etch stop layer 324 , a third work function control layer 321 , It may include a third insertion layer 322 and a third peeling layer 323 .

The fourth gate electrode 420 includes a fourth lower conductive layer 425 sequentially formed on the fourth gate insulating layer 430 , a fourth etch stop layer 424 , a fourth work function control layer 421 , and It may include a fourth insertion layer 422 and a fourth peeling layer 423 .

The third lower conductive layer 325 and the fourth lower conductive layer 425 may be formed on the third and fourth gate insulating layers 330 and 430 . The third lower conductive layer 325 may be in contact with the third gate insulating layer 330 , and the fourth lower conductive layer 425 may be in contact with the fourth gate insulating layer 430 .

The third lower conductive layer 325 may be formed on the third active region 30 and the second field insulating layer 106 . The fourth lower conductive layer 425 may be formed on the fourth active region 40 and the second field insulating layer 106 .

The third lower conductive layer 325 and the fourth lower conductive layer 425 may extend along sidewalls and bottom surfaces of the second trench 70t. The third lower conductive layer 325 may extend along the profile of the third gate insulating layer 330 , and the fourth lower conductive layer 425 may extend along the profile of the fourth gate insulating layer 430 .

The third lower conductive layer 325 and the fourth lower conductive layer 425 may be divided by the second contact surface MI1 of the second gate electrode structure 70 .

The first to fourth lower conductive layers 125 , 225 , 325 , and 425 may include the same material.

The third etch stop layer 324 and the fourth etch stop layer 424 may be formed on the third and fourth lower conductive layers 325 and 425 . The third etch stop layer 324 may be formed on the third active region 30 and the second field insulating layer 106 . A fourth etch stop layer 424 may be formed on the fourth active region 40 and the second field insulating layer 106 .

The third etch stop layer 324 and the fourth etch stop layer 424 may extend along sidewalls and bottom surfaces of the second trench 70t. The third etch stop layer 324 may extend along the profile of the third lower conductive layer 325 , and the fourth etch stop layer 424 may extend along the profile of the fourth lower conductive layer 425 .

The third etch stop layer 324 and the fourth etch stop layer 424 may be divided by the second contact surface MI2 of the second gate electrode structure 70 . The first to fourth etch stop layers 124 , 224 , 324 , and 424 may be formed at the same level. Each of the first to fourth etch stop layers 124 , 224 , 324 , and 424 may have substantially the same thickness, but is not limited thereto.

The first to fourth etch stop layers 124 , 224 , 324 , and 424 may include the same material.

The third work function control layer 321 and the fourth work function control layer 421 may be formed on the third and fourth etch stop layers 324 and 424 . The third work function control layer 321 may contact the third etch stop layer 324 , and the fourth work function control layer 421 may contact the fourth etch stop layer 424 .

The third work function control layer 321 may be formed on the third active region 30 and the second field insulating layer 106 . The fourth work function control layer 421 may be formed on the fourth active region 40 and the second field insulating layer 106 . The third work function control layer 321 and the fourth work function control layer 421 may directly contact each other.

The third work function control layer 321 and the fourth work function control layer 421 may extend along sidewalls and bottom surfaces of the second trench 70t. The third work function control layer 321 extends along the profiles of the third gate insulating layer 330 and the third etch stop layer 324 , and the fourth work function control layer 421 includes the fourth gate insulating layer 430 and It may extend along the profile of the fourth etch stop layer 424 .

The first to fourth work function control layers 121 , 221 , 321 , and 421 may include the same material. More specifically, the first to fourth work function control layers 121 , 221 , 321 , and 421 may be the same material layer.

A thickness t31 of the third work function control layer 321 may be different from a thickness t41 of the fourth work function control layer 421 . For example, the thickness t31 of the third work function control layer 321 may be greater than the thickness t41 of the fourth work function control layer 421 .

That is, the thickness t31 of the third work function control layer 321 included in the p-type gate electrode may be greater than the thickness t41 of the fourth work function control layer 421 included in the n-type gate electrode. For example, the thickness t31 of the third work function control layer 321 is the thickness on the third active region 30 , and the thickness t41 of the fourth work function control layer 421 is the fourth active region. It may be the thickness on (40), but is not limited thereto.

In the semiconductor device according to some embodiments of the present disclosure, the difference between the thickness t31 of the third work function control layer 321 and the thickness t41 of the fourth work function control layer 421 is the first work function control layer. It may be greater than or equal to a difference between the thickness t11 of the layer 121 and the thickness t21 of the second work function control layer 221 .

The second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 is defined between the third work function control layer 321 and the fourth work function control layer 421 having different thicknesses. do. That is, the second gate electrode along the normal line of the substrate 100 with a boundary between the third work function control layer 321 and the fourth work function control layer 421 extending on the second field insulating layer 106 . When the structure 70 is cut, it becomes the second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 .

In FIG. 18 , the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is located closer to the second active region 20 than to the first active region 10 , so the The overlapping width W11 of the 1 work function control layer 121 and the first field insulating layer 105 is greater than the overlapping width W12 of the second work function control layer 221 and the first field insulating layer 105 . .

In addition, since the second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 is located closer to the fourth active region 40 than the third active region 30 , the third work The overlapping width W21 of the function control layer 321 and the second field insulating layer 106 is greater than the overlapping width W22 of the fourth work function control layer 421 and the second field insulating layer 106 .

In addition, since the first active region 10 , the first center line CL1 , the first contact surface MI1 , and the second active region 20 are arranged in this order, the second work function control layer 221 is formed in the first field It does not overlap the first center line CL1 of the insulating layer 105 . Since the third active region 30 , the second center line CL2 , the second contact surface MI2 , and the fourth active region 40 are arranged in this order, the fourth work function control layer 421 is formed by the second field insulating layer ( It does not overlap with the second center line CL2 of 106 .

The third and fourth intercalation layers 322 and 422 may be formed on the third and fourth work function control layers 321 and 421 . The third interposing layer 322 and the fourth interposing layer 422 may directly contact each other.

The third insertion layer 322 may be formed on the third active region 30 and the second field insulating layer 106 . The fourth insertion layer 422 may be formed on the fourth active region 40 and the second field insulating layer 106 .

The third insertion layer 322 and the fourth insertion layer 422 may extend along sidewalls and bottom surfaces of the second trench 70t. The third and fourth intercalation layers 322 and 422 may extend along profiles of the third and fourth work function control layers 321 and 421 in direct contact with each other.

The third insertion layer 322 and the fourth insertion layer 422 may be divided by the second contact surface MI2 of the second gate electrode structure 70 . The first to fourth insertion layers 122 , 222 , 322 , and 422 may be formed at the same level.

A thickness t12 of the first insertion layer 122 may be substantially the same as a thickness t22 of the second insertion layer 222 . A thickness t32 of the third interposing layer 322 may be substantially the same as a thickness t42 of the fourth interposing layer 422 . A thickness t12 of the first interlayer 122 may be substantially the same as a thickness t32 of the third interlayer 322 .

The first to fourth insertion layers 122 , 222 , 322 , and 422 may include the same material.

In the semiconductor device according to some embodiments of the present invention, the first to fourth interposed layers 122 , 222 , 322 , and 422 will be described as a layer including TiAl.

The third filling layer 323 and the fourth filling layer 423 may be formed on the third and fourth insertion layers 322 and 422 . The third peeling layer 323 and the fourth peeling layer 423 may directly contact each other.

The third filling layer 323 may be formed on the third active region 30 and the second field insulating layer 106 . The fourth filling layer 423 may be formed on the fourth active region 40 and the second field insulating layer 106 .

The third filling layer 323 and the fourth filling layer 423 may be divided by the second contact surface MI2 of the second gate electrode structure 70 . The first to fourth filling layers 123 , 223 , 323 , and 423 may be formed at the same level.

The first to fourth filling layers 123 , 223 , 323 , and 423 may include the same material.

The third interposed layer 322 and the third filling layer 323 on the third work function control layer 321 may be the third upper gate electrode, and the fourth interposed layer ( 322 ) on the fourth work function control layer 421 . 422 and the fourth filling layer 423 may be a fourth upper gate electrode.

The thickness h3 of the third upper gate electrodes 322 and 323 is the distance from the top surface of the interlayer insulating layer 190 to the third work function control layer 321 on the bottom surface of the second trench 70t, and the fourth The thickness h4 of the upper gate electrodes 422 and 423 may be a distance from the top surface of the interlayer insulating layer 190 to the fourth work function control layer 421 on the bottom surface of the second trench 70t.

In this case, on the first field insulating layer 105 , the thickness h3 of the third upper gate electrodes 322 and 323 may be different from the thickness h4 of the fourth upper gate electrodes 422 and 423 . For example, the thickness h3 of the third upper gate electrodes 322 and 323 may be smaller than the thickness h4 of the fourth upper gate electrodes 422 and 423 .

19 is a diagram for describing a semiconductor device according to some embodiments of the present invention. For convenience of description, descriptions will be made mainly of things different from those described with reference to FIGS. 17 and 18 .

Referring to FIG. 19 , in the semiconductor device according to some embodiments of the present disclosure, the fourth gate electrode 420 includes a fourth lower conductive layer 425 sequentially formed on the fourth gate insulating layer 430 , and a fourth It may include an etch stop layer 424 , a fourth insertion layer 422 , and a fourth peeling layer 423 .

The fourth etch stop layer 424 may contact the fourth interlayer 422 on the fourth etch stop layer 424 .

In addition, in the third gate electrode 320 , the third work function control layer 321 may contact the third interposed layer 322 on the third work function control layer 321 .

Since the fourth gate electrode 420 does not include a work function control layer including TiN between the fourth etch stop layer 424 and the fourth insertion layer 422 , the third gate electrode 320 and the fourth gate electrode The second contact surface MI2 between the 420 may be positioned at an end of the third work function control layer 321 extending on the second field insulating layer 106 .

20 is a diagram for describing a semiconductor device according to some embodiments of the present invention. For convenience of description, descriptions will be made mainly of things different from those described with reference to FIGS. 17 and 18 .

Referring to FIG. 20 , in the semiconductor device according to some embodiments of the present invention, the first work function control layer 121 is in contact with the first gate insulating layer 130 , and the second work function control layer 221 is the second work function control layer 221 . 2 may be in contact with the gate insulating layer 230 .

Also, the third work function control layer 321 may contact the third gate insulating layer 330 , and the fourth work function control layer 421 may contact the fourth gate insulating layer 430 .

21 is a plan view illustrating a semiconductor device according to some embodiments of the present invention. 22 is a plan view illustrating a semiconductor device according to some embodiments of the present invention. For convenience of description, descriptions will be made mainly of things different from those described with reference to FIGS. 17 and 18 .

Referring to FIG. 21 , in the semiconductor device according to some embodiments of the present disclosure, a width W21 at which the third gate electrode 320 and the second field insulating layer 106 overlap is the fourth gate electrode 420 and the second field insulating layer 106 . The overlapping width W22 of the two field insulating layers 106 may be substantially the same.

In other words, the second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 may coincide with the second center line CL2 of the second field insulating layer 106 .

The second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 may be spaced apart from the third active region 30 and the fourth active region 40 by the same distance.

Since the second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 is located at the same distance from the third active region 30 and the fourth active region 40 , the second contact surface ( MI2) may be spaced apart by the same distance from the channel region of the p-type transistor and the channel region of the n-type transistor.

Referring to FIG. 22 , the overlapping width W21 of the third gate electrode 320 and the second field insulating layer 106 is the overlapping width W22 of the fourth gate electrode 420 and the second field insulating layer 106 . ) may be smaller than

The second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 may be positioned adjacent to the fourth active region 40 and the third active region 30 .

Since the second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 is located closer to the third active region 30 than the fourth active region 40 , the second contact surface MI2 ) is closer to the channel region of the p-type transistor than the channel region of the n-type transistor.

That is, in the first region I, the first contact surface MI1 between the first gate electrode 120 and the second gate electrode 220 is closer to the channel region of the n-type transistor than the channel region of the p-type transistor, In the second region II, the second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 may be closer to the channel region of the p-type transistor than the channel region of the n-type transistor.

23 is a plan view illustrating a semiconductor device according to some embodiments of the present invention. 24 is a cross-sectional view taken along lines A - A and D - D of FIG. 23 .

The first fin-shaped pattern 110 , the second fin-shaped pattern 210 , and the first gate electrode structure 50 shown in the first region I of FIGS. 23 and 24 are shown in FIGS. 1 to 3B , 8 and 8 . Since it is substantially the same as that described with reference to reference numeral 9, the contents shown in the second region II will be mainly described with reference to FIGS. 23 and 24 .

In addition, since the second gate electrode structure 70 illustrated in FIGS. 23 and 24 in the second region II is substantially the same as that described with reference to FIGS. 17 and 18 , overlapping content will be briefly described or omitted. do.

23 and 24 , in the semiconductor device according to some embodiments of the present invention, a first fin-shaped pattern 110 formed in the first region I and a second fin-shaped pattern adjacent to the first fin-shaped pattern 110 are provided. The pattern 210 may include a third fin-shaped pattern 310 formed in the second region II and a fourth fin-shaped pattern 410 adjacent to the third fin-shaped pattern 310 .

For example, the first fin-shaped pattern 110 and the second fin-shaped pattern 210 are formed in the SRAM region, and the third fin-shaped pattern 310 and the fourth fin-shaped pattern 410 are formed in the logic region or the I/O region. can be formed.

The third fin-shaped pattern 310 and the fourth fin-shaped pattern 410 may protrude from the substrate 100 . The third fin-shaped pattern 310 and the fourth fin-shaped pattern 410 may each extend in the third direction X2 .

The third fin-shaped pattern 310 may be used as a channel region of the PMOS, and the fourth fin-shaped pattern 410 may be used as a channel region of the NMOS.

The third fin-shaped pattern 310 and the fourth fin-shaped pattern 410 may be a part of the substrate 100 and may include an epitaxial layer grown from the substrate 100 .

Each of the third fin-shaped pattern 310 and the fourth fin-shaped pattern 410 may include, for example, silicon or germanium, which is an elemental semiconductor material. In addition, each of the third fin-shaped pattern 310 and the fourth fin-shaped pattern 410 may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. .

Since the second field insulating layer 106 covers a portion of the sidewall of the third fin-shaped pattern 310 and a portion of the sidewall of the fourth fin-shaped pattern 410 , the third fin-shaped pattern 310 and the fourth fin-shaped pattern 410 . ) may protrude above the top surface of the second field insulating layer 106 formed on the substrate 100 .

A fin-shaped pattern protruding above the upper surface of the second field insulating layer 106 may not be formed between the third fin-shaped pattern 310 and the fourth fin-shaped pattern 410 .

The second gate electrode structure 70 may cross the third fin-shaped pattern 310 , the fourth fin-shaped pattern 410 , and the second field insulating layer 106 . The second gate electrode structure 70 may extend long in the fourth direction Y2 .

The second contact surface MI2 of the second gate electrode structure 70 crossing the third fin-shaped pattern 310 and the fourth fin-shaped pattern 410 is at the fourth fin-shaped pattern 410 rather than the third fin-shaped pattern 310 . can be close

A width W21 at which the third gate electrode 320 formed on the third fin-shaped pattern 310 and the second field insulating layer 106 overlap each other is the fourth gate electrode 420 formed on the fourth fin-shaped pattern 410 . and the width W22 at which the second field insulating layer 106 overlaps.

The third gate insulating layer 330 may be formed on the second field insulating layer 106 and the third fin-shaped pattern 310 . The third gate insulating layer 330 may be formed along the top surface of the second field insulating layer 106 and the profile of the third fin-shaped pattern 310 .

The fourth gate insulating layer 430 may be formed on the second field insulating layer 106 and the fourth fin-shaped pattern 410 . The fourth gate insulating layer 430 may be formed along the top surface of the second field insulating layer 106 and the profile of the fourth fin-shaped pattern 410 .

The third and fourth gate insulating layers 330 and 430 extending along the bottom surface of the second trench 70t have the profile of the third fin-shaped pattern 310 , the top surface of the second field insulating layer 106 , and the fourth fin-shaped pattern. It may be formed along the profile of 410 .

The second gate electrode structure 70 may be formed on the third and fourth gate insulating layers 330 and 430 .

The third gate electrode 320 may be formed on the third gate insulating layer 330 and intersect the third fin-shaped pattern 310 . The fourth gate electrode 420 is formed on the fourth gate insulating layer 430 and may cross the fourth fin-shaped pattern 410 .

Each of the third lower conductive layer 325 , the third etch stop layer 324 , the third work function control layer 321 , and the third interposed layer 322 has a profile of the third gate insulating layer 330 . Thus, it can be formed.

In other words, each of the third lower conductive layer 325 , the third etch stop layer 324 , the third work function control layer 321 , and the third insert layer 322 includes the third fin-shaped pattern 310 . ) and the top surface of the second field insulating layer 106 .

Each of the fourth lower conductive layer 425 , the fourth etch stop layer 424 , the fourth work function control layer 421 , and the fourth interposer layer 422 has a profile of the fourth gate insulating layer 430 . Thus, it can be formed.

Each of the fourth lower conductive layer 425 , the fourth etch stop layer 424 , the fourth work function control layer 421 , and the fourth interlayer layer 422 has a profile of the fourth fin-shaped pattern 410 and It may extend along the top surface of the second field insulating layer 106 .

The third and fourth work function control layers 321 and 421 extending along the bottom surface of the second trench 70t have the profile of the third fin-shaped pattern 310 , the top surface of the second field insulating layer 106 , and the fourth work function control layer 106 . It may extend continuously along the profile of the fin-shaped pattern 410 .

In FIG. 25 , a thickness t31 of the third work function control layer 321 may be greater than a thickness t41 of the fourth work function control layer 421 . However, the thickness t32 of the third interposing layer 322 may be substantially the same as the thickness t42 of the fourth interposing layer 422 .

The second contact surface MI2 of the second gate electrode structure 70 is defined at a boundary between the third work function control layer 321 and the fourth work function control layer 421 . Accordingly, the overlapping width W21 of the third work function control layer 321 and the second field insulating layer 106 formed along the profile of the third fin-shaped pattern 310 is along the profile of the fourth fin-shaped pattern 410 . The width W22 at which the formed fourth work function control layer 421 and the second field insulating layer 106 overlap is larger than the overlapping width W22 .

The thickness h3 of the third upper gate electrodes 322 and 323 from the top surface of the interlayer insulating layer 190 to the third work function control layer 321 is from the top surface of the interlayer insulating layer 190 to the fourth work function control layer 321 . It may be smaller than the thickness h4 of the fourth upper gate electrodes 422 and 423 up to 421 .

25 is a diagram for describing a semiconductor device according to some embodiments of the present invention. For convenience of description, the points different from those described with reference to FIGS. 23 and 24 will be mainly described.

Referring to FIG. 25 , the third gate electrode 320 includes a third work function regulating layer 321 on the third gate insulating layer 330 and in contact with the third gate insulating layer 330 , and a third work function regulating layer on the third gate insulating layer 330 . A third insertion layer 322 on the 321 and a third peeling layer 323 on the third insertion layer 322 may be included.

The fourth gate electrode 420 includes a fourth work function control layer 421 on the fourth gate insulating layer 430 and in contact with the fourth gate insulating layer 430 , and a fourth work function control layer 421 on the fourth work function control layer 421 . It may include an insertion layer 422 and a fourth peeling layer 423 on the fourth insertion layer 422 .

26 is a plan view for explaining a semiconductor device according to some embodiments of the present invention. 27 is a cross-sectional view taken along lines A - A and D - D of FIG. 26 . For convenience of description, the points different from those described with reference to FIGS. 11 and 12 will be mainly described.

The first active region 10 , the second active region 20 , and the first gate electrode structure 50 shown in the first region I of FIGS. 26 and 27 are the same as those described with reference to FIGS. 11 and 12 . Since they are substantially the same, FIGS. 26 and 27 will be mainly described with reference to the contents shown in the second area II.

26 and 27 , a semiconductor device according to some embodiments of the present invention includes a substrate 100 including a first region (I) and a second region (II), and a substrate formed in the first region (I). It may include a first gate electrode structure 50 and a second gate electrode structure 70 formed in the second region II.

The substrate 100 includes a first active region 10 , a second active region 20 , a third active region 30 , a fourth active region 40 , a first field insulating layer 105 , and a second field insulating layer ( 106) may be included.

The first region I and the second region II may be regions in which devices having different functions are formed. For example, the first region I may be an SRAM region, and the second region II may be a logic region or an I/O region.

The substrate 100 of the first region I may include a first active region 10 , a second active region 20 , and a first field insulating layer 105 .

The substrate 100 of the second region II may include a third active region 30 , a fourth active region 40 , and a second field insulating layer 106 .

The third active region 30 is a region in which a PMOS is formed, and the fourth active region 40 is a region in which an NMOS is formed.

The second field insulating layer 106 may be disposed between the third active region 30 and the fourth active region 40 , and may directly contact the third active region 30 and the fourth active region 40 . The second field insulating layer 106 includes a second center line CL2 positioned at the same distance from the third active region 30 and the fourth active region 40 .

The second gate electrode structure 70 may be formed on the substrate 100 in the second region II. The second gate electrode structure 70 may cross the third active region 30 , the fourth active region 40 , and the second field insulating layer 106 . The second gate electrode structure 70 may extend long in the fourth direction Y2 .

The second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 may be located closer to the third active region 30 than the fourth active region 40 .

Since the third active region 30 , the second contact surface MI2 , the second center line CL2 , and the fourth active region 40 are arranged in this order, the third gate electrode 320 is formed by the second field insulating layer 106 . does not overlap with the second center line CL2 of

The second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 is located closer to the third active region 30 than the fourth active region 40 . Accordingly, the width W21 of the third gate electrode 320 overlapping the second field insulating layer 106 is smaller than the width W22 of the fourth gate electrode 420 overlapping the second field insulating layer 106 . .

The third gate electrode 320 includes a third lower conductive layer 325 sequentially formed on the third gate insulating layer 330 , a third etch stop layer 324 , a third work function control layer 321 , It may include a third insertion layer 322 and a third peeling layer 323 .

The fourth gate electrode 420 includes a fourth lower conductive layer 425 sequentially formed on the fourth gate insulating layer 430 , a fourth etch stop layer 424 , a fourth work function control layer 421 , and It may include a fourth insertion layer 422 and a fourth peeling layer 423 .

The description of the third gate electrode 320 and the fourth gate electrode 420 is substantially the same as the description of the first gate electrode 120 and the second gate electrode 220 , and thus will be omitted below.

In addition, it is obvious that the first to fourth active regions 10 , 20 , 30 , and 40 may be, for example, multi-channel active patterns such as fin-type patterns.

Unlike the illustration, the second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 may be located closer to the fourth active region 40 than the third active region 30 . have. Alternatively, the second contact surface MI2 between the third gate electrode 320 and the fourth gate electrode 420 is defined at a position spaced apart from the third active region 30 and the fourth active region 40 by the same distance. it might be

1 to 27 , a first work function control layer 121 and a second work function control layer 221 having different thicknesses, and a third work function control layer 321 and a fourth work function control layer 221 having different thicknesses The work function control layer 421 may be formed by patterning the TiN layer at least once.

The first region I including the first work function regulating film 121 and the second work function regulating film 221 , and the third work function regulating film 321 and the fourth work function regulating film 421 are formed. The included second region II may be a region having different functions.

It will be described that the first region I is an SRAM region, and the second region II is a logic region.

In this case, depending on the process of forming the transistor included in the first region (I), when the boundary between the n-type gate electrode and the p-type gate electrode is close to the channel region of the n-type transistor, each other gate electrode structure Threshold voltages of n-type transistors and p-type transistors that share a can be improved.

Alternatively, when the boundary between the n-type gate electrode and the p-type gate electrode is close to the channel region of the p-type transistor, the threshold voltages of the n-type transistor and the p-type transistor sharing the gate electrode structure with each other may be improved.

Meanwhile, according to the process of forming the transistor included in the second region II in which the logic element is formed, when the boundary between the n-type gate electrode and the p-type gate electrode approaches the channel region of the n-type transistor, each other Threshold voltages of n-type transistors and p-type transistors sharing the gate electrode structure can be improved.

Alternatively, when the boundary between the n-type gate electrode and the p-type gate electrode is close to the channel region of the p-type transistor, the threshold voltages of the n-type transistor and the p-type transistor sharing the gate electrode structure with each other may be improved.

Alternatively, when the boundary between the n-type gate electrode and the p-type gate electrode is in the middle between the channel region of the p-type transistor and the channel region of the n-type transistor, the n-type transistor and the p-type transistor sharing a gate electrode structure with each other The threshold voltage can be improved.

The boundary between the n-type gate electrode and the p-type gate electrode may change in regions having different functions depending on what materials are included in the n-type gate electrode and the p-type gate electrode.

Alternatively, the boundary between the n-type gate electrode and the p-type gate electrode in regions having different functions may be changed according to a large or small gap between the channel region of the p-type transistor and the channel region of the n-type transistor.

In addition, depending on which process method is used to manufacture the n-type gate electrode and the p-type gate electrode, the boundary between the n-type gate electrode and the p-type gate electrode may change in regions having different functions.

28 is a block diagram of an SoC system including a semiconductor device according to embodiments of the present invention.

Referring to FIG. 28 , the SoC system 1000 includes an application processor 1001 and a DRAM 1060 .

The application processor 1001 may include a central processing unit 1010 , a multimedia system 1020 , a bus 1030 , a memory system 1040 , and a peripheral circuit 1050 .

The central processing unit 1010 may perform an operation necessary for driving the SoC system 1000 . In some embodiments of the present invention, the central processing unit 1010 may be configured as a multi-core environment including a plurality of cores.

The multimedia system 1020 may be used to perform various multimedia functions in the SoC system 1000 . The multimedia system 1020 may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, and the like. .

The bus 1030 may be used for data communication between the central processing unit 1010 , the multimedia system 1020 , the memory system 1040 , and the peripheral circuit 1050 . In some embodiments of the present invention, such bus 1030 may have a multi-layer structure. Specifically, as an example of the bus 1030, a multi-layer AHB (multi-layer Advanced High-performance Bus) or a multi-layer AXI (multi-layer Advanced eXtensible Interface) may be used, but the present invention is not limited thereto.

The memory system 1040 may provide an environment necessary for the application processor 1001 to be connected to an external memory (eg, the DRAM 1060 ) to operate at a high speed. In some embodiments of the present invention, the memory system 1040 may include a separate controller (eg, a DRAM controller) for controlling an external memory (eg, the DRAM 1060).

The peripheral circuit 1050 may provide an environment necessary for the SoC system 1000 to be smoothly connected to an external device (eg, a main board). Accordingly, the peripheral circuit 1050 may include various interfaces that allow an external device connected to the SoC system 1000 to be compatible.

The DRAM 1060 may function as a working memory required for the application processor 1001 to operate. In some embodiments of the present invention, the DRAM 1060 may be disposed outside the application processor 1001 as shown. Specifically, the DRAM 1060 may be packaged with the application processor 1001 in the form of a package on package (PoP).

At least one of the components of the SoC system 1000 may include at least one of the semiconductor devices according to the embodiments of the present invention described above.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains can realize that the present invention can be embodied in other specific forms without changing the technical spirit or essential features. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

10, 20, 30, 40: active region 50, 70: gate structure
105, 106: field insulating film 110, 210, 310, 410: fin-shaped pattern
120, 220, 320, 420: gate electrodes 121, 221, 321, 421: work function control layer
CL: center line of the field insulating film
MI: the contact surface of the n-type gate electrode and the p-type gate electrode

Claims (20)

a substrate comprising a first active region, a second active region, and a first field insulating layer in direct contact between the first active region and the second active region; and
a first gate electrode structure crossing the first active region, the second active region, and the first field insulating layer on the substrate;
The first gate electrode structure includes a first p-type gate electrode and a first n-type gate electrode in direct contact with each other,
the first p-type gate electrode includes a first work function control layer on the first active region and the first field insulating layer, and a first upper gate electrode on the first work function control layer;
the first n-type gate electrode includes a second work function regulating film on the second active region and the first field insulating film, and a second upper gate electrode on the second work function regulating film,
The first work function regulating film and the second work function regulating film are in direct contact with each other and are the same material film,
The thickness of the first work function control layer is different from the thickness of the second work function control layer,
The overlapping width of the first p-type gate electrode and the first field insulating layer is different from the overlapping width of the first n-type gate electrode and the first field insulating layer. The method of claim 1,
A thickness of the first work function control layer is greater than a thickness of the second work function control layer. The method of claim 1,
An overlapping width of the first p-type gate electrode and the first field insulating layer is greater than an overlapping width of the first n-type gate electrode and the first field insulating layer. The method of claim 1,
An overlapping width of the first p-type gate electrode and the first field insulating layer is smaller than an overlapping width of the first n-type gate electrode and the first field insulating layer. The method of claim 1,
The first active region and the second active region are included in an SRAM region. The method of claim 1,
The substrate includes a first region and a second region having different functions,
The first active region and the second active region are formed in the first region,
The substrate of the second region includes a third active region, a fourth active region, and a second field insulating film in direct contact between the third active region and the fourth active region,
a second gate electrode structure crossing the third active region, the fourth active region, and the second field insulating layer on the substrate;
The second gate electrode structure includes a second p-type gate electrode and a second n-type gate electrode in direct contact with each other,
the second p-type gate electrode is formed on the third active region and the second field insulating layer;
The second n-type gate electrode is formed on the fourth active region and the second field insulating layer. 7. The method of claim 6,
A contact surface of the second p-type gate electrode and the second n-type gate electrode is closer to the fourth active region than the third active region. 7. The method of claim 6,
The overlapping width of the second p-type gate electrode and the second field insulating layer is substantially the same as the overlapping width of the second n-type gate electrode and the second field insulating layer. 7. The method of claim 6,
A contact surface of the second p-type gate electrode and the second n-type gate electrode is closer to the third active region than the fourth active region. The method of claim 1,
The first work function control layer and the second work function control layer are each a TiN layer. a first fin-shaped pattern and a second fin-shaped pattern adjacent to each other;
a first field insulating layer between the first fin-shaped pattern and the second fin-shaped pattern and covering a portion of the first fin-shaped pattern and the second fin-shaped pattern;
a first gate electrode structure intersecting the first fin-shaped pattern, the first field insulating layer, and the second fin-shaped pattern;
The first gate electrode structure includes a first p-type gate electrode and a first n-type gate electrode in direct contact with each other,
the first p-type gate electrode includes a first work function control layer on the first fin pattern and the first field insulating layer, and a first upper gate electrode on the first work function control layer;
the first n-type gate electrode includes a second work function control layer on the second fin pattern and the first field insulating layer, and a second upper gate electrode on the second work function control layer;
The first work function regulating film and the second work function regulating film are in direct contact with each other and are the same material film,
The thickness of the first work function control layer is thicker than the thickness of the second work function control layer,
An overlapping width of the first p-type gate electrode and the first field insulating layer is greater than an overlapping width of the first n-type gate electrode and the first field insulating layer. 12. The method of claim 11,
A contact surface between the first p-type gate electrode and the first n-type gate electrode is closer to the second fin-type pattern than the first fin-type pattern. 12. The method of claim 11,
a gate insulating layer extending under the first gate electrode structure along the profile of the first fin-shaped pattern, the upper surface of the first field insulating layer, and the profile of the second fin-shaped pattern;
The first gate electrode structure further includes a TiN film extending along the gate insulating film on the gate insulating film, and a TaN film on the TiN film,
The first work function control layer and the second work function control layer contact the TaN layer on the TaN layer, respectively. 12. The method of claim 11,
a gate insulating layer extending under the first gate electrode structure along the profile of the first fin-shaped pattern, the upper surface of the first field insulating layer, and the profile of the second fin-shaped pattern;
The first work function control layer and the second work function control layer contact the gate insulating layer, respectively. 12. The method of claim 11,
a third fin-shaped pattern and a fourth fin-shaped pattern adjacent to each other;
a second field insulating layer between the third fin-shaped pattern and the fourth fin-shaped pattern and covering a portion of the third fin-shaped pattern and the fourth fin-shaped pattern;
a second gate electrode structure crossing the third fin-shaped pattern, the second field insulating layer, and the fourth fin-shaped pattern;
The second gate electrode structure includes a second p-type gate electrode and a second n-type gate electrode in direct contact with each other,
A contact surface of the second p-type gate electrode and the second n-type gate electrode is closer to the fourth fin pattern than the third fin pattern. 16. The method of claim 15,
The first fin-shaped pattern and the second fin-shaped pattern are formed in an SRAM region, and the third fin-shaped pattern and the fourth fin-shaped pattern are formed in a logic region. a substrate comprising a first active region, a second active region, and a field insulating layer in direct contact between the first active region and the second active region;
an interlayer insulating layer on the substrate, the interlayer insulating layer including a trench crossing the first active region, the field insulating layer, and the second active region;
a gate insulating layer extending along sidewalls and bottom surfaces of the trench; and
a gate electrode structure filling the trench on the gate insulating layer and crossing the first active region, the second active region, and the field insulating layer;
The gate electrode structure includes a p-type gate electrode and an n-type gate electrode in direct contact with each other,
the p-type gate electrode extends over the first active region and the field insulating layer, and the n-type gate electrode extends over the second active region and the field insulating layer;
the p-type gate electrode includes a first TiN film extending along the gate insulating film, and a first upper gate electrode on the first TiN film;
the n-type gate electrode includes a second TiN film extending along the gate insulating film and in direct contact with the first TiN film, and a second upper gate electrode on the second TiN film,
a thickness of the first upper gate electrode on the field insulating layer is smaller than a thickness of the second upper gate electrode on the field insulating layer;
The overlapping width of the first TiN layer and the field insulating layer is different from the overlapping width of the second TiN layer and the field insulating layer. 18. The method of claim 17,
A thickness of the first TiN layer is greater than a thickness of the second TiN layer. 18. The method of claim 17,
The overlapping width of the first TiN layer and the field insulating layer is greater than the overlapping width of the second TiN layer and the field insulating layer. 18. The method of claim 17,
The overlapping width of the first TiN layer and the field insulating layer is smaller than the overlapping width of the second TiN layer and the field insulating layer.

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