KR102411345B1 - Organic light emitting display device - Google Patents

Abstract

An organic light emitting display device according to the present invention includes a substrate having a display area and a non-display area defined, signal lines disposed in the display area, pads disposed in the non-display area, and corresponding pads disposed in the non-display area and link lines connecting the signal lines and the pads and having different lengths, and an auxiliary dielectric layer locally disposed on the link lines.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

The present invention relates to an organic light emitting display device.

Various display devices capable of reducing weight and volume, which are disadvantages of a cathode ray tube, are being developed. Such display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting display device (OLED). ) can be implemented as

Among these display devices, the organic light emitting display device is a self-luminous display device that emits light by excitation of an organic compound, and it does not require a backlight used in LCDs, so it can be lightweight and thin and has the advantage of simplifying the process. In addition, the organic light emitting display device is widely used in that it can be manufactured at a low temperature, has a high response speed with a response speed of 1 ms or less, and has characteristics such as low power consumption, wide viewing angle, and high contrast. have.

The organic light emitting diode display includes a display area in which pixels are arranged and a non-display area outside the display area. Pixels may be defined by an intersection structure of a gate line and a data line. Each of the pixels includes an Organic Light Emitting Diode that converts electrical energy into light energy. The organic light emitting diode includes an anode, a cathode, and an organic compound layer disposed therebetween. In the organic light emitting display device, holes and electrons respectively injected from an anode and a cathode combine in an emission layer to form excitons, which are excitons, and the formed excitons are converted from an excited state to a ground state. As it falls, it emits light to display an image.

The non-display area includes gate link lines and data link lines. The gate link lines receive a gate signal from a gate IC (Gate-Integrated Circuit) and transmit it to the gate line of the display area. The data link lines receive a data signal from a source-integrated circuit (IC) and supply it to the data line of the display area.

Recently, in order to improve the aesthetics and image immersion of the display device, efforts to minimize the bezel have been made. Due to design constraints for implementing the narrow bezel, the above-mentioned link lines need to be designed to be integrated in a narrow area. As part of that, the link lines may be formed to have different lengths depending on the location. In this case, there is a difference in the resistance and capacitance values between the link lines, so that the difference in the RC delay level between the link lines is reduced. will occur In this case, a problem may occur in image quality such as a decrease in luminance uniformity in the display panel, and a method for improving this may be required.

SUMMARY OF THE INVENTION An object of the present invention is to provide an organic light emitting diode display having improved display quality.

An organic light emitting display device according to the present invention includes a substrate having a display area and a non-display area defined, signal lines disposed in the display area, pads disposed in the non-display area, and corresponding pads disposed in the non-display area and link lines connecting the signal lines and the pads and having different lengths, and an auxiliary dielectric layer locally disposed on the link lines.

An organic light emitting diode display according to the present invention includes a substrate having a display area and a non-display area defined thereon, signal lines disposed in the display area, pads disposed in the non-display area, and corresponding electrodes disposed in the non-display area and link lines connecting the signal lines and the pads and having different lengths, and a dielectric layer extending from the link lines to the display area and the non-display area. The dielectric layer includes a portion having a locally thick thickness on the link line compared to other regions.

The present invention can improve the RC deviation between link lines having different lengths by reducing the parasitic capacitance generated therebetween. Accordingly, it is possible to provide an organic light emitting diode display with significantly improved display quality.

1 is a schematic block diagram of an organic light emitting diode display.
2 and 3 are diagrams schematically illustrating the pixel illustrated in FIG. 1 .
4 is a plan view illustrating an organic light emitting display device according to a first exemplary embodiment of the present invention.
FIG. 5 is an enlarged plan view of the AR region of FIG. 4 .
6 is a view for explaining a problem of the related art.
7 is a cross-sectional view schematically illustrating a sub-pixel structure in a display area according to a first exemplary embodiment of the present invention.
8 is a diagram schematically illustrating a stacked structure of a link unit in a non-display area according to a first exemplary embodiment of the present invention.
9 is a view for explaining the effect according to the first embodiment of the present invention.
10 is a cross-sectional view schematically illustrating a sub-pixel structure in a display area according to a second exemplary embodiment of the present invention.
11 to 13 are views schematically illustrating a stacked structure of a link unit in a non-display area according to a second exemplary embodiment of the present invention.
14A is a cross-sectional view schematically illustrating a stacked structure in a display area according to a third exemplary embodiment of the present invention.
14B is a cross-sectional view schematically illustrating a stacked structure of a link unit in a non-display area according to a third exemplary embodiment of the present invention.
15 is a plan view illustrating an organic light emitting display device according to a first exemplary embodiment of the present invention.
16 is an enlarged plan view of the AR region of FIG. 15 .
17 is an enlarged plan view of the AR region of FIG. 4 .
18 is an enlarged plan view of the AR region of FIG. 4 according to a fifth embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In describing various embodiments, the same components are representatively described in the introduction and may be omitted in other embodiments.

Terms including an ordinal number such as 1st, 2nd, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

1 is a schematic block diagram of an organic light emitting diode display. 2 and 3 are diagrams schematically illustrating the pixel illustrated in FIG. 1 .

Referring to FIG. 1 , the organic light emitting display device includes an image processor 10 , a timing controller 20 , a data driver 30 , a gate driver 40 , and a display panel 50 .

The image processing unit 10 outputs a data enable signal DE along with the data signal DATA supplied from the outside. The image processing unit 10 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of description. The image processing unit 10 is formed in the form of an IC (Integrated Circuit) on the system circuit board.

The timing controller 20 receives the data signal DATA from the image processing unit 10 as well as a driving signal including a data enable signal DE or a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

The timing controller 20 includes a gate timing control signal GDC for controlling an operation timing of the gate driver 40 and a data timing control signal DDC for controlling an operation timing of the data driver 30 based on the driving signal. to output The timing controller 20 is formed in the form of an IC on the control circuit board.

The data driver 30 samples and latches the data signal DATA supplied from the timing controller 20 in response to the data timing control signal DDC supplied from the timing controller 20 , converts it into a gamma reference voltage, and outputs it . The data driver 30 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 30 is attached to the substrate in the form of an IC.

The gate driver 40 outputs a gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 20 . The gate driver 40 outputs a gate signal through the gate lines GL1 to GLm. The gate driver 40 is formed in the form of an IC on the gate circuit board or in the form of a gate in panel on the display panel 50 .

The display panel 50 displays an image in response to the data signal DATA and the gate signal supplied from the data driver 30 and the gate driver 40 . The display panel 50 includes sub-pixels SP displaying an image.

Referring to FIG. 2 , one sub-pixel includes a switching transistor SW, a driving transistor DR, a compensation circuit CC, and an organic light emitting diode (OLED). The organic light emitting diode OLED operates to emit light according to a driving current formed by the driving transistor DR.

The switching transistor SW performs a switching operation such that the data signal supplied through the first data line DL1 is stored as a data voltage in the capacitor in response to the gate signal supplied through the first gate line GL1 . The driving transistor DR operates so that a driving current flows between the high potential power line VDD and the low potential power line GND according to the data voltage stored in the capacitor. The compensation circuit CC is a circuit for compensating the threshold voltage of the driving transistor DR. Also, a capacitor connected to the switching transistor SW or the driving transistor DR may be located inside the compensation circuit CC.

The compensation circuit CC is composed of one or more thin film transistors and a capacitor. The configuration of the compensation circuit CC varies greatly depending on the compensation method, and detailed examples and descriptions thereof will be omitted.

In addition, as shown in FIG. 3 , when the compensation circuit CC is included, the sub-pixel further includes a signal line and a power supply line for driving the compensation thin film transistor and supplying a specific signal or power. The added signal line may be defined as the first-second gate line GL1b for driving the compensation thin film transistor included in the sub-pixel. In addition, the added power line may be defined as an initialization power line INIT for initializing a specific node of the sub-pixel to a specific voltage. However, this is only an example and is not limited thereto.

Meanwhile, in FIGS. 2 and 3 , the compensation circuit CC is included in one sub-pixel as an example. However, when the subject of compensation is located outside the sub-pixel, such as the data driver 30 , the compensation circuit CC may be omitted. That is, one sub-pixel is basically composed of a 2T (Transistor) 1C (Capacitor) structure including a switching transistor (SW), a driving transistor (DR), a capacitor, and an organic light emitting diode (OLED), but a compensation circuit (CC) When is added, it may be variously configured as 3T1C, 4T2C, 5T2C, 6T2C, 7T2C, and the like.

In addition, although the compensation circuit CC is shown to be positioned between the switching transistor SW and the driving transistor DR in FIGS. 2 and 3 , it may be further positioned between the driving transistor DR and the organic light emitting diode (OLED). may be The position and structure of the compensation circuit CC are not limited to FIGS. 2 and 3 .

<First embodiment>

4 is a plan view illustrating an organic light emitting display device according to a first exemplary embodiment of the present invention. FIG. 5 is an enlarged plan view of the AR region of FIG. 4 . 6 is a view for explaining a problem of the related art.

4 and 5 , the organic light emitting diode display includes a substrate SUB and a circuit unit CO. The substrate SUB includes a display area AA and a non-display area NA defined outside the display area AA. A plurality of sub-pixels SP are disposed in the display area AA. The sub-pixels SP are arranged in R (red), G (green), B (blue), or R, G, B, and W (white) schemes in the display area AA to implement a full color. The sub-pixel SP may be partitioned by a gate line and a data line crossing each other, but is not limited thereto.

The non-display area NA includes a gate pad part GP and a link part LP. The gate pad part GP may be defined on at least one side of the display area AA. The link part LP may be defined between the display area AA and the gate pad part GP.

For example, the gate pad part GP may be disposed on either the right side or the left side of the display area AA. ((a) of FIG. 4 ) As another example, the gate pad part GP may be separately disposed on the left and right sides of the display area AA to minimize signal delay caused by the RC delay. (FIG. 4(b)) That is, as shown in FIG. 4(b), in the first embodiment of the present invention, a gate signal is simultaneously applied to both sides of one gate line by double feeding. By adopting the method, it is possible to compensate for the delay of the gate signal in the display area AA.

The gate pad part GP includes a plurality of gate pads GPD, and the link part LP includes a gate link line GLS. The gate pad GPD is electrically connected to the gate link line GSL extending from the display area AA. The circuit unit CO includes bumps (or terminals). The bumps of the circuit unit CO may be respectively bonded to the gate pads through an anisotropic conductive film. The circuit unit CO may be implemented in a chip on film (COF) method in which a driving IC (GIC) is mounted on a flexible film. There may be a plurality of circuit units CO, and the circuit units CO are bonded to assigned gate pads to supply gate signals to corresponding gate link lines GSL. In the drawings, the number of gate link lines GSL (or gate pads) allocated to each circuit unit CO is 7 as an example, but the present invention is not limited thereto.

The gate link line GSL supplies the gate signal applied through the circuit unit CO to the gate line GL of the display area AA. To this end, one end of the gate link line GSL is connected to the gate pad GPD, and the other end of the gate link line GSL is connected to the gate line GL.

A pitch P1 between the gate pads GPD (or a pitch between bumps in the circuit unit CO) is set to be narrower than a pitch P2 between the gate lines GL. Accordingly, at least a partial section in which the pitch between the gate link lines GSL is gradually narrowed as it approaches the gate pad GPD is included. That is, the gate link line GSL connecting the gate pad GPD and the gate line GL by the difference between the pitch P1 between the gate pads GPD and the pitch P2 between the gate lines GL. The lengths of these are different depending on the location. For example, as shown in the drawing, assuming that seven gate link lines GSL are allocated per one circuit unit CO, the gate link line GSL4 disposed at the center among the gate link lines GSL. has the shortest length, and the gate link lines GSL1, GSL2, GSL3, GSL5, GSL6, and GSL7 disposed farther from the center have a relatively long length.

When the length of the gate link line GSL is different depending on the location, a difference in resistance and capacitance values (hereinafter, referred to as “RC deviation”) between the gate link lines GSL is large, and thus the display area AA ), a uniform gate signal may not be supplied to the gate lines GL.

Specifically, due to the difference in length between the gate link lines GSL, a difference occurs in the RC delay level of the gate signal pulse between the gate link lines GSL. In this case, a current deviation occurs between the pixels receiving the gate signal from the short gate link line GSL and the pixels receiving the gate signal from the long gate link line GSL, so that the luminance uniformity of the display panel is significantly reduced problems may arise.

In particular, the RC deviation between the gate link lines GSL may be weighted by the parasitic capacitance generated between the gate link line GSL and the cathode. More specifically, referring to FIG. 6 , since the cathode CAT constituting the organic light emitting diode is formed widely over the entire surface of the substrate to cover all sub-pixels arranged in the display area AA, the link part LP ) overlaps the gate link line GSL with one or more dielectric layers, for example, the interlayer insulating layer ILD, the passivation layer PAS, and the planarization layer OC interposed therebetween. Since the gate link line GSL overlaps the cathode CAT with one or more dielectric layers interposed therebetween, a parasitic capacitance Cp is generated between the gate link line GSL and the cathode CAT. In this case, even if the thickness of the dielectric layer interposed between the gate link line GSL and the cathode CAT is the same, the parasitic capacitance value generated by the area difference between the gate link lines GSL is different. That is, the parasitic capacitance Cp between the long gate link line GSL and the cathode CAT is greater than the parasitic capacitance Cp between the long gate link line GSL and the cathode CAT. Accordingly, the RC deviation between the gate link lines GSL having different lengths may be further increased due to the magnitude of the parasitic capacitance formed between the gate link line GSL and the cathode CAT.

The first embodiment of the present invention proposes a novel structure capable of reducing the parasitic capacitance between the gate link line GSL and the cathode CAT in order to reduce the RC deviation between the gate link lines GSL.

7 is a cross-sectional view schematically illustrating a sub-pixel structure in a display area according to the first exemplary embodiment of the present invention. 8 is a diagram schematically illustrating a stacked structure of a link unit in a non-display area according to a first exemplary embodiment of the present invention. 9 is a view for explaining the effect according to the first embodiment of the present invention.

Referring to FIG. 7 , the organic light emitting diode display according to the first exemplary embodiment includes a substrate SUB provided with a thin film transistor T and an organic light emitting diode OLE. Although not shown, an encapsulation layer covering the thin film transistor T and the organic light emitting diode OLE may be further provided on the substrate SUB. The encapsulation layer may protect the internal device from moisture and oxygen that may be introduced from the outside.

The substrate SUB may be made of glass or plastic. For example, the substrate SUB may be formed of a plastic material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polycarbonate (PC), and may have flexible properties.

A thin film transistor T and an organic light emitting diode OLE connected to the thin film transistor T are formed on the substrate SUB. A light blocking layer (not shown) and a buffer layer (not shown) may be formed between the substrate SUB and the thin film transistor T. The light blocking layer is disposed to overlap the semiconductor layer of the thin film transistor T, in particular, a channel, and may function to protect the semiconductor device from external light. The buffer layer may function to block ions or impurities diffusing from the substrate SUB and block external moisture penetration.

The thin film transistor T includes a semiconductor layer A, a gate electrode G, and source/drain electrodes S and D. A gate insulating layer GI and a gate electrode G are disposed on the semiconductor layer A. The gate insulating layer GI insulates the gate electrode G, and may be formed of a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx), but is not limited thereto. The gate insulating layer GI may be formed to cover the entire surface of the substrate SUB. Although not shown, the gate insulating layer GI and the gate electrode G may be patterned using the same mask. In this case, the gate insulating layer GI and the gate electrode G may have the same planar shape.

The gate electrode G is disposed to overlap the semiconductor layer A with the gate insulating layer GI interposed therebetween. The gate electrode G includes copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and tantalum (Ta). And it may be made of a single layer or multiple layers of any one selected from the group consisting of tungsten (W) or an alloy thereof.

An interlayer insulating layer ILD is disposed on the gate electrode G. The interlayer insulating layer (ILD) insulates the gate electrode (G) and the source/drain electrodes (S, D) from each other, and may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof, but is not limited thereto. it is not

Source/drain electrodes S and D are disposed on the interlayer insulating layer ILD. The source electrode S and the drain electrode D are spaced apart from each other by a predetermined distance. The source electrode S contacts one side of the semiconductor layer A through a source contact hole penetrating the interlayer insulating layer ILD. The drain electrode D contacts the other side of the semiconductor layer A through a drain contact hole penetrating the interlayer insulating layer ILD.

The source electrode S and the drain electrode D may be formed of a single layer or multiple layers, and in the case of a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), It may be made of any one selected from the group consisting of nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. In addition, when the source electrode S and the drain electrode D are multi-layered, molybdenum/aluminum-neodymium, molybdenum/aluminum, titanium/aluminum, or a double layer of copper/motitanium, or molybdenum/aluminum-neodymium/molybdenum, molybdenum It may be made of a triple layer of /aluminum/molybdenum, titanium/aluminum/titanium, or motitanium/copper/mo-titanium.

A passivation layer PAS is positioned on the thin film transistor T. The passivation layer PAS protects the thin film transistor T and may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

A planarization layer OC is positioned on the passivation layer PAS. The planarization film (OC) is to planarize the lower step, and may be made of organic materials such as photo acryl, polyimide, benzocyclobutene resin, and acrylate. have.

An organic light emitting diode OLE is positioned on the planarization layer OC. The organic light emitting diode OLE includes an anode ANO and a cathode CAT facing each other, and an organic compound layer OL interposed between the anode ANO and the cathode CAT.

In more detail, the anode ANO is positioned on the planarization layer OC. The anode ANO is connected to the drain electrode D of the thin film transistor T through a contact hole penetrating the passivation layer PAS and the planarization layer OC.

The anode (ANO) is made of a transparent conductive material such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or Zinc Oxide (ZnO) to function as a transparent electrode. Alternatively, the anode ANO may include a reflective layer to function as a reflective electrode. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or an alloy thereof, preferably APC (silver/palladium/copper alloy). The anode ANO may be formed of multiple layers including a reflective layer. The anode ANO may function as a transmissive electrode or a reflective electrode according to a light emitting method.

A bank layer BNK partitioning neighboring pixels is positioned on the substrate SUB on which the anode ANO is formed. The bank layer BNK may be formed of an organic material such as polyimide, benzocyclobutene series resin, or acrylate. A central portion of the anode ANO exposed by the bank layer BNK may be defined as a light emitting area. The bank layer BNK may be disposed to expose a central portion of the anode ANO but cover a side end of the anode ANO.

An organic compound layer OL is positioned on the anode ANO. The organic compound layer OL includes an emission layer (EML), and a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer. It may further include any one or more of an electron injection layer (EIL). The emission layer may be separately disposed for each sub-pixel, or may be formed widely on the entire surface of the substrate SUB to cover the sub-pixels.

On the organic compound layer OL, a cathode CAT is positioned. The cathode CAT may be widely formed on the entire surface of the substrate SUB to cover the pixels. The cathode (CAT) is formed of a transparent conductive material such as ITO (Indium Tin Oxide) IZO (Indium Zinc Oxide), or magnesium (Mg), calcium (Ca), aluminum ( Al), silver (Ag), or an alloy thereof may function as a transmissive electrode. Alternatively, the cathode CAT may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof to function as a reflective electrode. The cathode CAT may function as a transmissive electrode or a reflective electrode according to a light emitting method.

Referring to FIG. 8 , on the substrate SUB of the link part LP, a gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PAS, and a planarization layer OC extending from the display area AA are sequentially formed. are placed A gate link line GSL is formed between the gate insulating layer GI and the interlayer insulating layer ILD. The gate link line GSL is connected to a gate line (not shown) disposed in the display area AA, and may be formed of the same material on the same layer as the gate line and the gate electrode G disposed in the display area AA. can The cathode CAT is formed widely over the entire surface of the substrate to cover all the sub-pixels arranged in the display area AA, with the interlayer insulating layer ILD, the passivation layer PAS, and the planarization layer OC interposed therebetween. It overlaps with the gate link line GSL.

A first embodiment of the present invention provides an auxiliary dielectric layer (ASL) between the cathode (CAT) and the gate link line (GSL) in order to reduce the parasitic capacitance (Cp′) between the cathode (CAT) and the gate link line (GSL). to form more The auxiliary dielectric layer ASL is formed to have a predetermined thickness and is interposed between the cathode CAT and the gate link line GSL to sufficiently space the cathode CAT and the gate link line GSL from each other. The auxiliary dielectric layer ASL is configured to be localized between the cathode CAT and the gate link line GSL in the link part LP. In the drawings, a case in which the auxiliary dielectric layer ASL is interposed between the planarization layer OC and the passivation layer PAS is illustrated as an example, but the present invention is not limited thereto.

The first embodiment of the present invention provides an auxiliary dielectric layer (ASL) to sufficiently space the cathode (CAT) and the gate link line (GSL) apart, thereby reducing the parasitic capacitance generated between the cathode (CAT) and the gate link line (GSL). Since it can be reduced, the RC deviation between the gate link lines GSL having different lengths can be improved. That is, in the first embodiment of the present invention, since the parasitic capacitance between the gate link lines GSL and the cathode CAT is insignificant, the ratio between the gate link lines GSL due to the parasitic capacitance is the same as in the prior art. Even if the RC deviation occurs, the absolute value of the RC deviation is small and the image quality is not affected. In other words, in the first embodiment of the present invention, since parasitic capacitance between the gate link lines GSL and the cathode CAT can be significantly reduced, RC deviation between the gate link lines GSL having different lengths. In considering , there is no need to consider the deviation of the parasitic capacitance value. Accordingly, the first embodiment of the present invention has an advantage in that it is possible to prevent a decrease in the luminance uniformity of the display panel, thereby providing an organic light emitting diode display with remarkably improved display quality.

Hereinafter, an effect of improving the RC deviation between the gate link lines GSL will be described through a comparative experiment. The structure according to the comparative example has a structure in which an interlayer insulating layer ILD, a passivation layer PAS, and a planarization layer OC are sequentially interposed between the gate link line GSL and the cathode CAT as shown in FIG. 6 . In the structure according to the experimental example, an interlayer insulating layer (ILD), a passivation layer (PAS), an auxiliary dielectric layer (ASL), and a planarization layer (OC) are sequentially interposed between the gate link line (GSL) and the cathode (CAT) as shown in FIG. 8 . has a structured structure. An interlayer insulating film (ILD), a passivation film (PAS), and a planarization film (OC) having the same thickness were respectively stacked on the structures according to the comparative example and the experimental example, and in the experimental example, an auxiliary dielectric layer including a photo resist ( ASL) is different from the comparative example in that it is further formed. That is, except that the auxiliary dielectric layer (ASL) is added in the experimental example, the experimental conditions of the experimental example and the comparative example are the same.

In the structures of Comparative Examples and Experimental Examples, when the gate link lines GSL1, GSL2, GSL3, GSL5, GSL6, and GSL7 are arranged as shown in FIG. 5, the gate link lines GSL1, GSL2, GSL3, GSL5, GSL6 , the parasitic capacity profile of GSL7) is as shown in FIG. 9 .

In the case of the comparative example, the deviation of the parasitic capacitance between the gate link lines (GSL) was about 7 pF, and in the case of the experimental example, the deviation of the parasitic capacitance between the gate link lines (GSL) was about 4 pF. As can be seen, in the case of the experimental example, the parasitic capacitance value between the gate link lines (GSL) and the cathode (CAT) was reduced compared to the comparative example, as well as the deviation of the parasitic capacitance between the gate link lines (GSL) was markedly It can be seen that improved As described above, the present invention can improve the RC deviation between the gate link lines GSL having different lengths by reducing the parasitic capacitance generated therebetween. Accordingly, it is possible to provide an organic light emitting diode display with significantly improved display quality.

<Second embodiment>

10 is a cross-sectional view schematically illustrating a sub-pixel structure in a display area according to a second exemplary embodiment of the present invention. 11 to 13 are diagrams schematically illustrating a stacked structure of a link unit in a non-display area according to a second exemplary embodiment of the present invention. In the description of the second embodiment of the present invention, descriptions of components substantially the same as those of the first embodiment will be omitted.

Referring to FIG. 10 , the organic light emitting diode display according to the second exemplary embodiment includes a display area AA in which sub-pixels SP are arranged. Each pixel includes a thin film transistor T and an organic light emitting diode OLE provided on a substrate SUB. The organic light emitting diode OLE includes an anode ANO, a cathode CAT, and an organic compound layer OL interposed between the anode ANO and the cathode CAT.

The organic light emitting diode display according to the second embodiment of the present invention may be implemented as a bottom emission type. Accordingly, the light emitted from the organic light emitting diode OLE passes through the substrate SUB and is recognized by the user. For example, the organic light emitting display device according to the second exemplary embodiment of the present invention includes an organic compound layer OL emitting white (W) light to realize red (R), green (G), and blue (B) colors; , a color filter (CF) of red (R), blue (B), and green (G) may be included. That is, in the organic light emitting display device, white (W) light emitted from the organic light emitting layer OL is provided in red (R) regions corresponding to red (R), green (G), and blue (B) sub-pixels, respectively. , by passing the color filters CF of green (G) and blue (B), red (R), green (G), and blue (B) may be realized.

The color filter CF is disposed under the organic light emitting diode OLE. That is, the color filter CF may be disposed under the anode ANO with at least one insulating layer interposed therebetween. In the drawings, a case in which the color filter CF is interposed between the planarization layer OC and the passivation layer PAS is illustrated as an example, but the present invention is not limited thereto.

Referring to FIG. 11 , the organic light emitting diode display according to the second exemplary embodiment includes a non-display area NA having a link part LP. A gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PAS, and a planarization layer OC extending from the display area AA are sequentially disposed on the substrate SUB of the link part LP. A gate link line GSL is formed between the gate insulating layer GI and the interlayer insulating layer ILD. The gate link line GSL is connected to a gate line (not shown) disposed in the display area AA, and may be formed of the same material on the same layer as the gate line and the gate electrode G disposed in the display area AA. can The cathode CAT is formed widely over the entire surface of the substrate to cover all the sub-pixels arranged in the display area AA, with the interlayer insulating layer ILD, the passivation layer PAS, and the planarization layer OC interposed therebetween. It overlaps with the gate link line GSL.

The second embodiment of the present invention provides a color filter pattern CFP between the cathode CAT and the gate link line GSL in order to reduce the parasitic capacitance Cp' between the cathode CAT and the gate link line GSL. ) to form more The color filter pattern CFP functions substantially the same as the auxiliary dielectric layer of the first embodiment. The color filter pattern CFP is formed to have a predetermined thickness and is interposed between the cathode CAT and the gate link line GSL to sufficiently space the cathode CAT and the gate link line GSL from each other. The color filter pattern CFP is locally disposed between the cathode CAT and the gate link line GSL in the link part LP.

According to the second embodiment of the present invention, the cathode CAT and the gate link line GSL may be sufficiently spaced apart from each other by providing the color filter pattern CFP on the link part LP. Accordingly, a parasitic capacitance occurring between the cathode CAT and the gate link line GSL may be reduced, and thus RC deviation between the gate link lines GSL having different lengths may be improved. The second embodiment of the present invention has an advantage in that it is possible to prevent a decrease in luminance uniformity of a display panel, and thus an organic light emitting display device having significantly improved display quality can be provided.

The color filter pattern CFP of the link part LP is formed simultaneously with the color filter CF disposed in the display area AA. Accordingly, the color filter pattern CFP of the link part LP may be formed on the same layer as the color filter CF disposed in the display area AA. The color filter pattern CFP may be formed together when any one of the red (R), green (G), and blue (B) color filters CF disposed in the display area are formed. In the second embodiment of the present invention, since there is no need to separately form a structure for reducing the parasitic capacitance of the cathode CAT and the gate link line GSL in the link part LP, manufacturing cost and manufacturing time are reduced. There is an advantage in that the production yield can be improved because an additional process is not required.

Referring to FIG. 12 , thicknesses of the color filter CF in the display area AA and the color filter pattern CFP in the link part LP may be different from each other. FIG. 12A schematically illustrates a stacked structure in the display area AA, and FIG. 12B schematically illustrates a stacked structure of the link part LP in the non-display area NA.

The color filters CF disposed in the display area AA need to be formed to have a predetermined first thickness t1 for a specific purpose, for example, to match a target color coordinate, and the link part LP ), the color filter pattern CFP needs to be formed to have a preset second thickness t1' in order to effectively reduce the parasitic capacitance. In consideration of this, in the second embodiment of the present invention, the color filter CF and the color filter pattern CFP are simultaneously formed through the same process using a multi-tone mask, but both thicknesses It can be formed by changing (t1, t1').

Referring further to FIG. 13 , the color filter pattern CFP disposed between the cathode CAT and the gate link line GSL in the link unit LP includes at least two color filters CF1 and CF2 stacked. can have a structure. That is, the color filter pattern CFP has a form in which at least two color filters CF among red (R), green (G), and blue (B) color filters CF disposed in the display area AA are stacked. can have In this case, since the cathode CAT and the gate link line GSL can be spaced apart more sufficiently compared to the structure shown in FIG. 10 , the parasitic capacitance Cp'' can be effectively reduced.

<Third embodiment>

14A is a cross-sectional view schematically illustrating a stacked structure in a display area according to a third exemplary embodiment of the present invention. 14B is a cross-sectional view schematically illustrating a stacked structure of a link unit in a non-display area according to a third exemplary embodiment of the present invention. In the description of the third embodiment of the present invention, descriptions of components substantially the same as those of the first embodiment will be omitted.

Referring to FIG. 14 , at least one dielectric layer is interposed between the organic light emitting diode and the gate link line GSL on the substrate SUB. For example, the dielectric layer may include an interlayer insulating layer ILD, a passivation layer PAS, and a planarization layer OC. At least one of the dielectric layers interposed between the organic light emitting diode and the gate link line GSL may have different thicknesses in the display area AA and the link portion LP. Dielectric layers having different thicknesses may be formed using a multi-tone mask.

For example, it is formed widely over the entire surface of the substrate SUB to cover the display area AA and the non-display area NA, and the cathode CAT and the gate link line GSL (and the gate line GL) ), the planarization layer OC interposed between them may have a greater thickness than other regions in the link portion LP. That is, the planarization layer OC may be formed to have a first thickness t2 on the substrate SUB and to have a second thickness t2 ′ locally at the link portion LP. A portion of the second thickness t2 exceeding the first thickness t1' functions substantially the same as the auxiliary dielectric layer of the first embodiment.

In the third embodiment of the present invention, at least one of the dielectric layers interposed between the cathode CAT and the gate link line GSL (and the gate line GL) is locally thickly formed in the link portion LP. , the cathode CAT and the gate link line GSL may be sufficiently spaced apart. Accordingly, a parasitic capacitance occurring between the cathode CAT and the gate link line GSL may be reduced, and thus RC deviation between the gate link lines GSL having different lengths may be improved. The second embodiment of the present invention has an advantage in that it is possible to prevent a decrease in luminance uniformity of a display panel, and thus an organic light emitting display device having significantly improved display quality can be provided.

<Fourth embodiment>

15 is a plan view illustrating an organic light emitting display device according to a first exemplary embodiment of the present invention. 16 is an enlarged plan view of the AR region of FIG. 15 . In the description of the fifth embodiment of the present invention, descriptions of components substantially the same as those of the first embodiment will be omitted.

Referring to FIG. 15 , the organic light emitting diode display includes a substrate SUB and a circuit unit CO. The substrate SUB includes a display area AA and a non-display area NA defined outside the display area AA.

The display area AA includes a plurality of sub-pixels SP. The non-display area NA includes a source pad part DP and a link part LP. The source pad part DP may be defined on at least one side of the display area AA. The link part LP may be defined between the display area AA and the source pad part DP. For example, the source pad part DP may be disposed on any one of an upper side and a lower side of the display area AA.

The source pad part DP includes a plurality of source pads DPD, and the link part LP includes a link line DSL. The source pad DPD is electrically connected to the link line DSL extending from the display area AA. The bumps of the circuit unit CO may be respectively bonded to the source pads DPD through the anisotropic conductive film. There may be a plurality of circuit units CO, and the circuit units CO are bonded to the allocated source pads DPD to supply gate signals to the corresponding link lines DSL.

The link line DSL supplies a preset signal applied through the circuit unit CO to the signal line SL of the display area AA. To this end, one end of the link line DSL is connected to the source pad DPD, and the other end of the link line DSL is connected to the signal line SL. The signal line SL may include a data line to which a data voltage is applied, a sensing line for implementing a compensation circuit, and the like.

The pitch P1 between the source pads DPD is set to be narrower than the pitch P2 between the signal lines SL. Accordingly, at least a partial section in which the pitch between the link lines DSL is gradually narrowed as it approaches the source pad DPD is included. That is, by the difference between the pitch P1 between the source pads DPD and the pitch P2 between the signal lines SL, the link lines DSL connecting the source pad DPD and the signal line SL are The length is different depending on the position. Due to the difference in length between the link lines DSL, a difference may occur in the RC delay level of a preset signal between the link lines DSL, and in this case, the display quality of the display device may be deteriorated, which is a problem.

To solve this problem, the fifth embodiment of the present invention may apply the complementary structures described in the first to fourth embodiments in the same way. For example, in the fifth embodiment of the present invention, as in the first embodiment, the auxiliary dielectric layer may be locally provided between the link line DSL and the cathode CAT in the link part LP. Accordingly, since parasitic capacitance generated between the cathode CAT and the link line DSL can be reduced, RC deviation between the link lines DSL having different lengths can be improved. The fifth embodiment of the present invention has an advantage in that it is possible to prevent a decrease in luminance uniformity of a display panel, and thus an organic light emitting display device having significantly improved display quality can be provided.

<Fifth embodiment>

17 is an enlarged plan view of the AR region of FIG. 4 . 18 is an enlarged plan view of the AR region of FIG. 4 according to a fifth embodiment of the present invention.

Referring to FIG. 17 , a pitch P1 between the gate pads GPD (or a pitch between bumps in the circuit unit CO) is set to be narrower than a pitch P2 between the gate lines GL. Accordingly, at least a partial section in which the pitch between the gate link lines GSL is gradually narrowed as it approaches the gate pad GPD is included. That is, the gate link line GSL connecting the gate pad GPD and the gate line GL by the difference between the pitch P1 between the gate pads GPD and the pitch P2 between the gate lines GL. The lengths of these are different depending on the location. For example, as shown in the drawing, assuming that 7 gate link lines GSL are allocated per one circuit unit CO, the gate link line GSL4 disposed at the center among the gate link lines GSL. has the shortest length, and the gate link lines GSL1, GSL2, GSL3, GSL5, GSL6, and GSL7 farther from the center have a relatively long length.

In the first to fourth embodiments of the present invention, the cathode CAT and the gate link line GSL are sufficiently spaced apart to reduce the parasitic capacitance generated between the cathode CAT and the gate link line GSL. is starting However, although the parasitic capacitance deviation between the gate link lines GSL having different lengths may be improved by this configuration, as shown in FIG. 9B , the parasitic capacitance between the gate link lines GSL is Deviations still exist. That is, the overlapping areas OA1, OA2, OA3, OA4, OA5, OA6, OA7 of the first to seventh gate link lines GSL1, GSL2, GSL3, GSL4, GSL5, GSL6, GSL7 and the cathode CAT are Since it is not constant, a parasitic capacitance variation exists between the gate link lines GSL1 , GSL2 , GSL3 , GSL4 , GSL5 , GSL6 , and GSL7 .

The fifth embodiment of the present invention proposes a novel structure for substantially eliminating parasitic capacitance variation between gate link lines GSL having different lengths. That is, in the fifth embodiment of the present invention, the shape of the cathode CAT may be formed differently depending on the position in order to improve the deviation of the parasitic capacitance.

Referring to FIG. 18 , in the fifth embodiment of the present invention, the overlapping area OA' of each of the cathode CAT and the gate link lines GSL in order to reduce the variation in the parasitic capacitance between the gate link lines GSL. ) to be practically the same. For this, the shape of the cathode CAT may have a shape different from that of the related art.

For example, overlapping areas OA1', OA2', OA3', OA4', OA5 of the first to seventh gate link lines GSL1, GSL2, GSL3, GSL4, GSL5, GSL6, and GSL7 and the cathode CAT ', OA6', OA7') are controlled substantially the same. Accordingly, the cathode may have a free form planar shape. That is, the shape of the cathode includes overlapping areas OA1', OA2', OA3', OA4', OA5' of the gate link lines GSL1, GSL2, GSL3, GSL4, GSL5, GSL6, and GSL7 and the cathode CAT. If it is a shape that can control OA6' and OA7') substantially the same, both are possible.

According to the fifth embodiment of the present invention, a decrease in luminance uniformity of the display panel may be prevented by controlling the gate link lines GSL to have a constant parasitic capacitance. Accordingly, the fifth embodiment of the present invention has an advantage in that it is possible to provide an organic light emitting display device with significantly improved display quality. In the fifth embodiment of the present invention, only the gate link line GSL to which the gate signal is applied has been described as an example, but the present invention is not limited thereto.

Those skilled in the art through the above description will be able to make various changes and modifications without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SUB : Substrate T : Thin Film Transistor
OLE : organic light emitting diode ANO : anode
OL: organic compound layer CAT: cathode
GL: gate line GSL: gate link line
SL: signal line DSL: link line
ASL: auxiliary dielectric layer CF: color filter
CFP: color filter pattern

Claims (11)

An organic light emitting diode display comprising a substrate having a display area and a non-display area defined therein, comprising:
signal lines disposed in the display area;
pads disposed in the non-display area;
link lines disposed in the non-display area, connecting the corresponding signal lines and the pads, and having different lengths;
an auxiliary dielectric layer locally disposed on the link lines; and
and a cathode disposed on the auxiliary dielectric layer.
The method of claim 1,
Further comprising a color filter disposed in the display area,
The auxiliary dielectric layer is
An organic light emitting display device that is disposed on the same layer as the color filter and is a color filter pattern made of the same material.
3. The method of claim 2,
The color filter and the color filter pattern,
An organic light emitting diode display having different thicknesses.
3. The method of claim 2,
The color filter is
red, green, and blue color filters assigned to each pixel;
The color filter pattern is
An organic light emitting diode display having a structure in which at least two of the red, green, and blue color filters are stacked.
The method of claim 1,
The spacing between the pads is narrower than the spacing between the signal lines,
The distance between the link lines is,
In at least some sections, the organic light emitting diode display is gradually narrowed as it approaches the pad.
The method of claim 1,
a cathode disposed in the display area and the non-display area;
The auxiliary dielectric layer is
an organic light emitting diode display interposed between the cathode and the link lines.
The method of claim 1,
the signal line is a gate line,
The gate line is
and receiving a gate signal through the link line.
The method of claim 1,
the signal line is a data line,
The data line is
and receiving a data signal through the link line.
The method of claim 1,
Further comprising a cathode disposed in the display area and the non-display area,
and an overlapping area of the cathode and each of the link lines is constant.
An organic light emitting diode display comprising a substrate having a display area and a non-display area defined therein, comprising:
signal lines disposed in the display area;
pads disposed in the non-display area;
link lines disposed in the non-display area, connecting the corresponding signal lines and the pads, and having different lengths; and
a dielectric layer disposed to extend in the display area and the non-display area on the link lines;
The dielectric layer is
The organic light emitting display device comprising a portion having a locally thick thickness on the link line compared to other regions.
11. The method of claim 10,
a cathode disposed in the display area and the non-display area;
The part is
An organic light emitting diode display positioned between the cathode and the link lines.

Images