KR102382488B1 - Thin Film Transistor Substrate - Google Patents

Abstract

The present invention includes a thin film transistor, a pixel electrode, a common electrode, and a double electrode layer. The pixel electrode is connected to the thin film transistor. The common electrode overlaps the pixel electrode with an insulating layer interposed therebetween. The double electrode layer is positioned on the same layer as an upper electrode among the pixel electrode and the common electrode, and has a transparent layer having a first width and an opaque layer having a second width. In this case, the first width is wider than the second width.

Description

Thin Film Transistor Substrate

The present invention relates to a thin film transistor substrate. In particular, the present invention relates to a thin film transistor substrate including a light blocking layer or a common wiring having a double layer structure in which layers having different widths are stacked.

The display device field has rapidly changed to a thin, light, and large-area Flat Panel Display Device (FPD) that replaces a bulky cathode ray tube (CRT). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device. : ED), etc.

In the case of a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device that are actively driven, a thin film transistor substrate is included in which thin film transistors allocated in pixel regions arranged in a matrix manner are disposed. A liquid crystal display device (LCD) displays an image by adjusting the light transmittance of liquid crystal using an electric field. The liquid crystal display device is classified into a vertical electric field type and a horizontal electric field type according to the direction of the electric field driving the liquid crystal.

The vertical electric field type liquid crystal display drives liquid crystals in twisted nematic (TN) mode by a vertical electric field formed between a pixel electrode and a common electrode disposed to face an upper and lower substrate. Such a vertical electric field type liquid crystal display device has an advantage of a large aperture ratio, but has a disadvantage in that the viewing angle is as narrow as 90 degrees.

In the horizontal electric field type liquid crystal display device, a horizontal electric field is formed between a pixel electrode and a common electrode disposed parallel to a lower substrate to drive liquid crystal in an in-plane switching (IPS) mode. The liquid crystal display of the IPS mode has the advantage of having a wide viewing angle of about 160 degrees, but has disadvantages of low aperture ratio and low transmittance. Specifically, in the liquid crystal display of the IPS mode, the gap between the common electrode and the pixel electrode is wider than the gap between the upper substrate and the lower substrate (cell gap) in order to form an in-plane field, and an appropriate intensity In order to obtain an electric field of An electric field substantially parallel to the substrate is formed between the pixel electrode and the common electrode in the IPS mode, but no electric field is formed in the pixel electrode having a predetermined width and the liquid crystal on the common electrode. That is, the liquid crystal molecules placed on the pixel electrode and the common electrode are not driven and maintain their initial arrangement. The liquid crystal maintaining the initial state does not transmit light, which is a factor of lowering the aperture ratio and transmittance.

In order to improve the disadvantages of the IPS mode liquid crystal display, a fringe field switching (FFS) liquid crystal display operated by a fringe field has been proposed. An FFS-type liquid crystal display device includes a common electrode and a pixel electrode having an insulating film interposed therebetween in each pixel region, and the common electrode and the pixel electrode overlap each other in a vertical direction, or even if they do not overlap each other, a horizontal separation distance is an upper portion It is formed to be narrower than the gap between the substrate and the lower substrate to form a parabolic fringe field on the common electrode and the pixel electrode. All liquid crystal molecules interposed between the upper and lower substrates by the fringe field operate, so that the aperture ratio and transmittance are improved.

Hereinafter, a thin film transistor substrate according to the prior art will be described with reference to FIGS. 1 and 2 . 1 is a plan view showing a thin film transistor substrate according to the prior art. FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along line I-I'.

1 and 2 , the thin film transistor substrate is defined by a gate line GL and a data line DL intersecting each other with a gate insulating layer GI interposed therebetween on the substrate SUB, and the cross structure thereof. Each pixel area is included. On one side of the pixel region, the gate electrode G branched from the gate line GL, the source electrode S branched from the data line DL, and the drain disposed to face the source electrode D at a predetermined distance from each other A thin film transistor T including an electrode D is disposed.

A semiconductor layer A is formed on the gate insulating layer GI that covers the gate electrode G to overlap the gate electrode G. One side of the semiconductor layer (A) is in contact with the source electrode (S), and the other side is in contact with the drain electrode (D). The semiconductor layer (A) overlaps the gate electrode (G) to form a channel region (CA) between the source electrode (S) and the drain electrode (D).

When the channel region CA is driven while being exposed to light, there is a problem in that the off-current characteristic of the thin film transistor T is rapidly deteriorated. That is, when the channel region CA is exposed to light, a photocurrent is generated, and an operation failure of the thin film transistor T occurs due to the generated light leakage current.

For example, light introduced from a backlight unit (not shown) disposed under the thin film transistor T is directly incident DRL on the lower portion of the channel region CA or a color filter substrate above the thin film transistor T. It may be reflected by the black matrix provided in (not shown) to be incident RL on the upper portion of the channel area CA. The gate electrode G is disposed under the channel area CA to block light flowing toward the lower part of the channel area, but the upper part of the channel area CA is exposed as it is, so that light flowing into the upper part of the channel area CA is exposed. vulnerable to light Accordingly, it is required to have a structure capable of blocking light flowing into the upper portion of the channel area CA.

A first passivation layer PAS1 for protecting the device and a planarization layer PAC for planarization are sequentially formed on the thin film transistor T. A pixel electrode PXL made of a conductive material is formed on the planarization layer PAC.

The pixel electrode PXL contacts the drain electrode D through the pixel contact hole PH penetrating the planarization layer PAC and the first passivation layer PAS1 . The pixel electrode PXL is electrically connected to the drain electrode D to receive a data voltage. The pixel electrode PXL may be formed to cover most of the pixel area of the substrate SUB. That is, the pixel electrode PXL has a structure that occupies most of the pixel area in the form of a planar electrode.

A common electrode COM is formed on the second passivation layer PAS2 covering the pixel electrode PXL. The common electrode COM may have a comb-tooth structure in which a plurality of line segments are arranged in parallel at regular intervals within the pixel area. The common electrode COM contacts the common line CL through the common contact hole CH passing through the second passivation layer PAS2 , the planarization layer PAC, and the first passivation layer PAS1 . The common electrode COM is electrically connected to the common line CL to receive a common voltage. By overlapping the common electrode COM and the pixel electrode PXL with the second passivation layer PAS2 interposed therebetween, a horizontal electric field may be formed by the fringe field.

The common line CL is arranged in parallel with the gate line GL. The common line CL is made of the same material as the gate line GL and is formed on the same layer as the gate line GL. Since different signals are applied to the common line CL and the gate line GL, the common line CL needs to be spaced apart from the gate line GL by a predetermined distance M1 formed on the same layer. That is, the common line CL is formed to be spaced apart from the gate line by a predetermined distance M1 to prevent a short circuit with the gate line GL. Since the common line CL is a low-resistance opaque metal line, a region through which the common line CL passes becomes a non-opening area. If the common line CL is not disposed adjacent to the gate line GL within the limited area of the pixel area, there is a problem in that the opening area is reduced by the separation distance M1.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a thin film transistor substrate capable of effectively blocking light incident to a channel region by including a light blocking layer having a double layer structure having different widths. Another object of the present invention is to provide a thin film transistor substrate having a sufficient opening area within a limited pixel area including common wirings having a double layer structure having different widths.

The present invention includes a thin film transistor, a pixel electrode connected to the thin film transistor to receive a data voltage, and a common electrode receiving a common voltage to form an electric field with the pixel electrode. In this case, a double electrode layer positioned on the same layer as an upper electrode among the pixel electrode and the common electrode is included. The double electrode layer is formed by stacking a transparent layer having a first width and an opaque layer having a second width. The first width is wider than the second width.

The double electrode layer may be a light blocking layer disposed to overlap the channel region of the thin film transistor to block light that may flow into the channel region.

The double electrode layer may be a common wiring connected to the common electrode to apply a common voltage to the common electrode.

The thin film transistor substrate according to the present invention includes a light blocking layer formed together with an electrode layer positioned on the uppermost layer among the pixel electrode and the common electrode. Accordingly, the present invention can provide a thin film transistor substrate in which the characteristics of the thin film transistor are prevented from being deteriorated by the light, since light entering from the upper portion of the channel region can be effectively blocked.

The thin film transistor substrate according to the present invention includes a common wiring formed together with a common electrode. Since the common wiring is formed on a layer different from that of the gate wiring, a gap between the common wiring and the gate wiring can be minimized or overlapped without structural restrictions depending on the location of the gate wiring. According to the present invention, the opening area can be sufficiently secured within the limited area of the pixel area by reducing the gap between the common wiring and the gate wiring.

In the present invention, when the electrode layer positioned on the uppermost layer is formed, the light blocking layer or the opaque layer of the common wiring may be formed together. Therefore, since an additional process is not required in the present invention, it is possible to prevent a problem of a yield decrease due to the addition of the process, and to prevent an increase in manufacturing cost and manufacturing time.

The present invention does not use a diffraction mask or a half-tone mask, but uses a full tone mask to form an electrode layer located on the uppermost layer, a light blocking layer, or a common wiring at the same time. carry out the process Accordingly, the present invention can provide a thin film transistor substrate having improved pattern uniformity compared to the case of using a diffraction mask or a halftone mask.

1 is a plan view showing a thin film transistor substrate according to the prior art.
FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along line II'.
3 is a plan view illustrating a structure of a thin film transistor substrate according to a first embodiment of the present invention.
4 is a cross-sectional view of the thin film transistor substrate according to the first embodiment of the present invention shown in FIG. 3 taken along the cut line II-II'.
5A to 5G are views for explaining a method of manufacturing a thin film transistor substrate according to the first embodiment of the present invention, which is cut along the perforated line II-II' in FIG. 3 .
6 is a plan view showing the structure of a thin film transistor substrate according to a second embodiment of the present invention.
7 is a cross-sectional view of the thin film transistor substrate according to the second embodiment of the present invention shown in FIG. 6 taken along line III-III'.
8A to 8G are diagrams for explaining a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention, which is cut along the perforated line III-III' in FIG. 6 .

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of writing the specification, and may be different from the component names of the actual product.

The thin film transistor substrate according to the present invention is characterized in that it includes double electrode layers having different widths. The double electrode layer may function as a light blocking layer to block light that may flow into the channel region of the thin film transistor. The double electrode layer functions as a common wiring to apply a common voltage to the common electrode, and by being formed on a layer different from the gate electrode, may be formed adjacent to or overlapping the gate electrode.

The thin film transistor according to the present invention includes a thin film transistor, a pixel electrode, a common electrode, and a double electrode layer. The pixel electrode is connected to the thin film transistor in the pixel area. The common electrode overlaps the pixel electrode with an insulating layer interposed therebetween. The double electrode layer is positioned on the same layer as an upper electrode among the pixel electrode and the common electrode, and has a transparent layer having a first width and an opaque layer having a second width. In this case, the first width is wider than the second width.

Hereinafter, the technical features of the present invention will be described in detail through preferred embodiments of the present invention. A preferred embodiment of the present invention will be divided into a case in which the double electrode layer is a light blocking layer and a case in which the double electrode layer is a common wiring layer. It should be noted that the technical spirit of the present invention is not limited by the following examples.

<First embodiment>

Hereinafter, a thin film transistor substrate according to a first embodiment of the present invention will be described with reference to FIGS. 3 and 4 . 3 is a plan view illustrating a structure of a thin film transistor substrate according to a first embodiment of the present invention. 4 is a cross-sectional view of the thin film transistor substrate according to the first embodiment of the present invention shown in FIG. 3 taken along the cut line II-II'.

3 and 4 , the thin film transistor substrate according to the first embodiment of the present invention includes a gate line GL and a data line DL that cross each other on the substrate SUB. A gate line GL and a data line DL crossing each other with the gate insulating layer GI interposed therebetween define a pixel area. At one side of the pixel region, the gate electrode G branched from the gate line GL, the source electrode S branched from the data line DL, and the drain electrode disposed to face the source electrode D at a predetermined distance from each other. A thin film transistor T including (D) is disposed.

A semiconductor layer A is formed on the gate insulating layer GI that covers the gate electrode G to overlap the gate electrode G. One side of the semiconductor layer (A) is in contact with the source electrode (S), and the other side is in contact with the drain electrode (D). The semiconductor layer (A) overlaps the gate electrode (G) to form a channel region (CA) between the source electrode (S) and the drain electrode (D). A first passivation layer PAS1 for protecting the device and a planarization layer PAC for planarization are sequentially formed on the thin film transistor T.

The pixel electrode PXL and the common electrode COM are formed on the planarization layer PAC with the second passivation layer PAS2 interposed therebetween. The pixel electrode PXL contacts the drain electrode D through the pixel contact hole PH. The pixel electrode PXL is electrically connected to the drain electrode D to receive a data voltage. The common electrode COM contacts the common line CL arranged parallel to the gate line GL through the common contact hole CH. The common electrode COM is electrically connected to the common line CL to receive a common voltage.

The positions and shapes of the common electrode COM and the pixel electrode PXL may be formed in various ways according to a design environment and purpose. For example, after the pixel electrode PXL is formed, the second passivation layer PAS2 and the common electrode COM may be sequentially formed. As another example, after the common electrode COM is formed, the second passivation layer PAS2 and the pixel electrode PXL may be sequentially formed. Hereinafter, in the description of the first embodiment, a case in which the common electrode COM is positioned above the pixel electrode PXL will be described as an example.

A light blocking layer LS and a common electrode COM are formed on the second passivation layer PAS2 . The light blocking layer LS has a double-layer structure in which a transparent layer TP and an opaque layer OP are stacked. The transparent layer TP of the light blocking layer LS has a first width W1 . The opaque layer OP of the light blocking layer LS has a second width W2 . The first width W1 is wider than the second width W2 . The light blocking layer LS is formed to overlap the channel area CA.

The common electrode COM includes slits COMS having a plurality of line segment shapes parallel to each other. The slits COMS are positioned to overlap the pixel electrode PXL. The common electrode COM is a transparent layer TP formed of the same material as the transparent layer TP of the light blocking layer LS and formed on the same layer. The slits COMS of the common electrode COM have a third width W3 . The third width W3 is narrower than the first width W1 .

In the present invention, the light that may be introduced into the upper portion of the channel area CA may be blocked by providing the light blocking layer LS. Accordingly, according to the present invention, it is possible to prevent a defect in the thin film transistor T due to a light leakage current that may occur when the channel region CA is exposed to light. The present invention may provide a thin film transistor substrate in which the characteristics of the thin film transistor T are prevented from being deteriorated by blocking light that may be incident to the channel region CA through the light blocking layer LS.

Hereinafter, a method of manufacturing the thin film transistor substrate according to the first embodiment of the present invention will be described with reference to FIGS. 5A to 5G . 5A to 5G are views for explaining a method of manufacturing a thin film transistor substrate according to the first embodiment of the present invention, which is cut along the perforated line II-II' in FIG. 3 .

Referring to FIG. 5A , a gate element is formed by coating a gate metal material on a substrate SUB and patterning it through a mask process. Since the mask process may be performed by a known method, a detailed description thereof will be omitted. The gate element includes a gate electrode G and a common wiring CL (FIG. 3). The gate electrode G is branched from the gate wiring GL ( FIG. 3 ) running in one direction of the substrate SUB. The common line CL is formed to be spaced apart from each other so as not to contact the gate line GL ( FIG. 3 ) and the gate electrode G . The common line CL is arranged in parallel with the gate line GL ( FIG. 3 ). A common voltage is applied to the common line CL. A gate insulating layer GI is coated on the substrate SUB on which the gate element is formed.

Referring to FIG. 5B , a semiconductor material is coated on the substrate SUB on which the gate insulating layer GI is formed. A semiconductor layer (A) overlapping the gate electrode (G) is formed by patterning the semiconductor material through a mask process. A source-drain metal material is deposited on the substrate SUB on which the semiconductor layer A is formed. A source electrode (S) and a drain electrode (D) are formed by patterning a source-drain metal material through a mask process. The source electrode S contacts one side of the semiconductor layer A, and the drain electrode D contacts the other side of the semiconductor layer A. The source electrode S and the drain electrode D are separated from each other and are formed to be spaced apart from each other by a predetermined interval. Thereby, the thin film transistor T having the gate electrode G, the semiconductor layer A, the source electrode A, and the drain electrode D is completed. A first passivation layer PAS1 is formed by coating an insulating material on the substrate SUB on which the thin film transistor T is formed.

Referring to FIG. 5C , a planarization layer PAC is formed by coating an organic material on the substrate SUB on which the first passivation layer PAS1 is formed. A pixel contact hole PH is formed by patterning the first passivation layer PAS1 and the planarization layer PAC through a mask process. A portion of the drain electrode D is exposed through the pixel contact hole PH.

Referring to FIG. 5D , a transparent conductive material is deposited on the substrate SUB on which the planarization layer PAC is formed. The transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto. A pixel electrode PXL is formed by patterning a transparent conductive material through a mask process. A second passivation layer PAS2 is formed by coating an insulating material on the substrate SUB on which the pixel electrode PXL is formed.

5E to 5G , a transparent conductive material TPM and an opaque conductive material OPM are continuously deposited on the substrate SUB on which the planarization layer PAC is formed. The light blocking layer LS and the common electrode COM are formed by patterning the transparent conductive material TPM and the opaque conductive material OPM through a mask process. In a preferred embodiment of the present invention, when an electrode positioned on the uppermost layer among the pixel electrode PXL and the common electrode COM is formed without a separate mask process for forming the light blocking layer LS, the light blocking layer It is characterized in that it forms (LS) together.

In order to simultaneously pattern different materials, a diffractive mask or a halftone mask may be used. However, when such a diffraction mask or a halftone mask is used, there is a problem in that the uniformity of the structure to be formed is significantly reduced. In particular, such as the slits COMS of the common electrode COM, when it is required to finely pattern the width in order to improve the light transmission efficiency, the problem becomes more serious. When the pattern formation uniformity of the slits COMS is low, the luminance deviation in the panel becomes severe, thereby degrading the display quality.

In a preferred embodiment of the present invention, the above-described problem is solved through a conductive material having an etch selectivity and an over-etch process using the conductive material. The opaque conductive material (OPM) uses a material having a large etch selectivity difference from that of the transparent conductive material (TPM). For example, the opaque conductive material (OPM) may be CuNx, and the transparent conductive material (TPM) may be ITO. However, the present invention is not limited thereto.

A photoresist is applied on successively deposited transparent conductive material (TPM) and opaque conductive material (OPM), and a mask is prepared to pattern the same. The photoresist may be of a negative type or a positive type. In the following description, a case in which the photoresist is a positive type will be described as an example.

The photoresist is selectively irradiated with light through the mask. When the photoresist exposed through the mask is developed, the photoresist in the area irradiated with light is removed and the photoresist PR1 and PR2 in the area to which the light is not irradiated remain. The photoresists PR1 and PR2 remain in the region where the light blocking layer LS and the common electrode COM ( FIG. 3 ) are to be disposed. The slits COMS branched from the common electrode COM are formed to have a narrow width in a fine pattern, and the light blocking layer LS overlaps the channel region CA and is relatively wide to block the incoming light. formed to have a width. Accordingly, the photoresist PR1 remaining at the position where the slits COMS are to be formed has a narrower width than the photoresist PR2 remaining at the position where the light blocking layer LS is to be formed.

Then, the transparent conductive material (TPM) and the opaque conductive material (OPM) are patterned through an etching process. The over-etching process is performed until the opaque conductive material OPM positioned in the region where the slits COMS is formed is completely removed. A portion of the opaque conductive material OPM positioned in the region where the light blocking layer LS is formed remains. Since the opaque conductive material OPM and the transparent conductive material TPM have a large difference in etch selectivity, the transparent conductive material OPM may maintain a preset width even if the opaque conductive material OPM is over-etched. Accordingly, slits COMS having a single layer structure having a transparent layer TP are formed, and a light blocking layer LS having a double layer structure in which a transparent layer TP and an opaque layer OP are stacked is formed.

The transparent layer TP of the light blocking layer LS has a first width W1 . The opaque layer OP of the light blocking layer LS has a second width W2 that is narrower than the first width W1 . It is preferable that the opaque layer OP of the light blocking layer LS overlaps the channel region CA and has a sufficient width to block light flowing into the channel region CA. The slits COMS are preferably formed in a fine pattern to improve light transmission efficiency. The slits COMS are formed to have a third width W3 narrower than the first width W1 . also. The third width W3 is preferably narrower than the second width W2 .

In the present invention, when the electrode layer positioned on the uppermost layer among the pixel electrode and the common electrode is formed, the opaque layer OP of the light blocking layer may be formed together. Therefore, since an additional process is not required in the present invention, it is possible to prevent a problem of a yield decrease due to the addition of the process, and to prevent an increase in manufacturing cost and manufacturing time.

The present invention does not use a diffraction mask or a half-tone mask, but uses a full tone mask to simultaneously form the uppermost electrode layer and the light blocking layer among the pixel electrode and the common electrode. to perform an over-etching process. Accordingly, the present invention can provide a thin film transistor substrate having improved pattern uniformity compared to the case of using a diffraction mask or a halftone mask.

<Second embodiment>

Hereinafter, a thin film transistor substrate according to a second embodiment of the present invention will be described with reference to FIGS. 6 and 7 . 6 is a plan view showing the structure of a thin film transistor substrate according to a second embodiment of the present invention. 7 is a cross-sectional view of the thin film transistor substrate according to the second embodiment of the present invention shown in FIG. 6 taken along line III-III'.

6 and 7 , the thin film transistor substrate according to the second exemplary embodiment of the present invention includes a gate line GL and a data line DL that cross each other on the substrate SUB. A gate line GL and a data line DL crossing each other with the gate insulating layer GI interposed therebetween define a pixel area. At one side of the pixel region, the gate electrode G branched from the gate line GL, the source electrode S branched from the data line DL, and the drain electrode disposed to face the source electrode D at a predetermined distance from each other. A thin film transistor T including (D) is disposed.

A semiconductor layer A is formed on the gate insulating layer GI that covers the gate electrode G to overlap the gate electrode G. One side of the semiconductor layer (A) is in contact with the source electrode (S), and the other side is in contact with the drain electrode (D). The semiconductor layer (A) overlaps the gate electrode (G) to form a channel region (CA) between the source electrode (S) and the drain electrode (D). A first passivation layer PAS1 for protecting the device and a planarization layer PAC for planarization are sequentially formed on the thin film transistor T.

A pixel electrode PXL is formed on the planarization layer PAC. The pixel electrode PXL contacts the drain electrode D through the pixel contact hole PH passing through the planarization layer PAC and the first passivation layer PAS1 . The pixel electrode PXL is electrically connected to the drain electrode D to receive a data voltage. The pixel electrode PXL preferably has a rectangular shape having a maximum size in the pixel area.

A second passivation layer PAS2 is formed to cover the pixel electrode PXL. A common electrode COM is formed on the second passivation layer PAS2 . The common electrode COM includes slits COMS having a plurality of line segment shapes parallel to each other in the pixel area. The slits COMS are positioned to overlap the pixel electrode PXL. A common wiring CL is formed on the same layer as the common electrode COM. The common electrode COM is directly connected to the common line CL to receive a common voltage. The common wiring CL has a structure in which a transparent layer TP and an opaque layer OP are stacked. The transparent layer TP of the common wiring COM and the common electrode COM are formed as a connected body. That is, the transparent layer TP formed of the transparent conductive material is located in both the region where the common electrode COM and the common wiring CL are formed, and the opaque layer OP formed of the low resistance opaque conductive material is the common wiring CL. It is located in the region where it is formed. Accordingly, the common wiring CL has a double-layer structure including the transparent layer TP and the opaque layer OP, and the common electrode COM has a single-layer structure including the transparent layer TP. The transparent layer TP of the common line CL has a first width W1', and the opaque layer OP of the common line CL has a second width W2'. The first width W1' is wider than the second width W2'. The slits COMS branched from the common electrode COM have a third width W3 ′. The third width W3' is narrower than the first width W1'.

The common wiring CL is formed on a different layer from the gate wiring GL. Accordingly, the common line CL can minimize or overlap the gap M2 with the gate line GL without structural restrictions depending on the location of the gate line GL, such as a short circuit problem with the gate line GL. there is. Accordingly, according to the present invention, it is not necessary to secure the separation distance M1 ( FIG. 1 ) for preventing a short circuit between the common line CL and the gate line GL as in the prior art. That is, assuming that the widths of the common line CL and the gate line GL, which are non-opening areas, are the same, the present invention reduces the gap between the common line CL and the gate line GL in the limited pixel area. The opening area can be sufficiently secured within the area. Accordingly, the present invention can prevent an increase in the non-opening according to the separation distance M1 ( FIG. 1 ) between the common line CL and the gate line GL, thereby providing a thin film transistor substrate having an improved aperture ratio.

Hereinafter, a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention will be described with reference to FIGS. 8A to 8G . 8A to 8G are views for explaining a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention, which is cut along the perforated line III-III' in FIG. 6 .

Referring to FIG. 8A , a gate metal material is coated on a substrate SUB and patterned by a mask process to form a gate line GL and a gate electrode G branched from the gate line GL. Since the mask process may be performed by a known method, a detailed description thereof will be omitted. A gate insulating layer GI is coated on the substrate SUB on which the gate wiring GL and the gate electrode G are formed.

Referring to FIG. 8B , a semiconductor material is coated on the substrate SUB on which the gate insulating layer GI is formed. A semiconductor layer (A) overlapping the gate electrode (G) is formed by patterning the semiconductor material through a mask process. A source-drain metal material is deposited on the substrate SUB on which the semiconductor layer A is formed. A source electrode (S) and a drain electrode (D) are formed by patterning a source-drain metal material through a mask process. The source electrode S contacts one side of the semiconductor layer A, and the drain electrode D contacts the other side of the semiconductor layer A. The source electrode S and the drain electrode D are separated from each other and are formed to be spaced apart from each other by a predetermined interval. Thereby, the thin film transistor T having the gate electrode G, the semiconductor layer A, the source electrode A, and the drain electrode D is completed. A first passivation layer PAS1 is formed by coating an insulating material on the substrate SUB on which the thin film transistor T is formed.

Referring to FIG. 8C , a planarization layer PAC is formed by coating an organic material on the substrate SUB on which the first passivation layer PAS1 is formed. A pixel contact hole PH is formed by patterning the first passivation layer PAS1 and the planarization layer PAC through a mask process. A portion of the drain electrode D is exposed through the pixel contact hole PH.

Referring to FIG. 8D , a transparent conductive material is deposited on the substrate SUB on which the planarization layer PAC is formed. The transparent conductive material may be ITO or IZO, but is not limited thereto. A pixel electrode PXL is formed by patterning a transparent conductive material through a mask process. A second passivation layer PAS2 is formed by coating an insulating material on the substrate SUB on which the pixel electrode PXL is formed.

8E to 8G , a transparent conductive material (TPM) and a low resistance opaque conductive material (OPM) are continuously deposited on the substrate SUB on which the planarization layer PAC is formed. A common wiring CL and a common electrode COM are formed by patterning the transparent conductive material TPM and the opaque conductive material OPM through a mask process. A preferred embodiment of the present invention is characterized in that the common wiring CL is formed together when the common electrode COM is formed without a separate mask process for forming the common wiring CL.

In order to simultaneously pattern different materials, a diffractive mask or a halftone mask may be used. However, when such a diffraction mask or a halftone mask is used, there is a problem in that the uniformity of the structure to be formed is significantly reduced. In particular, such as the slits COMS of the common electrode COM, when it is required to finely pattern the width in order to improve the light transmission efficiency, the problem becomes more serious. When the pattern formation uniformity of the slits COMS is low, the luminance deviation in the panel becomes severe, thereby degrading the display quality.

In a preferred embodiment of the present invention, the above-described problem is solved through a conductive material having an etch selectivity and an over-etch process using the conductive material. The opaque conductive material (OPM) uses a material having a large etch selectivity difference from that of the transparent conductive material (TPM).

A photoresist is applied on successively deposited transparent conductive material (TPM) and opaque conductive material (OPM), and a mask is prepared to pattern the same. The photoresist may be of a negative type or a positive type. In the following description, a case in which the photoresist is a positive type will be described as an example.

The photoresist is selectively irradiated with light through the mask. When the photoresist exposed through the mask is developed, the photoresist in the area irradiated with light is removed and the photoresist PR1 and PR2 in the area to which the light is not irradiated remain. The photoresists PR1 and PR2 remain in regions where the common wiring CL and the common electrode COM ( FIG. 3 ) are to be disposed. The slits COMS branched from the common electrode COM are formed to have a narrow width in a fine pattern, and the common line CL is formed to have a relatively wide width to reduce resistance. Accordingly, the photoresist PR1 remaining at the position where the slits COMS are to be formed has a narrower width than the photoresist PR2 remaining at the position where the common wiring CL is to be formed.

Then, the transparent conductive material (TPM) and the opaque conductive material (OPM) are patterned through an etching process. The over-etching process is performed until the opaque conductive material OPM positioned in the region where the slits COMS is formed is completely removed. A portion of the opaque conductive material OPM positioned in the region where the common line CL is formed remains. Since the opaque conductive material OPM and the transparent conductive material TPM have a large difference in etch selectivity, the transparent conductive material TPM may maintain a preset width even if the opaque conductive material OPM is over-etched. Accordingly, slits COMS having a single layer structure having a transparent layer TP are formed, and a common wiring CL having a double layer structure in which a transparent layer TP and an opaque layer OP are stacked is formed. The slits COMS have a structure directly branched from the transparent layer TP of the common wiring CL. A common voltage is applied to the common line CL.

The transparent layer TP of the common wiring CL has a first width W1 . The opaque layer OP of the common line CL has a second width W2 that is narrower than the first width W1 . The opaque layer OP of the common wiring CL is formed of a low-resistance conductive material and has a predetermined width in consideration of resistance. The slits COMS are preferably formed in a fine pattern to improve light transmission efficiency. The slits COMS are formed to have a third width W3 narrower than the first width W1 . also. The third width W3 is preferably narrower than the second width W2 .

In the present invention, the transparent layer TP of the common wiring CL and the common electrode COM are formed as one body. However, since the common electrode COM is formed of a high-resistance transparent material such as ITO, it is necessary to further form a low-resistance metal wire to smoothly apply a common voltage to the pixel regions. To this end, the present invention can solve the above-mentioned problems by laminating an opaque layer OP made of a low-resistance opaque conductive material on the transparent layer TP.

In the present invention, when the common electrode COM is formed, the transparent layer TP and the opaque layer OP of the common wiring CL may be formed together. Therefore, in the present invention, since an additional process for forming the opaque layer OP of the common wiring CL is not required, it is possible to prevent a problem of a decrease in yield due to the addition of the process, and to prevent an increase in manufacturing cost and manufacturing time. can do.

In the present invention, in order to simultaneously form a single-layer common electrode COM and a double-layer common wiring CL, a full tone mask is used without using a diffraction mask or a half-tone mask. to perform an over-etching process. Accordingly, the present invention can provide a thin film transistor substrate having improved pattern uniformity compared to the case of using a diffraction mask or a halftone mask.

Those skilled in the art through the above description will be able to make various changes and modifications without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

PXL: pixel electrode COM: common electrode
LS: light blocking layer CA: channel region
TP: Transparent layer OP: Opaque layer
COMS: Slit CL: Common wiring
W1: first width W2: second width
W3: third width

Claims (9)

a thin film transistor disposed on either side of the pixel area;
a pixel electrode connected to the thin film transistor;
a common electrode overlapping the pixel electrode with an insulating layer interposed therebetween;
a double electrode layer disposed on the same layer as an upper electrode among the pixel electrode and the common electrode and having a transparent layer of a first width and an opaque layer of a second width disposed on the transparent layer;
The transparent layer and the opaque layer are configured to have an etch selectivity,
The electrode positioned on an upper layer of the pixel electrode and the common electrode is made of the same material as the transparent layer, has a third width, and includes a plurality of slits branched from the electrode,
The first width is wider than the second width,
The third width is narrower than the first width and the second width. delete delete delete The method of claim 1,
The opaque layer is
A thin film transistor substrate overlapping a channel region of the thin film transistor. The method of claim 1,
The double electrode layer,
A thin film transistor substrate as a common wiring connected to the common electrode to apply a common voltage. 7. The method of claim 6,
The transparent layer is
A thin film transistor substrate having a single body with the common electrode. 7. The method of claim 6,
The pixel area is defined by crossing a gate line and a data line,
The common wiring is
A thin film transistor substrate disposed on a layer different from the gate wiring. 9. The method of claim 8,
The common wiring is
A thin film transistor substrate overlapping the gate wiring.

Images