KR102382076B1 - Semiconductor package - Google Patents

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KR102382076B1
KR102382076B1 KR1020150045141A KR20150045141A KR102382076B1 KR 102382076 B1 KR102382076 B1 KR 102382076B1 KR 1020150045141 A KR1020150045141 A KR 1020150045141A KR 20150045141 A KR20150045141 A KR 20150045141A KR 102382076 B1 KR102382076 B1 KR 102382076B1
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South Korea
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package
circuit pattern
opening
conductive part
protective layer
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KR1020150045141A
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Korean (ko)
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KR20160116838A (en
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이지행
김동선
류성욱
서현석
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엘지이노텍 주식회사
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Priority to KR1020150045141A priority Critical patent/KR102382076B1/en
Publication of KR20160116838A publication Critical patent/KR20160116838A/en
Priority to KR1020220039119A priority patent/KR20220045128A/en
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Publication of KR102382076B1 publication Critical patent/KR102382076B1/en

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    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
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    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract

본 발명은 반도체 패키지에 관한 것으로, 하부 패키지; 상기 하부 패키지 상의 단차가 생성된 개구부를 포함하는 보호층; 상기 개구부를 통해 노출되는 상기 하부 패키지의 회로 패턴 상에 형성되는 도전부; 및 상기 도전부와 접속되는 상부 패키지;를 포함한다.The present invention relates to a semiconductor package, comprising: a lower package; a protective layer including an opening in which a step is created on the lower package; a conductive part formed on the circuit pattern of the lower package exposed through the opening; and an upper package connected to the conductive part.

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}Semiconductor package {SEMICONDUCTOR PACKAGE}

본 발명의 실시예는 반도체 패키지에 관한 것이다.An embodiment of the present invention relates to a semiconductor package.

반도체 기술의 발전과 함께 사용자의 요구에 따라 전자기기는 더욱 소형화/경량화하고 있으며, 이에 따라 동일 또는 이종의 반도체 칩들을 하나의 단위 패키지로 구현하는 멀티칩 패키징(Multi-Chip Packing) 기술이 사용되고 있다.With the development of semiconductor technology, electronic devices are becoming smaller/lighter according to user needs. Accordingly, multi-chip packaging technology that implements the same or different types of semiconductor chips into one unit package is used. .

이러한 멀티칩 패키징 중 패키지 기판 위에 패키지 기판을 적층하는 스택(stack) 타입을 패키지 온 패키지(Package on Package: PoP)라고 하며, 일반적으로 프로세서 다이가 실장된 하부 패키지와 메모리 다이가 실장된 상부 패키지가 솔더볼 부착(Solder Ball Attach) 방식 등을 통해 상호 접속되는 패키지를 말한다.Among such multi-chip packaging, a stack type in which a package substrate is stacked on a package substrate is called a package on package (PoP), and in general, a lower package in which a processor die is mounted and an upper package in which a memory die is mounted. It refers to a package that is interconnected through a solder ball attachment method, etc.

종래의 패키지 온 패키지형 반도체 패키지는 솔더볼 인쇄 및 리플로우 공정을 통해 두 개의 패키지를 연결하거나, 먼저 하부 패키지를 몰딩한 후 몰딩 부위에 비아(Via)를 형성하고, 솔더볼을 비아 내 인쇄하여 메모리 다이가 실장된 상부 패키지를 리플로우 공정을 통해 연결하는 방식을 적용하고 있다.In the conventional package-on-package type semiconductor package, two packages are connected through solder ball printing and reflow processes, or a lower package is first molded, then vias are formed in the molding area, and solder balls are printed in the vias to form a memory die. A method of connecting the upper package on which is mounted is applied through a reflow process.

종래 기술에 따른 패키지 온 패키지형 반도체 패키지는 고집적 및 고성능 구현을 위해 Die의 실장 개수를 늘리거나 수동소자를 탑재하기 위한 시도가 이루어 지고 있으며, 이를 구현하기 위해서는 패키지 간의 간격을 넓혀야 한다.In the package-on-package type semiconductor package according to the prior art, attempts have been made to increase the number of dies mounted or to mount passive devices in order to realize high integration and high performance.

그러나, 종래 기술에 따른 반도체 패키지는 패키지 간의 간격을 넓히기 위하여 솔더 볼(solder ball)의 크기 또는 높이를 크게 하는 경우에는, 솔더 볼에 크랙(crack) 또는 붕괴가 발생하는 문제점이 있었다.However, the semiconductor package according to the prior art has a problem in that the solder balls are cracked or collapsed when the size or height of the solder balls is increased in order to widen the distance between the packages.

본 발명은 전술한 문제를 해결하기 위해 안출된 것으로서, 하부 패키지 상의 단차가 생성된 보호층을 통해 미세 피치(pitch)의 인쇄회로기판 및 반도체 패키지를 제공하고, 종래 기술에 비해 구조를 단순화하여 구조적 견고성을 높이고 제조 비용을 절감하고자 한다.The present invention has been devised to solve the above-described problem, and provides a printed circuit board and a semiconductor package having a fine pitch through a protective layer in which a step on the lower package is generated, and by simplifying the structure compared to the prior art They want to increase robustness and reduce manufacturing costs.

또한, 본 발명은 상부 패키지와 하부 패키지 간의 간격을 증가시켜 실장되는 칩의 개수를 증가시켜 고밀도를 실현하고, 상부 패키지와 하부 패키지 간의 접합 신뢰성이 우수한 반도체 패키지를 제공하고, 상부 패키지의 적층 시에 안정적인 공정 수율을 확보하고자 한다.In addition, the present invention provides a semiconductor package that realizes high density by increasing the distance between the upper package and the lower package to increase the number of mounted chips, and has excellent bonding reliability between the upper package and the lower package, and when the upper package is stacked We want to secure a stable process yield.

전술한 문제를 해결하기 위한 본 실시예에 따른 반도체 패키지는 하부 패키지; 상기 하부 패키지 상의 단차가 생성된 개구부를 포함하는 보호층; 상기 개구부를 통해 노출되는 상기 하부 패키지의 회로 패턴 상에 형성되는 도전부; 및 상기 도전부와 접속되는 상부 패키지;를 포함한다.A semiconductor package according to the present embodiment for solving the above-described problem includes a lower package; a protective layer including an opening in which a step is created on the lower package; a conductive part formed on the circuit pattern of the lower package exposed through the opening; and an upper package connected to the conductive part.

본 발명의 다른 일실시예에 따르면, 상기 개구부의 단차는 상기 하부 패키지 측의 제1 단차부; 및 상기 제1 단차부 상의 제2 단차부;를 포함할 수 있다.According to another embodiment of the present invention, the step of the opening is a first step portion of the lower package side; and a second step portion on the first step portion.

본 발명의 다른 일실시예에 따르면, 상기 제1 단차부의 개구부의 폭은 상기 제2 단차부의 개구부의 폭보다 작게 형성될 수 있다.According to another embodiment of the present invention, the width of the opening of the first step portion may be formed to be smaller than the width of the opening of the second step portion.

본 발명의 다른 일실시예에 따르면, 상기 도전부는 금속 재료의 범프(bump) 형태로 형성될 수 있다.According to another embodiment of the present invention, the conductive part may be formed in the form of a bump of a metal material.

본 발명의 다른 일실시예에 따르면, 상기 도전부는 구리(Cu)를 포함할 수 있다.According to another embodiment of the present invention, the conductive part may include copper (Cu).

본 발명의 다른 일실시예에 따르면, 상기 회로 패턴과 상기 도전부 사이에 형성되는 회로 패턴 연장부;를 더 포함할 수 있다.According to another embodiment of the present invention, the circuit pattern extension portion formed between the circuit pattern and the conductive portion; may further include.

본 발명의 다른 일실시예에 따르면, 상기 도전부의 높이는 상기 하부 패키지에 실장되는 반도체 칩의 높이보다 크게 형성될 수 있다.According to another embodiment of the present invention, the height of the conductive portion may be greater than the height of the semiconductor chip mounted on the lower package.

본 발명의 다른 일실시예에 따르면, 상기 하부 패키지 및 상기 상부 패키지 중 적어도 어느 하나는, 반도체 칩이 실장된 인쇄회로기판을 포함하여 구성될 수 있다.According to another embodiment of the present invention, at least one of the lower package and the upper package may include a printed circuit board on which a semiconductor chip is mounted.

본 발명의 실시예에 따르면, 하부 패키지 상의 단차가 생성된 보호층을 통해 미세 피치(pitch)의 인쇄회로기판 및 반도체 패키지를 제공하고, 종래 기술에 비해 구조를 단순화하여 구조적 견고성을 높이고 제조 비용을 절감할 수 있다.According to an embodiment of the present invention, a printed circuit board and a semiconductor package of a fine pitch are provided through a protective layer having a step difference on the lower package, and the structure is simplified compared to the prior art to increase structural robustness and reduce manufacturing cost can save

또한, 본 발명의 실시예에 따르면, 상부 패키지와 하부 패키지 간의 간격을 증가시켜 실장되는 칩의 개수를 증가시켜 고밀도를 실현하고, 상부 패키지와 하부 패키지 간의 접합 신뢰성이 우수한 반도체 패키지를 제공할 수 있으며, 상부 패키지의 적층 시에 안정적인 공정 수율을 확보할 수 있다.In addition, according to an embodiment of the present invention, it is possible to provide a semiconductor package that realizes high density by increasing the number of mounted chips by increasing the gap between the upper package and the lower package, and has excellent bonding reliability between the upper package and the lower package. , it is possible to secure a stable process yield when stacking the upper package.

도 1은 본 발명의 일실시예에 따른 반도체 패키지를 도시한 도면이다.
도 2는 본 발명의 다른 일실시예에 따른 반도체 패키지의 보호층과 도전부를 도시한 도면이다.
도 3 내지 도 6은 본 발명의 일실시예에 따른 반도체 패키지의 제조 방법을 설명하기 위한 도면이다.1 is a diagram illustrating a semiconductor package according to an embodiment of the present invention.
2 is a view illustrating a protective layer and a conductive part of a semiconductor package according to another embodiment of the present invention.
3 to 6 are views for explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention.

이하에서는 첨부한 도면을 참조하여 바람직한 본 발명의 일실시예에 대해서 상세히 설명한다. 다만, 실시형태를 설명함에 있어서, 관련된 공지 기능 혹은 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그에 대한 상세한 설명은 생략한다. 또한, 도면에서의 각 구성요소들의 크기는 설명을 위하여 과장될 수 있으며, 실제로 적용되는 크기를 의미하는 것은 아니다.Hereinafter, an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, in describing the embodiment, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, a detailed description thereof will be omitted. In addition, the size of each component in the drawings may be exaggerated for explanation, and does not mean the size actually applied.

도 1은 본 발명의 일실시예에 따른 반도체 패키지를 도시한 도면이다.1 is a diagram illustrating a semiconductor package according to an embodiment of the present invention.

도 1을 참조하여 본 발명의 일실시예에 따른 반도체 패키지의 구성을 설명하기로 한다.A configuration of a semiconductor package according to an embodiment of the present invention will be described with reference to FIG. 1 .

도 1에 도시된 바와 같이 본 발명의 일실시예에 따른 반도체 패키지는 상부 패키지(400)가 하부 패키지(300) 상에 적층되어 이들이 서로 전기적으로 연결된 패키지 온 패키지(Package On Package: POP) 타입의 패키지로 구성될 수 있다.As shown in FIG. 1 , in the semiconductor package according to an embodiment of the present invention, an upper package 400 is stacked on a lower package 300 and the package on package (POP) type is electrically connected to each other. It can consist of packages.

본 발명의 일실시예에 따른 반도체 패키지는 하부 패키지(300), 상부 패키지(400) 및 도전부(500)를 포함하여 구성된다.A semiconductor package according to an embodiment of the present invention includes a lower package 300 , an upper package 400 , and a conductive part 500 .

하부 패키지(300)는 하부 패키지 기판(310) 상에 적어도 하나의 하부 소자(370)가 실장되며, 상부 패키지(400)는 상부 패키지 기판(410) 상에 적어도 하나의 상부 소자(430)가 실장된다. 한편, 상기 소자(340)는 반도체로 구성될 수 있다.In the lower package 300 , at least one lower device 370 is mounted on a lower package substrate 310 , and in the upper package 400 , at least one upper device 430 is mounted on an upper package substrate 410 . do. Meanwhile, the device 340 may be formed of a semiconductor.

이때, 상기 하부 패키지 기판(310)과 상부 패키지 기판(410) 중에서 적어도 어느 하나는 인쇄회로기판(PCB)으로 구성될 수 있다.In this case, at least one of the lower package substrate 310 and the upper package substrate 410 may be formed of a printed circuit board (PCB).

일례로서, 하부 패키지(300)는 하부 패키지 기판(310)과, 하부 패키지 기판 상에 실장된 하부 소자(370)를 포함할 수 있다. 하부 소자(370)가 복수개로 구성되는 경우에는 절연 물질층의 개재하에 적층될 수 있다.As an example, the lower package 300 may include a lower package substrate 310 and a lower device 370 mounted on the lower package substrate. When a plurality of lower elements 370 are formed, they may be stacked with an insulating material layer interposed therebetween.

하부 패키지 기판(310)의 하면에는 반도체 패키지를 외부 장치와 전기적으로 연결시키는 솔더볼 형태의 외부 단자(350)들이 구비될 수 있다.Solder ball-shaped external terminals 350 for electrically connecting the semiconductor package to an external device may be provided on the lower surface of the lower package substrate 310 .

유사하게, 상부 패키지(400)는 상부 패키지 기판(410)과, 그리고 상부 패키지 기판(410)의 상면 상에 실장된 상부 소자(430)를 포함할 수 있다. 상기 상부 소자(430)가 복수개로 구성되는 경우에는 절연성 물질막의 개재하에 적층될 수 있다.Similarly, the upper package 400 may include an upper package substrate 410 and an upper device 430 mounted on the upper surface of the upper package substrate 410 . When the upper element 430 is configured in plurality, it may be stacked with an insulating material layer interposed therebetween.

상부 소자(430)와 상부 패키지 기판(410)은 복수개의 본딩 와이어(442)를 통해 서로 전기적으로 연결될 수 있다.The upper device 430 and the upper package substrate 410 may be electrically connected to each other through a plurality of bonding wires 442 .

도전부(500)는 상기와 같이 구성되는 하부 패키지(300)에 접속된다.The conductive part 500 is connected to the lower package 300 configured as described above.

이때, 상기 하부 패키지(300)의 기판(310) 상에 회로 패턴(530)이 형성되고, 상기 도전부(510)는 상기 회로 패턴(530) 상에 형성될 수 있다.In this case, a circuit pattern 530 may be formed on the substrate 310 of the lower package 300 , and the conductive part 510 may be formed on the circuit pattern 530 .

보다 상세하게 설명하면, 도 1에 도시된 바와 같이 하부 패키지(300) 상에 보호층(505)이 형성되며, 상기 보호층(505)에는 단차가 형성된 개구부가 형성된다.More specifically, as shown in FIG. 1 , a protective layer 505 is formed on the lower package 300 , and an opening having a step is formed in the protective layer 505 .

이때, 상기 보호층(505)의 개구부의 단차는 제1 단차부(511)와 제2 단차부(512)를 포함하여 구성될 수 있으며, 상기 제1 단차부(511)는 하부 패키지(300) 측에 형성되고, 상기 제2 단차부(512)는 상기 제1 단차부(511) 상에 형성될 수 있다.In this case, the step of the opening of the protective layer 505 may include a first step 511 and a second step 512 , and the first step 511 is the lower package 300 . is formed on the side, and the second stepped portion 512 may be formed on the first stepped portion 511 .

한편, 도 1에 도시된 바와 같이 상기 제1 단차부(511)의 개구부의 폭은 상기 제2 단차부(512)의 개구부의 폭보다 작게 형성될 수 있다.Meanwhile, as shown in FIG. 1 , the width of the opening of the first stepped portion 511 may be smaller than the width of the opening of the second stepped portion 512 .

상기 도전부(500)는 상기 개구부를 통해 노출되는 회로 패턴(530) 상에 형성될 수 있으며, 상기 도전부(500)의 높이는 상기 하부 패키지(300)에 실장되는 소자(370)의 높이보다 크게 형성될 수 있다.The conductive part 500 may be formed on the circuit pattern 530 exposed through the opening, and the height of the conductive part 500 is greater than the height of the device 370 mounted on the lower package 300 . can be formed.

이때, 상기 도전부(510)는 금속 재료를 이용해 범프(bump) 형태로 형성될 수 있으며, 상기 금속 재료로는 구리(Cu)를 사용할 수 있다.
In this case, the conductive part 510 may be formed in a bump shape using a metal material, and copper (Cu) may be used as the metal material.

도 2는 본 발명의 다른 일실시예에 따른 반도체 패키지의 보호층과 도전부를 도시한 도면이다.2 is a view illustrating a protective layer and a conductive part of a semiconductor package according to another embodiment of the present invention.

도 2에 도시된 바와 같이 본 발명의 다른 일실시예에 따른 반도체 패키지는 회로 패턴(530), 보호층(505), 회로 패턴 연장부(535) 및 도전부(500)를 포함한다.As shown in FIG. 2 , the semiconductor package according to another embodiment of the present invention includes a circuit pattern 530 , a protective layer 505 , a circuit pattern extension part 535 , and a conductive part 500 .

도 2의 실시예에서는 회로 패턴(530) 상에 보호층(505)이 형성되며, 상기 보호층(505)의 개구부(501)의 단차는 상기 하부 패키지 측의 제1 단차부(511)와 상기 제1 단차부(511) 상의 제2 단차부(512)로 형성된다.In the embodiment of FIG. 2 , the protective layer 505 is formed on the circuit pattern 530 , and the step of the opening 501 of the protective layer 505 is different from that of the first step 511 on the lower package side. It is formed of the second step portion 512 on the first step portion 511 .

이때, 상기 제1 단차부(511)의 개구부의 폭은 상기 제2 단차부(512)의 개구부의 폭보다 작게 형성될 수 있다.In this case, the width of the opening of the first stepped portion 511 may be smaller than the width of the opening of the second stepped portion 512 .

또한, 상기 회로 패턴(530)에는 회로 패턴 연장부(535)가 형성되어 도전부(500)와 연결될 수 있다.In addition, a circuit pattern extension part 535 may be formed on the circuit pattern 530 to be connected to the conductive part 500 .

또한, 도 1의 실시예와 마찬가지로 상기 도전부(510)는 금속 재료를 이용해 범프(bump) 형태로 형성될 수 있으며, 상기 금속 재료로는 구리(Cu)를 사용할 수 있다.
Also, like the embodiment of FIG. 1 , the conductive part 510 may be formed in a bump shape using a metal material, and copper (Cu) may be used as the metal material.

도 3 내지 도 6은 본 발명의 일실시예에 따른 반도체 패키지의 제조 방법을 설명하기 위한 도면이다.3 to 6 are views for explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention.

이후부터는 도 3 내지 도 6을 참조하여 본 발명의 일실시예에 따른 반도체 패키지의 제조 방법을 설명하기 한다.Hereinafter, a method of manufacturing a semiconductor package according to an embodiment of the present invention will be described with reference to FIGS. 3 to 6 .

먼저, 도 3에 도시된 바와 같이 회로 패턴(530)이 형성된 하부 패키지 상에 제1 보호 재료층(510)을 형성한 후, 도 4에 도시된 바와 같이 상기 제1 보호 재료층(510)을 패터닝하여 제1 단차부(511)를 형성한다.First, as shown in FIG. 3 , a first protective material layer 510 is formed on the lower package on which the circuit pattern 530 is formed, and then, as shown in FIG. 4 , the first protective material layer 510 is formed. The first step portion 511 is formed by patterning.

이후에는, 도 5에 도시된 바와 같이 상기 제1 단차부(511) 상에 제2 보호 재료층(520)을 형성하고, 도 6에 도시된 바와 같이 상기 제2 보호 재료층(520)을 패터닝하여 제2 단차부(521)를 형성하여 개구부(501)에 단차가 형성된 보호층(505)을 완성한다.Thereafter, as shown in FIG. 5 , a second protective material layer 520 is formed on the first stepped portion 511 , and as shown in FIG. 6 , the second protective material layer 520 is patterned. Thus, the second step portion 521 is formed to complete the protective layer 505 in which the step is formed in the opening 501 .

도 6에 도시된 바와 같이 상기 제1 단차부(511)의 개구부의 폭(d1)은 상기 제2 단차부(512)의 개구부의 폭(d2)보다 작게 형성될 수 있다.6 , the width d1 of the opening of the first stepped portion 511 may be smaller than the width d2 of the opening of the second stepped portion 512 .

이상에서 설명한 바와 같이, 본 발명의 실시예에 따르면, 하부 패키지 상의 단차가 생성된 보호층을 통해 미세 피치(pitch)의 인쇄회로기판 및 반도체 패키지를 제공하고, 종래 기술에 비해 구조를 단순화하여 구조적 견고성을 높이고 제조 비용을 절감할 수 있다.As described above, according to an embodiment of the present invention, a printed circuit board and a semiconductor package having a fine pitch are provided through a protective layer in which a step is generated on the lower package, and the structure is simplified compared to the prior art to provide structural It can increase the robustness and reduce the manufacturing cost.

또한, 본 발명의 실시예에 따르면, 상부 패키지와 하부 패키지 간의 간격을 증가시켜 실장되는 칩의 개수를 증가시켜 고밀도를 실현하고, 상부 패키지와 하부 패키지 간의 접합 신뢰성이 우수한 반도체 패키지를 제공할 수 있으며, 상부 패키지의 적층 시에 안정적인 공정 수율을 확보할 수 있다.In addition, according to an embodiment of the present invention, it is possible to provide a semiconductor package that realizes high density by increasing the number of mounted chips by increasing the gap between the upper package and the lower package, and has excellent bonding reliability between the upper package and the lower package. , it is possible to secure a stable process yield when stacking the upper package.

전술한 바와 같은 본 발명의 상세한 설명에서는 구체적인 실시예에 관해 설명하였다. 그러나 본 발명의 범주에서 벗어나지 않는 한도 내에서는 여러 가지 변형이 가능하다. 본 발명의 기술적 사상은 본 발명의 전술한 실시예에 국한되어 정해져서는 안 되며, 특허청구범위뿐만 아니라 이 특허청구범위와 균등한 것들에 의해 정해져야 한다.In the detailed description of the present invention as described above, specific embodiments have been described. However, various modifications are possible without departing from the scope of the present invention. The technical spirit of the present invention should not be limited to the above-described embodiments of the present invention, and should be defined by the claims as well as the claims and equivalents.

300: 하부 패키지
310: 하부 패키지 기판
350: 외부 단자
370: 하부 소자
400: 상부 패키지
410: 상부 패키지 기판
430: 상부 소자
442: 본딩 와이어
501: 개구부
505: 보호층
511: 제1 단차부
521: 제2 단차부
530: 회로 패턴
535: 회로 패턴 연장부300: lower package
310: lower package substrate
350: external terminal
370: lower element
400: upper package
410: upper package substrate
430: upper element
442: bonding wire
501: opening
505: protective layer
511: first step part
521: second step part
530: circuit pattern
535: circuit pattern extension

Claims (8)

회로 패턴을 포함하는 하부 패키지;
상기 하부 패키지 상에 형성되고, 상기 회로 패턴의 상면을 노출하는 개구부를 포함하는 보호층;
상기 보호층의 상기 개구부를 통해 노출된 상기 회로 패턴의 상면에 배치되는 회로 패턴 연장부; 및
상기 회로 패턴 연장부 상에 형성되는 도전부; 및
상기 도전부와 접속되는 상부 패키지;를 포함하고,
상기 보호층은,
상기 회로 패턴 상에 배치되고, 상기 회로 패턴의 상면을 노출하는 제1 개구부를 포함하는 제1 단차부와,
상기 보호층의 상기 제1 단차부 상에 배치되고, 상기 제1 개구부의 폭보다 큰 제2 개구부를 포함하는 제2 단차부를 포함하고,
상기 회로 패턴 연장부는,
상기 보호층의 상기 제1 단차부의 상기 제1 개구부 내에 배치되는 제1 부분과,
상기 제1 부분 상에 배치되고, 상기 제2 단차부의 상기 제2 개구부 내에 배치되는 제2 부분을 포함하고,
상기 회로 패턴 연장부의 상기 제1 부분은, 상기 제1 단차부의 상기 제1 개구부의 내벽과 접촉하고,
상기 회로 패턴 연장부의 상기 제2 부분 및 상기 도전부는, 상기 제2 단차부의 상기 제2 개구부의 내벽과 접촉하지 않으며,
상기 도전부는 상기 제2 단차부의 상기 제2 개구부의 내벽과 이격되며,
상기 회로 패턴 연장부의 상기 제2 부분의 상면은,
상측 방향으로 볼록한 곡면을 가지는 제1 상면과,
상기 제1 상면으로부터 연장되고, 상기 도전부와 접촉하며, 하측 방향으로 오목한 곡면을 가지는 제2 상면을 포함하는, 반도체 패키지.a lower package including a circuit pattern;
a protective layer formed on the lower package and including an opening exposing an upper surface of the circuit pattern;
a circuit pattern extension portion disposed on an upper surface of the circuit pattern exposed through the opening of the protective layer; and
a conductive part formed on the circuit pattern extension part; and
Including; an upper package connected to the conductive part;
The protective layer is
a first step portion disposed on the circuit pattern and including a first opening exposing an upper surface of the circuit pattern;
and a second step portion disposed on the first step portion of the protective layer and including a second opening that is larger than a width of the first opening,
The circuit pattern extension part,
a first portion disposed in the first opening of the first stepped portion of the protective layer;
a second portion disposed on the first portion and disposed within the second opening of the second step portion;
The first portion of the circuit pattern extension portion is in contact with an inner wall of the first opening of the first step portion,
The second portion and the conductive portion of the circuit pattern extension do not contact an inner wall of the second opening of the second step portion,
The conductive part is spaced apart from the inner wall of the second opening of the second stepped part,
The upper surface of the second portion of the circuit pattern extension portion,
A first upper surface having a convex curved surface in an upward direction;
and a second upper surface extending from the first upper surface, in contact with the conductive part, and having a curved surface concave in a downward direction. 청구항 1에 있어서,
상기 도전부는,
금속 재료의 범프(bump) 형태로 형성되는 반도체 패키지.The method according to claim 1,
The conductive part,
A semiconductor package formed in the form of a bump of a metal material. 청구항 1에 있어서,
상기 도전부는,
구리(Cu)를 포함하는 반도체 패키지.The method according to claim 1,
The conductive part,
A semiconductor package including copper (Cu). 삭제delete 삭제delete 삭제delete 청구항 1에 있어서,
상기 도전부의 높이는,
상기 하부 패키지에 실장되는 반도체 칩의 높이보다 크게 형성되는 반도체 패키지.The method according to claim 1,
The height of the conductive part,
A semiconductor package formed to be greater than a height of a semiconductor chip mounted on the lower package. 청구항 1에 있어서,
상기 하부 패키지 및 상기 상부 패키지 중 적어도 어느 하나는,
반도체 칩이 실장된 인쇄회로기판을 포함하여 구성되는 반도체 패키지.
The method according to claim 1,
At least one of the lower package and the upper package,
A semiconductor package comprising a printed circuit board on which a semiconductor chip is mounted.
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