CN104409448A - Semiconductor package and manufacture method thereof - Google Patents
Semiconductor package and manufacture method thereof Download PDFInfo
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- CN104409448A CN104409448A CN201410674592.5A CN201410674592A CN104409448A CN 104409448 A CN104409448 A CN 104409448A CN 201410674592 A CN201410674592 A CN 201410674592A CN 104409448 A CN104409448 A CN 104409448A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor package and a manufacture method thereof. The semiconductor package comprises a base plate with an occupied area, a first chip installed on the base plate and located in the occupied area of the base plate, a second chip which is arranged on the first chip, and comprises a first portion arranged in the occupied area and a second portion arranged on the exterior of the occupied area, and a packaging component which packages the first chip and the second chip, and comprises a substrate portion arranged in the occupied area and a suspended portion arranged on the exterior of the occupied area, wherein the substrate portion comprises a first portion of the second chip, the suspended portion comprises a second portion of the second chip, and the lower portion of the suspended portion is recessed towards the second portion of the second chip so as to limit an indentation. The semiconductor package can contain a chip large in size on the premise of not increasing the occupied area. Additionally, the semiconductor package can facilitate guaranteeing of electrical performance of a chip relatively small in size.
Description
Technical field
The present invention relates to the field of semiconductor device, more particularly, relate to a kind of semiconductor packages and manufacture method thereof.
Background technology
Along with the size of electronic installation is more and more less, realize high integration density by multiple chip stacking in a semiconductor packages.In multilayered semiconductor chip package, multiple bare chip can be stacked on substrate one by one along the direction perpendicular to substrate, each bare chip is electrically connected with substrate by the mode then by wire bonding.
Fig. 1 is the schematic cross sectional views that traditional semiconductor packages 100 is shown.With reference to Fig. 1, semiconductor packages 100 comprises substrate 110, is in turn layered in the first chip 121, second chip 122, the 3rd chip 123 and the 4th chip 124 on substrate 110, is all stacked on the 5th chip 130, the 6th chip 141 and the 7th chip 142 on the 4th chip 124, and encapsulating the first chip 121 is to the encapsulating component 150 of the 7th chip 142.Each in first chip 121, second chip 122, the 3rd chip 123 and the 4th chip 124 has larger size, and can be such as nand flash memory chip.Each in 5th chip 130, the 6th chip 141 and the 7th chip 142 has less size, and the 5th chip 130 can be such as controller chip, and the 6th chip 141 and the 7th chip 142 can be all such as dram chips.First chip 121 is electrically connected to each other to the 7th chip 142 by corresponding bonding line 171,172,173,174 and 175 or is electrically connected to substrate 110.Semiconductor packages 100 also can comprise the external connection terminals 160 on the surface contrary to the surface of the 7th chip 142 with being provided with the first chip 121 being attached to substrate 110.
Because the first chip 121 has the size larger than the 5th chip 130, the 6th chip 141 and the 7th chip 142 to each in the 4th chip 124, so in order to engineering stability, first chip 121 to the 4th chip 124 is stacked on below, and the 5th chip 130, the 6th chip 141 and the 7th chip 142 are arranged on the first chip 121 on the 4th chip 124.As a result, the 5th chip 130, the 6th chip 141 and the 7th chip 142 are electrically connected to the length of the bonding line 173,174 and 175 of substrate 110, thus affect the electrical property of the 5th chip 130, the 6th chip 141 and the 7th chip 142.Especially, when the 5th chip 130 is controller chip and the 6th chip 141 and the 7th chip 142 are dram chips, the electrical property of controller chip and dram chip is subject to larger impact.
In addition, along with the trend of the miniaturization of electronic installation, the occupied area (footprint) (such as, being encapsulated in the occupied area on SMT plate) of encapsulation is restricted.But in order to obtain large capacity, chip becomes increasing.The encapsulation that occupied area is restricted can not hold large chip.Therefore, the size of chip can only be reduced and the quantity of chip increased in an encapsulation, but this problem causing productive rate/yield of chip and/or encapsulation to reduce.
Summary of the invention
One object of the present invention is to provide the semiconductor packages of at least one in a kind of can solving the problems of the technologies described above and manufacture method thereof.
Another object of the present invention is to provide a kind of semiconductor packages and the manufacture method thereof that can hold large size chip when not increasing occupied area (footprint).
Another object of the present invention is to provide a kind of semiconductor packages and the manufacture method thereof that are conducive to the electrical property ensureing relatively little chip.
Semiconductor packages according to the present invention comprises: substrate, has occupied area; First chip, to be arranged on substrate and to be positioned at the occupied area of substrate; Second chip, is arranged on the first chip, and comprises the Part I be arranged in occupied area and the Part II being arranged on outside, occupied area; And encapsulating component, encapsulate the first chip and the second chip, and comprise the body portion be arranged in occupied area and the overhanging portion being arranged on outside, occupied area, body portion encapsulates the Part I of the second chip, overhanging portion encapsulates the Part II of the second chip, wherein, the bottom of overhanging portion is recessed towards the Part II of the second chip, to limit depression.
According to an aspect of the present invention, the size of the second chip is greater than, is equal to or less than the size of occupied area.
According to an aspect of the present invention, the second chip on the direction being basically parallel to substrate relative to the first chip offset.
According to an aspect of the present invention, described semiconductor packages also comprises the 3rd chip be arranged between substrate and the second chip, and the 3rd chip is positioned at the occupied area of substrate.
According to an aspect of the present invention, described semiconductor packages also comprises the 4th chip be arranged on the second chip, 4th chip comprises the Part I be arranged in occupied area and the Part II being arranged on outside, occupied area, the Part I of body portion encapsulating the 4th chip of encapsulating component, the Part II of overhanging portion encapsulating the 4th chip of encapsulating component.
According to an aspect of the present invention, the 4th chip on the direction being basically parallel to substrate relative to the second chip offset.
According to an aspect of the present invention, overhanging portion has upper surface, from the outer end of upper surface to the side surface of downward-extension, and extend to the lower surface of lower end of side surface from the edge of substrate, or overhanging portion has upper surface and extends to the lower surface of outer end of upper surface from the edge of substrate.
According to an aspect of the present invention, the lower surface of overhanging portion has the shape of arcs of recesses, convex, straight line, broken line, parabola or wave.
According to an aspect of the present invention, described semiconductor packages also comprises the external connection terminals be arranged on the surface contrary with the surface it being provided with the first chip and the second chip of substrate.
Manufacture method according to semiconductor packages of the present invention comprises: provide size to be greater than the substrate precursor of substrate; Substrate precursor installed the first chip and the second chip is set on the first chip, encapsulating the first chip and the second chip with encapsulating component precursor; The marginal portion of removing substrate precursor and the part encapsulating component precursor be arranged on the marginal portion of substrate precursor, thus obtain substrate and encapsulating component.
Accompanying drawing explanation
By below in conjunction with the description of accompanying drawing to embodiment, above and/or other side of the present invention and advantage will become to be known and is easier to understand, in the accompanying drawings:
Fig. 1 is the schematic cross sectional views that traditional semiconductor packages is shown;
Fig. 2 is the schematic cross sectional views of the semiconductor packages illustrated according to the first exemplary embodiment of the present invention;
Fig. 3 is the schematic, bottom view of the semiconductor packages illustrated according to the first exemplary embodiment of the present invention;
Fig. 4 is the schematic cross sectional views of the semiconductor packages illustrated according to the second exemplary embodiment of the present invention;
Fig. 5 is the schematic cross sectional views of the semiconductor packages illustrated according to the third exemplary embodiment of the present invention;
Fig. 6 illustrates that the semiconductor packages according to the third exemplary embodiment of the present invention installs the schematic cross sectional views of state onboard;
Fig. 7 is the schematic cross sectional views of the semiconductor packages illustrated according to the fourth exemplary embodiment of the present invention;
Fig. 8 is the schematic plan view of the semiconductor packages illustrated according to the fifth exemplary embodiment of the present invention;
Fig. 9 illustrates the schematic cross sectional views intercepted along the A-A ' line in Fig. 8 according to the semiconductor packages of the fifth exemplary embodiment of the present invention;
Figure 10 illustrates the schematic cross sectional views intercepted along the B-B ' line in Fig. 8 according to the semiconductor packages of the fifth exemplary embodiment of the present invention; And
Figure 11 and Figure 12 illustrates the cutaway view manufactured according to the method for the semiconductor packages of the first exemplary embodiment of the present invention at least in part.
Embodiment
Hereinafter, come with reference to the accompanying drawings to describe the present invention more fully, embodiments of the invention shown in the drawings.The present invention can implement in a number of different ways, and should not be understood to the embodiment that is confined to set forth here.In the accompanying drawings, for clarity, the size in layer and region can be exaggerated.
Fig. 2 is the schematic cross sectional views of the semiconductor packages 200 illustrated according to the first exemplary embodiment of the present invention, and Fig. 3 is the schematic, bottom view of the semiconductor packages 200 illustrated according to the first exemplary embodiment of the present invention.With reference to Fig. 2 and Fig. 3, comprise substrate 210, in turn stacked the first chip 221, second chip 222, the 3rd chip 223 and the 4th chip 224 over the substrate 210 and encapsulating the first chip 221 encapsulating component 250 to the 4th chip 224 according to the semiconductor packages 200 of the first exemplary embodiment of the present invention.Substrate 110 has occupied area (footprint) F, and the first chip 221 is arranged in the F of occupied area, and the second chip 222, the 3rd chip 223, the 4th chip 224 and encapsulating component 250 all have the part being arranged on F outside, occupied area.
Substrate 210 can be printed circuit board (PCB) (PCB).Substrate 210 has the lower surface of upper surface and relative with upper surface (or back to upper surface).The inside that substrate 210 can comprise setting upper pad (not shown) on an upper, arrange lower pad (not shown) on the lower surface and be arranged on substrate 210 is with the inner lead be electrically connected with lower pad by upper pad.Substrate 210 can have occupied area F, the occupied area F such as limited by the edge 210e of substrate 210, or as is known in the art, the occupied area that the region limited than the edge 210e by substrate 210 is large or little.Here, occupied area F can be the upright projection region of substrate 210 on the plate of such as SMT plate.
First chip 221 is installed over the substrate 210 and is electrically connected to substrate 210.First chip 221 passes through the mode formal dress of wire bonding over the substrate 210.Specifically, non-active of first chip 221 (namely, in the face of the surface of substrate 210) the wafer support portion of substrate 210 is attached to by adhesive die attachment film, the upper pad arranged of first chip 221 active surface (that is, back to the surface of substrate 210) is electrically connected to the upper pad of substrate 210 by bonding line 271.Selectively, the first chip 221 can upside-down mounting over the substrate 210 and be electrically connected to substrate 210.In this case, the active surface of the first chip 221 (namely, in the face of the surface of substrate 210) to be arranged on by projection (bump) and to be electrically connected to the upper pad of substrate 210, non-active of the first chip 221 can back to the upper surface of substrate 210.First chip 221 installation form is over the substrate 210 not limited to formal dress or upside-down mounting.
Second chip 222, the 3rd chip 223 and the 4th chip 224 are in turn layered on the first chip 221, and offset relative to the first chip 221 on the direction being basically parallel to substrate 210.More particularly, as shown in Figure 2, the second chip 222 is layered on the first chip 221, and direction to the right offsets to expose the pad area on the first chip 221 active surface relative to the first chip 221; 3rd chip 223 is layered on the second chip 222, and direction to the right offsets to expose the pad area on the second chip 222 active surface relative to the second chip 222; 4th chip 224 is layered on the 3rd chip 223, and direction to the right offsets to expose the pad area on the 3rd chip 223 active surface relative to the 3rd chip 223.Second chip 222 formal dress is on the first chip 221, and the 3rd chip 223 formal dress is on the second chip 222, and the 4th chip 224 formal dress is on the 3rd chip 223.Each bonding line 271 by being connected to the pad on its active surface in second chip 222, the 3rd chip 223 and the 4th chip 224 is electrically connected to each other and/or is electrically connected to the upper pad of substrate 210.Selectively, the installation form of the second chip 222, the 3rd chip 223 and the 4th chip 224 can be upside-down mounting, in this case, each in the second chip 222, the 3rd chip 223 and the 4th chip 224 there is no need in one direction relative to the chip offset below it.
The entirety of the first chip 221 can be arranged in the F of occupied area, and such as, the entirety of the first chip 221 can be arranged in the Free Region of the upper surface of substrate 210.Second chip 222 can comprise the Part I 222a be arranged in the F of occupied area and the Part II 222b being arranged on F outside, occupied area, and Part I 222a and Part II 222b can form as one.3rd chip 223 can comprise the Part I 223a be arranged in the F of occupied area and the Part II 223b being arranged on F outside, occupied area, and Part I 223a and Part II 223b can form as one.4th chip 224 can comprise the Part I 224a be arranged in the F of occupied area and the Part II 224b being arranged on F outside, occupied area, and Part I 224a and Part II 224b can form as one.
Although illustrated in Fig. 2 that the first chip 221 to the 4th chip 224 has substantially the same size (such as, width, length, diameter or span etc.), the present invention is not limited thereto.Second chip 222 to the 4th chip 224 all can have the size larger than the first chip 221.Selectively, the second chip 222 to the 4th chip 224 all can have the size less than the first chip 221.Second chip 222 all can have the size larger than occupied area F to the 4th chip 224.Selectively, the second chip 222 all can have equal with occupied area F or less than occupied area F size to the 4th chip 224.That is, the second chip 222 is not particularly limited to the size of the 4th chip 224.
Encapsulating component 250 encapsulates the first chip 221 to the 4th chip 224, is not subject to the impact of external environment or external impact to protect the first chip 221 to the 4th chip 224.Encapsulating component 250 also can encapsulate the upper surface of substrate 210 at least partially.In one embodiment, encapsulate component 250 and encapsulate upper surface whole of the first chip 221 to the 4th chip 224 and substrate 210.Encapsulating component 250 can be the epoxy molding plastic of solidification, and the epoxy molding plastic of solidification can comprise the inserts of epoxy resin and the such as silica such as solidified.
Encapsulating component 250 can comprise the body portion 250a be arranged in the F of occupied area and the overhanging portion 250b being arranged on F outside, occupied area.Therefore, body portion 250a encapsulates the Part II 224b that Part I 222a, the Part I 223a of the 3rd chip 223 of the first chip 221, second chip 222 and the Part I 224a of the 4th chip 224, overhanging portion 250b encapsulate the Part II 222b of the second chip 222, the Part II 223b of the 3rd chip 223 and the 4th chip 224.
The Part II 224b encapsulating the Part II 222b of bottom towards the second chip 222 of the overhanging portion 250b of component 250, the Part II 223b of the 3rd chip 223 and the 4th chip 224 is recessed into, to limit depression R.
With reference to Fig. 2, the overhanging portion 250b of encapsulating component 250 can have upper surface 250b1 (such as, substantially parallel with the upper surface of substrate 210), from the outer end of upper surface 250b1 to downward-extension (such as, the direction of upper surface along being basically perpendicular to substrate 210) side surface 250b2, and extend to the lower surface 250b3 of the lower end of side surface 250b2 obliquely from the edge 210e of substrate 210.Here, lower surface 250b3 has the shape of arcs of recesses substantially; But the present invention is not limited thereto, the lower surface 250b3 of the overhanging portion 250b of encapsulating component 250 can have the shapes such as convex, straight line, broken line, parabola, wave.Here, encapsulating component 250 comprises side surface 250b2, but the present invention is not limited thereto, and lower surface 250b3 can be directly connected to the outer end of upper surface 250b1 obliquely, thus omits side surface 250b2.
As mentioned above, the second chip 222, the 3rd chip 223, the 4th chip 224 all have the part being arranged on F outside, occupied area.Therefore, each size in second chip 222, the 3rd chip 223, the 4th chip 224 all can be greater than the size of occupied area F, therefore can hold according to the semiconductor packages 200 of the first exemplary embodiment of the present invention large chip that size is greater than occupied area F.
In addition, as mentioned above, the Part II 224b encapsulating the Part II 222b of bottom towards the second chip 222 of the overhanging portion 250b of component 250, the Part II 223b of the 3rd chip 223 and the 4th chip 224 is recessed into, to limit depression R.The space that depression R provides allows other device (such as, passive device) easily to install on the plate of such as SMT plate.Therefore, the occupied area F of substrate 210 or semiconductor packages 200 does not increase, thus improves the space availability ratio of the plate of such as SMT plate.
Therefore, when not increasing occupied area F, the semiconductor packages 200 according to the first exemplary embodiment of the present invention can hold large size chip.
Although described above is semiconductor packages 200 to comprise three chips 222,223 and 224 extending beyond occupied area F, the present invention is not limited thereto.Semiconductor packages can comprise at least one chip extending beyond occupied area F according to an exemplary embodiment of the present invention, such as one or two chip.
Semiconductor packages 200 also can comprise the external connection terminals 260 on the lower surface being arranged on substrate 210.External connection terminals 260 can be arranged on the lower pad on the lower surface of substrate 210.Therefore, the first chip 221 is electrically connected to external connection terminals 260 to the 4th chip 224 by substrate 210, particularly, is electrically connected to external connection terminals 260 by the upper pad of substrate 210, inner lead and lower pad.External connection terminals 260 can be soldered ball.Semiconductor packages 200 also can not comprise external connection terminals.
Fig. 4 is the schematic cross sectional views of the semiconductor packages 300 illustrated according to the second exemplary embodiment of the present invention.Have and the structure identical in fact according to the semiconductor packages 200 of the first exemplary embodiment of the present invention described that see figures.1.and.2 according to the semiconductor packages 300 of the second exemplary embodiment of the present invention, therefore the same or analogous Reference numeral of use is represented the element identical with the element in semiconductor packages 200.Description is below by the difference that concentrates between semiconductor packages 300 and semiconductor packages 200.
With reference to Fig. 4, comprise substrate 310 according to the semiconductor packages 300 of the second exemplary embodiment of the present invention, be all directly installed on the first chip 330, second chip 341 on substrate 310 and the 3rd chip 342, be in turn layered in the 4th chip 321 on the first chip 330, second chip 341 and the 3rd chip 342 and the 5th chip 322, and encapsulating the first chip 330 is to the encapsulating component 350 of the 5th chip 322.
In first chip 330, second chip 341 and the 3rd chip 342 each can formal dress or upside-down mounting on substrate 310.Each in first chip 330, second chip 341 and the 3rd chip 342 has less size, its entirety can be arranged in the F of occupied area, such as, each entirety in the first chip 330, second chip 341 and the 3rd chip 342 can be arranged in the Free Region of the upper surface of substrate 310.First chip 330 can be such as controller chip, and the second chip 341 and the 3rd chip 342 can be all such as dram chips.
Because each in the first chip 330, second chip 341 and the 3rd chip 342 is all directly installed on substrate 310, and be chip nearest from substrate 310 in the first chip 330 to the 5th chip 322, so the length each in the first chip 330, second chip 341 and the 3rd chip 342 being electrically connected to the bonding line of substrate 310 or projection is little, thus the electrical property of the first chip 330, second chip 341 and the 3rd chip 342 can not be affected.Especially, when the first chip 330 is controller chip and/or the second chip 341 and the 3rd chip 342 is dram chips, the electrical property of the first chip 330, second chip 341 and the 3rd chip 342 is guaranteed.
With reference to Fig. 4, the 4th chip 321 and the 5th chip 322 are electrically connected to substrate 310 respectively by bonding line 371 and bonding line 372, and the 5th chip 322 adheres to the 4th chip 321 by adhesive die attachment film 380.But the mounting means of the 4th chip 321 and the 5th chip 322 is not limited to formal dress, its can successively upside-down mounting on the first chip 330, second chip 341 and the 3rd chip 342.
The size of the 4th chip 321 and the 5th chip 322 is all greater than each size in the first chip 330, second chip 341 and the 3rd chip 342.Because the first chip 330, second chip 341 and the 3rd chip 342 all have substantially the same thickness, so the 4th chip 321 and the 5th chip 322 can suitably be arranged on the first chip 330, second chip 341 and the 3rd chip 342.4th chip 321 and the 5th chip 322 have substantially the same size, and relative to each other do not offset; But the present invention is not limited thereto, the 4th chip 321 and the 5th chip 322 can be of different sizes, or can relative to each other offset.4th chip 321 and the 5th chip 322 all can have the size being greater than, being equal to or less than occupied area F.
4th chip 321 and the 5th chip 322 and encapsulating component 350 all have the part being arranged on F outside, occupied area.Here, 4th chip 321 and the 5th chip 322 and encapsulating component 350 and the second chip 222 described with reference to Fig. 2, the 3rd chip 223, the 4th chip 224 and encapsulate component 250 can be identical in fact and effect identical in fact can be realized, therefore will the detailed description of omission to them.
Fig. 5 is the schematic cross sectional views of the semiconductor packages 400 illustrated according to the third exemplary embodiment of the present invention.Have and the structure identical in fact according to the semiconductor packages 300 of the second exemplary embodiment of the present invention described with reference to Fig. 4 according to the semiconductor packages 400 of the third exemplary embodiment of the present invention, therefore the same or analogous Reference numeral of use is represented the element identical with the element in semiconductor packages 300.Description is below by the difference that concentrates between semiconductor packages 400 and semiconductor packages 300.
With reference to Fig. 5, comprise substrate 410 according to the semiconductor packages 400 of the third exemplary embodiment of the present invention, be all directly installed on the first chip 430, second chip 441 on substrate 410 and the 3rd chip 442, be in turn layered in the 4th chip 421, the 5th chip 422, the 6th chip 423 and the 7th chip 424 on the first chip 430, second chip 441 and the 3rd chip 442, and encapsulating the first chip 430 is to the encapsulating component 450 of the 7th chip 424.
As describe with reference to Fig. 2 according to the second chip 222 in the semiconductor packages 200 of the first exemplary embodiment of the present invention, the 3rd chip 223 and the 4th chip 224, with reference to Fig. 5, each in the 4th chip 421, the 5th chip 422, the 6th chip 423 and the 7th chip 424 all has the part be arranged in the F of occupied area and the part being arranged on F outside, occupied area.4th chip 421 all can have the size being greater than, being equal to or less than occupied area F to the 7th chip 424.
4th chip 421, the 5th chip 422, the 6th chip 423 and the 7th chip 424 are in turn layered on the first chip 430, second chip 441 and the 3rd chip 442, and offset relative to the first chip 430, second chip 441 and the 3rd chip 442 on the direction being basically parallel to substrate 410.More particularly, the 4th chip 421 is layered on the first chip 430, second chip 441 and the 3rd chip 442; 5th chip 422 is layered on the 4th chip 421, and direction to the right offsets to expose the pad area on the 4th chip 421 active surface relative to the 4th chip 421; 6th chip 423 is layered on the 5th chip 422, and direction to the right offsets to expose the pad area on the 5th chip 422 active surface relative to the 5th chip 422; 7th chip 424 is layered on the 6th chip 423, and direction to the right offsets to expose the pad area on the 6th chip 423 active surface relative to the 6th chip 423.4th chip 421 formal dress is on the first chip 430, second chip 441 and the 3rd chip 442, and the 5th chip 422 formal dress is on the 4th chip 421, and the 6th chip 423 formal dress is on the 5th chip 422, and the 7th chip 424 formal dress is on the 6th chip 423.
Encapsulating component 450 also has the body portion be arranged in the F of occupied area and the overhanging portion being arranged on F outside, occupied area.Here, encapsulating component 450 and the encapsulating component 250 described with reference to Fig. 2 can be identical in fact and can realize effect identical in fact, therefore will the detailed description of omission to it.
Fig. 6 illustrates that the semiconductor packages 400 according to the third exemplary embodiment of the present invention is arranged on the schematic cross sectional views of the state on plate 10.With reference to Fig. 6, semiconductor packages 400 is arranged on plate 10 under being arranged at the state between the plate 10 of substrate 410 and such as SMT plate with its external connection member 460 '.More specifically, can by the external connection terminals 460 of semiconductor packages 400 (such as, soldered ball) be arranged on the pad of plate 10, then perform Reflow Soldering and make external connection terminals 460 become external connection member 460 ', semiconductor packages 400 to be arranged on plate 10.
4th chip 421, the 5th chip 422, the 6th chip 423 and the 7th chip 424 all have the part being arranged on F outside, occupied area.Therefore, each size in 4th chip 421, the 5th chip 422, the 6th chip 423 and the 7th chip 424 all can be greater than the size of occupied area F, therefore can hold according to the semiconductor packages 400 of the third exemplary embodiment of the present invention large chip that size is greater than occupied area F.
In addition, the bottom of the overhanging portion of encapsulating component 450 is recessed towards the part being arranged on F outside, occupied area of the 4th chip 421, the 5th chip 422, the 6th chip 423 and the 7th chip 424, to limit depression R.The space that depression R provides allows other device 20 (such as, passive device) easily to install on plate 10.Therefore, the occupied area F of substrate 410 or semiconductor packages 400 does not increase, thus improves the space availability ratio of the plate of such as SMT plate.
Therefore, when not increasing occupied area F, the semiconductor packages 400 according to the third exemplary embodiment of the present invention can hold large size chip.
In addition, because each in the first chip 430, second chip 441 and the 3rd chip 442 is all directly installed on substrate 410, and be chip nearest from substrate 410 in the first chip 430 to the 7th chip 424, so the length each in the first chip 430, second chip 441 and the 3rd chip 442 being electrically connected to the bonding line of substrate 410 or projection is little, thus the electrical property of the first chip 430, second chip 441 and the 3rd chip 442 can not be affected.Especially, when the first chip 430 is controller chip and/or the second chip 441 and the 3rd chip 442 is dram chips, the electrical property of the first chip 430, second chip 441 and the 3rd chip 442 is guaranteed.
Fig. 7 is the schematic cross sectional views of the semiconductor packages 500 illustrated according to the fourth exemplary embodiment of the present invention.Have and the structure identical in fact according to the semiconductor packages 400 of the third exemplary embodiment of the present invention described with reference to Fig. 5 according to the semiconductor packages 500 of the fourth exemplary embodiment of the present invention, therefore the same or analogous Reference numeral of use is represented the element identical with the element in semiconductor packages 400.Description is below by the difference that concentrates between semiconductor packages 500 and semiconductor packages 400.
With reference to Fig. 7, the overhanging portion 550b of encapsulating component 550 can have upper surface 550b1 (such as, substantially parallel with the upper surface of substrate 510), from the outer end of upper surface 550b1 to downward-extension (such as, the direction of upper surface along being basically perpendicular to substrate 510) side surface 550b2, and extend to the lower surface 550b3 of the lower end of side surface 550b2 from the edge 510e of substrate 510.Here, lower surface 550b3 has the shape of broken line, comprises the horizontal part of the rake extended from the edge 510e of substrate 510 and lower end rake being connected to side surface 550b2.
Fig. 8 is the schematic plan view of the semiconductor packages 600 illustrated according to the fifth exemplary embodiment of the present invention, Fig. 9 illustrates the schematic cross sectional views intercepted along the A-A ' line in Fig. 8 according to the semiconductor packages 600 of the fifth exemplary embodiment of the present invention, and Figure 10 illustrates the schematic cross sectional views intercepted along the B-B ' line in Fig. 8 according to the semiconductor packages 600 of the fifth exemplary embodiment of the present invention.Have and the structure identical in fact according to the semiconductor packages 400 of the third exemplary embodiment of the present invention described with reference to Fig. 5 according to the semiconductor packages 600 of the fifth exemplary embodiment of the present invention, therefore the same or analogous Reference numeral of use is represented the element identical with the element in semiconductor packages 400.Description is below by the difference that concentrates between semiconductor packages 600 and semiconductor packages 400.
With reference to Fig. 8 to Figure 10, semiconductor packages 600 is arranged on the first chip 630, second chip 641 on substrate 610 and the 3rd chip 642 except comprising, be in turn layered on the first chip 630, second chip 641 and the 3rd chip 642 the 4th chip 621, the 5th chip 622, the 6th chip 623 and the 7th chip 624 except, also comprise the 8th chip 625 be in turn layered on the 7th chip 624, the 9th chip 626, the tenth chip the 627 and the 11 chip 628.
4th chip 621, the 5th chip 622, the 6th chip 623 and the 7th chip 624 are in turn layered on the first chip 630, second chip 641 and the 3rd chip 642, and in the Y direction (such as, the longitudinal direction of semiconductor packages 600) on offset successively relative to the first chip 630, second chip 641 and the 3rd chip 642, to expose the pad area of the respective chip being positioned at bottom.8th chip 625, the 9th chip 626, the tenth chip the 627 and the 11 chip 628 are in turn layered on the 7th chip 624, and in X-direction (such as, the transverse direction of semiconductor packages 600) on offset successively relative to the 7th chip 624, to expose the pad area of the respective chip being positioned at bottom.
Each in 4th chip 621, the 5th chip 622, the 6th chip 623 and the 7th chip 624 includes the Part I be arranged in the F of occupied area and the Part II being arranged on F outside, occupied area in the Y direction.Each in 8th chip 625, the 9th chip 626, the tenth chip the 627 and the 11 chip 628 includes the Part I be arranged in the F of occupied area and the Part II being arranged on F outside, occupied area in the X direction.
Encapsulating component 650 comprises the body portion 650a be arranged in the F of occupied area and the first overhanging portion 650b being arranged on F outside, occupied area and the second overhanging portion 650b.First overhanging portion 650b encapsulates the Part II of the 4th chip 621, the 5th chip 622, the 6th chip 623 and the 7th chip 624, and the second overhanging portion 650b encapsulates the Part II of the 8th chip 625, the 9th chip 626, the tenth chip the 627 and the 11 chip 628.The bottom of the first overhanging portion 650b is recessed towards the Part II of the 4th chip 621, the 5th chip 622, the 6th chip 623 and the 7th chip 624, to limit the first depression R1.The bottom of the second overhanging portion 650b is recessed towards the Part II of the 8th chip 625, the 9th chip 626, the tenth chip the 627 and the 11 chip 628, to limit the second depression R2.
Therefore, encapsulating component 650 not only can comprise the overhanging portion of the outside of the side being projected into occupied area F, also can comprise the overhanging portion of the outside of the opposite side being projected into occupied area F or more side, the bottom of these overhanging portions all can have towards the recessed lower surface of chip wherein.
Semiconductor packages 600 according to the fifth exemplary embodiment of the present invention has more chip, therefore can realize more capacity and function and higher integrated level.
Figure 11 and Figure 12 illustrates the cutaway view manufactured according to the method for the semiconductor packages 200 of the first exemplary embodiment of the present invention at least in part.
Manufacture and can comprise according to the method for the semiconductor packages 200 of the first exemplary embodiment of the present invention: provide size to be greater than the substrate precursor of substrate 210; Substrate precursor is installed multiple chip 221,222,223 and 224; Multiple chip 221,222,223 and 224 is encapsulated with encapsulating component precursor; The surface contrary with the surface being provided with multiple chip 221,222,223 and 224 of substrate precursor arranges external connection terminals 260; The marginal portion of removing substrate precursor and the part encapsulating component precursor be arranged on the marginal portion of substrate precursor, thus obtain substrate 210 and encapsulating component 250.Here, the step arranging external connection terminals 260 is optional.
It can be known for substrate precursor being installed the step of multiple chip 221,222,223 and 224, encapsulates the step of multiple chip 221,222,223 and 224 with encapsulating component precursor, on the surface contrary with the surface being provided with multiple chip 221,222,223 and 224 of substrate precursor, arrange the step of external connection terminals 260, does not repeat them here.
These parts can be removed by encapsulating component precursor by the marginal portion of cutter cutting substrate precursor and the part be arranged on the marginal portion of substrate precursor.
With reference to Figure 11 and Figure 12, when (or) manufactures multiple semiconductor packages 200 simultaneously together, same motherboard is installed each multiple chips be used in multiple semiconductor packages 200, jointly encapsulate multiple chip with encapsulating component precursor and external connection terminals is set, then, component precursor can be encapsulated by a part corresponding with the overhanging portion of the encapsulating component that will be formed for the first cutter BL1 cutting motherboard and the part be arranged in this part of motherboard, then can cut with the second cutter BL2 the part encapsulating component precursor be arranged in this part of motherboard further, thus obtain multiple semiconductor packages 200.First cutter BL1 can have the shape corresponding with the shape of the depression R of the encapsulating component 250 that will be formed.Because the upper surface with the chip distance substrate precursor of the part being positioned at F outside, occupied area has certain distance, so can guarantee the depth of cut of the first cutter BL1 fully.Second cutter BL2 can be cutter conventional in traditional segmentation (singulation) step.The size of the second cutter BL2 can be less than the size of the first cutter BL1.
Therefore, when (or) manufactures multiple semiconductor packages 200 simultaneously together, the step and the segmentation step that form the encapsulating component 250 with depression R can perform in same technique, therefore easily can manufacture multiple semiconductor packages 200.
By manufacturing semiconductor packages 300,400,500 and 600 according to an exemplary embodiment of the present invention with the same or analogous method of said method.In addition, the shape by adjusting cutter BL1 easily adjusts the shape of the lower surface of the overhanging portion of encapsulating component.
According to the semiconductor packages of exemplary embodiment of the present invention, when not increasing occupied area, this semiconductor packages can hold large size chip.
In addition, in the semiconductor packages of exemplary embodiment according to the present invention, less chip can closer (such as, directly) be arranged on substrate, so the length these chip electrical being received the bonding line of substrate or projection is little, thus the electrical property of these chips can not be affected.
Although specifically illustrate with reference to exemplary embodiment of the present invention and describe the present invention, it should be appreciated by those skilled in the art that without departing from the spirit and scope of the present invention, the various changes in form and in details can be made.The feature described in conjunction with an embodiment or aspect go for other embodiments.
Claims (10)
1. a semiconductor packages, is characterized in that, described semiconductor packages comprises:
Substrate, has occupied area;
First chip, to be arranged on substrate and to be positioned at the occupied area of substrate;
Second chip, is arranged on the first chip, and comprises the Part I be arranged in occupied area and the Part II being arranged on outside, occupied area; And
Encapsulating component, encapsulates the first chip and the second chip, and comprises the body portion be arranged in occupied area and the overhanging portion being arranged on outside, occupied area, and body portion encapsulates the Part I of the second chip, and overhanging portion encapsulates the Part II of the second chip,
Wherein, the bottom of overhanging portion is recessed towards the Part II of the second chip, to limit depression.
2. semiconductor packages according to claim 1, is characterized in that, the size of the second chip is greater than, is equal to or less than the size of occupied area.
3. semiconductor packages according to claim 1, is characterized in that, the second chip on the direction being basically parallel to substrate relative to the first chip offset.
4. semiconductor packages according to claim 1, is characterized in that, described semiconductor packages also comprises the 3rd chip be arranged between substrate and the second chip, and the 3rd chip is positioned at the occupied area of substrate.
5. semiconductor packages according to claim 4, it is characterized in that, described semiconductor packages also comprises the 4th chip be arranged on the second chip, 4th chip comprises the Part I be arranged in occupied area and the Part II being arranged on outside, occupied area, the Part I of body portion encapsulating the 4th chip of encapsulating component, the Part II of overhanging portion encapsulating the 4th chip of encapsulating component.
6. semiconductor packages according to claim 5, is characterized in that, the 4th chip on the direction being basically parallel to substrate relative to the second chip offset.
7. semiconductor packages according to claim 1, it is characterized in that, overhanging portion has upper surface, from the outer end of upper surface to the side surface of downward-extension, and extend to the lower surface of lower end of side surface from the edge of substrate, or overhanging portion has upper surface and extends to the lower surface of outer end of upper surface from the edge of substrate.
8. semiconductor packages according to claim 7, is characterized in that, the lower surface of overhanging portion has the shape of arcs of recesses, convex, straight line, broken line, parabola or wave.
9. semiconductor packages according to claim 1, is characterized in that, described semiconductor packages also comprises the external connection terminals be arranged on the surface contrary with the surface it being provided with the first chip and the second chip of substrate.
10. the manufacture method of the semiconductor packages according to any one in claim 1 to 9, is characterized in that, described method comprises:
Size is provided to be greater than the substrate precursor of substrate;
Substrate precursor is installed the first chip and the second chip is set on the first chip,
The first chip and the second chip is encapsulated with encapsulating component precursor;
The marginal portion of removing substrate precursor and the part encapsulating component precursor be arranged on the marginal portion of substrate precursor, thus obtain substrate and encapsulating component.
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| CN1858907A (en) * | 2005-05-06 | 2006-11-08 | 冲电气工业株式会社 | Semiconductor device and fabrication method thereof |
| US20090108470A1 (en) * | 2007-10-29 | 2009-04-30 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN102790042A (en) * | 2012-07-12 | 2012-11-21 | 日月光半导体制造股份有限公司 | Semiconductor chip stacking structure |
| CN102891136A (en) * | 2011-07-18 | 2013-01-23 | 三星电子株式会社 | Semiconductor packages and methods of forming the same |
| CN103426872A (en) * | 2013-07-30 | 2013-12-04 | 三星半导体(中国)研究开发有限公司 | Semiconductor packaging part and manufacturing method thereof |
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| CN1858907A (en) * | 2005-05-06 | 2006-11-08 | 冲电气工业株式会社 | Semiconductor device and fabrication method thereof |
| US20090108470A1 (en) * | 2007-10-29 | 2009-04-30 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN102891136A (en) * | 2011-07-18 | 2013-01-23 | 三星电子株式会社 | Semiconductor packages and methods of forming the same |
| CN102790042A (en) * | 2012-07-12 | 2012-11-21 | 日月光半导体制造股份有限公司 | Semiconductor chip stacking structure |
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