KR102370950B1 - Buffer circuit between different voltage domains - Google Patents

Abstract

The circuit includes a first inverter and a second inverter. A first inverter is coupled to the input terminal. The input terminal receives an input signal that varies in a first voltage domain. A second inverter is coupled between the first inverter and the output terminal. A second inverter generates an output signal that varies in a second voltage domain. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal varies in a third voltage domain. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in a second voltage domain.

Description

Buffer circuit between different voltage domains {BUFFER CIRCUIT BETWEEN DIFFERENT VOLTAGE DOMAINS}

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Patent Application No. 62/871,587, filed on July 8, 2019, which is incorporated herein by reference.

With the advent of sub-micron technology, the device dimensions of the core components of IC chips are getting smaller and smaller to achieve speed and cost. At the same time, the operating voltage of the core component must also be scaled down to accommodate shrinkage dimensions such as thinner oxides and tighter spaces. However, at the circuit board level, signals still travel at traditional high voltages to and from the core components of the interface to maintain signal integrity and interoperability with other chips. For example, the core component of an IC chip may have an internal operating voltage of 1.0V, but may interface with other devices at the 2.5V level. For these IC chips, the input buffer must convert an external signal with a larger voltage swing range into an internal signal with a narrower voltage swing range.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
1 is a schematic diagram illustrating an input buffer circuit according to various embodiments of the present disclosure;
FIG. 2 is a signal waveform illustrating an input signal to an input buffer circuit and an output signal generated by the input buffer circuit in FIG. 1 according to various embodiments of the present disclosure;
3A is a signal relationship diagram illustrating a relationship between an input signal and a first input tracking signal according to various embodiments of the present disclosure;
3B is a signal relationship diagram illustrating a relationship between an input signal and a second input tracking signal according to various embodiments of the present disclosure;
4A is a signal waveform illustrating a relationship between an input signal and a first input tracking signal according to various embodiments of the present disclosure;
4B is a signal waveform illustrating a relationship between an input signal and a second input tracking signal according to various embodiments of the present disclosure;
4C is a signal waveform illustrating a relationship between an input signal SIN and a first inverted signal according to various embodiments of the present disclosure.
4D is a signal waveform illustrating a relationship between an input signal and a second inverted signal according to various embodiments of the present disclosure;
5A is a schematic diagram illustrating another structure of the tracking high circuit of FIG. 1 .
5B is a schematic diagram illustrating another structure of the tracking high circuit of FIG. 1 .
6 is a schematic diagram illustrating an input buffer circuit according to various embodiments of the present disclosure;
7 is a signal waveform illustrating an input signal to the input buffer circuit of FIG. 6 and an output signal generated by the input buffer circuit in accordance with various embodiments of the present disclosure;
8 is a schematic diagram illustrating an input buffer circuit according to various embodiments of the present disclosure;
9 is a signal waveform illustrating an input signal SIN to an input buffer circuit and an output signal generated by the input buffer circuit of FIG. 8 in accordance with various embodiments of the present disclosure;
10 is a schematic diagram illustrating an input buffer circuit according to various embodiments of the present disclosure;
11 is a flowchart illustrating a method according to various embodiments of the present disclosure.

The following disclosure provides a number of different embodiments or examples for implementing different features of the present subject matter. Specific examples of components and devices are described below to simplify the invention. Of course, these are examples only and are not intended to be limiting. For example, in the description below, the formation of a first feature on or on a second feature includes embodiments in which the first and second features are formed in direct contact, wherein the additional feature is with the first feature. It may also include embodiments that may be formed between second features so that the first and second features cannot be in direct contact. Also, this disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the sake of simplicity and clarity, and does not necessarily dictate a relationship between the various embodiments and/or configurations being discussed.

Terms used in this specification generally have their ordinary meanings in the industry in which they are used and in the particular context. The use of examples in this specification, including examples of any term discussed herein, is descriptive only and in no way limits the scope and meaning of the disclosure or any illustrated term. Likewise, the present disclosure is not limited to the various embodiments given herein.

Although the terms “first,” “second,” etc. may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of embodiments. As used herein, the term “and/or” includes any or all combinations of one or more associated listed items.

As used herein, the terms “comprising,” “including,” “having,” “containing,” “accompanying,” and the like are understood to be open-ended, i.e., including, but not limited to, should be

References throughout the specification to “one embodiment,” “an embodiment,” or “some embodiments,” indicate that a particular feature, structure, implementation, or characteristic described in connection with the embodiment(s) is at least one implementation of the present disclosure. means included in the example. Thus, the use of the phrases "in one embodiment" or "in an embodiment" or "in some embodiments" in various places in this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, implementations, or characteristics may be combined in any suitable manner in one or more embodiments.

1 is a schematic diagram illustrating an input buffer circuit 100a according to various embodiments of the present disclosure. In some embodiments, the input buffer circuit 100a is coupled between the input terminal N0 and the output terminal N2 . Based on the input signal SIN at the input terminal N0, the input buffer circuit 100a is configured to generate the output signal SOUT at the output terminal N2.

See also FIG. 2 . 2 is a signal waveform illustrating an input signal SIN to the input buffer circuit 100a and an output signal SOUT generated by the input buffer circuit 100a of FIG. 1 according to various embodiments of the present disclosure. With respect to the embodiment of FIG. 1 , similar elements in FIG. 2C are designated with the same reference numbers for ease of understanding.

FIG. 2 shows that the voltage level of the input signal SIN is raised from the negative supply level VSS to the first positive supply level VDDH, and then decreased again from the first positive supply level VDDH to the negative supply level VSS. In response, the simulation result of the output signal SOUT is shown. 2 , when the input signal SIN is higher than the threshold voltage Vt, the output signal SOUT generated by the input buffer circuit 100a is at a logic “1” or high level; When the input signal SIN is lower than the threshold voltage Vt, the output signal SOUT generated by the input buffer circuit 100a is at a logic “0” or low level. That is, the output signal SOUT has the same logic as the input signal SIN.

1 and 2 , the input signal SIN and the output signal SOUT are operated in different voltage domains. In some embodiments, the input signal SIN is a signal from an external circuit or interface circuit (not shown) on the I/C chip, and the input signal SIN is a negative supply level VSS to a first positive supply level ( VDDH) in the first voltage domain with a larger voltage difference window. For example, the input signal SIN varies from about 0V to about 1.8V. In some embodiments, the output signal SOUT is a signal transmitted from the I/C chip to a core component (not shown), and the output signal SOUT is from a negative supply level VSS, a first positive supply level It changes in the second voltage domain with a narrower voltage difference window to a second positive supply level (VDDM) lower than (VDDH). For example, the output signal SOUT varies from about 0V to about 1.2V.

In some embodiments, the core component is implemented with smaller dimensions, such as thinner oxide and narrower space, such that the core component is susceptible to over-driving voltage and operates in a voltage domain within a narrower voltage differential window. is required In some embodiments, the input buffer circuit 100a converts the input signal SIN changing in the first voltage domain to the output changing in the second voltage domain to protect core components driven by the output signal SOUT. and converted to a signal SOUT.

1 , the input buffer circuit 100a includes a first inverter 110 , a second inverter 120 , a tracking high circuit 131 , a tracking low circuit 132 , and another tracking row circuit 134 . In some embodiments, the first inverter 110 is configured to generate the first inverted signal INB1 in response to the input signal SIN, and the second inverter 120 is configured to generate the first inverted signal INB1 in response to the first inverted signal INB1. and generate an output signal SOUT.

1 , the tracking high circuit 131 is configured to convert an input signal SIN into a first input tracking signal INH. 3A, which is a signal relationship diagram illustrating a relationship between the input signal SIN and the first input tracking signal INH according to various embodiments of the present disclosure, is further referenced to FIG. 3A . 1 and 2, similar elements in FIG. 3 are designated by the same reference numerals for ease of understanding. 3A , when the input signal SIN is above the reference level VDDL, the tracking high circuit 131 duplicates the input signal SIN as the first input tracking signal INH. . 3A , when the input signal SIN is lower than the reference level VDDL, the tracking high circuit 131 maintains the first input tracking signal INH fixed to the reference level VDDL. In other words, in response to the input signal SIN changing in the first voltage domain (from VSS to VDDH), the tracking high circuit 131 changes the first input tracking signal in the third voltage domain (from VDDL to VDDH) (INH) is created.

In some embodiments, the reference level VDDL is a voltage level between the negative supply level VSS and the second positive supply level VDDM. In some embodiments, the reference level VDDL may be configured by subtracting the second positive supply level VDDM from the first positive supply level VDDH. For example, when the first positive supply level VDDH is about 1.8V and the second positive supply level VDDM is about 1.2V, the reference level VDDL may be about 0.6V.

1 , the tracking high circuit 132 is configured to convert the input signal SIN into the second input tracking signal INL. 3B, which is a signal relationship diagram illustrating a relationship between an input signal SIN and a second input tracking signal INL according to various embodiments of the present disclosure, is further referenced. With respect to the embodiment of FIG. 3A , similar elements in FIG. 3B are designated with the same reference numbers for ease of understanding. As shown in FIG. 3B , when the input signal SIN is below the second positive supply level VDDM, the tracking high circuit 132 duplicates the input signal SIN as the second input tracking signal INL. do. As shown in FIG. 3B , when the input signal SIN exceeds the second positive supply level VDDM, the tracking high circuit 132 operates the second input tracking signal fixed to the second positive supply level VDDM. (INL) is maintained. In other words, in response to the input signal SIN varying in the first voltage domain (VSS to VDDH), the tracking high circuit 132 provides a second input varying in the second voltage domain (VSS to VDDM). A tracking signal INH is generated.

1 , in some embodiments, the first inverter 110 includes five transistors connected in series between a first positive supply level VDDH and a negative supply level VSS. . In the embodiment shown in FIG. 1 , three PMOS transistors MP1 to MP3 and two NMOS transistors MN1 to MN2 are present in the first inverter 110 .

1 , in some embodiments, the source terminal of the PMOS transistor MP2 is coupled to the first positive supply level VDDH. The gate terminal of the PMOS transistor MP2 is biased by the reference level VDDL. Since the reference level VDDL is lower than the first positive supply level VDDH, the PMOS transistor MP2 is normally turned on. The drain terminal of the PMOS transistor MP2 is coupled to the source terminal of the PMOS transistor MP1. The source terminal of the PMOS transistor MP1 is coupled to the drain terminal of the PMOS transistor MP2. The gate terminal of the PMOS transistor MP1 is biased by the first input tracking signal INH that changes in the third voltage domain. The drain terminal of the PMOS transistor MP1 is coupled to the source terminal of the PMOS transistor MP3. The gate terminal of the PMOS transistor MP3 is biased by the reference level VDDL. The drain terminal of the PMOS transistor MP3 is coupled to the first node N1 .

The PMOS transistors MP1 to MP3 have the voltage level of the first inversion signal INB1 at the first node N1 (ie, the output node of the first inverter 110 ) in response to the first input tracking signal INH. is configured to pull up.

Reference is further made to FIGS. 4A-4D . 4A is a signal waveform illustrating a relationship between an input signal SIN and a first input tracking signal INH according to various embodiments of the present disclosure. 4B is a signal waveform illustrating a relationship between an input signal SIN and a second input tracking signal INL according to various embodiments of the present disclosure. 4C is a signal waveform illustrating a relationship between an input signal SIN and a first inverted signal INB1 according to various embodiments of the present disclosure. 4D is a signal waveform illustrating a relationship between an input signal SIN and a second inverted signal INB2 according to various embodiments of the present disclosure. 1 and 2 , similar elements in FIGS. 4A-4D are designated by the same reference numerals for ease of understanding.

4A and 4C , when the input signal SIN is lower than the threshold voltage Vt, correspondingly, the first input tracking signal INH is lower than the threshold voltage Vt and turns on the PMOS transistor MP1. turn on Accordingly, the PMOS transistor MP3 is also turned on (MP2 is also turned on), and the first inverted signal INB1 is pulled high to the first positive supply level VDDH.

It can be seen that the terminals of the PMOS transistors MP1 to MP3 are operated in the third voltage domain (from VDDL to VDDH). The third voltage difference window VDDH-VDDL of the third voltage domain is smaller than the first voltage difference window VDDH-VSS of the first voltage domain. For example, when VDDH=1.8V, VDDL=0.6V, and VSS=0V, the third voltage difference window 1.2V is smaller than the first voltage difference window 1.8V. In this case, since the terminals of the PMOS transistors MP1 to MP3 are operated in the third voltage domain, the PMOS transistors MP1 to MP3 of the first inverter 110 are smaller-sized transistors having a relatively lower voltage tolerance. (compared to a transistor operated in the first voltage domain with a larger voltage difference window), the smaller size transistors MP1 to MP3 have lower leakage currents and lower power consumption. can operate as

1 , the drain terminal of the NMOS transistor MN2 is coupled to the first node N1 . The gate terminal of the NMOS transistor is biased by a second positive supply level (VDDM). The source terminal of the NMOS transistor MN2 is coupled to the drain terminal of the NMOS transistor MN1. The gate terminal of the NMOS transistor MN1 is biased by the second input tracking signal INL generated by the second tracking circuit 132 from the input signal. The source terminal of MOS transistor MN1 is coupled to negative supply level VSS.

The NMOS transistors MN1 to MN2 are configured to pull low the voltage level of the first inversion signal INB1 at the first node N1 in response to the second input tracking signal INL.

As shown in FIGS. 4A and 4C , when the input signal SIN is higher than the threshold voltage Vt, the second input tracking signal INL is higher than the threshold voltage Vt and turns on the NMOS transistor MN1. turn on Accordingly, the NMOS transistor MP2 is also turned on, and the first inverted signal INB1 is pulled to the first negative supply level VSS.

It can be seen that the terminals of the NMOS transistors MN1 to MN2 are operated in the second voltage domain (from VDDL to VDDH). The second voltage difference window VDDM-VSS of the second voltage domain is smaller than the first voltage difference window VDDS-VSS of the first voltage domain. For example, when VDDH=1.8V, VDDM=1.2V, and VSS=0V, the second voltage difference window 1.2V is smaller than the first voltage difference window 1.8V. In some embodiments, the second voltage difference window VDDM-VSS may be substantially the same as the aforementioned third voltage difference window VDDH-VDDL. In this case, since the terminals of the NMOS transistors MN1 to MN2 are operated in the second voltage domain, the NMOS transistors MN1 to MN2 of the first inverter 110 are smaller-sized transistors having a relatively lower voltage tolerance. (compared to a transistor operated in the first voltage domain with a larger voltage difference window), and the smaller size transistors MN1 to MN2 can operate with lower leakage current and lower power consumption. there is.

In some examples, pull-up transistors (eg, MP1-MP3) and pull-low transistors (eg, MN1-MN2) are connected in a second voltage domain (VSS to VDDM) ) when driven by the same input tracking signal, such as a second input tracking signal (INL) that varies in The bias voltage for V will be shifted to a lower voltage range (VSS to VDDM) compared to the full voltage range (VSS to VDDH). Shifting these bias voltages to a lower voltage range is not ideal, since it is desirable that the threshold voltage Vt of the input buffer circuit 100a can be at about an intermediate level between VSS to VDDH of the input signal SIN. not. In order to compensate for the bias voltage shifting to a lower voltage range and to maintain the threshold voltage (Vt), the size of the pull-up transistors (eg, MP1 to MP3) is larger than that of the pull-up transistors (eg, MN1 to MN2). Being large is desired, the pull-up transistors (eg MP1 to MP3) can be operated in a wider voltage difference window from VSS to VDDH. In some examples, a ratio between the sizes of the pull-up transistors MP1 to MP3 and the sizes of the pull low transistors (eg, MN1 to MN2) may reach 50:1 to 100:1. PMOS transistors and NMOS transistors are difficult to implement on a circuit arrangement having such a large size difference. In other words, the first inverter may have a reasonable size ratio between the PMOS transistor and the NMOS transistor.

As exemplarily shown in FIG. 1 , the pull-up transistors (eg, MP1-MP3) and the pull-low transistors (eg, MN1-MN2) are driven by different input tracking signals (INH and INL). Therefore, the first input tracking signal INH for the pull-up transistors (eg, MP1 to MP3) and the second input tracking signal INL for the pull-low transistors (eg, MN1 to MN2) are input signals It will cover the entire voltage range (VSS to VDDH) of SIN. In some embodiments, the input buffer circuit 100a of FIG. 1 is biased so that the size of the pull-up transistors (eg, MP1-MP3) can be similar to that of the pull-low transistors (eg, MN1-MN2). There is no need to compensate for voltage shifts. In some embodiments, a ratio between the sizes of the pull-up transistors MP1 to MP3 and the sizes of the pull-low transistors MN1 to MN2 may be about 1:1, 2:1, or 3:2. there is. PMOS transistors and NMOS transistors are easier to implement on circuit layouts with similar dimensions.

It can be seen that the aforementioned voltage values of the input signal SIN (about 0V to about 1.8V) and the output signal SOUT (about 0V to about 1.2V) are provided for demonstration purposes. The present disclosure is not limited thereto. In some embodiments, the second positive supply level VDDM may be at least half of the first positive supply level VDDH. For example, when the first positive supply level VDDH is set to 3.6V, the second positive supply level VDDM may be greater than or equal to 1.8V. When the second positive supply level VDDM is lower than half of the first positive supply level VDDH, the first input tracking signal INH and the second input tracking signal INL are at (VSS) of the input signal SIN. It will not be able to cover the entire voltage range (up to VDDH).

1 and 4C , the first inverted signal INB1 at the first node N1 is pulled up to the first positive supply level VDDH by MP1 to MP3 or negative by MN1 to MN2. It may be pulled down to the supply level VSS, so that the first inversion signal INB1 changes in the first voltage domain.

1 , 4C and 4D , the first inverted signal INB1 is converted into a second inverted signal INB2 that is changed in the second voltage domain by the tracking row circuit 134 . The behavior of the tracking row circuit 134 is similar to the above-mentioned tracking row circuit 132 , and the relationship between the first inverted signal INB1 and the second inverted signal INB2 is the input signal SIN shown in FIG. 3B . ) and the second input tracking signal INL. 4C and 4D , when the first inversion signal INB1 is below the second positive supply level VDDM, the tracking high circuit 134 inverts the first inversion signal INB1 to the second inversion. It is copied as a signal INB2. 4C and 4D , when the first inverted signal INB1 exceeds the second positive supply level VDDM, the tracking high circuit 134 is fixed to the second positive supply level VDDM. The second inversion tracking signal INB2 is maintained. In other words, according to the first inverted signal INB1 changing in the first voltage domain (VSS to VDDH), the tracking high circuit 134 changes in the second voltage domain (VSS to VDDM) An inverted signal INB2 is generated.

1, 2, and 4D, the second inverter 120 converts the second inverted signal INB2 in the second voltage domain to the output signal SOUT in the second voltage domain (Fig. 2) to be inverted. In some embodiments, the second inverter 120 is configured to invert a signal in the same voltage domain, so that the second inverter 120 may be implemented as a CMOS inverter.

1 , the tracking high circuit 131 includes two PMOS transistors MP4 and MP5. The source terminal of the PMOS transistor MP4 is coupled to the gate terminal of the PMOS transistor MP1. The gate terminal of the PMOS transistor MP4 is coupled to the input terminal N0. The drain terminal of the PMOS transistor MP4 is coupled to the reference level VDDL. The source terminal of the PMOS transistor MP5 is coupled to the gate terminal of the PMOS transistor MP1. The gate terminal of the PMOS transistor MP5 is coupled to the reference level VDDL. A drain terminal of the PMOS transistor MP5 is coupled to the first terminal N0. When the input signal SIN is high, the PMOS transistor MP4 is turned off and the PMOS transistor MP5 is turned on to duplicate the input signal SIN as the first input tracking signal INH. When the input signal SIN is low, the PMOS transistor MP4 is turned on, and the PMOS transistor MP4 pulls the first input tracking signal INH to the reference level VDDL.

1 , the tracking row circuit 132 includes two NMOS transistors MN3 and MN4. The source terminal of the NMOS transistor MN3 is coupled to the second positive supply level VDDM. The gate terminal of the NMOS transistor MN3 is coupled to the input terminal N0. The drain terminal of the NMOS transistor MN3 is coupled to the gate terminal of the NMOS transistor MN1. The source terminal of the NMOS transistor MN4 is coupled to the gate terminal of the NMOS transistor MN1. The gate terminal of the NMOS transistor MN4 is coupled to a second positive supply level VDDM. The drain terminal of NMOS transistor MN4 is coupled to input N0. When the input signal SIN is low, the NMOS transistor MP3 is turned off and the NMOS transistor MP4 is turned on to duplicate the input signal SIN as the second input tracking signal INL. When the input signal SIN is high, the NMOS transistor MP3 is turned on, and the NMOS transistor MP3 maintains the second input tracking signal INL fixed to the second positive supply level VDDM. In some embodiments, the structure of the tracking row circuit 134 is similar to the structure of the tracking row circuit 132 .

It can be seen that the tracking high circuit 131 and the tracking low circuits 132 and 134 are not limited to the structure shown in FIG. 1 . Reference is further made to FIGS. 5A and 5B . FIG. 5A is a schematic diagram showing another structure of the tracking high circuit 131 of FIG. 1 . FIG. 5B is a schematic diagram showing another structure of the tracking high circuit 131 of FIG. 1 . 1 , similar elements in FIGS. 5A and 5B are designated by the same reference numerals for ease of understanding.

5A, the tracking high circuit 131 includes a PMOS transistor MN4a and a resistor R1. The source terminal of the PMOS transistor MN4a is coupled to the gate terminal of the PMOS transistor MP1 (see FIG. 1 ) to output the first input tracking signal INH. The gate terminal of the PMOS transistor MN4a is coupled to the input terminal N0 (see FIG. 1 ) for receiving the input signal SIN. The drain terminal of the fourth PMOS transistor is coupled to the reference level VDDL. A first terminal of resistor R1 is coupled to a first positive supply level VDDH. The second terminal of the resistor R2 is coupled to the gate terminal of the PMOS transistor MP1 (see FIG. 1 ) to output the first input tracking signal INH. The structure of the tracking high circuit 131 of FIG. 5A will generate the first input tracking signal INH in response to the input signal SIN similar to the relationship illustrated in FIG. 3A .

5B, the tracking row circuit 132 includes an NMOS transistor MN3a and a resistor R2. A source terminal of the NMOS transistor MN3a is coupled to a gate terminal of the NMOS transistor MN1 to output a second input tracking signal INL (see FIG. 1 ). The gate terminal of the NMOS transistor MN3a is coupled to the input terminal N0 (see FIG. 1 ) for receiving the input signal SIN. The drain terminal of the NMOS transistor MN3a is coupled to the second positive supply level VDDM. A first terminal of the resistor R2 is coupled to the gate terminal of the NMOS transistor MN1 (see FIG. 1 ) to output a second input tracking signal INL. The second terminal of resistor R2 is coupled to negative supply level VSS. The structure of the tracking row circuit 132 of FIG. 5B will generate the second input tracking signal INL in response to the input signal SIN similar to the relationship shown in FIG. 3A .

In other words, the tracking high circuit 131 and the tracking low circuits 132 and 134 are not limited to the structure shown in FIG. 1 . Any equivalent circuit (refer to the correspondence shown in FIGS. 3A and 3B) capable of generating a tracking signal corresponding to the input signal may be used for the input buffer circuit 100a.

In some embodiments, the input buffer circuit 100a shown in FIG. 1 includes cascade-connected PMOS and NMOS transistors, each biased by a gate signal in the appropriate voltage domain, PMOS and NMOS transistors have smaller standby leakage power and can be formed in a smaller size. Also, the first inverter 110 of the input buffer circuit 100a may have an appropriate size ratio between the PMOS transistor and the NMOS transistor. As shown in FIG. 2 , the duty cycle of the output signal SOUT generated by the input buffer circuit 100a in response to the input signal SIN is about 50%. Since the first inverter 1 can detect the entire voltage range of the input signal SIN, the duty cycle of the output signal SOUT generated by the input buffer circuit 100a is the partial voltage of the input signal SIN. It may be closer to about 50% (eg, from about 40% to about 60%) under different process/voltage/temperature (PVT) conditions as compared to biasing the first inverter in a range. In the above-described embodiments, the input buffer circuit 100a changes the level of the output signal SOUT in response to the input signal SIN with respect to the threshold voltage.

In some other embodiments, the input buffer circuit may include a Schmitt trigger function that may have different threshold voltages, one for the low to high input signal SIN, and the other One is for the high to low input signal (SIN).

See also FIG. 6 . 6 is a schematic diagram illustrating an input buffer circuit 100b according to various embodiments of the present disclosure. In some embodiments, the input buffer circuit 100b is coupled between the input terminal N0 and the output terminal N2 . Based on the input signal SIN at the input terminal N0 , the input buffer circuit 100b is configured to generate the output signal SOUT at the output terminal N2 . 1-5B , similar elements in FIG. 6 are designated by the same reference numerals for ease of understanding.

Compared to the input buffer circuit 100a of FIG. 1 , the input buffer circuit 100b of FIG. 6 further includes a feedback loop 141 coupled between the output terminal N2 and the first node N1 . The feedback loop 141 includes NMOS transistors MN5 and MN6. A drain terminal of the NMOS transistor MN5 is coupled to the first node N1 . The gate terminal of the NMOS transistor MN5 is coupled to a second positive supply level VDDM. The drain terminal of the NMOS transistor MN6 is coupled to the source terminal of the NMOS transistor MN5. The gate terminal of the NMOS transistor MN6 is coupled to the output terminal N2. The source terminal of NMOS transistor MN6 is coupled to negative supply level VSS. In the embodiment shown in FIG. 6 , the feedback loop 141 is another pull-low path for the first node N1 in addition to the NMOS transistors MN1 to MN2 of the first inverter 110 .

See also FIG. 7 . 7 is a signal waveform illustrating an input signal SIN to the input buffer circuit 100b of FIG. 6 and an output signal SOUT generated by the input buffer circuit 100b of FIG. 6 according to various embodiments of the present disclosure. 6 , similar elements in FIG. 7 are designated with the same reference numbers for ease of understanding.

6 and 7, when the input signal SIN transitions from a logic “1” to a logic “0”, for example, from a first positive supply level VDDH to a negative supply level VSS. while, the input signal SIN is initially at a first positive supply level VDDH (logic “1”), and the first inverted signal INB1 is initially at a negative supply level VSS (logic “0”). and the output signal SOUT is initially at the second positive supply level VDDM (logic "1"). The NMOS transistors MN1 to MN2 of the first inverter 110 are turned on to pull the first inverted signal INB1 from the first node N1 to full low. Also, the output signal SOUT is a feedback for turning on the NMOS transistor MN6 in the feedback loop 141 . Accordingly, the NMOS transistors MN5 and MN6 are also turned on to bring the voltage level of the first node N1 to full low.

While the input signal SIN gradually transitions from the first positive supply level VDDH to the negative supply level VSS, two pull low paths MN1 to MN2 and Since there are MN5 to MN6 , the first inversion signal INB1 and the output signal SOUT may be flipped later than the original threshold voltage Vt. 7 , when the input signal SIN reaches the low threshold voltage Vt−, the output signal SOUT is flipped from the second positive supply level VDDM to the negative supply level VSS. In this case, the input buffer circuit 100b has one threshold voltage Vt associated with the input signal SIN from logic “0” to logic “1” and an input from logic “1” to logic “0”. It has a Schmitt trigger function with another threshold voltage Vt associated with the signal SIN.

In other words, when the input signal SIN changes from logic “1” to logic “0”, the feedback loop 141 of the input buffer circuit 100b operates at the low threshold voltage Vt− of the input buffer circuit 100b. ) is used to reduce

In some other embodiments, the input buffer circuit is configured to change when the input signal SIN changes from a logic “1” to a logic “0” and also when the input signal SIN changes from a logic “0” to a logic “1”. In this case, a Schmitt trigger function may be included on both sides of the threshold voltage. See also FIG. 8 . 8 is a schematic diagram illustrating an input buffer circuit 100c according to various embodiments of the present disclosure. In some embodiments, the input buffer circuit 100c is coupled between the input terminal N0 and the output terminal N2 . Based on the input signal SIN at the input terminal N0 , the input buffer circuit 100c is configured to generate the output signal SOUT at the output terminal N2 . 1 and 6, similar elements in FIG. 8 are designated by the same reference numerals for ease of understanding.

Compared with the input buffer circuit 100b of FIG. 6 , the input buffer circuit 100c of FIG. 8 has a tracking high circuit 133 , a third inverter 150 and another feedback loop 142 (feedback loop 141 ). other than that) are included. In some embodiments, the structure of the tracking high circuit 133 is similar to the tracking high circuit 131 discussed in FIG. 1 or FIG. 5A , and the behavior of the tracking high circuit 133 is similar to the tracking high circuit discussed in FIGS. 3A and 4A . It is similar to the high circuit 131 . Accordingly, the structure and behavior of the tracking high circuit 133 will not be described again. The tracking high circuit 133 is used to convert the first inverted signal INB1 changing in the first voltage domain into a third inverted signal INBH changing in the third voltage domain. The third inverted signal INBH is inverted into the high output signal OUTH that is changed in the third voltage domain by the third inverter 150 . The high output signal OUTH is fed back to the feedback loop 142 .

As shown in Fig. 8, feedback loop 142 includes PMOS transistors MP6 and MP7. The source terminal of the PMOS transistor MP6 is coupled to the first positive supply level VDDH. The gate terminal of the PMOS transistor MP6 is coupled to the third inverter 150 . The source terminal of the PMOS transistor MP7 is coupled to the drain terminal of the PMOS transistor MP6. The gate terminal of the PMOS transistor MP7 is coupled to the reference level VDDL. The drain terminal of the PMOS transistor MP7 is coupled to the first node N1 .

In the embodiment shown in FIG. 8 , the feedback loop 141 is another pull-high path for the first node N1 in addition to the PMOS transistors MP1 to MP3 of the first inverter 110 .

See also FIG. 9 . 9 is a signal waveform illustrating an input signal SIN to the input buffer circuit 100c of FIG. 8 and an output signal SOUT generated by the input buffer circuit 100c of FIG. 8 according to various embodiments of the present disclosure. With respect to the embodiment of FIG. 8 , similar elements in FIG. 9 are designated with the same reference numbers for ease of understanding.

8 and 9 , the input signal SIN transitions from a logic “0” to a logic “1”, for example, from a negative supply level VSS to a first positive supply level VDDH. while, the input signal SIN is initially at the negative supply level VSS (logic “0”), and the first inverted signal INB1 is initially at the first positive supply level VDDH (logic “1”). and the output signal SOUT is initially at the negative supply level VSS (logic "0"). The PMOS transistors MP1 to MP3 of the first inverter 110 are turned on to pull high the first inversion signal INB1 at the first node N1 . Also, the high output signal OUTH is a feedback for turning on the PMOS transistor MN6 in the feedback loop 142 . Accordingly, the PMOS transistors MN6 and MN7 are also turned on to pull high the voltage level of the first node N1.

While the input signal SIN gradually transitions from the negative supply level VSS to the first positive supply level VDDH, since there are two full low paths MP1 to MP3 and MP6 to MP7, the first inverted signal (INB1) and the output signal SOUT will be flipped later than the original threshold voltage Vt. 7 , when the input signal SIN reaches the high threshold voltage Vt+, the output signal SOUT is flipped from the second positive supply level VDDM to the negative supply level VSS. In this case, the input buffer circuit 100c has one high threshold voltage Vt+ associated with the input signal SIN from logic “0” to logic “1” and an input from logic “1” to logic “0”. It has a Schmitt trigger function with one low threshold voltage Vt− associated with the signal SIN. The high threshold voltage Vt+ is higher than the threshold voltage Vt, and the low threshold voltage Vt- is lower than the threshold voltage Vt.

In other words, the feedback loop 141 of the input buffer circuit 100b controls the low threshold voltage Vt− of the input buffer circuit 100b when the input signal SIN changes from logic “1” to logic “0”. used to reduce In other words, the input buffer circuit 100c changes when the input signal SIN changes from a logic “1” to a logic “0” and also when the input signal SIN changes from a logic “0” to a logic “1”. When we have a Schmitt trigger function for both sides of the threshold voltage.

See also FIG. 10 . 10 is a schematic diagram illustrating an input buffer circuit 100d according to various embodiments of the present disclosure. In some embodiments, the input buffer circuit 100d is coupled between the input terminal N0 and the output terminal N2 . Based on the input signal SIN at the input terminal N0, the input buffer circuit 100d is configured to generate the output signal SOUT at the output terminal N2. 1 and 9, similar elements in FIG. 10 are designated with the same reference numerals for ease of understanding.

In some embodiments, the input buffer circuit 100d of FIG. 10 further includes an input enable function controlled by an enable signal. When the enable signal is high or a logic “1”, the input buffer circuit 100d is activated to generate the output signal SOUT in response to the input signal SIN. On the other hand, when the enable signal is low or logic “0”, the input buffer circuit 100d is deactivated and does not respond to the input signal SIN.

Compared with the input buffer circuit 100b of FIG. 6 , the input buffer circuit 100d of FIG. 10 has a PMOS transistor PM8 , an NMOS transistor MN7 , another NMOS transistor MN8 and an AND-logic gate 142 . further includes In addition, the second inverter 120 of the input buffer circuit 100d is implemented using a NOR-logic inverter. The second inverter 120 performs NOR-logic between the second inverted signal INB2 changing in the second voltage domain and the inverted enable signal IEB changing in the second voltage domain.

The source terminal of the PMOS transistor PM8 is coupled to the first positive supply level VDDH. A gate terminal of the PMOS transistor PM8 is coupled to a first enable signal IEH that varies in a third voltage domain. The drain terminal of the PMOS transistor PM8 is coupled to the source terminal of the PMOS transistor MP3.

The source terminal of NMOS transistor MN7 is coupled to negative supply level VSS. A gate terminal of the seventh NMOS transistor is coupled to a second enable signal IE that varies in a second voltage domain. The drain terminal of the NMOS transistor MN7 is coupled to the source terminal of the NMOS transistor MN1.

The source terminal of NMOS transistor MN8 is coupled to negative supply level VSS. The gate terminal of the seventh NMOS transistor is coupled to an AND-logic gate 142 . The drain terminal of the NMOS transistor MN8 is coupled to the source terminal of the NMOS transistor MN6.

The AND-logic gate 142 is configured to perform AND-logic between a second enable signal IE varying in a second voltage domain and a Schmitt trigger enable signal ST varying in a second voltage domain.

When the input activation function is on and the Schmitt trigger function is on, the first enable signal IEH and the second enable signal IE are configured at logic “1”; The inverting enable signal IEB is configured at logic "0"; Schmitt trigger enable signal ST is at logic "1". The PMOS transistor PM8 is turned off. The NMOS transistors MN7 and MN8 are turned on. The input buffer circuit 100d is activated with a Schmitt trigger function.

When the input activation function is on and the Schmitt trigger function is on, the first enable signal IEH and the second enable signal IE are configured with logic “1”; The inverting enable signal IEB is configured at logic "0"; The Schmitt trigger enable signal ST is at logic "0". The PMOS transistor PM8 is turned off. The NMOS transistor MN7 is turned on and the NMOS transistor MN8 is turned off. The input buffer circuit 100d is activated without a Schmitt trigger function.

when the input enable function is off, the first enable signal IEH and the second enable signal IE are configured at logic “0”; The inverting enable signal IEB is configured at a logic "1". The PMOS transistor PM8 is turned on. The NMOS transistor MN7 is turned off. The input buffer circuit 100d is deactivated.

In some embodiments, the second enable signal IE, the inverted enable signal IEB, and the Schmitt trigger enable signal ST change in the second voltage domain, and the first enable signal IEH By changing in the three voltage domain, the transistor of the input buffer circuit 100d can be operated in an appropriate voltage change window.

In the embodiment shown in FIG. 10 , the input buffer circuit 100d describes a method for integrating an input enable function into the input buffer circuit 100b shown in FIG. 6 . In some other embodiments, the input enable function shown in input buffer circuit 100d shown in FIG. 10 is also the input buffer circuit 100a shown in FIG. 1 or input buffer circuit 100c shown in FIG. can be integrated into

11 is a flowchart illustrating a method 200 in accordance with various embodiments of the present disclosure. In some embodiments, the method 200 of FIG. 11 may be used in the input buffer circuits 100a - 100d discussed in the foregoing embodiments shown in FIGS. 1 , 6 , 8 , and/or 10 . . 1-10, similar elements in FIG. 11 are designated by the same reference numerals for ease of understanding. For the sake of brevity, the method 200 in the following paragraph will be discussed in conjunction with the embodiment of the input buffer circuit 100a shown in FIG. 1 and the related embodiments of FIGS. 2-5B . It is noted that method 200 is also suitable for use in other embodiments of input buffer circuits 100b - 100d shown in FIG. 6 , 8 , or 10 .

In some embodiments, the method 200 of FIG. 11 changes in a second voltage domain, such as VSS to VDDM, according to an input signal SIN, which varies in a first voltage domain, such as VSS to VDDH, with reference to FIG. 2 . used to generate an output signal SOUT.

1 , 4A, and 11 , for example, in response to the input signal SIN changing in the first voltage domain of VSS to VDDH, operation S211 is a tracking high circuit 131 to generate, for example, a first input tracking signal INH that varies in a third voltage domain from VDDL to VDDH.

1, 4B, and 11 , for example, in response to an input signal SIN varying in a first voltage domain of VSS to VDDH, operation S212 is a tracking row circuit 132 to generate a second input tracking signal INL that varies in a second voltage domain, eg, from VSS to VDDH.

In some embodiments, the first voltage domain has a larger voltage difference window that ranges from a negative supply level (VSS) to a first positive supply level (VDDH). For example, the first voltage domain covers from about 0V to about 1.8V. In some embodiments, the second voltage domain has a narrower voltage difference window that ranges from a negative supply level (VSS) to a second positive supply level (VDDM). For example, the second voltage domain covers from about 0V to about 1.2V. In some embodiments, the third voltage domain has another narrower voltage difference window ranging from the reference level VDDL to the first positive supply level VDDH. For example, the third voltage domain covers from about 0.6V to about 1.8V. It is noted that the voltage values mentioned above are provided for demonstration purposes.

1 and 11 , operation S221 is performed to bias the pull-up transistor (eg, the PMOS transistor MP1 ) with the first input tracking signal INH. 1 and 11 , operation S222 is performed to bias a full-row transistor (eg, an NMOS transistor MN1 ) with a second input tracking signal INL.

1 , 4C , and 11 , the first inverter 110 operates to generate a first inverted signal INB1 that is changed in a first voltage domain by a pull-up transistor and a pull-low transistor in the first inverter 110 . (S230) is performed.

As exemplarily shown in FIGS. 1, 4D, and 11 , the operation S240 converts the first inverted signal INB1 in the second voltage domain by the tracking row circuit 134 to the second inverted signal (INB2) to convert

As exemplarily shown in FIGS. 1, 2, 4D, and 11 , the operation S250 outputs the second inverted signal INB2 by the second inverter 120 to change the second voltage domain. This is done to invert the signal SOUT. In some embodiments, the output signal SOUT is a signal transmitted from an integrated circuit chip toward a core component (not shown).

In some embodiments, the circuit includes a first inverter and a second inverter. A first inverter is coupled to the input terminal. The input terminal receives an input signal that varies in a first voltage domain from a negative supply level to a first positive supply level. A second inverter is coupled between the first inverter and the output terminal. The second inverter generates an output signal that varies in a second voltage domain from a negative supply level to a second positive supply level. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal varies in a third voltage domain from a reference level to a first positive supply level. The reference level is higher than the negative supply level. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in a second voltage domain.

In some embodiments, the first voltage difference window of the first voltage domain is greater than the second voltage difference window of the second voltage domain. The first voltage difference window is larger than the third voltage difference window of the third voltage domain. In some embodiments, the second voltage difference window is substantially equal to the third voltage difference window.

In some embodiments, the first inverter further includes a second PMOS transistor, a third PMOS transistor, and a second NMOS transistor. The source terminal of the second PMOS transistor is coupled to the first positive supply level. The gate terminal of the second PMOS transistor is biased by the reference level. The drain terminal of the second PMOS transistor is coupled to the source terminal of the first PMOS transistor. The source terminal of the third PMOS transistor is coupled to the drain terminal of the first PMOS transistor. The gate terminal of the third PMOS transistor is biased by the reference level. A drain terminal of the third PMOS transistor is coupled to the first node. A drain terminal of the second NMOS transistor is coupled to the first node. The gate terminal of the second NMOS transistor is biased by a second positive supply level. The source terminal of the second NMOS transistor is coupled to the drain terminal of the first NMOS transistor. The source terminal of the first NMOS transistor is coupled to a negative supply level. The first inverter is configured to generate a first inverted signal that varies in a first voltage domain on the first node.

In some embodiments, the circuit further includes a first tracking high circuit, a first tracking low circuit, and a second tracking low circuit. A first tracking high circuit is coupled between the input terminal and the gate terminal of the first PMOS transistor. The first tracking high circuit is configured to convert the input signal into a first input tracking signal. A first tracking high circuit is coupled between the input terminal and the gate terminal of the first NMOS transistor. The first tracking row circuit is configured to convert the input signal into a second input tracking signal. A second tracking row circuit is coupled between the first node and the second inverter. The second tracking row circuit is configured to convert the first inverted signal into a second inverted signal that varies in a second voltage domain. The second inverter is configured to invert the second inverted signal to the output signal.

In some embodiments, the first tracking high circuit includes a fourth PMOS transistor and a fifth PMOS transistor. The source terminal of the fourth PMOS transistor is coupled to the gate terminal of the first PMOS transistor. A gate terminal of the fourth PMOS transistor is coupled to the input terminal. The drain terminal of the fourth PMOS transistor is coupled to the reference level. A source terminal of the fifth PMOS transistor is coupled to a gate terminal of the first PMOS transistor. The gate terminal of the fifth PMOS transistor is coupled by a reference level. A drain terminal of the fifth PMOS transistor is coupled to the input terminal. The first tracking row circuit includes a third NMOS transistor and a fourth NMOS transistor. The source terminal of the third NMOS transistor is coupled to the second positive supply level. A gate terminal of the third NMOS transistor is coupled to the input terminal. A drain terminal of the third NMOS transistor is coupled to a gate terminal of the first NMOS transistor. The source terminal of the fourth NMOS transistor is coupled to the gate terminal of the first NMOS transistor. The gate terminal of the fourth NMOS transistor is coupled to the second positive supply level. A drain terminal of the fourth NMOS transistor is coupled to the input terminal.

In some embodiments, the first tracking high circuit includes a fourth PMOS transistor and a first resistor. The source terminal of the fourth PMOS transistor is coupled to the gate terminal of the first PMOS transistor. A gate terminal of the fourth PMOS transistor is coupled to the input terminal. The drain terminal of the fourth PMOS transistor is coupled to the reference level. A first terminal of the first resistor is coupled by a first positive supply level. The second terminal of the first resistor is coupled to the gate terminal of the first PMOS transistor. The first tracking row circuit includes a third NMOS transistor and a second resistor. The source terminal of the third NMOS transistor is coupled to the gate terminal of the first NMOS transistor. A gate terminal of the third NMOS transistor is coupled to the input terminal. The drain terminal of the third NMOS transistor is coupled to the second positive supply level. A first terminal of the second resistor is coupled to a gate terminal of the first NMOS transistor. A second terminal of the second resistor is coupled to the negative supply level.

In some embodiments, the circuit includes a first feedback loop. The first feedback loop includes a fifth NMOS transistor and a sixth NMOS transistor. A drain terminal of the fifth NMOS transistor is coupled to the first node. The gate terminal of the fifth NMOS transistor is coupled to the second positive supply level. The drain terminal of the sixth NMOS transistor is coupled to the source terminal of the fifth NMOS transistor. A gate terminal of the sixth NMOS transistor is coupled to an output terminal. The source terminal of the sixth NMOS transistor is coupled to the negative supply level.

In some embodiments, the circuit further includes a third inverter, a second tracking high circuit, and a second feedback loop. A second tracking high circuit is coupled between the first node and the third inverter. The second tracking high circuit is configured to convert the first inverted signal into a third inverted signal that varies in a third voltage domain. The second feedback loop includes a sixth PMOS transistor and a seventh PMOS transistor. The source terminal of the sixth PMOS transistor is coupled to the first positive supply level. The gate terminal of the sixth PMOS transistor is coupled to the third inverter. The source terminal of the seventh PMOS transistor is coupled to the drain terminal of the sixth PMOS transistor. The gate terminal of the seventh PMOS transistor is coupled by a reference level. A drain terminal of the seventh PMOS transistor is coupled to the first node.

In some embodiments, the circuit further includes an eighth PMOS transistor and a seventh NMOS transistor. The source terminal of the eighth PMOS transistor is coupled to the first positive supply level. A gate terminal of the eighth PMOS transistor is coupled to the first enable signal in a third voltage domain. The drain terminal of the eighth PMOS transistor is coupled to the source terminal of the third PMOS transistor. The source terminal of the seventh NMOS transistor is coupled to the negative supply level. A gate terminal of the seventh NMOS transistor is coupled to a second enable signal in a second voltage domain. A drain terminal of the seventh NMOS transistor is coupled to a source terminal of the first NMOS transistor.

In some embodiments, the reference level is substantially equal to the first positive supply level minus the second positive supply level.

In some embodiments, the circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The input signal varies in a first voltage domain from a negative supply level to a first positive supply level. The first input tracking signal varies in a third voltage domain from a reference level to a first positive supply level. The reference level is higher than the negative supply level. The source terminal of the second PMOS transistor is coupled to the first positive supply level. The gate terminal of the second PMOS transistor is biased by the reference level. The drain terminal of the second PMOS transistor is coupled to the source terminal of the first PMOS transistor. The source terminal of the third PMOS transistor is coupled to the drain terminal of the first PMOS transistor. The gate terminal of the third PMOS transistor is biased by the reference level. A drain terminal of the third PMOS transistor is coupled to the first node. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in a second voltage domain from a negative supply level to a second positive supply level. The source terminal of the first NMOS transistor is coupled to a negative supply level. A drain terminal of the second NMOS transistor is coupled to the first node. The gate terminal of the second NMOS transistor is biased by a second positive supply level. The source terminal of the second NMOS transistor is coupled to the drain terminal of the first NMOS transistor. A first inverted signal that varies in a first voltage domain is generated at a first node.

In some embodiments, the first voltage difference window of the first voltage domain is greater than the second voltage difference window of the second voltage domain. The first voltage difference window is larger than the third voltage difference window of the third voltage domain. In some embodiments, the second voltage difference window is substantially equal to the third voltage difference window.

In some embodiments, the circuit further includes a first tracking high circuit and a first tracking low circuit. A first tracking high circuit is coupled between the input terminal and the gate terminal of the first PMOS transistor. The first tracking high circuit is configured to convert the input signal into a first input tracking signal. A first tracking row circuit is coupled between the input terminal and the gate terminal of the first NMOS transistor. The first tracking row circuit is configured to convert the input signal into a second input tracking signal.

In some embodiments, the circuit further comprises a second tracking row circuit coupled with the first node. The second tracking row circuit is configured to convert the first inverted signal into a second inverted signal that varies in a second voltage domain. In some embodiments, the circuit further comprises an inverter coupled between the second tracking row circuit and the output terminal. The inverter generates an output signal that varies in the second voltage domain according to the second inverted signal.

In some embodiments, the method comprises a first varying in a third voltage domain from a reference level to a first positive supply level based on an input signal varying in a first voltage domain from a negative supply level to a first positive supply level. 1 generating an input tracking signal; generating, based on the input signal, a second input tracking signal that varies in a second voltage domain from a reference level to a first positive supply level; biasing the pull-up transistor using the first input tracking signal; and biasing the full row transistor using the second input tracking signal.

In some embodiments, the first voltage difference window of the first voltage domain is greater than the second voltage difference window of the second voltage domain, and the first voltage difference window is greater than the third voltage difference window of the third voltage domain. In some embodiments, the second voltage difference window is substantially equal to the third voltage difference window.

The foregoing description sets forth features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. In addition, those skilled in the art should appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Examples

Embodiment 1. A circuit comprising:

a first inverter coupled to an input terminal, the input terminal receiving an input signal varying in a first voltage domain from a negative supply level to a first positive supply level; and

a second inverter coupled between the first inverter and an output terminal, the second inverter generating an output signal varying in a second voltage domain from the negative supply level to a second positive supply level;

including,

The first inverter,

a first PMOS transistor biased by a first input tracking signal generated from the input signal, the first input tracking signal varying in a third voltage domain from a reference level to the first positive supply level; , the reference level is higher than the negative supply level; and

a first NMOS transistor biased by a second input tracking signal generated from the input signal, wherein the second input tracking signal varies in the second voltage domain.

A circuit comprising

Example 2. The method of Example 1,

A first voltage difference window of the first voltage domain is larger than a second voltage difference window of the second voltage domain, and the first voltage difference window is larger than a third voltage difference window of the third voltage domain. Big one, circuit.

Example 3. The method of Example 2,

and the second voltage difference window is substantially the same as the third voltage difference window.

Example 4. The method of Example 1,

The first inverter,

a second PMOS transistor - the source terminal of the second PMOS transistor is coupled to the first positive supply level, the gate terminal of the second PMOS transistor is biased by the reference level, and the drain terminal of the second PMOS transistor is coupled to the source terminal of the first PMOS transistor;

a third PMOS transistor - a source terminal of the third PMOS transistor coupled to a drain terminal of the first PMOS transistor, a gate terminal of the third PMOS transistor biased by the reference level, and a drain of the third PMOS transistor terminal coupled to the first node; and

a second NMOS transistor - a drain terminal of the second NMOS transistor coupled to the first node, a gate terminal of the second NMOS transistor biased by the second positive supply level, and a source terminal of the second NMOS transistor is coupled to the drain terminal of the first NMOS transistor -

further comprising,

and the source terminal of the first NMOS transistor is coupled to the negative supply level, and the first inverter is configured to generate on the first node a first inverted signal that varies in the first voltage domain.

Example 5. The method of Example 4,

a first tracking high circuit coupled between the input terminal and a gate terminal of the first PMOS transistor, the first tracking high circuit configured to convert the input signal to the first input tracking signal;

a first tracking low circuit coupled between the input terminal and a gate terminal of the first NMOS transistor, the first tracking low circuit configured to convert the input signal to the second input tracking signal; and

a second tracking row circuit coupled between the first node and the second inverter, the second tracking row circuit configured to convert the first inverted signal to a second inverted signal with a change in the second voltage domain;

further comprising,

and the second inverter is configured to invert the second inverted signal to the output signal.

Example 6. The method of Example 5,

The first tracking high circuit,

a fourth PMOS transistor - a source terminal of the fourth PMOS transistor is coupled to a gate terminal of the first PMOS transistor, a gate terminal of the fourth PMOS transistor is coupled to the input terminal, and a drain terminal of the fourth PMOS transistor is coupled to the reference level; and

a fifth PMOS transistor - a source terminal of the fifth PMOS transistor coupled to a gate terminal of the first PMOS transistor, a gate terminal of the fifth PMOS transistor coupled to the reference level, and a drain terminal of the fifth PMOS transistor coupled to the reference level is coupled to the input terminal -

including,

The first tracking row circuit,

a third NMOS transistor - a source terminal of the third NMOS transistor is coupled to the second positive supply level, a gate terminal of the third NMOS transistor is coupled to the input terminal, and a drain terminal of the third NMOS transistor is coupled to the coupled to the gate terminal of the first NMOS transistor; and

a fourth NMOS transistor - the source terminal of the fourth NMOS transistor is coupled to a gate terminal of the first NMOS transistor, the gate terminal of the fourth NMOS transistor is coupled to the second positive supply level, the fourth NMOS transistor the drain terminal of the coupled to the input terminal -

A circuit comprising:

Example 7. The method of Example 5,

The first tracking high circuit,

a fourth PMOS transistor - a source terminal of the fourth PMOS transistor is coupled to a gate terminal of the first PMOS transistor, a gate terminal of the fourth PMOS transistor is coupled to the input terminal, and a drain terminal of the fourth PMOS transistor is coupled to the reference level; and

a first resistor, a first terminal of the first resistor coupled to the first positive supply level, and a second terminal of the first resistor coupled to a gate terminal of the first PMOS transistor;

including,

The first tracking row circuit,

a third NMOS transistor - a source terminal of the third NMOS transistor is coupled to a gate terminal of the first NMOS transistor, a gate terminal of the third NMOS transistor is coupled to the input terminal, and a drain terminal of the third NMOS transistor is coupled to the second positive supply level; and

a second resistor, a first terminal of the second resistor coupled to a gate terminal of the first NMOS transistor, and a second terminal of the second resistor coupled to the negative supply level;

A circuit comprising:

Example 8. The method of Example 5,

A first feedback loop further comprising:

a fifth NMOS transistor, a drain terminal of the fifth NMOS transistor coupled to the first node, and a gate terminal of the fifth NMOS transistor coupled to the second positive supply level; and

sixth NMOS transistor - a drain terminal of the sixth NMOS transistor is coupled to a source terminal of the fifth NMOS transistor, a gate terminal of the sixth NMOS transistor is coupled to the output terminal, and a source terminal of the sixth NMOS transistor is coupled to the negative supply level -

A circuit comprising:

Example 9. The method of Example 8,

a third inverter;

a second tracking high circuit coupled between the first node and the third inverter, the second tracking high circuit configured to convert the first inverted signal to a third inverted signal that varies in the third voltage domain; and

second feedback loop

further comprising,

The second feedback loop,

a sixth PMOS transistor, a source terminal of the sixth PMOS transistor coupled to the first positive supply level, and a gate terminal of the sixth PMOS transistor coupled to the third inverter; and

seventh PMOS transistor - a source terminal of the seventh PMOS transistor is coupled to a drain terminal of the sixth PMOS transistor, a gate terminal of the seventh PMOS transistor is coupled to the reference level, and a drain terminal of the seventh PMOS transistor is coupled to the first node -

A circuit comprising:

Example 10. The method of Example 4,

eighth PMOS transistor—the source terminal of the eighth PMOS transistor is coupled to the first positive supply level, and the gate terminal of the eighth PMOS transistor is coupled to a first enable signal in the third voltage domain. and a drain terminal of the eighth PMOS transistor is coupled to a source terminal of the third PMOS transistor; and

a seventh NMOS transistor—a source terminal of the seventh NMOS transistor is coupled to the negative supply level, a gate terminal of the seventh NMOS transistor is coupled to a second enable signal in the second voltage domain, the seventh NMOS transistor the drain terminal of the transistor is coupled to the source terminal of the first NMOS transistor;

Further comprising a circuit.

Example 11. The method of Example 1,

and the reference level is substantially equal to the first positive supply level minus the second positive supply level.

Embodiment 12. A circuit comprising:

a first PMOS transistor biased by a first input tracking signal generated from an input signal, the input signal varying in a first voltage domain from a negative supply level to a first positive supply level, the first input tracking signal being a reference varying in a third voltage domain from a level to the first positive supply level, the reference level being higher than the negative supply level;

a second PMOS transistor - the source terminal of the second PMOS transistor is coupled to the first positive supply level, the gate terminal of the second PMOS transistor is biased by the reference level, the drain terminal of the second PMOS transistor is coupled to the source terminal of the first PMOS transistor;

a third PMOS transistor - a source terminal of the third PMOS transistor coupled to a drain terminal of the first PMOS transistor, a gate terminal of the third PMOS transistor biased by the reference level, and a drain of the third PMOS transistor terminal coupled to the first node;

a first NMOS transistor biased by a second input tracking signal generated from the input signal, the second input tracking signal varying in a second voltage domain from the negative supply level to a second positive supply level, wherein the first the source terminal of the NMOS transistor is faulted to the negative supply level; and

a second NMOS transistor - a drain terminal of the second NMOS transistor coupled to the first node, a gate terminal of the second NMOS transistor biased by the second positive supply level, and a source terminal of the second NMOS transistor is coupled to the drain terminal of the first NMOS transistor -

including,

and a first inverted signal varying in the first voltage domain is generated on the first node.

Example 13. The method of Example 12,

wherein a first voltage difference window of the first voltage domain is greater than a second voltage difference window of the second voltage domain, and the first voltage difference window is greater than a third voltage difference window of the third voltage domain. .

Example 14. The method of Example 13,

and the second voltage difference window is substantially the same as the third voltage difference window.

Example 15. The method of Example 12,

a first tracking high circuit coupled between an input terminal and a gate terminal of the first PMOS transistor, the first tracking high circuit configured to convert the input signal to the first input tracking signal; and

a first tracking row circuit coupled between the input terminal and a gate terminal of the first NMOS transistor, the first tracking row circuit configured to convert the input signal to the second input tracking signal;

Further comprising a circuit.

Example 16. The method of Example 12,

further comprising a second tracking row circuit coupled with the first node, wherein the second tracking row circuit is configured to convert the first inverted signal to a second inverted signal that varies in the second voltage domain. Circuit.

Example 17. The method of Example 16,

and an inverter coupled between the second tracking row circuit and an output terminal, wherein the inverter generates an output signal that varies in the second voltage domain in response to the second inverted signal.

Example 18. A method comprising:

generating a first input tracking signal varying in a third voltage domain from a reference level to the first positive supply level based on an input signal varying in a first voltage domain from a negative supply level to a first positive supply level step;

generating, based on the input signal, a second input tracking signal that varies in a second voltage domain from a reference level to the first positive supply level;

biasing a pull-up transistor using the first input tracking signal; and

biasing a pull-low transistor using the second input tracking signal;

A method comprising

Example 19. The method of Example 18,

wherein a first voltage difference window of the first voltage domain is larger than a second voltage difference window of the second voltage domain, and the first voltage difference window is larger than a third voltage difference window of the third voltage domain. .

Embodiment 20 The method of embodiment 19, wherein the second voltage difference window is substantially the same as the third voltage difference window.

Claims (10)

in the circuit,
a first inverter coupled to an input terminal, the input terminal receiving an input signal varying in a first voltage domain from a negative supply level to a first positive supply level;
a second inverter coupled between the first inverter and an output terminal, the second inverter generating an output signal that varies in a second voltage domain from the negative supply level to a second positive supply level; and
a first feedback loop coupled between an output of the first inverter and an output of the second inverter, the first feedback loop configured to receive an output signal from the second inverter and operate in response to the output signal from the second inverter
including,
The first inverter,
a first PMOS transistor biased by a first input tracking signal generated from the input signal, the first input tracking signal varying in a third voltage domain from a reference level to the first positive supply level; , the reference level is higher than the negative supply level;
a first NMOS transistor biased by a second input tracking signal generated from the input signal, the second input tracking signal varying in the second voltage domain; and
a second PMOS transistor configured to be biased by the reference level independent of the first input tracking signal, a source terminal of the second PMOS transistor coupled to the first positive supply level, a drain terminal of the second PMOS transistor comprising: coupled to the source terminal of the first PMOS transistor;
A circuit comprising According to claim 1,
A first voltage difference window of the first voltage domain is larger than a second voltage difference window of the second voltage domain, and the first voltage difference window is larger than a third voltage difference window of the third voltage domain. Big one, circuit. 3. The method of claim 2,
and the second voltage difference window is the same as the third voltage difference window. According to claim 1,
The first inverter,
a third PMOS transistor—a source terminal of the third PMOS transistor coupled to a drain terminal of the first PMOS transistor, a gate terminal of the third PMOS transistor biased by the reference level, and a drain of the third PMOS transistor terminal coupled to the first node; and
a second NMOS transistor - a drain terminal of the second NMOS transistor coupled to the first node, a gate terminal of the second NMOS transistor biased by the second positive supply level, and a source terminal of the second NMOS transistor is coupled to the drain terminal of the first NMOS transistor -
further comprising,
and the source terminal of the first NMOS transistor is coupled to the negative supply level, and the first inverter is configured to generate on the first node a first inverted signal that varies in the first voltage domain. 5. The method of claim 4,
a first tracking high circuit coupled between the input terminal and a gate terminal of the first PMOS transistor, the first tracking high circuit configured to convert the input signal to the first input tracking signal;
a first tracking low circuit coupled between the input terminal and a gate terminal of the first NMOS transistor, the first tracking low circuit configured to convert the input signal to the second input tracking signal; and
a second tracking row circuit coupled between the first node and the second inverter, the second tracking row circuit configured to convert the first inverted signal to a second inverted signal with a change in the second voltage domain;
further comprising,
and the second inverter is configured to invert the second inverted signal to the output signal. 6. The method of claim 5,
The first feedback loop.
a fifth NMOS transistor, a drain terminal of the fifth NMOS transistor coupled to the first node, and a gate terminal of the fifth NMOS transistor coupled to the second positive supply level; and
sixth NMOS transistor - a drain terminal of the sixth NMOS transistor is coupled to a source terminal of the fifth NMOS transistor, a gate terminal of the sixth NMOS transistor is coupled to the output terminal, and a source terminal of the sixth NMOS transistor is coupled to the negative supply level -
A circuit comprising: According to claim 1,
The first inverter,
a third PMOS transistor - a source terminal of the third PMOS transistor coupled to a drain terminal of the first PMOS transistor, a gate terminal of the third PMOS transistor biased by the reference level, and a drain of the third PMOS transistor terminal coupled to the first node; and
a second NMOS transistor - a drain terminal of the second NMOS transistor coupled to the first node, a gate terminal of the second NMOS transistor biased by the second positive supply level, and a source terminal of the second NMOS transistor is coupled to the drain terminal of the first NMOS transistor -
further comprising: wherein the first inverter is configured to generate on the first node a first inverted signal that varies in the first voltage domain;
The circuit is
eighth PMOS transistor—the source terminal of the eighth PMOS transistor is coupled to the first positive supply level, and the gate terminal of the eighth PMOS transistor is coupled to a first enable signal in the third voltage domain. and a drain terminal of the eighth PMOS transistor is coupled to a source terminal of the third PMOS transistor; and
a seventh NMOS transistor—a source terminal of the seventh NMOS transistor is coupled to the negative supply level, a gate terminal of the seventh NMOS transistor is coupled to a second enable signal in the second voltage domain, the seventh NMOS transistor the drain terminal of the transistor is coupled to the source terminal of the first NMOS transistor;
Further comprising a circuit. According to claim 1,
and the reference level is equal to the first positive supply level minus the second positive supply level. in the circuit,
a first PMOS transistor biased by a first input tracking signal generated from an input signal, the input signal varying in a first voltage domain from a negative supply level to a first positive supply level, the first input tracking signal being a reference varying in a third voltage domain from level to said first positive supply level, said reference level being higher than said negative supply level;
a second PMOS transistor - the source terminal of the second PMOS transistor is coupled to the first positive supply level, the gate terminal of the second PMOS transistor is biased by the reference level, the drain terminal of the second PMOS transistor is coupled to the source terminal of the first PMOS transistor;
a third PMOS transistor—a source terminal of the third PMOS transistor coupled to a drain terminal of the first PMOS transistor, a gate terminal of the third PMOS transistor biased by the reference level, and a drain of the third PMOS transistor terminal coupled to the first node;
a first NMOS transistor biased by a second input tracking signal generated from the input signal, the second input tracking signal varying in a second voltage domain from the negative supply level to a second positive supply level, wherein the first the source terminal of the NMOS transistor is faulted to the negative supply level; and
a second NMOS transistor - a drain terminal of the second NMOS transistor coupled to the first node, a gate terminal of the second NMOS transistor biased by the second positive supply level, and a source terminal of the second NMOS transistor is coupled to the drain terminal of the first NMOS transistor -
including,
and a first inverted signal varying in the first voltage domain is generated on the first node. In the method,
generating a first input tracking signal varying in a third voltage domain from a reference level to the first positive supply level based on an input signal varying in a first voltage domain from a negative supply level to a first positive supply level step;
generating, based on the input signal, a second input tracking signal that varies in a second voltage domain from the negative supply level to a second positive supply level;
biasing a first pull-up transistor of a first inverter using the first input tracking signal;
biasing a pull-low transistor of the first inverter using the second input tracking signal;
biasing a second pull up transistor of the first inverter using the reference level independent of the first input tracking signal, a first terminal of the second pull up transistor coupled to the first positive supply level and , a second terminal of the second pull-up transistor coupled to a terminal of the first pull-up transistor;
generating an output signal by a second inverter based on the output of the first inverter; and
a first feedback loop receiving an output signal from the second inverter and operating in response to an output signal from the second inverter;
A method comprising

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