KR102360352B1 - Display device - Google Patents

Abstract

An object of the present invention is to provide a method for preventing an electrical short between a gate metal layer and a data metal layer in a stepped portion of a gate insulating layer.
To this end, the data metal layer may be configured to be positioned inside the gate metal layer region while having a distance greater than or equal to the overlay margin. In addition, the intersection portion (ie, the intersection line or the intersection region) of the data metal layer and the gate metal layer may be configured to be positioned within the semiconductor pattern region while having a distance greater than or equal to the overlay margin.
Accordingly, an electrical short circuit between the data metal layer and the gate metal layer in the stepped portion of the gate insulating layer can be effectively prevented.

Description

Display device

The present invention relates to a display device, and more particularly, to a display device capable of preventing an electrical short between a gate metal layer and a data metal layer.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display devices (PDPs), organic Various flat display devices such as an organic light emitting diode (OLED) are being used.

Among these flat panel display devices, the liquid crystal display device is widely used because it has advantages of miniaturization, light weight, thinness, and low power driving.

1 is a cross-sectional view schematically illustrating a thin film transistor of an array substrate for a conventional liquid crystal display device.

Referring to FIG. 1 , the thin film transistor includes a gate electrode 24 , a semiconductor pattern 42 on the gate electrode 24 , and source and drain electrodes 54 and 56 spaced apart from each other on the semiconductor pattern 42 . includes In addition, a gate insulating layer 30 is formed on the gate electrode 24 along the entire surface of the substrate 11 .

As a display device has a large area, a panel load increases, which may cause a problem in signal transmission through the signal wiring.

The semiconductor pattern 42 and the source and drain electrodes 54 and 56 are formed through a separate mask process. However, in the mask process for forming the semiconductor pattern 42 , in the dry etching process for forming the semiconductor pattern 42 , the portion of the gate insulating film 30 located in the region from which the semiconductor material is removed is dry etched. A problem of thinning occurs as part of the thickness is removed under the influence of In particular, since the stepped portion ST, which is the portion of the gate insulating film 30 on the outer side of the gate electrode 24, is formed to have a thinner thickness than other portions due to deposition characteristics, the stepped portion ST is dry-type for forming the semiconductor pattern 42 . During the etching process, it has a thinner thickness. Moreover, microcracks may exist in the stepped portion ST.

On the other hand, when the source and drain electrodes 54 and 56 are formed, the source and drain electrodes 54 and 56 are shifted ( shift) to be present on the stepped portion ST of the gate insulating layer 30 .

In this case, dielectric breakdown occurs in the step portion ST of the thin gate insulating film in a reliable environment such as high temperature, and the source electrode 54 or drain electrode 56 and the gate electrode 24 are electrically shorted. defects will occur. That is, the low-resistance copper that forms the source and drain electrodes 54 and 56 or the gate electrode 56 through the dielectric breakdown caused by a micro-crack or the like existing in the stepped portion ST. The material moves and causes an electrical short.

As such, in the conventional structure, there is a problem in that the gate metal layer and the data metal layer are electrically short-circuited through the step portion of the gate insulating layer.

An object of the present invention is to provide a method for preventing an electrical short between a gate metal layer and a data metal layer in a stepped portion of a gate insulating layer.

In order to achieve the above object, the present invention provides a gate wiring and a gate electrode on a substrate, a gate insulating film on the gate wiring and the gate electrode, a first semiconductor pattern positioned on the gate insulating film to correspond to the gate electrode, Provided is a display device comprising a source electrode and a drain electrode spaced apart from each other on a semiconductor pattern, wherein the source electrode is spaced apart from an outer edge of the gate electrode by an overlay margin or more to be positioned inside the gate electrode region.

In this case, the cross line, which is an outer edge portion of the gate electrode that intersects the drain electrode, may be spaced apart from the outer edge of the first semiconductor pattern by an overlay margin or more to be positioned inside the first semiconductor pattern region.

In addition, the cross region of the gate wiring and the data wiring may be configured to be spaced apart from the outer edge of the second semiconductor pattern by an overlay margin or more to be located inside the region of the second semiconductor pattern.

In addition, the source electrode may be configured to be positioned inside the first semiconductor pattern region.

In addition, the gate electrode and/or the source electrode and the drain electrode may include copper (Cu).

In the present invention, the data metal layer (eg, the source electrode) may have a distance greater than or equal to the overlay margin and may be configured to be positioned inside the region of the gate metal layer (eg, the gate electrode). Accordingly, even if the position of the data metal layer is relatively shifted due to an overlay error, it is located inside the gate metal layer region, and thus an electrical short between the data metal layer and the gate metal layer through the stepped portion of the gate insulating layer can be prevented.

In addition, the intersection portion (ie, intersection line or cross region) of the data metal layer (eg, drain electrode or data line) and the gate metal layer (eg, gate electrode or gate wiring) has a distance greater than or equal to the overlay margin, and the semiconductor pattern region to be located inside. Accordingly, even if the position of the intersection is relatively shifted due to an overlay error, it is located inside the semiconductor pattern region, thereby preventing an electrical short between the data metal layer and the gate metal layer through the stepped portion of the gate insulating film at the intersection. .

As such, according to the present invention, it is possible to effectively prevent an electrical short between the gate metal layer and the data metal layer in the stepped portion of the gate insulating layer.

1 is a cross-sectional view schematically showing a thin film transistor of an array substrate for a conventional liquid crystal display device.
2 is a plan view schematically illustrating an array substrate of a liquid crystal display according to an embodiment of the present invention.
FIG. 3 is an enlarged view of a portion of the thin film transistor shown in FIG. 2 and an intersection region of the data line and the gate line;
4 is a view showing a case in which the source electrode and the drain electrode are relatively shifted in the embodiment of the present invention.
5 is a diagram illustrating a case in which a data line is relatively shifted according to an embodiment of the present invention;
6 is a cross-sectional view taken along cut lines AA and BB of FIG. 3 ;

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

2 is a plan view schematically illustrating an array substrate of a liquid crystal display according to an embodiment of the present invention. FIG. 3 is an enlarged view of the portion of the thin film transistor and the intersection area of the data line and the gate line of FIG. 2, and for convenience of explanation, the pixel electrode and the common electrode located in the pixel area are omitted.

The liquid crystal display according to the embodiment of the present invention includes an array substrate 100 and a counter substrate facing the same, for example, a color filter substrate, and a liquid crystal layer filled between the array substrate 100 and the color filter substrate.

2 and 3 , on the array substrate 100 , a plurality of gate wirings and data wirings 122 and 152 that cross each other and define a plurality of pixel regions P are formed on the inner surface of the substrate. The plurality of pixel areas P are arranged in a matrix form in the display area.

The gate wiring 122 extends in the first direction, for example, along the row direction, and the data wiring 152 extends in the second direction, for example, along the column direction.

In this embodiment, the pixel arrangement structure of the Z inversion method is illustrated as an example. In this regard, each data line 152 may be configured to be alternately connected to the pixel areas P located on both sides. That is, one side of the data line 156 is connected to the pixel region P connected to the (2n-1)-th gate line 122 (ie, the pixel region P located in the (2n-1)-th row line). and the other side of the data line 156 may be configured to be connected to the pixel area P connected to the 2n-th gate line 122 (ie, the pixel area P located in the 2n-th row line).

In such a connection structure, when dot inversion is implemented, each data line 152 receives a data voltage having the same polarity during each frame. That is, the data driving circuit outputs the data voltage of the same polarity to the data line 156 during each frame. Accordingly, the voltage output variation width of the data driving circuit, that is, the swing width is reduced, and power consumption can be reduced.

Meanwhile, a pixel arrangement structure different from the pixel arrangement structure of the Z inversion driving method may be used.

In the pixel region P, a thin film transistor T connected to the corresponding gate and data lines 122 and 152 is formed.

The thin film transistor T includes a gate electrode 124 , a first semiconductor pattern 142 , and source and drain electrodes 154 and 156 .

The gate electrode 124 is connected to the gate wiring 122 and is formed in the same mask process as the gate wiring 122 . The gate electrode 124 may be configured to protrude from the gate wiring 122 into the pixel region P, for example. The gate wiring and the gate electrodes 122 and 124 are preferably formed of, for example, copper (Cu) as a low-resistance material, but the present invention is not limited thereto.

A gate insulating layer (see 130 of FIG. 6 ) may be formed along the entire surface of the substrate on the gate wiring and the gate electrodes 122 and 124 . At this time, a stepped portion ST of the gate insulating layer is present along the gate wiring and the outer edges of the gate electrodes 122 and 124 .

The first semiconductor pattern 142 is positioned on the gate insulating layer on the gate electrode 124 . The first semiconductor pattern 142 may be made of amorphous silicon, but is not limited thereto.

Meanwhile, the second semiconductor pattern 144 may be formed on the gate insulating layer corresponding to the cross region Ac where the gate wiring and the data wirings 122 and 152 intersect and overlap each other.

The source and drain electrodes 154 and 156 are positioned to be spaced apart from each other on the first semiconductor pattern 142 . The source electrode 154 is connected to the data line 152 , and the source and drain electrodes 154 and 156 are formed in the same mask process as the data line 152 . The data line 152 and the source and drain electrodes 154 and 156 are preferably formed of, for example, copper (Cu) as a low-resistance material, but the present invention is not limited thereto.

Meanwhile, the source and drain electrodes 154 and 156 and the data line 152 are formed by a separate mask process from the first and second semiconductor patterns 142 and 144 .

The source electrode 154 may be formed to have a “U” shape. In this case, the channel of the semiconductor layer 124 is also configured to have a “U” shape, but is not limited thereto.

A substantially plate-shaped pixel electrode 172 connected to the drain electrode 156 of the thin film transistor T may be formed in the pixel region P. The pixel electrode 172 may be configured to directly contact the drain electrode 156 without a contact hole. As another example, an insulating layer having a drain contact hole may be formed between the drain electrode 156 and the pixel electrode 172 , and the pixel electrode 172 is configured to contact the drain electrode 156 through the drain contact hole. can be

A passivation layer (refer to 180 of FIG. 6 ) serving as an insulating layer may be formed on the pixel electrode 172 over the entire surface of the substrate, and the common electrode 182 may be formed substantially over the entire surface of the display area on the passivation layer. The common electrode 182 may be configured to have a plurality of bar-shaped electrode patterns 183 extending in the second direction to correspond to the pixel region P. In addition, openings 184 may be formed between the plurality of electrode patterns 183 .

As described above, an electric field is generated between the common electrode 182 and the pixel electrode 172 formed on the same array substrate 100, and the liquid crystal layer can be driven by the electric field.

As described above, the so-called AH-IPS (advanced high-performance in-plane switching) method in which the plate-shaped pixel electrode 172 and the common electrode 182 having the plurality of electrode patterns 183 thereon are disposed is used. It has been described as an example, but is not limited thereto.

For example, another type of AH-IPS method in which the pixel electrode 172 having a plurality of bar-shaped electrode patterns is disposed with a plate-shaped common electrode 182 and a protective film interposed thereon may be used.

As another example, the common electrode 182 having a plurality of electrode patterns and the pixel electrode 172 having a plurality of electrode patterns are positioned on the same layer or on different layers with an insulating film interposed therebetween, and the electrode pattern of the common electrode 182 . An IPS method in which the electrode patterns of the pixel electrode 172 and the pixel electrode 172 are alternately arranged in the pixel region P may be used.

As another example, unlike the above, the common electrode is not formed on the array substrate 100 but on the color filter substrate opposite to it, and drives the liquid crystal through the electric field generated between the array substrate 100 and the color filter substrate. A TN (twisted nematic) or VA (vertical alignment) type liquid crystal display device may be used.

In addition, a liquid crystal display device of a liquid crystal driving method different from the above example may be used.

Hereinafter, a structure for preventing a short circuit between the data metal layer and the gate metal layer as a characteristic structure of the present embodiment will be described in more detail.

Referring again to FIG. 3 , in the thin film transistor T, the source electrode 154 is configured to be disposed inside the region where the gate electrode 124 is formed, that is, the gate electrode region GA. In particular, the source electrode 154 is preferably formed such that a distance d1 spaced apart from the outer edge Lg of the gate electrode 124 is greater than or equal to a specific distance. Here, the specific distance corresponds to the overlay margin of the exposure equipment. In this case, the overlay margin is in the range of about 1.5 to 4.5 m, which corresponds to the range of the overlay margin of exposure equipments currently commonly used.

In this way, if the source electrode 154 is designed to be formed inside the gate electrode 124 while being spaced apart from the outer edge Lg of the gate electrode 124 by more than an overlay margin, although the mask process for forming the gate electrode 124 or the source electrode Even if an exposure process error, ie, an overlay error, occurs in the mask process for forming 154 , the overlay error does not exceed the designed separation distance d1 between the source electrode 154 and the gate electrode 124 .

Referring to FIG. 4 in this regard, even if the source electrode 154 is shifted in any direction relative to the gate electrode 124 by the overlay error, the overlay error is less than or equal to the designed separation distance d1, The source electrode 154 is positioned within the gate electrode area GA without leaving the gate electrode area GA.

Accordingly, even if the source electrode 154 is relatively shifted by the overlay error, the source electrode 154 does not exist in the stepped portion ST of the gate insulating layer formed along the outer edge Lg of the gate electrode 124 . .

As such, even if an overlay error occurs, as the source electrode 154 does not exist in the stepped portion ST of the gate insulating film, even if insulation breakdown occurs in the stepped portion ST of the thin gate insulating film, the stepped portion ( An electrical short circuit failure between the gate electrode 124 and the source electrode 154 through ST) can be prevented.

Furthermore, the first semiconductor pattern 142 is preferably designed to substantially cover the entire source electrode 154 . That is, the source electrode 154 may be designed to be positioned inside the region where the first semiconductor pattern 142 is formed. In particular, as shown in FIG. 3 , the source electrode 154 may be designed to be spaced apart from the outer edge Ls1 of the first semiconductor pattern 142 by a predetermined distance. In this case, an electrical short between the source electrode 154 and the gate electrode 124 may be reduced.

In this regard, in the dry etching process for forming the first semiconductor pattern 142 , the portion of the gate insulating film located near the outer edge Ls1 of the first semiconductor pattern 142 is more strongly affected by the dry etching and thus has a thickness The degree of loss tends to be relatively high compared to other parts. As such, when the edge of the source electrode is designed to protrude out of the first semiconductor pattern region as in the prior art, the gate insulating film portion positioned below the edge portion of the source electrode is a portion positioned near the first semiconductor pattern and has a thickness loss. Since the degree of insulation breakdown is increased, the possibility that the edge of the source electrode is electrically shorted with the gate electrode through the lower gate insulating film also increases.

On the other hand, as in the present embodiment, the first semiconductor pattern 142 covers the entire source electrode 154 , in particular, the source electrode 154 is a predetermined distance from the outer edge Ls1 of the first semiconductor pattern 142 . When the source electrode 154 is designed to be spaced apart and positioned inside the first semiconductor pattern 142 , the first semiconductor pattern 142 is a short circuit preventing means between the source electrode 154 and the gate electrode 124 . , it is possible to reduce an electrical short between the source electrode 154 and the gate electrode 124 through the gate insulating layer near the first semiconductor pattern 142 .

On the other hand, part of the drain electrode 156 is located inside the gate electrode region GA, and the remaining part extends into the pixel region P beyond the outer edge Lg of the gate electrode 124 , that is, the gate electrode region GA. configured to be As such, the drain electrode 156 has a shape substantially crossing the outer edge Lg of the gate electrode 124 .

As such, the drain electrode 156 and the gate electrode 124 through the gate insulating film step ST at the intersection line Lc, which is the outer edge Lg portion of the gate electrode 124 crossing the drain electrode 156, The first semiconductor pattern 142 is designed to prevent an electrical short circuit between them.

In this regard, the first semiconductor pattern 142 extends to the outside of the gate electrode 124 in the extending direction of the drain electrode 156 while covering the crossing line Lc. A portion of the first semiconductor pattern 142 extending along the drain electrode 156 is referred to as an extension portion 142a.

At this time, the end edge Ls1e, which is the outer edge of the extended portion 142a that intersects the drain electrode 156, is an overlay margin from the outer edge Lg of the gate electrode 124 closest thereto, that is, the intersection line Lc, to the outside direction. It is preferable to be designed to be spaced apart by the above distance d2.

In addition, both sides Ls1s, which are the outer edges of the extended portion 142a positioned in both directions of the drain electrode 156, are from both sides of the corresponding drain electrode 156, that is, from both ends of the crossing line Lc, respectively. Preferably, it is designed to be spaced apart by a distance d2 equal to or greater than the overlay margin in the outward direction.

As such, the first semiconductor pattern 142 is designed such that the distance d2 from the outer edge Lg of the gate electrode 124 crossing the drain electrode 156, that is, the separation distance d2 from the crossing line Lc, is equal to or greater than the overlay margin. it is preferable

When the first semiconductor pattern 142 is designed in this shape, even if an overlay error occurs in the mask process of forming the gate electrode 124 or the mask process of forming the drain electrode 156, the overlay error is The designed separation distance d2 between the first semiconductor pattern 142 and the intersecting line Lc is not exceeded.

Referring to FIG. 4 in this regard, even if the drain electrode 156 is relatively shifted in any direction by the overlay error, that is, even if the crossing line Lc is relatively shifted in any direction, this overlay error is determined by the designed separation distance d2. Hereinafter, the crossing line Lc is positioned within the region of the first semiconductor pattern 142 without departing from the region of the first semiconductor pattern 142 .

Accordingly, even if the crossing line Lc is relatively shifted by the overlay error, the first semiconductor pattern 142 is present in the step portion ST of the gate insulating layer positioned at the crossing line Lc. Therefore, even if dielectric breakdown occurs in the stepped portion ST of the gate insulating film of the crossing line Lc, the first semiconductor pattern 142 present in this portion is short-circuited between the drain electrode 156 and the gate electrode 124 . As it acts as a prevention means, an electrical short circuit between the drain electrode 156 and the gate electrode 124 through the stepped portion ST can be prevented.

Meanwhile, in the present embodiment, the second semiconductor pattern 144 is used to prevent an electrical short between the gate wirings 122 and the data wirings 152 in the intersection region Ac where they intersect.

In this regard, the second semiconductor pattern 144 is formed to cover the cross region Ac. That is, the cross region Ac is configured to be disposed inside the region of the second semiconductor pattern 144 . In particular, the intersection region Ac is preferably formed such that a distance d3 spaced apart from the outer edge Ls2 of the second semiconductor pattern 144 is equal to or greater than the overlay margin.

As such, when the cross region Ac is designed to be formed inside the region of the second semiconductor pattern 144 by being spaced apart from the outer edge Ls2 of the second semiconductor pattern 144 by an overlay margin or more, although the gate wiring 122 is formed Even if an overlay error occurs during a mask process for performing a mask process or a process for forming the data line 152 , the overlay error does not exceed the designed separation distance d3 between the intersection region Ac and the second semiconductor pattern 144 . .

Referring to FIG. 5 in this regard, even if the intersection area Ac is shifted in any direction relative to the overlay error based on the second semiconductor pattern 144, the overlay error is less than or equal to the designed separation distance d3, The crossing region Ac is positioned within the region of the second semiconductor pattern 144 without departing from the region of the second semiconductor pattern 144 .

Accordingly, even if the crossing region Ac is relatively shifted by the overlay error, the width of the gate wiring 122 of the gate insulating layer step ST (that is, the crossing region Ac) positioned in the crossing region Ac The second semiconductor pattern 144 is present on both sides of the direction). Accordingly, even if dielectric breakdown occurs in the step portion ST of the gate insulating film of the crossing region Ac, the second semiconductor pattern 144 existing in this portion is short-circuited between the data line 152 and the gate line 122 . As it acts as a prevention means, an electrical short between the gate wiring 122 and the data wiring 152 through the stepped portion ST can be prevented.

The above-described electrical short circuit protection structure is particularly effective when at least one of the data metal layer and the gate metal layer is formed of copper. That is, copper has a higher movement characteristic through the dielectric breakdown step ST than other metal materials, and thus an electrical short occurs when the data metal layer and the gate metal layer are formed of copper. Therefore, the data metal layer and/or the gate metal layer It is effective when it is formed of copper. Of course, even when it is formed of a metal material other than copper, the above-described electrical short circuit preventing structure can be effectively used.

Hereinafter, a cross-sectional structure of an array substrate for a liquid crystal display according to an embodiment of the present invention will be described with further reference to FIG. 6 . 6 is a cross-sectional view taken along cutting lines AA and BB of FIG. 3, and the diagram taken along the cutting line AA on the left shows an intersection area of the gate wiring and the data wiring, and is shown along the cutting line BB on the right. One drawing shows a cross-sectional structure of a film transistor and a pixel region.

6 , in the array substrate 100 for a liquid crystal display device, a gate wiring 122 and a gate electrode 124 are formed on the substrate 111 . The gate wiring and the gate electrodes 122 and 124 may be formed through a first mask process. Here, the gate wiring and the gate electrodes 122 and 124 are preferably formed of copper (Cu) as a low-resistance metal material, but the present invention is not limited thereto.

The gate insulating layer 130 is formed substantially along the entire surface of the substrate 111 on the gate wiring and the gate electrodes 122 and 124 . The gate insulating layer 130 may be formed in a single-layer or multi-layer structure using, for example, at least one of silicon oxide (SiO ₂ ) and silicon nitride (SiNx) as an inorganic insulating material.

A first semiconductor pattern 142 is formed on the gate insulating layer 130 to correspond to the gate electrode 124 . Furthermore, the second semiconductor pattern 144 may be formed on the gate line 122 to correspond to the cross region Ac with the data line 152 .

The first and second semiconductor patterns 142 and 144 may be formed through a second mask process. In the second mask process, a dry etching process is performed. During this dry etching, portions other than the gate insulating film 130 located under the first and second semiconductor patterns 142 and 144 are in the thickness direction due to the effect of dry etching. Part of it is removed to make it thinner. In particular, since the stepped portion of the gate insulating layer 130 is formed to have a relatively thin thickness during the deposition process, it has a thinner thickness when the dry etching process is performed.

In this regard, for example, the gate insulating layer 130 may be formed to a thickness of about 5900 Å during deposition. After the etching process for the first and second semiconductor patterns 142 and 144 is performed, the stepped portion ST is about 2500 Å. Since it has a thickness of a certain degree, a significant thickness loss may occur. Accordingly, dielectric breakdown may occur in the stepped portion ST of the gate insulating layer 130 .

Source and drain electrodes 154 and 156 spaced apart from each other are formed on the first semiconductor pattern 142 . The source and drain electrodes 154 and 156 , the first semiconductor pattern 142 and the gate electrode 124 constitute the thin film transistor T .

In addition, a data line 152 intersecting the gate line 122 is formed on the second semiconductor pattern 144 .

The data line 152 and the source and drain electrodes 154 and 156 may be formed through a third mask process.

Here, in order to prevent an electrical short circuit through the stepped portion ST of the gate insulating layer 130 , the source electrode 154 is a distance d1 from the outer edge of the gate electrode 124 (see Lg in FIG. 3 ) greater than or equal to the overlay margin. is spaced apart from each other and is designed to be positioned inside the gate electrode 124 . Accordingly, even if the source electrode 154 is relatively shifted by the overlay error, the shifted source electrode 154 is still located inside the gate electrode area GA, so that the step portion of the thin gate insulating layer 130 is formed. Since it does not exist in ST, an electrical short between the source electrode 154 and the gate electrode 122 through the stepped portion ST can be prevented.

In addition, the source electrode 154 may be designed to be positioned inside the region of the first semiconductor pattern 142 . Accordingly, the first semiconductor pattern 142 can reduce an electrical short between the source electrode 154 and the gate electrode 122 .

In addition, the first semiconductor pattern 142 extending to the outside of the gate electrode 124 along the drain electrode 154 is an outer portion of the gate electrode 124 crossing the drain electrode 154 , that is, the crossing line Lc. ) and is designed to be spaced apart by a distance d2 equal to or greater than the overlay margin. Accordingly, even if the intersecting line Lc is relatively shifted by the overlay error, the shifted intersecting line Lc is still located inside the region of the first semiconductor pattern 142, and thus the gate at the intersecting line Lc Since the stepped portion ST of the insulating layer 130 is covered by the first semiconductor pattern 142, the drain electrode 156 and the gate electrode 122 are passed through the stepped portion ST of the crossing line Lc. An electrical short circuit between them can be prevented.

In addition, the cross region Ac of the gate wiring and the data wiring 122 and 152 is spaced apart from the outer edge of the second semiconductor pattern 144 (see Ls2 in FIG. 3 ) by a distance equal to or greater than the overlay margin, and the second semiconductor pattern 144 region It is designed to be located inside. Accordingly, even if the intersecting region Ac is positioned relatively shifted by the overlay error, the shifted intersecting region Ac is still located inside the region of the second semiconductor pattern 144, so that the gate in the intersecting region Ac is Since the step portion ST of the insulating layer is covered by the second semiconductor pattern 144 , an electrical short between the gate wiring 122 and the data line 152 through the stepped portion ST of the crossing region Ac This can be prevented.

A pixel electrode 172 may be formed on the drain electrode 156 in units of the pixel region P and contact the drain electrode 156 . The pixel electrode 172 may be formed through a fourth mask process.

Meanwhile, after the pixel electrode 172 is formed, the data line 152 and the source and drain electrodes 154 and 156 may be formed.

A passivation layer 180 may be formed substantially on the entire surface of the substrate 111 on the pixel electrode 172 . Although not specifically illustrated, a fifth mask process may be performed in forming the passivation layer 180 . Accordingly, the contact hole exposing the gate pad positioned at the end of the gate line 122 and the data line 152 are formed. A contact hole exposing the data pad positioned at the end may be formed in the passivation layer 180 . Here, a contact hole exposing the gate pad is also formed on the gate insulating layer 130 on the gate pad.

A common electrode 182 may be formed on the passivation layer 180 . The common electrode 182 may be formed through a sixth mark process. The common electrode 182 may include a plurality of electrode patterns 183 facing the pixel electrode 172 in the pixel region P. In addition, openings 184 may be formed between the plurality of electrode patterns 183 .

The array substrate 100 configured as described above is a counter substrate facing the same, and is bonded to the color filter substrate with the liquid crystal layer interposed therebetween.

Meanwhile, in the above-mentioned bar, the structure for preventing the short circuit between the gate metal layer and the data metal layer in the liquid crystal display has been mainly described, but the structure for preventing the short circuit can be applied to other types of display devices such as organic light emitting devices.

As described above, according to an embodiment of the present invention, the data metal layer (eg, the source electrode) may be configured to be positioned within the region of the gate metal layer (eg, the gate electrode) while having a distance greater than or equal to the overlay margin. Accordingly, even if the position of the data metal layer is relatively shifted due to an overlay error, it is located inside the gate metal layer region, and thus an electrical short between the data metal layer and the gate metal layer through the stepped portion of the gate insulating layer can be prevented.

In addition, the intersection portion (ie, intersection line or cross region) of the data metal layer (eg, drain electrode or data line) and the gate metal layer (eg, gate electrode or gate wiring) has a distance greater than or equal to the overlay margin, and the semiconductor pattern region to be located inside. Accordingly, even if the position of the intersection is relatively shifted due to an overlay error, it is located inside the semiconductor pattern region, thereby preventing an electrical short between the data metal layer and the gate metal layer through the stepped portion of the gate insulating film at the intersection. .

As such, according to the present embodiment, it is possible to effectively prevent an electrical short between the gate metal layer and the data metal layer in the stepped portion of the gate insulating layer.

The above-described embodiment of the present invention is an example of the present invention, and free modifications are possible within the scope included in the spirit of the present invention. Accordingly, the present invention is intended to cover the modifications of the present invention provided they come within the scope of the appended claims and their equivalents.

100: liquid crystal display device 111: substrate
122: gate wiring 124: gate electrode
130: gate insulating layer 142: first semiconductor pattern
144: second semiconductor pattern 152: data wiring
154: source electrode 156: drain electrode
180: protective film 182: common electrode
T: thin film transistor
GA: gate electrode area
ST: Gate insulating film step part
Lc: intersecting line
Ac: intersection
Lg: outer edge of the gate electrode
Ls1: outer edge of the first semiconductor pattern
Ls1e: the end of the first semiconductor pattern extension
Ls1s: both sides of the first semiconductor pattern extension
Ls2: outer edge of the second semiconductor pattern

Claims (6)

a gate wiring and a gate electrode on the substrate;
a gate insulating film on the gate wiring and the gate electrode;
a first semiconductor pattern positioned on the gate insulating layer to correspond to the gate electrode;
a source electrode and a drain electrode spaced apart from each other on the first semiconductor pattern;
The source electrode is spaced apart from the outer edge of the gate electrode by an overlay margin or more and is configured to be located inside the gate electrode region,
The source electrode is disposed within the first semiconductor pattern forming region to be spaced apart from a side of the first semiconductor pattern by a predetermined distance.
The method of claim 1,
the first semiconductor pattern extends outside the gate electrode along the drain electrode;
An intersecting line, which is an outer edge portion of the gate electrode that intersects the drain electrode, is spaced apart from the outer edge of the first semiconductor pattern by at least the overlay margin to be positioned inside the first semiconductor pattern region
display device.
The method of claim 1,
a data line crossing the gate line;
Further comprising a second semiconductor pattern positioned to correspond to the intersection region of the gate wiring and the data wiring,
The intersecting region is spaced apart from the outer edge of the second semiconductor pattern by at least the overlay margin and is configured to be located inside the second semiconductor pattern region.
display device.


delete 4. The method according to any one of claims 1 to 3,
The gate electrode and/or the source electrode and the drain electrode include copper (Cu).
display device. The display device of claim 1 , wherein the overlay margin is 1.5 μm to 4.5 μm.

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