KR102300372B1 - Display device and method for driving thereof - Google Patents

Abstract

The present embodiments relate to a display device that alleviates or prevents gate low voltage distortion caused by a coupling phenomenon, thereby improving image quality, and a driving method thereof.

Description

Display device and its driving method

The present invention relates to a display device for displaying an image.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display device (LCD), a plasma display panel (PDP), an organic Various display devices such as an organic light emitting display device (OLED) are being used.

Various types of signal lines are arranged on the display panel of the display device. In particular, for driving the display panel, gate low voltage lines supplying a gate low voltage to be commonly applied to all sub-pixels are disposed on the display panel.

These gate low voltage lines are disposed adjacent to other signal lines such as data lines. Due to such physical proximity, when a voltage applied through other signal lines such as the gate low voltage lines and adjacent data lines is rapidly changed, a coupling phenomenon occurs to the gate low voltage applied to the display panel through the gate low voltage lines. This can happen.

This coupling phenomenon makes the charging characteristics of the capacitors in the subpixels non-uniform, which may lead to image defects such as horizontal cross talk.

An object of the present exemplary embodiments is to provide a display device and a driving method thereof, which alleviate or prevent gate low voltage distortion caused by a coupling phenomenon, thereby improving image quality.

According to an exemplary embodiment, a display panel in which data lines, gate lines, and gate low voltage lines are disposed and a plurality of subpixels are disposed, a data driver supplying data voltages to the data lines, and gate low voltage lines are provided. Gate low voltage compensation for applying a compensated gate low voltage compensated for the gate low voltage to the display panel through the gate low voltage lines based on the feedback gate low voltage and the reference gate low voltage to which the gate low voltage applied to the display panel is fed back It provides a display device including a part.

Another embodiment includes the steps of applying a gate low voltage to the display panel through gate low voltage lines, receiving a feedback gate low voltage and a reference gate low voltage from which the gate low voltage applied to the display panel is fed back; Provided is a method of driving a display device, comprising: applying a compensated gate low voltage compensated for a gate low voltage based on a gate low voltage and a reference gate low voltage to a display panel through gate low voltage lines.

According to the present embodiments as described above, it is possible to provide a display device and a driving method thereof, which alleviate or prevent gate low voltage distortion caused by a coupling phenomenon, thereby improving image quality.

1 is a schematic system configuration diagram of a display device according to the present exemplary embodiment.
2 is a diagram illustrating a gate low voltage supply of the display device according to the present exemplary embodiment.
3 is a diagram illustrating a gate low voltage (VGL) coupling phenomenon of the display device according to the present exemplary embodiment.
4A may be implemented by using a white organic light emitting diode (WOLED) and RGB color filters (CFr, CFg, CFb).
4B and 4C are diagrams exemplarily explaining the setting of each data signal in the N frame and the N+1 frame in the display panel of FIG. 4A .
5A is a diagram illustrating a gate low voltage compensation configuration for alleviating gate low voltage distortion caused by a gate low voltage coupling phenomenon of the display device according to the present exemplary embodiment.
5B is an exemplary diagram of the gate low voltage compensator 400 of the display device according to the present exemplary embodiment.
6 is another exemplary diagram of a gate low voltage compensator of the display device according to the present exemplary embodiment.
7 is another exemplary diagram of a gate low voltage compensator of the display device according to the present exemplary embodiment.
8A is a circuit diagram of a gate low voltage compensator when there is only one feedback line.
8B is a circuit diagram of a gate low voltage compensator when there are two feedback lines.
9 is an exemplary diagram of a sub-pixel structure of a display device according to the present exemplary embodiment.
10 is a diagram illustrating a gate low voltage (VGL) coupling phenomenon under the subpixel structure of FIG. 9 .
11 is a diagram illustrating that the gate low voltage (VGL) coupling phenomenon and the reference voltage distortion caused by the gate low voltage (VGL) compensation of the display device according to the present exemplary embodiment are alleviated.
12 is a flowchart of a method of driving a display device according to example embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It will be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a schematic system configuration diagram of a display device 100 according to the present exemplary embodiment. 2 is a diagram illustrating a gate low voltage supply of the display device 100 according to the present exemplary embodiments.

Referring to FIG. 1 , the display device 100 according to the present exemplary embodiments includes m data lines DL1, ... , DLm, m: natural numbers) and n gate lines GL1, ... , GLn, In order to drive the display panel 110 in which n: a natural number) is crossed and a plurality of sub-pixels (SP) are arranged in a matrix type, and m data lines DL1, ..., DLm The data driver 120 supplies voltages to the m data lines DL1, ..., DLm, and the n gate lines GL1 to sequentially drive the n gate lines GL1, ..., GLn. , ... , GLn) and a gate driver 130 for sequentially supplying scan signals, and a timing controller 140 for controlling the data driver 120 and the gate driver 130 .

In the display panel 110 , sub-pixels (SPs) may be disposed at points where one data line and one or more gate lines cross each other.

The timing controller 140 starts scanning according to the timing implemented in each frame, and converts the image data (Data) input from the interface to match the data signal format used by the data driver 120 to convert the converted image data ( Data') and control the data drive at an appropriate time according to the scan.

The timing controller 140 outputs various control signals to control the data driver 120 and the gate driver 130 .

The gate driver 130 sequentially supplies a scan signal of an on voltage or an off voltage to the n gate lines GL1, ..., GLn under the control of the timing controller 140, The n gate lines GL1, ..., GLn are sequentially driven.

The gate driver 130 may be positioned on only one side of the display panel 110 , or may be divided into two and positioned on both sides of the display panel 110 as shown in FIG. 2 , depending on the driving method. .

In addition, as shown in FIG. 2 , the gate driver 130 includes a plurality of gate driver integrated circuits (Gate Driver IC, GDIC #1, ..., GDIC #5) positioned on both sides of the display panel 110 . , GDIC #1', ... , GDIC #5'), and a plurality of these gate driver integrated circuits (GDIC #1, ..., GDIC #5, GDIC #1', ... , GDIC #5') is connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method, or a gate in panel (GIP) method. ) type and may be disposed directly on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases.

Each of the above-mentioned gate driver integrated circuits (GDIC #1, ..., GDIC #5, GDIC #1', ..., GDIC #5') may include a shift register, a level shifter, and the like. .

The data driver 120 stores image data inputted from a host system (not shown) in a memory (not shown) under the control of the timing controller 140 , and when a specific gate line is opened, the corresponding image data (Data') is converted into analog data voltage Vdata and supplied to the m data lines DL1, ..., DLm, thereby driving the m data lines DL1, ..., DLm.

As shown in FIG. 2 , the data driver 120 includes a plurality of source driver integrated circuits (Source Driver IC, also referred to as a Data Driver IC), SDIC #1, ... , SDIC #12. ), the plurality of source driver integrated circuits SDIC #1, ... , SDIC #12 may include a Tape Automated Bonding (TAB) method or a Chip-on-Glass (COG) method. As a result, it may be connected to a bonding pad of the display panel 110 , or may be directly disposed on the display panel 110 , or may be integrated and disposed on the display panel 110 in some cases.

Each of the plurality of source driver integrated circuits (SDIC #1, ... , SDIC #12) mentioned above includes a shift register, a latch, a digital analog converter (DAC), an output butter, and the like. Accordingly, for sub-pixel compensation, an analog-to-digital converter (ADC) may further include an analog-to-digital converter (ADC) that senses an analog voltage value, converts it into a digital value, and generates and outputs sensed data.

Referring to FIG. 2 , the plurality of source driver integrated circuits SDIC #1, ... , SDIC #12 may be implemented in a Chip On Film (COF) method. In each of the plurality of source driver integrated circuits (SDIC #1, ... , SDIC #12), one end is at least one source printed circuit board (Source Printed Circuit Board, S-PCB #1, S-PCB #2) ), and the other end is bonded to the display panel 110 .

On the other hand, the above-mentioned host system (not shown), along with the digital video data (Data) of the input image, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, Various timing signals including the clock signal CLK are transmitted to the timing controller 140 .

The timing controller 140 converts the data input from the host system (not shown) to match the data signal format used by the data driver 120 and outputs the converted image data Data'. In order to control the data driver 120 and the gate driver 130 , a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, a clock signal, etc. timing signals are received, and various control signals are generated. It outputs to the data driver 120 and the gate driver 130 .

For example, the timing controller 140 controls the gate driver 130 , a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). : Gate Control Signals (GCSs) including Gate Output Enable) are output. The gate start pulse GSP starts the operation of the gate driver integrated circuits GDIC #1, ..., GDIC #5, GDIC #1', ..., GDIC #5' constituting the gate driver 130 . Control the timing. The gate shift clock GSC is a clock signal commonly input to the gate driver integrated circuits GDIC #1, ..., GDIC #5, GDIC #1', ..., GDIC #5', and is a scan signal Controls the shift timing of (gate pulse). The gate output enable signal GOE designates timing information of the gate driver integrated circuits GDIC #1, ..., GDIC #5, GDIC #1', ..., GDIC #5'.

The timing controller 140 controls the data driver 120 , a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE). ) and the like, and output data control signals (DCSs: Data Control Signals). The source start pulse SSP controls the data sampling start timing of the source driver integrated circuits SDIC #1, ..., SDIC #12 constituting the data driver 120 . The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source driver integrated circuits SDIC #1, ..., SDIC #12. The source output enable signal SOE controls the output timing of the data driver 120 . In some cases, a polarity control signal POL may be further included in the data control signals DCSs to control the polarity of the data voltage of the data driver 120 . If the data 'input to the data driver 120 is transmitted according to the mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

The display device 100 schematically illustrated in FIG. 1 is, for example, a Liquid Crystal Display Device (LCD), a Plasma Display Device, and an Organic Light Emitting Display Device (OLED). ) and so on.

Each subpixel disposed on the above-described display panel 110 includes circuit elements such as transistors and capacitors. For example, when the display panel 110 is an organic light emitting display panel, circuit elements such as an organic light emitting diode, two or more transistors, and one or more capacitors are formed in each sub-pixel.

Meanwhile, referring to FIGS. 1 and 2 , in order to drive each subpixel, the gate driver 130 includes a gate signal Gate including a gate high voltage VGH and a gate low voltage VGL through each gate line. Signal) is applied to the display panel 110 .

Referring to FIG. 1 , a gate signal may be applied to a gate of a switching transistor in each subpixel through gate lines GLs. In this case, a unique pixel voltage of the corresponding sub-pixel, such as the data voltage Vdata, may be applied to one end of the capacitor C in each sub-pixel.

Referring to FIG. 2 , the display device 100 may further include a power supply unit 200 that generates a gate high voltage VGH and a gate low voltage VGL and supplies them to the gate driver 130 . The power supply unit 200 generates a gate high voltage VGH greater than or equal to the threshold voltage of the switching transistor included in each subpixel and a gate low voltage VGL less than the threshold voltage.

Here, the power supply unit 200 is also called a power management integrated circuit (PMIC), and a source printed circuit board (S-PCB #1, S-PCB #2) and a flexible flat cable (FFC: Flexible Flat Cable) Alternatively, it may be disposed on a control printed circuit board (C-PCB) connected through a flexible printed circuit (FPC) or the like. The timing controller 140 may also be disposed on the control printed circuit board (C-PCB).

The power supply unit 200 integrates the gate low voltage extended to the control printed circuit board (C-PCB) and/or the source printed circuit board (S-PCB) and the display panel 110 through the gate low voltage line to the gate driver. A gate low voltage is supplied to the circuits.

It may be supplied to the display panel 110 through the source driver integrated circuits SDIC #1, ... , SDIC #12 disposed on the source printed circuit board (S-PCB #1, S-PCB #2). .

Meanwhile, referring to FIGS. 1 and 2 , a plurality of gate driver integrated circuits (Gate Driver IC, GDIC #1, ..., GDIC) positioned on both sides of the display panel 110 to drive each sub-pixel. #5, GDIC #1', ..., GDIC #5') transmits a gate signal including a gate high voltage VGH and a gate low voltage VGL through each gate line to the display panel 110 ) is approved. Accordingly, the display panel 110 has a power supply unit (Gate Driver IC, GDIC #1, ..., GDIC #5, GDIC #1', ..., GDIC #5') A gate high voltage line (not shown) for supplying the gate high voltage VGH from 200 is formed. In addition, the display panel 110 has a gate low voltage (Gate Driver IC, GDIC #1, ..., GDIC #5, GDIC #1', ..., GDIC #5') A gate low voltage line VGLL for supplying VGL is formed.

For example, as shown in FIG. 2 , some of the gate driver integrated circuits (GDIC #1, ..., GDIC #5, GDIC #1', ..., GDIC #5') are of the display panel 110 . A first gate low voltage line VGLL1 is formed on one side and supplies a gate low voltage to them. In addition, since the other parts of the gate driver integrated circuits (GDIC #1', ..., GDIC #5') are located on the other side of the display panel 110 , the second gate low voltage line VGLL2 supplies them with a gate low voltage. ) is formed.

Meanwhile, in the display panel 110 , other voltage lines such as data lines are formed in addition to the gate high voltage line (not shown) and the gate low voltage line VGLL.

In particular, a coupling phenomenon may occur in the gate low voltage VGL applied to the gate low voltage line VGLL by other voltage lines adjacent to the gate low voltage line VGLL.

This coupling phenomenon of the gate low voltage VGL will be described with reference to FIG. 3 .

3 is a diagram illustrating a gate low voltage (VGL) coupling phenomenon of the display device 100 according to the present exemplary embodiment.

Referring to FIG. 3 , when the data voltage Vdata supplied through the data lines changes rapidly, that is, the data voltage Vdata changes from a high level to a low level, or the data voltage Vdata changes from a low level to a high level. , a phenomenon in which the gate low voltage VGL applied through the gate low voltage lines VGLL adjacent to the data lines becomes smaller or larger than the desired voltage value may occur at the point where the data voltage Vdata rapidly changes. have.

For example, the display panel 110 has a red sub-pixel (SPr), a green sub-pixel (SPg), a blue sub-pixel (SPb), and a white sub-pixel (SPb) to prevent a decrease in luminance and color deterioration of a pure color while increasing light efficiency. SPw) (hereinafter abbreviated as RGBW sub-pixel) may be implemented as a sub-pixel structure. At this time, the RGBW sub-pixels (SPr, SPg, SPb, and SPw) are an organic light emitting diode that emits red, green, blue and white light or a white organic light emitting diode (WOLED) and RGB color filters (CFr, CFg as shown in FIG. 4A ). , CFb) can be implemented in such a way.

The display device 100 described above uses the RGBW sub-pixels SPr, SPg, SPb, and SPw to express the desired color coordinates on the display panel 110 in addition to the W sub-pixel SPw and the RGB sub-pixels SPr and SPg. , SPb), some or all of them are compensated for light emission.

For example, as shown in FIG. 4B , the R data signal of the R sub-pixel SPr in the N frame has the lowest luminance value compared to the GB data signal of the GB sub-pixels SPg and SPb, so the luminance value of the R data signal is W It can be replaced with a data signal, and the R data signal can be set to 0. In addition, the luminance of the GB data signal may be lowered based on the R data signal set to 0. As a result, the luminance of the RGB data signal is set to 50, 120, and 80 before data conversion, but is changed to 0, 70, 30, and 50 after data conversion. Meanwhile, as shown in Fig. 4c, for the same RGBW sub-pixels (SPr, SPg, SPb, SPw) in the N+1 frame, the luminance value of the lowest G data signal is replaced with the W data signal, and the luminance of the RB data signal is set to 0. It can be lowered based on the G data signal.

As shown in FIGS. 4B and 4C , the data voltage Vdata of the R subpixel SPr or the G subpixel SPg supplied through the data lines in the N frame and the N+1 frame changes from the high level to the low level. or changes from a low level to a high level, the gate low voltage VGL applied through the gate low voltage lines VGLL adjacent to the data lines in the R subpixel SPr or the G subpixel SPg A phenomenon in which the voltage becomes smaller or larger than the desired voltage value may be more severe.

That is, as shown in FIGS. 4B and 4C , when the data voltage Vdata supplied through the data lines swings, the data line is caused by a kick-back phenomenon inside the display panel 110 . A coupling phenomenon may occur in the gate low voltage VGL applied to the gate low voltage lines VGLLs adjacent to each other.

The coupling phenomenon of the gate low voltage VGL causes non-uniform characteristics of the switching transistor SW to which the gate signal including the gate low voltage VGL is applied, for example, parasitic capacitance between the source and the gate. Due to the non-uniform characteristics of the switching transistor SW, image defects such as horizontal cross talk may occur.

Accordingly, the present embodiments provide a gate low voltage compensation function for reducing gate low voltage distortion caused by a gate low voltage coupling phenomenon, and a configuration and method therefor.

Hereinafter, gate low voltage compensation according to the present embodiments will be described with reference to FIGS. 5A to 11 .

5A is a diagram illustrating a gate low voltage compensation configuration for alleviating a gate low voltage distortion caused by a gate low voltage coupling phenomenon of the display device 100 according to the present exemplary embodiment.

Referring to FIG. 5A , the display device 100 according to the present exemplary embodiments receives the gate low voltage applied to the gate driver 130 through the gate low voltage lines VGLLs as feedback, and the fed back gate low voltage ( Based on VGL_FB (hereinafter referred to as “feedback gate low voltage”) and the reference gate low voltage (VGL_REF), the gate low voltage is compensated, and the compensated gate low voltage (VGL_COMP, hereinafter referred to as “compensated gate low voltage”) and a gate low voltage compensator 400 for applying the voltage to the display panel 130 through the gate low voltage lines VGLLs.

The above-mentioned compensation gate low voltage VGL_COMP is a voltage that causes the reference gate low voltage VGL_REF to be applied to the gate driver 130 to be actually applied to the gate driver 130 . If there is no coupling phenomenon, the compensation gate low voltage VGL_COMP is the same as or almost similar to the reference gate low voltage VGL_REF, but if there is a coupling phenomenon, the compensation gate low voltage VGL_COMP is the reference gate low voltage VGL_REF ) is different from This difference is removed by the coupling phenomenon, so that a voltage equal to the reference gate low voltage VGL_REF is actually applied to the gate driver 130 .

When the gate low voltage compensator 400 is used, when a gate low voltage having a voltage value different from the desired voltage value is applied to the gate driver 130 due to the gate low voltage coupling phenomenon, the gate low voltage having the desired voltage value By allowing the voltage to be compensated and applied to the gate driver 130 , the gate low voltage distortion caused by the gate low voltage coupling phenomenon can be alleviated, and the image quality can be improved accordingly.

Referring to FIG. 5A , the gate low voltage compensator 400 receives a reference gate low voltage VGL_REF from the power supply unit 200 and operates on at least one of the gate low voltage lines VGLL. A feedback gate low voltage (VGL_FB) is received through a feedback line (FBL: Feed Back Line) connected to a feedback node (FBN: Feed Back Node) in the . Here, the feedback node FBN is a specific or arbitrary node on one or two or more gate low voltage lines among the gate low voltage lines VGLL and is a node on the display panel 110 .

The gate low voltage compensator 400 applies the compensation gate low voltage VGL_COMP to the gate low voltage lines VGLLs based on the input reference gate low voltage VGL_REF and the feedback gate low voltage VGL_FB. .

Through the gate low voltage feedback structure and the compensation gate low voltage supply structure as described above, it is possible to efficiently provide gate low voltage compensation.

The compensation gate low voltage VGL_COMP, which the gate low voltage compensator 400 compensates for the gate low voltage applied to the gate driver 130 and applies it back to the gate driver 130 , is commonly applied to a plurality of sub-pixels. As the voltage, it may be a voltage applied to one end of the capacitor C in each sub-pixel.

In this way, by applying the compensation gate low voltage VGL_COMP to one end of the capacitor C in each sub-pixel, it is possible to prevent the charging characteristic of the capacitor C from becoming non-uniform, thereby improving the image quality. can

5B is an exemplary diagram of the gate low voltage compensator 400 of the display device 100 according to the present exemplary embodiment.

Referring to FIG. 5B , the gate low voltage compensator 400 of the display device 100 according to the present exemplary embodiment includes a deviation voltage output unit 510 and a compensation gate low voltage output unit 520 , and the like. can be

Referring to FIG. 5B , the deviation voltage output unit 510 includes the first input terminal I1 receiving the reference gate low voltage VGL_REF from the power supply 200 and the feedback gate low voltage (VGL_REF) from the feedback line FBL. It has a second input terminal I2 that receives VGL_FB and an output terminal O that outputs a deviation voltage (ΔVGL=VGL_REF-VGL_FB) between the reference gate low voltage VGL_REF and the feedback gate low voltage VGL_FB.

The deviation voltage output unit 510 may be implemented as, for example, a kind of comparator or an amplifier (OP AMP). For example, the deviation voltage output unit 510 may be implemented using a commonly used OM AMP.

The compensation gate low voltage output unit 520 outputs the compensation gate low voltage VGL_COMP based on the reference gate low voltage VGL_REF and the deviation voltage ΔVGL to connect the gate low voltage lines through the supply node SN. (VGLLs).

As an example, the compensation gate low voltage output unit 520 may be implemented as a kind of adder, and the compensation gate low voltage VGL_COMP may be obtained by adding the reference gate low voltage VGL_REF and the deviation voltage ΔVGL. .

For example, the compensation gate low voltage output unit 520 outputs the compensation gate low voltage VGL_COMP of V+ΔVGL[V], so that even if a deviation voltage ΔVGL occurs, the gate driver 130 has a desired A voltage value may be applied to the gate low voltage lines VGLLs.

As described above, by implementing the gate low voltage compensator 400 with a simple circuit configuration, when the gate low voltage actually applied to the gate driver 130 is different from the desired voltage value, that is, the gate low voltage due to the coupling phenomenon. When a voltage distortion phenomenon occurs, the compensation gate low voltage VGL_COMP is applied to the gate low voltage lines VGLLs through gate low voltage compensation without using a complicated circuit or expensive device, so that the It is possible to effectively mitigate or prevent gate low voltage distortion from occurring.

6 is another exemplary diagram of the gate low voltage compensator 400 of the display device 100 according to the present exemplary embodiment.

Referring to FIG. 6 , the gate low voltage compensator 400 may include operational amplifier (OP AMP) circuits 610 and 620 .

FIG. 6 is an exemplary diagram in which the gate low voltage compensator 400 is implemented with the OP AMP circuit 610 under the system configuration of the display device 100 illustrated in FIG. 2 .

Referring to FIG. 6 , the OP AMP circuit 610 includes one side of the display panel 110 , for example, five gate driver integrated circuits (GDIC #1, ... , GDIC #5) on the left side of FIG. 6 . A compensation gate low voltage VGL_COMP is applied from the display panel 110 to the gate low voltage line VGLL2 disposed in the left region.

In order for the OP AMP circuit 610 to apply the compensating gate low voltage VGL_COMP to the gate low voltage line VGLL1 disposed in the right region of the display panel 110 , the The gate low voltage actually applied to the first feedback node FBN #1 on the one gate low voltage line VGLL1 is fed back as a feedback gate low voltage VGL_FB through the first feedback line FBL1, and the power supply unit 200 ) receives the reference gate low voltage VGL_REF.

The OP AMP circuit 610 receives the reference gate low voltage VGL_REF and the feedback gate low voltage VGL_FB, and obtains and outputs the compensation gate low voltage VGL_COMP in the manner described above with reference to FIG. The compensation gate low voltage VGL_COMP is applied to the first gate low voltage line VGLL1 disposed in the left region of the panel 110 .

Similarly, the OP AMP circuit 610 connects the other side of the display panel 110, for example, five gate driver integrated circuits (GDIC #1', ..., GDIC #5') on the right side of FIG. 6 . Through this, the compensation gate low voltage VGL_COMP is applied to the second gate low voltage lines VGLL2 disposed in the right region of the display panel 110 .

In order for the OP AMP circuit 620 on the right side to apply the compensation gate low voltage VGL_COMP to the second gate low voltage line VGLL2 disposed in the right region of the display panel 110 , the right side of the display panel 110 . The gate low voltage actually applied to the second feedback node FBN #2 on the second gate low voltage line VGLL2 disposed in the region is fed back as a feedback gate low voltage VGL_FB through the second feedback line FBL2. , the reference gate low voltage VGL_REF is input from the power supply unit 200 .

The OP AMP circuit 610 receives the reference gate low voltage VGL_REF and the feedback gate low voltage VGL_FB, and obtains and outputs the compensation gate low voltage VGL_COMP in the manner described above with reference to FIG. A compensation gate low voltage VGL_COMP is applied to the second gate low voltage lines VGLL2 disposed in the right region of the panel 110 .

As described above, by implementing the gate low voltage compensator 400 with a simple OP AMP circuit 610 configuration, the gate low voltage compensation is achieved through gate low voltage compensation without using a complicated circuit or expensive devices. By allowing it to be applied to the lines VGLL1 and VGLL2, it is possible to effectively alleviate or prevent gate low voltage distortion caused by a coupling phenomenon.

The gate low voltage compensator 400 may be a circuit implemented on a control printed circuit board (C-PCB). In this case, the gate low voltage compensator 400 may be designed with the circuit of FIG. 5 or FIG. 6 . As described above, since the gate low voltage compensator 400 is implemented on the control printed circuit board (C-PCB), there is an advantage in that it is not necessary to change the expensive source driver integrated circuit. In particular, when the gate low voltage compensator 400 is configured with a simple circuit as shown in FIG. 5 or FIG. 6 , the gate low voltage compensator 400 can be easily implemented at low cost on a control printed circuit board (C-PCB). will be able However, the gate low voltage compensator 400 may be included in each source driver integrated circuit SDIC or source printed circuit board S-PCB constituting the data driver 120 .

The first feedback node FBN#1 in which the first feedback line FBL1 is connected to the first gate low voltage line VGLL1 and the second feedback line FBL2 are connected to the second gate low voltage line VGLL2 The positions of the second feedback nodes FBN#2 may be different from each other on the gate low voltage line. For example, as shown in FIG. 5 , the first feedback line FBL1 is connected to the first feedback node FBN#1 of the end point of the first gate low voltage line VGLL1, and the second feedback line FBL2. may be connected to the second feedback node FBN#2 at the midpoint of the second gate low voltage line VGLL2. Accordingly, since different gate low voltages are fed back, the feedback effect of the gate low voltage can be improved.

7 is another exemplary diagram of the gate low voltage compensator 400 of the display device 100 according to the present exemplary embodiment. 8A is a circuit diagram of a gate low voltage compensator when there is only one feedback line. 8B is a circuit diagram of a gate low voltage compensator when there are two feedback lines.

Referring to FIG. 7 , the gate low voltage compensator 400 of the display device 100 according to the present exemplary embodiment includes a first input terminal I1 receiving a reference gate low voltage from the power supply 200 , and a feedback line. A deviation voltage output unit 710 including a second input terminal I2 receiving a feedback gate low voltage from FBL and an output terminal O outputting a deviation voltage between a reference gate low voltage and the feedback gate low voltage, and a compensation It may include a gate low voltage output unit 720 , a filter 730 , and the like.

The deviation voltage output unit 710 and the compensation gate low voltage output unit 720 may be the same as the deviation voltage output unit 510 and the compensation gate low voltage output unit 520 described with reference to FIG. 5B . For example, the deviation voltage output unit 710 may be implemented as a kind of comparator or amplifier (OP AMP), for example, and the compensation gate low voltage output unit 720 may be implemented as a kind of adder. Meanwhile, the filter 730 may be a filter for filtering high-frequency components, that is, a low-frequency pass filter. For example, the filter 730 may be implemented with a capacitor (C) and a resistor (R). Also, the output gain may be adjusted by including a feedback impedance between the second input terminal I2 and the output terminal O of the deviation voltage output unit 710 .

For example, when there is one feedback line (FBL), as shown in FIG. 8A , the gate low voltage compensator 400 includes an amplifier OP AMP serving as a deviation voltage output unit 710, one capacitor C, and a resistor. It may include a low-frequency pass filter 720, a second input (I2) and an output terminal (O) between the feedback resistor (R _H) of the amplifier (OP aMP) for adjusting the output gain, including (R _L). When there are two feedback lines FBL1 and FBL2, the gate low voltage compensator 400 is connected to the amplifier OP AMP which is the deviation voltage output unit 710 and the first feedback line FBL1 as shown in FIG. 8B . Low-frequency pass filter 720 including one capacitor (C1) and resistor (R _L1 ), one capacitor (C2) and resistor (R _{L2 ) connected to the second feed pack line (FBL2), to adjust the output gain For this purpose, a feedback resistor R H} between the second input terminal I2 and the output terminal O of the amplifier OP AMP may be included.

In the above, the gate low voltage compensation for alleviating or preventing the gate low voltage distortion caused by the gate low voltage coupling phenomenon according to the present embodiments has been described.

Hereinafter, when the display device 100 according to the present embodiments is an organic light emitting display device, gate low voltage compensation will be briefly described.

9 is an exemplary diagram of a sub-pixel structure of the display device 100 according to the present exemplary embodiment. 10 is a diagram illustrating a reference voltage (Vref) coupling phenomenon under the sub-pixel structure of FIG. 9 .

When the display device 100 according to the present exemplary embodiments is an organic light emitting display device, each sub-pixel includes an organic light emitting diode (OLED) and at least two transistors and at least one capacitor to drive the same. It may consist of a circuit including

The exemplary diagram of FIG. 9 is an equivalent circuit diagram of a subpixel composed of three transistors T1 , T2 , and T3 and one capacitor C1 . 10 is a diagram illustrating a gate low voltage (VGL) coupling phenomenon under the subpixel structure of FIG. 9 .

Referring to FIG. 9 , each subpixel includes an organic light emitting diode (OLED), a first transistor T1 , a second transistor T2 , a third transistor T3 , and a first capacitor C1 . ) is included.

The first transistor T1 is a driving transistor for driving the organic light emitting diode, and is connected between the organic light emitting diode and a pattern connected to a driving voltage line (DVL) or a driving voltage line (DVL). do. In the first transistor T1 , the second node N2 is a gate node, the first node N1 is a source node or a drain node, and the third node N3 is a drain node or a source node.

The second transistor T2 is a switching transistor that controls on-off of the first transistor T1 , and includes a second node N2 (gate node) and a data line DL of the first transistor T1 . : Data Line).

The third transistor T3 is connected between a first node (N1, a source node or a drain node) of the first transistor T1 and a reference voltage line (RVL) or a pattern connected to the reference voltage line. do.

The first capacitor C1 is connected between the first node N1 and the second node N2 of the first transistor T1 and operates as a storage capacitor that maintains a constant voltage for one frame. do.

Referring to FIG. 9 , on-off of the second transistor T2 is controlled by a scan signal supplied from the first gate line GL. When the second transistor T1 is turned on, the data voltage Vdata supplied from the data line DL is applied to the second node N2 of the first transistor T1.

A switch SW is connected to the end of the reference voltage line RVL. When this switch SW is turned on, the reference voltage Vref is supplied to the reference voltage line RVL, and when turned off, the reference voltage line RVL is converted to an analog-to-digital converter ADC. : Connect to Analog Digital Converter).

On-off of the third transistor T3 is controlled by a sense signal, which is a type of a gate signal supplied through the second gate line GL′. When the switch SW is turned on and the third transistor T3 is turned on, the reference voltage Vref is applied to the first node N1 of the first transistor T1.

When the switch SW is turned off and the third transistor T3 is turned on, the voltage of the first node N1 of the first transistor T1 is sensed by the analog-to-digital converter ADC. The analog-to-digital converter (ADC) converts the sensed voltage into a digital value to generate sensed data, and transmits the generated sensed data to the timing controller 140 .

Here, the sensing voltage of the first node N1 of the first transistor T1 is a voltage reflecting a unique characteristic value such as a threshold voltage of the first transistor T1. Accordingly, the timing controller 140 may perform a compensation process for compensating for a deviation in the intrinsic characteristic value of the first transistor T1 in each subpixel based on the received sensing data. In this sense, the third transistor T3 is also referred to as a sense transistor.

A gate signal including a gate low voltage and a gate high voltage is applied to the gate of the second transistor T2 through gate lines, and data lines crossing the gate line are applied to the second node N2 of the first transistor T1. The data voltage Vdata is applied through the

Accordingly, when the data voltage Vdata supplied through the data lines changes rapidly, that is, as described with reference to FIGS. 4A to 4C , the data voltage Vdata changes from a high level to a low level, or the data voltage Vdata ) is changed from the low level to the high level, at the point where the data voltage Vdata changes abruptly, the gate low voltage VGL of the gate signal crossing the data lines is smaller than the desired voltage value as shown in FIG. 3 . It may decrease or grow.

That is, referring to FIG. 10 , when the data voltage Vdata supplied through the data lines swings, the data lines intersect with the data lines due to a kick-back phenomenon inside the display panel 110 . A coupling phenomenon may occur in the gate low voltage VGL of the gate signal applied to the gate line.

As described above, the coupling phenomenon of the gate low voltage VGL causes non-uniformity of characteristics of the switching transistor SW to which the gate signal including the gate low voltage VGL is applied, for example, parasitic capacitance between the source and the gate. make it Due to the non-uniform characteristics of the switching transistor SW, image defects such as horizontal cross talk may occur.

11 is a diagram illustrating a case in which a gate low voltage (VGL) coupling phenomenon and a reference voltage distortion caused by the gate low voltage (VGL) compensation of the display device according to the present exemplary embodiment are alleviated.

Referring to FIG. 11 , when the gate low voltage VGL compensation as described above is applied, unlike FIG. 10 , the gate low voltage VGL of the gate signal is distorted even at a point where the data voltage Vdata changes rapidly. It can be seen that the phenomenon does not appear.

12 is a flowchart of a method of driving the display device 100 according to the present exemplary embodiment.

Referring to FIG. 12 , the driving method 1200 of the display device 100 according to the present exemplary embodiments applies a gate low voltage VGL to the gate driving unit 130 through the gate low voltage lines VGLL. The step S1210, the step of receiving the feedback gate low voltage VGL_FB and the reference gate low voltage VGL_REF to which the gate low voltage VGL applied to the gate driver 130 are fed back (S1220), and the feedback gate low voltage VGL_REF Applying the compensated gate low voltage VGL_COMP, the gate low voltage compensated for, to the gate driver 130 through the gate low voltage line VGL based on the voltage VGL_FB and the reference gate low voltage VGL_REF (S1230) ), etc.

According to the above-described driving method, when a gate low voltage having a voltage value different from a desired voltage value (reference gate low voltage) is applied to the gate driver 130 due to the coupling phenomenon, the gate low voltage having the desired voltage value is applied to the gate By allowing the driver 130 to compensate and apply, the gate low voltage distortion caused by the gate low voltage coupling phenomenon can be alleviated, and the image quality can be improved accordingly.

2, 6, 7, and 8B, the feedback gate low voltage VGL_FB may include a first gate low voltage VGL_FB1 and a second gate low voltage VGL_FB2. At this time, the first feedback line FBL1 connected to the first gate low voltage line VGLL1 connected to the gate driver integrated circuits (eg, GDIC#1 to GDIC#5) positioned on one side of both sides of the display panel 110 . ) through the first feedback gate low voltage VGL_FB1 may be input. Also, a second feedback line connected to the second gate low voltage line VGLL2 connected to the gate driver integrated circuits (eg, GDIC#1' to GDIC#5') positioned on the other sides of the display panel 110 . The second feedback gate low voltage VGL_FB2 may be input through FBL2.

In this case, the first feedback line FBL1 may be connected to the first feedback node FBN#1 at an end point of the first gate low voltage line VGL_FB1. Also, the second feedback line FBL2 may be connected to the second feedback node FBN#2 at a midpoint of the second gate low voltage line VGL_FB2. Since the positions of the first feedback node FBN#1 and the second feedback node FBN#2 are different, gate low voltages at various positions may be fed back.

Meanwhile, the above-described gate low voltage (VGL) compensation may be equally applied to the gate low voltage (VGL) compensation of the liquid crystal display as well as the organic light emitting display device.

According to the present exemplary embodiments as described above, it is possible to provide a display device 100 and a driving method thereof, which alleviate or prevent gate low voltage distortion caused by a coupling phenomenon, thereby improving image quality. .

In addition, according to the present embodiments, the display device 100 alleviates or prevents the reference voltage distortion caused by the coupling phenomenon of the reference voltage Vref applied to the organic light emitting display panel, thereby improving the image quality. and a driving method thereof.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine the configuration within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: data driving unit
130: gate driver
140: timing controller

Claims (12)

a display panel in which data lines and gate lines are disposed and a plurality of subpixels are disposed;
a data driver supplying a data voltage to the data lines;
a gate driver supplying a gate signal including a gate low voltage and a gate high voltage to the gate lines; and
A gate low voltage supplied to the gate driver through a gate low voltage line is fed back through a feedback line connected to a feedback node on the gate low voltage line based on a feedback gate low voltage and a reference gate low voltage. a gate low voltage compensator for applying the compensated gate low voltage for which the voltage is compensated to the gate driving unit through the gate low voltage line;
The feedback node is a node positioned on the display panel. delete According to claim 1,
The gate low voltage compensator,
a first input terminal receiving the reference gate low voltage from a power supply unit, a second input terminal receiving the feedback gate low voltage from the feedback line, and an output terminal outputting a voltage difference between the reference gate low voltage and the feedback gate low voltage; a deviation voltage output unit having a
and a compensation gate low voltage output unit for outputting the compensation gate low voltage and applying the compensation gate low voltage to the gate low voltage line based on the reference gate low voltage and the deviation voltage. According to claim 1,
The gate low voltage compensator,
A display device comprising an OP AMP (Operational Amplifier) circuit. 5. The method of claim 4,
The gate low voltage compensator,
A display device further comprising a filter for filtering high-frequency components between the feedback line and the OP AMP. According to claim 1,
The gate low voltage compensator,
A display device, characterized in that the circuit is implemented on a printed circuit board or a control printed circuit board. According to claim 1,
The gate driver,
comprising two or more gate driver integrated circuits,
and the gate low voltage line is sequentially connected to the gate driver integrated circuits. 8. The method of claim 7,
The two or more gate driver integrated circuits are located on both sides of the display panel,
The gate low voltage compensator,
A first feedback gate low voltage is input through a first feedback line connected to a first gate low voltage line connected to gate driver integrated circuits located on one side of both sides of the display panel, and the other side of both sides of the display panel A display device, characterized in that the second feedback gate low voltage is input through a second feedback line connected to a second gate low voltage line connected to the gate driver integrated circuits located in the . 9. The method of claim 8,
and the first feedback line is connected to an end point of the first gate low voltage line, and the second feedback line is connected to a midpoint of the second gate low voltage line. applying a gate low voltage to a gate driver through gate low voltage lines;
receiving a feedback gate low voltage and a reference gate low voltage fed back through a feedback line connected to a feedback node on the gate low voltage line in which the gate low voltage supplied to the gate driver is supplied through a gate low voltage line; and
applying a compensated gate low voltage compensated for the gate low voltage to the gate driver through the gate low voltage line based on the feedback gate low voltage and the reference gate low voltage;
The feedback node is a node positioned on a display panel on which at least a portion of the gate low voltage line is disposed. 11. The method of claim 10,
The feedback gate low voltage includes a first gate low voltage and a second gate low voltage,
A first feedback gate low voltage is input through a first feedback line connected to a first gate low voltage line connected to gate driver integrated circuits located on one side of both sides of the display panel, and the other side of both sides of the display panel A method of driving a display device, characterized in that the second feedback gate low voltage is input through a second feedback line connected to a second gate low voltage line connected to the gate driver integrated circuits located in the . 12. The method of claim 11,
The first feedback line is connected to a first feedback node of an end point of the first gate low voltage line, and the second feedback line is connected to a second feedback node of a midpoint of the second gate low voltage line. a method of driving a display device.

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