KR102273876B1 - Fabricating method for thin film transistor array substrate - Google Patents

Abstract

The present invention discloses a method of manufacturing a thin film transistor array substrate. In the disclosed method for manufacturing a thin film transistor array substrate of the present invention, a first region in which a second gate electrode is disposed, a second region in which a first gate electrode is disposed, and a third region disposed adjacent to the first and second regions are provided. A substrate comprising: is prepared, and a first gate insulating layer is disposed on the substrate. Thereafter, a semiconductor layer material is disposed on the substrate, and a gate insulating layer material is disposed on the semiconductor layer material. A third gate electrode material is disposed on the gate insulating layer material, and a photoresist is disposed on the gate electrode material. Then, the photoresist is formed by using a halftone mask disposed opposite to the substrate and including a transmissive portion facing the first region, a semi-transmissive portion facing the second region, and a blocking portion corresponding to the third region. Etch.

Description

Method for manufacturing a thin film transistor array substrate TECHNICAL FIELD

The present invention relates to a method of manufacturing a thin film transistor array substrate, and more particularly, to a method of manufacturing a thin film transistor array substrate that simplifies the process of a thin film transistor array substrate including a thin film transistor having a double gate electrode structure.

With the development of light and portable information display devices, the development of the information society is accelerating. Liquid crystal displays (LCDs), which are already representative of thin flat panel displays, have been commercialized and replaced cathode ray tube displays, and organic light emitting displays (Organic Lights) are a next-generation flat panel display. Emitting Diode Display) is in the spotlight.

The organic light emitting display device does not need a separate light source such as a backlight used in a liquid crystal display device, so it can be thinner than a liquid crystal display device, and has excellent color reproducibility, resulting in thinner and clearer image quality. In addition, the organic light emitting display device has a wide viewing angle, excellent contrast ratio, fast response time, and low power consumption.

The organic light emitting display device uses a thin film transistor array substrate including a plurality of thin film transistors for driving. Such a thin film transistor array substrate is manufactured through a manufacturing process using photolithography technology. However, a process using a photosensitive organic resin material called photoresist requires a number of processes such as exposure, development, firing and peeling. Accordingly, as the number of photolithography processes increases, there is a problem in that the manufacturing cost increases.

The present invention provides a thin film transistor array substrate with a simple process by arranging the second gate insulating film of the first thin film transistor, the third gate insulating film of the second thin film transistor, and the third gate electrode using one mask using one mask. An object of the present invention is to provide a manufacturing method of

The method of manufacturing a thin film transistor array substrate of the present invention for solving the problems of the prior art as described above includes a first region in which a second gate electrode is disposed, a second region in which a first gate electrode is disposed, and the first and second regions A substrate including a third region disposed adjacent to the region is prepared, and a first gate insulating layer is disposed on the substrate. Thereafter, a semiconductor layer material is disposed on the substrate, and a gate insulating layer material is disposed on the semiconductor layer material. A third gate electrode material is disposed on the gate insulating layer material, and a photoresist is disposed on the gate electrode material. Then, the photoresist is formed by using a halftone mask disposed opposite to the substrate and including a transmissive portion facing the first region, a semi-transmissive portion facing the second region, and a blocking portion corresponding to the third region. Etch. Through this, a process required for disposing the first thin film transistor and the second thin film transistor may be simplified, and manufacturing cost may be reduced.

The method for manufacturing a thin film transistor array substrate according to the present invention comprises disposing the second gate insulating film of the first thin film transistor, the third gate insulating film of the second thin film transistor, and the third gate electrode using one mask using a single mask. , which has the effect of simplifying the process.

1 is a cross-sectional view illustrating an organic light emitting display device including a thin film transistor array substrate according to the present invention.
2A to 2G are diagrams illustrating a method of manufacturing a thin film transistor array substrate according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments introduced below are provided as examples so that the spirit of the present invention can be sufficiently conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And in the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals refer to like elements throughout.

1 is a cross-sectional view illustrating an organic light emitting display device including a thin film transistor array substrate according to the present invention. Referring to FIG. 1 , an organic light emitting display device according to the present invention includes a first thin film transistor Ts1 , a second thin film transistor Ts2 , and an organic light emitting diode. Here, the first thin film transistor Ts1 and the second thin film transistor Ts2 are electrically connected, and the second thin film transistor Ts2 may drive the organic light emitting diode. In this case, the first thin film transistor Ts1 may be a switching thin film transistor, and the second thin film transistor Ts2 may be a driving thin film transistor.

In detail, the first gate electrode 101 of the first thin film transistor Ts1 is disposed on the substrate 100 . In addition, the second gate electrode 102 of the second thin film transistor Tr2 is disposed to be spaced apart from the first gate electrode 101 . Here, the second gate electrode 102 of the second thin film transistor Tr2 may serve as a light blocking layer of the second thin film transistor Tr2. Through this, the optical reliability of the organic light emitting display device can be improved.

The first gate electrode 101 and the second gate electrode 102 may be formed of the same material in the same layer. The first gate electrode 101 and the second gate electrode 102 may be alloys formed from Cu, Mo, Al, Ag, Ti, Ta, or a combination thereof. In addition, although it is formed as a single metal layer in the drawings, it may be formed by stacking at least two or more metal layers in some cases.

A first gate insulating layer 103 is disposed on the substrate including the first gate electrode 101 and the second gate electrode 102 . The first semiconductor layer 104 of the first thin film transistor Ts1 and the second semiconductor layer 105 of the second thin film transistor Ts2 are disposed on the first gate insulating layer 103 .

Here, the first semiconductor layer 104 and the second semiconductor layer 105 may be formed of an oxide semiconductor material. The oxide semiconductor material has high transmittance and high electron mobility.

The oxide semiconductor material may represent AxByCzO (x, y, z ≥ 0), and each of A, B, and C is selected from Zn, Cd, Ga, In, Sn, Hf and Zr. Preferably, the oxide semiconductor material may be selected from ZnO, InGaZnO ₄ , ZnInO, ZnSnO, InZnHfO, SnInO and SnO, but is not limited thereto.

A second gate insulating layer 106 is disposed on the first semiconductor layer 104 , and a third gate insulating layer 107 is disposed on the second semiconductor layer 105 . In detail, the second gate insulating film 106 is disposed to overlap the channel region of the first semiconductor layer 104 , and the third gate insulating film 107 is the channel region of the second semiconductor layer 105 . placed overlapping in In this case, the second gate insulating layer 106 and the third gate insulating layer 107 may serve as an etch stop layer.

A third gate electrode 108 of the second thin film transistor Tr2 is disposed on the third gate insulating layer 107 . Here, the second gate insulating layer 106 and the third gate insulating layer 107 may be formed using a mask used to form the third gate electrode 108 . Through this, there is an effect of simplifying the organic light emitting display device manufacturing process.

A passivation layer 113 is disposed on the substrate 100 including the third gate electrode 108 . A first source electrode 109 and a first drain electrode 110 of the first thin film transistor Tr1 are disposed on the passivation layer 113 . In addition, the second source electrode 111 and the second drain electrode 112 of the second thin film transistor Tr2 are disposed on the passivation layer 113 .

The first source electrode 109 , the first drain electrode 110 , the second source electrode 111 , and the second drain electrode 112 may be formed of the same material in the same layer. The first source electrode 109 , the first drain electrode 110 , the second source electrode 111 , and the second drain electrode 112 are formed from Cu, Mo, Al, Ag, Ti, Ta, or a combination thereof. It may be an alloy that is formed. In addition, although it is formed as a single metal layer in the drawings, it may be formed by stacking at least two or more metal layers in some cases.

The first source electrode 109 and the first drain electrode 110 are connected to the first semiconductor layer 104 through a contact hole formed on the passivation layer 113 . The second source electrode 111 and the second drain electrode 112 are connected to the second semiconductor layer 105 through a contact hole formed on the passivation layer 113 .

As described above, the first thin film transistor Tr1 and the second thin film transistor Tr2 are disposed on the substrate 100 . Here, the second thin film transistor Tr2 may have a double gate electrode structure including two gate electrodes. Here, the light reliability and current capability of the device may be improved due to the second gate electrode 102 of the second thin film transistor Tr2. Through this, electro-optical characteristics and luminance uniformity of the display device may be improved.

A planarization layer 114 is disposed on the substrate 100 including the first source electrode 109 , the first drain electrode 110 , the second source electrode 111 , and the second drain electrode 112 . . The first electrode 115 of the organic light emitting device is disposed on the planarization layer. The first electrode 115 is connected to the second drain electrode 112 of the second thin film transistor Tr2 through a contact hole formed on the planarization layer 114 . Here, the first electrode 115 may be an anode electrode. However, the first electrode 115 is not limited thereto, and the first electrode 115 may be a cathode. Hereinafter, an embodiment in which the first electrode 115 is an anode will be mainly described.

The first electrode 115 may be formed of a single layer made of a transparent conductive material having a relatively high work function value. Through this, a bottom emission type organic light emitting display device that emits light from the second electrode 118 to the first electrode 115 can be implemented.

In addition, a reflective layer may be further included under the first electrode 115 . Through this, a top emission type organic light emitting display device that emits light upward by reflecting light emitted from the second electrode 118 to the first electrode 115 may be implemented.

The shape of the first electrode 115 is not limited to the drawings, and the first electrode 115 may be formed in multiple layers. For example, it may be formed in a triple-layer structure in which the second layer is formed on the first layer and the third layer is formed on the second layer.

Here, the first layer and the third layer may be a transparent conductive material. For example, the transparent conductive material may be ITO or IZO. The second layer may be a reflective layer. In this case, the second layer may be a metal or a metal alloy layer. For example, it may be Ag or a metal alloy layer containing Ag. Through this, the organic light emitting device reflects the light emitted from the second electrode 118 to the first electrode 115, thereby realizing a top emission type organic light emitting display device.

A bank pattern 116 defining a light emitting area and a non-emission area of the organic light emitting display is disposed on a portion of the upper surface of the first electrode 115 . An organic light emitting layer 117 is disposed on the region surrounded by the bank pattern 116 .

The organic light emitting layer 117 may be composed of a single layer made of a light emitting material. In addition, the organic light emitting layer 117 may include a hole injection layer, a hole transporting layer, an emitting material layer, an electron transporting layer, and an electron injection layer to increase luminous efficiency. It may consist of multiple layers of electron injection layers.

The second electrode 118 of the organic light emitting device is disposed on the substrate 100 including the organic light emitting layer 117 . In this case, the second electrode 118 may be a cathode electrode. Also, although not shown in the drawings, a color filter array substrate may be disposed to face the substrate 100 including the organic electroluminescent device.

In the organic light emitting display device according to the present invention, since the second thin film transistor Tr2 includes the second gate electrode 102 and the third gate electrode 108 , the light reliability and current capability of the device may be improved. Through this, electro-optical characteristics and luminance uniformity of the display device may be improved. In addition, a single mask is used to dispose the second gate insulating film 106 of the first thin film transistor Tr1 , the third gate insulating film 107 of the second thin film transistor Tr2 , and the third gate electrode 108 . This has the effect of simplifying the process.

Next, a detailed review of the method of manufacturing the thin film transistor array substrate according to the present invention with reference to FIGS. 2A to 2G is as follows. 2A to 2G are diagrams illustrating a method of manufacturing a thin film transistor array substrate according to the present invention.

2A to 2G , a first region in which the second gate electrode 102 is disposed, a second region in which the first gate electrode 101 is disposed, and a second region adjacent to the first and second regions are disposed. A substrate 100 including three regions is provided.

A first gate insulating layer 103 is disposed on the substrate 100 , and a semiconductor layer material 204 is disposed on the substrate 100 . Thereafter, a gate insulating layer material 206 is disposed on the substrate 100 , and a third gate electrode material 208 is disposed on the gate insulating layer material 206 . Thereafter, a photoresist 200 is disposed on the third gate electrode material 208 .

A transmissive part 303 facing the first region, a transmissive part 302 facing the second region, and a blocking part 301 facing the third region, which are disposed to face the substrate 100 and face the third region The photoresist 200 is etched using the halftone mask 300 including Thereafter, the third gate electrode material 208 corresponding to the third region is removed by etching.

A portion of the gate insulating layer material 204 corresponding to the third region is etched using the photoresist disposed in the first region and the second region as a mask. Thereafter, a portion of the photoresist 200b corresponding to the first region and the photoresist 200a corresponding to the second region are etched. Then, the third gate electrode material 204 disposed to correspond to the second region is etched.

Thereafter, a portion of the gate insulating layer material disposed in the second region and the gate insulating layer material disposed in the third region are etched using the photoresist 200c disposed in the first region as a mask. Then, the photoresist 200c disposed in the first region is removed by etching.

Here, the second thin film transistor Tr2 may be disposed in the first region, the first thin film transistor Tr1 may be disposed in the second region, and the thin film transistor may not be disposed in the third region.

In detail, referring to FIG. 2A , a gate electrode material is disposed on the substrate 100 . The gate electrode material is patterned through a photolithography process. Through this, the first gate electrode 101 of the first thin film transistor and the second gate electrode 102 of the second thin film transistor spaced apart from the first gate electrode 101 are disposed on the substrate 100 . .

A first gate insulating layer 103 is disposed on the substrate 100 including the first gate electrode 101 and the second gate electrode 102 . A semiconductor layer material 204 is disposed on the substrate 100 including the first gate insulating layer 103 . A gate insulating layer material 206 for forming a second gate insulating layer and a third gate insulating layer is disposed on the semiconductor layer material 204 .

A third gate electrode material 208 is disposed on the gate insulating layer material 206 . A photoresist 200 is disposed on the third gate electrode material 208 . In this case, the photoresist 200 may be a negative photoresist. The negative photoresist is a photosensitive material that is a material that is cured when irradiated with light.

The mask 300 is disposed to face the substrate 100 on which the photoresist 200 is formed. The mask 300 may be a halftone mask. In detail, the mask 300 includes a blocking part 301 , a semi-transmissive part 302 , and a transmissive part 303 . The transmissive part 303 transmits light as it is, the semi-transmissive part 302 transmits less light than the transmissive part 303 , and the blocking part 301 completely blocks the light.

Light is irradiated to the photoresist 200 through the mask 300 . Here, the photoresist 200 facing the semi-transmissive portion 302 of the mask 300 is semi-cured by the irradiated light. In addition, the photoresist 200 facing the transmission portion 303 of the mask 300 is cured by the irradiated light.

Referring to FIG. 2B , the photoresist 200 facing the transflective portion 302 of the mask 300 overlaps with the first gate electrode 101 of the first thin film transistor to form a low first photoresist pattern ( 200a) is formed. In addition, the photoresist 200 facing the transmission portion 303 of the mask 300 overlaps the second gate electrode 102 of the second thin film transistor to form a second photoresist pattern 200b having a high height. . The photoresist 200 facing the blocking portion 301 of the mask 300 is removed to expose the third gate electrode material 208 .

Accordingly, the first photoresist pattern 200a formed in the region corresponding to the transmissive part 302 of the mask 300 is thinner than the second photoresist pattern 200b formed in the region corresponding to the transmissive part 303 . can be formed.

The photoresist may be formed using a positive photoresist. In this case, the pattern of the halftone mask that is the mask 300 should be manufactured in reverse.

Referring to FIG. 2C , the exposed third gate electrode material is etched using the first photoresist pattern 200a and the second photoresist pattern 200b as a mask. The third gate electrode material 111 may be etched to form a gate electrode pattern 208a and a third gate electrode pattern 108a.

The gate electrode pattern 208a may be formed under the first photoresist pattern 200a, and the third gate electrode pattern 108a may be formed under the second photoresist pattern 200b. The third gate electrode pattern 108a may be the same as the third gate electrode. Here, the gate insulating layer material 206 is exposed in a region where the gate electrode pattern 208a and the third gate electrode pattern 108a are not formed.

Referring to FIG. 2D , the exposed gate insulating layer material 206 is etched using the first photoresist pattern 200a and the second photoresist pattern 200b as a mask. In detail, the gate insulating layer material 206 is etched using the first photoresist pattern 200a and the gate electrode pattern 208a as masks. At the same time, the gate insulating layer material 206 is etched using the second photoresist pattern 200b and the third gate electrode pattern 108a as masks.

Through this, the thickness of the gate insulating layer material 206b disposed under the first photoresist pattern 200a and the second photoresist pattern 200b is the thickness of the first photoresist pattern 200a and the second photoresist pattern 200b. The pattern 200b may be formed to be thicker than a thickness of an area where the pattern 200b is not disposed.

Subsequently, referring to FIG. 2E , the first photoresist pattern 200a may be removed through an ashing process. In this case, a portion of the second photoresist pattern 200b may also be removed to form a third photoresist pattern 200c thinner than the second photoresist pattern 200b. Thereafter, the gate electrode pattern 208a is removed by etching. Through this, the gate insulating layer material 206a may be exposed in a region other than the lower region of the third photoresist pattern 200c.

Referring to FIG. 2F , a portion of the exposed gate insulating layer material 206a is etched using the third photoresist pattern 200c as a mask. In this case, the gate insulating layer material 106a disposed at a position overlapping the first gate electrode 101 of the first thin film transistor becomes the second gate insulating layer 106 .

Here, the height of the second gate insulating layer 106 is lower than that of the gate insulating layer material 107a disposed under the third photoresist pattern 200c. Then, all of the gate insulating layer material disposed in the remaining region is removed to expose the semiconductor layer material. In this case, the gate insulating layer material may be removed by a dry etching process.

The semiconductor layer material 204a of the exposed region may be conductively etched while the gate insulating layer material is dry etched. Through this, a separate doping process for making the semiconductor layer material 204a into a conductor may be omitted.

Here, the semiconductor layer material 204a disposed under the second gate insulating layer 106 and the third gate insulating layer material 107a may not be conductive. Subsequently, the regions of the semiconductor layer material 204a disposed under the second gate insulating layer 106 and the third gate insulating layer material 107a may become the channel region of the first semiconductor layer and the channel region of the second semiconductor layer, respectively. have.

Next, referring to FIG. 2G , the third photoresist pattern 200c is removed. Through this, the third gate electrode material 108a disposed under the third photoresist pattern 200c becomes the third gate electrode 108 . That is, the third gate electrode 108 may be formed through the same mask as the second gate insulating layer and the third gate insulating layer 107 .

In addition, the third gate insulating layer material 107a disposed under the third gate electrode 108 becomes the third gate insulating layer 107 . That is, the third gate insulating layer 107 may be formed of the same material in the same layer as the second gate insulating layer 106 . Through this, the process of forming the second gate insulating layer 106 and the third gate insulating layer 107 may be simplified.

Here, a height of the third gate insulating layer 107 may be higher than a height of the second gate insulating layer 106 . Through this, the parasitic capacitance of the organic light emitting display device may be reduced.

Also, although not shown in the drawings, the semiconductor layer material 204a may be etched to form the first semiconductor layer of the first thin film transistor and the second semiconductor layer of the second thin film transistor. In addition, a passivation layer 113 may be further formed on the substrate 100 on which the first semiconductor layer and the second semiconductor layer are disposed. Thereafter, a first source electrode and a first drain electrode of a first thin film transistor connected to the first semiconductor layer are formed through a contact hole formed in the passivation layer, and a second thin film transistor connected to the second semiconductor layer is formed. A second source electrode and a second drain electrode may be formed.

The method for manufacturing a thin film transistor array substrate for an organic light emitting display device according to the present invention includes the second gate insulating film 106 of the first thin film transistor, the third gate insulating film 107 of the second thin film transistor, and the third gate electrode 108 , by using one mask, there is an effect that the process is simplified and the manufacturing cost can be reduced.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: substrate 102: second gate electrode
103: first gate insulating film 105: second semiconductor layer
107: third gate insulating film 108: third gate electrode
111: second source electrode 112: second drain electrode

Claims (7)

providing a substrate including a first region in which a second gate electrode is disposed, a second region in which a first gate electrode is disposed, and a third region disposed adjacent to the first and second regions;
disposing a first gate insulating layer on the substrate;
disposing a semiconductor layer material comprising an oxide semiconductor material on the substrate;
disposing a gate insulating layer material on the substrate;
disposing a third gate electrode material on the substrate;
disposing a photoresist on the substrate; and
The photoresist is etched using a halftone mask disposed to face the substrate and including a transmissive portion facing the first region, a transflective portion facing the second region, and a blocking portion corresponding to the third region. step; including;
A first photoresist pattern overlapping the first gate electrode is formed in the second region by etching the photoresist, and the first photoresist pattern overlaps the second gate electrode in the first region A method of manufacturing a thin film transistor array substrate in which a thicker second photoresist pattern is formed.
The method of claim 1,
and etching the third gate electrode material corresponding to the third region using the first photoresist pattern and the second photoresist pattern as masks.
The method of claim 1,
and etching a portion of the material of the gate insulating layer corresponding to the third region using the first photoresist pattern and the second photoresist pattern as masks.
The method of claim 1,
The method of manufacturing a thin film transistor array substrate further comprising etching a portion of the second photoresist pattern and the first photoresist pattern.
The method of claim 1,
and etching a third gate electrode material disposed to correspond to the second region.
The method of claim 1,
and etching a portion of the gate insulating layer material disposed in the second region and the gate insulating layer material disposed in the third region using the remaining second photoresist pattern as a mask.
The method of claim 1,
The method of manufacturing a thin film transistor array substrate further comprising removing the remaining second photoresist pattern.

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