KR102263319B1 - Display Controller for improving display noise and System including the same - Google Patents

Abstract

A display controller for improving display noise and an electronic system including the display controller are disclosed. The display controller according to the present invention includes a memory for storing frame data including line data of M (an integer greater than or equal to 2), and a data size controller for variably adjusting the size of data transmitted to the display device. and a display driving circuit for reading data corresponding to the data size from the memory and transmitting the data to the display device.

Description

Display Controller for improving display noise and System including the same

The concept of the present invention relates to a device for improving display noise, and a system including the device, and more particularly, to a display controller for improving display noise of a display device supporting a MIPI DSI COMMAND MODE interface, and including the same It's about a system that

The use of devices (eg, smart phones, tablet PCs, etc.) equipped with a high resolution display device is increasing. In these devices, the quality of the display is a big reason. Accordingly, efforts are being made to reduce display noise.

Meanwhile, as a data transmission method between a system-on-chip (SoC) of a mobile device and a display device, the use of a device using the MIPI DSI transmission method has increased.

The MIPI DSI standard is based on line-unit image data transmission, so there is inevitably a section in which the data lane is stopped due to the idle period (or Stop State) between lines. do. In this case, there is a problem in that the power noise of the display panel generates noise at the output of the display panel in association with the data lane of the MIPI DSI receiving side.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display controller that improves display quality by reducing display noise and a system including the same.

According to an embodiment of the present invention for achieving the above technical problem, there is provided a display controller for controlling a display device. The display controller may include: a memory for storing frame data including line data of M (an integer greater than or equal to 2); a data size controller for variably adjusting the size of data transmitted to the display device; and a display driving circuit for reading data corresponding to the data size from the memory and transmitting the data to the display device.

According to an embodiment, the data size controller includes: a register for storing the maximum number of lines; and a random line generator for randomly varying a designated number of lines within a range not exceeding the maximum number of lines, wherein the display driving circuit reads line data from the memory according to the designated number of lines of the random line generator to obtain the can be transmitted to the display device.

According to an embodiment, the display driving circuit does not transmit the line data in the idle period, and transmits line data corresponding to the specified number of lines in the data transmission period, and the duration of the data transmission period is based on the specified number of lines. may vary accordingly.

According to an embodiment, the register further stores a mode setting signal, and when the mode setting signal is set to a first value, the number of specified lines is variable, and when the mode setting signal is set to a second value, the specified The number of lines may be fixed.

According to an embodiment, the data size controller may include: a pattern storage unit configured to store a plurality of predetermined random number sequences; a pattern generator for generating a random pattern by using the plurality of random number sequences stored in the pattern storage unit; and a data size determining unit that determines the size of the data according to the random pattern.

According to an embodiment, the pattern generator may randomly shuffle the plurality of random number sequences to generate the random pattern.

In some embodiments, the data size determiner may vary the size of the data according to the random pattern in response to a mode setting signal.

According to an embodiment of the present invention for achieving the above technical problem, a display device; and a display controller configured to control the display device. The display controller may include: a memory for storing frame data including line data of M (an integer greater than or equal to 2); a data size controller for variably adjusting the size of data transmitted to the display device; and a display driving circuit for reading data corresponding to the data size from the memory and transmitting the data to the display device.

According to an embodiment, the data size controller includes: a register for storing the maximum number of lines; and a random line generator for randomly varying a designated number of lines within a range not exceeding the maximum number of lines, wherein the display driving circuit reads line data from the memory according to the designated number of lines of the random line generator to obtain the can be transmitted to the display device.

According to an embodiment, the register further stores a mode setting signal, and when the mode setting signal is set to a first value, the number of specified lines is variable, and when the mode setting signal is set to a second value, the specified The number of lines may be fixed.

When the mode setting signal is set to the first value, power noise generated in the display device may be smaller than power noise generated in the display device when the mode setting signal is set to the second value.

According to an embodiment, the display driving circuit may ^{convert the frame data stored in the memory into a signal according to a MIPI ®} (Mobile Industry Processor Interface) standard, and transmit the converted signal to the display device, wherein the display controller includes It can operate in MIPI DSI COMMAND MODE.

According to an embodiment of the present invention for achieving the above technical problem, in an operating method of a display controller for controlling a display device, frame data including line data of M (an integer greater than or equal to 2) ) to store; variably adjusting the number of lines designating the number of line data to be transmitted to the display device; and reading line data from the memory according to the variable number of lines and transmitting the line data to the display device.

According to an embodiment, the step of variably adjusting the number of lines includes determining a data size sequence for the entire frame data before starting transmission of the frame data, wherein the data size sequence includes a plurality of lines. It may be a numeric string consisting of numbers.

According to an embodiment, the step of variably adjusting the number of lines includes determining the number of lines for each data transmission section, and the step of transmitting to the display device includes the determined number of lines during the data transmission section. and transmitting data to the display device. Line data may not be transmitted during an idle period alternately repeated with the data transmission period.

As described above, according to an embodiment of the present invention, by varying the size, that is, the number of lines, of line data transmitted in each data transmission section, the interval between the data transmission section and the idle section is varied and generated in the display device. Reduces power noise.

Accordingly, display noise is reduced, and display quality and performance of a device including a display device are improved.

1 is a transmission timing diagram of image data according to the MIPI D-PHY standard.
FIG. 2 shows a signal of a data lane according to the data transmission timing shown in FIG. 1 and power noise generated in a MIPI client (eg, a display device).
3 is a block diagram of an electronic system according to an embodiment of the present invention.
FIG. 4 is a configuration block diagram illustrating an embodiment of the SoC shown in FIG. 3 .
FIG. 5 is a configuration block diagram illustrating an embodiment of the display controller shown in FIG. 4 .
6 is a block diagram illustrating an embodiment of the data size controller shown in FIG. 5 .
FIG. 7 is a block diagram showing another embodiment of the data size controller shown in FIG. 5 .
8 is a table illustrating an example of a numeric string table stored in the pattern storage unit of FIG. 7 .
9 is a table illustrating an example of a random pattern generated by the pattern generator of FIG. 7 .
10 is a flowchart illustrating a method of operating a display controller according to an embodiment of the present invention.
11 is a flowchart illustrating a method of operating a display controller according to another embodiment of the present invention.
12 is a flowchart illustrating an embodiment of the randomization step shown in FIG. 11 .
13 is a diagram illustrating comparison of data transmission timing according to a mode setting signal in a display controller according to an embodiment of the present invention.
14 is a block diagram of an electronic system according to another embodiment of the present invention.

Specific structural or functional descriptions of the embodiments of the present invention disclosed in the present specification or application are only exemplified for the purpose of describing the embodiments according to the present invention, and the embodiments according to the present invention may be implemented in various forms. and should not be construed as being limited to the embodiments described in the present specification or application.

Since the embodiment according to the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the present specification or application. However, this is not intended to limit the embodiment according to the concept of the present invention to a specific disclosed form, and should be understood to include all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first and/or second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one element from another element, for example, without departing from the scope of the present invention, a first element may be called a second element, and similarly The second component may also be referred to as the first component.

When a component is referred to as being “connected” or “connected” to another component, it is understood that the other component may be directly connected or connected to the other component, but other components may exist in between. it should be On the other hand, when it is mentioned that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", etc., should be interpreted similarly.

The terms used herein are used only to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In this specification, terms such as "comprises" or "have" are intended to designate that the described features, numbers, steps, operations, components, parts, or combinations thereof exist, and include one or more other features or numbers. , it should be understood that it does not preclude the existence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as meanings consistent with the context of the related art, and unless explicitly defined in the present specification, they are not to be interpreted in an ideal or excessively formal meaning. .

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. Like reference numerals in each figure indicate like elements.

MIPI ^® (Mobile Industry Processor Interface) is a standard established by the MIPI Alliance as one of the serial interface standards for connecting a processor and peripheral devices.

MIPI supports two display standards. One is a video mode, and the other is a command mode.

1 is a transmission timing diagram of image data according to the MIPI D-PHY standard.

Referring to FIG. 1 , in the MIPI command mode, a MIPI host (eg, a display controller) transmits image data to a MIPI client (eg, a display device) in line units.

FIG. 2 shows a signal of a data lane according to the data transmission timing shown in FIG. 1 and power noise generated in a MIPI client (eg, a display device).

1 and 2 , in the signal of the data lane, an image data transmission period Trans and an idle period Idle may be regularly repeated. Accordingly, power noise may be generated in the MIPI client (eg, the display device) at an interval similar to the signal of the data lane. That is, as shown in FIG. 2 , a pattern in which power noise increases every idle period (Idle) may occur.

Accordingly, there is a need to improve display quality by reducing power noise in the display device.

3 is a block diagram of an electronic system including a semiconductor integrated circuit device according to an embodiment of the present invention. The semiconductor integrated circuit device may be implemented as a system-on-chip (SoC) 10 or an application processor (AP). FIG. 4 is a configuration block diagram illustrating an embodiment of the SoC shown in FIG. 3 .

3 to 4 , the electronic system 1 may be implemented as a portable electronic device. The portable electronic device includes a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), and a digital still camera. , digital video camera, portable multimedia player (PMP), mobile internet device (MID), wearable computer, internet of things (IoT) device, or internet of everything (IoE)) can be implemented as a device.

The electronic system 1 may display a still image signal (or still image) or a moving image signal (or moving image) on the display panel 25 .

The display device 20 includes a display driver 21 and a display panel 25 . According to an embodiment, the SoC 10 and the display driver 21 may be configured as one module, one system on chip, or one package, for example, a multi-chip package. can be implemented as According to another embodiment, the display driver 21 and the display panel 25 may be implemented as one module.

The display driver 21 controls the operation of the display panel 25 according to signals output from the SoC 10 . For example, the display driver 21 may transmit image data received from the SoC 10 as an output image signal to the display panel 25 through the selected interface.

The display panel 25 may display an output image signal output from the display driver 21 . For example, the display panel 25 may be implemented as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, or an active-matrix OLED (AMOLED) display.

The external memory 30 stores program instructions executed in the SoC 10 . Also, the external memory 30 may store image data for displaying still images or moving images on the display device 20 . The moving image is a series of different still images presented in a short time.

The external memory 30 may be a volatile memory or a nonvolatile memory. The volatile memory may be dynamic random access memory (DRAM), static random access memory (SRAM), thyristor RAM (T-RAM), zero capacitor RAM (Z-RAM), or twin transistor RAM (TTRAM). The nonvolatile memory may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a phase change RAM (PRAM), or a resistive memory.

The SoC 10 controls the external memory 30 and/or the display device 20 . In some embodiments, the SoC 10 may include an integrated circuit (IC), a processor, an application processor, a multimedia processor, or an integrated multimedia processor. can be called

The SoC 10 includes a central processing unit (CPU) 100 , a read only memory (ROM) 110 , a random access memory (RAM) 120 , and an image signal processor (ISP) 130 . , a display controller 200 , a graphics processing unit (GPU) 150 , a memory controller 160 , a post processor 170 , and a system bus 180 . The SoC 10 may further include other components in addition to the illustrated components.

The CPU 100 , which may also be referred to as a processor, may process or execute programs and/or data stored in the external memory 30 . For example, the CPU 100 may process or execute the programs and/or the data in response to an operation clock signal output from a clock signal module (not shown).

The CPU 100 may be implemented as a multi-core processor. The multi-core processor is a computing component having two or more independent substantive processors (referred to as 'cores'), each of which contains program instructions. ) can be read and executed.

The CPU 100 executes an operating system (OS). The operating system (OS) may manage resources (eg, memory, display, etc.) of the electronic system 1 . The operating system (OS) may allocate resources to applications executed in the electronic system 1 .

Programs and/or data stored in the ROM 110 , the RAM 120 , and/or the external memory 30 may be loaded into a memory (not shown) of the CPU 100 as needed.

ROM 110 may store persistent programs and/or data.

The ROM 110 may be implemented as an erasable programmable read-only memory (EPROM) or an electrically erasable programmable read-only memory (EEPROM).

The RAM 120 may temporarily store programs, data, or instructions. For example, programs and/or data stored in the memory 110 or 30 may be temporarily stored in the RAM 120 under the control of the CPU 100 or according to a booting code stored in the ROM 110 . have. The RAM 120 may be implemented as dynamic RAM (DRAM) or static RAM (SRAM).

The ISP 130 may perform various processing on the image signal.

The ISP 130 may process image data input from an image sensor (not shown). For example, the ISP 130 may correct the shake of the image data input from the image sensor and adjust the white balance.

In addition, the ISP 130 may perform color correction such as brightness and contrast, tonalization, quantization, color conversion to another color space, and the like. The ISP 130 may periodically store image-processed image data in the memory 30 through the bus 180 .

The GPU 150 may read and execute program commands related to graphic processing. For example, the GPU 150 may perform graphic-related figure processing and the like at high speed.

Also, the GPU 150 may convert data read from the external memory 30 by the memory controller 160 into a signal suitable for the display device 20 .

For graphic processing, in addition to the GPU 150 , a graphic engine (not shown) or a graphic accelerator may be used.

A post processor 170 performs post-processing suitable for an image or video signal to an output device (eg, the display device 20 ). The post processor 170 may perform a function of enlarging or reducing the size of an image or rotating the image to be suitable for output to the display device 20 .

The post-processor 170 stores the post-processed image data in the memory 30 through the bus 180 or directly through the bus 180 in an on-the-fly manner. (200) can be output.

The memory controller 160 interfaces with the external memory 30 . The memory controller 160 controls the overall operation of the external memory 30 and controls data exchange between the host and the external memory 30 . For example, the memory controller 160 may write data to or read data from the external memory 30 according to a request of the host. Here, the host may be a master device such as the CPU 100 , the ISP 130 , the GPU 150 , or the display controller 200 .

According to an embodiment, the memory controller 160 may read image data from the external memory 30 and provide it to the memory controller 160 according to a request for image data from the display controller 200 .

The display controller 200 controls the operation of the display device 20 .

The display controller 200 receives image data to be displayed through the display device 20 through the system bus 180 and converts it into a signal (eg, a signal according to the interface standard) for transmission to the display device 20 . Thus, it is transmitted to the display device 20 .

According to an embodiment, the display controller 200 may transmit image data to the display device 20 according to the ^{MIPI ® D-PHY standard.}

According to an embodiment, the display controller 200 may request frame data from the memory controller 160 at preset time intervals to receive image data in units of frames.

Each of the components 100 , 110 , 120 , 130 , 150 , 160 , 170 , and 200 may communicate with each other via the system bus 180 . That is, the system bus 180 connects each component of the SoC 10 and serves as a path for data transmission/reception between each component. In addition, the system bus 180 may serve as a transmission path for a control signal between each component.

According to an embodiment, the system bus 180 may include a data bus (not shown) for transmitting data, an address bus (not shown) for transmitting an address signal, and a control bus (not shown) for transmitting a control signal. have.

According to an embodiment, the system bus 180 may include a small bus for data communication between predetermined components, that is, an interconnector.

FIG. 5 is a configuration block diagram illustrating an embodiment of the display controller shown in FIG. 4 .

4 to 5 , the display controller 200 according to an embodiment of the present invention includes a data interface 210 , a control interface 220 , a buffer memory 230 , a data size controller 240 , and a timing controller ( 250 , and a display driving circuit 260 .

The data interface 210 may receive the input image data Din through the bus 180 and store it in the buffer memory 230 .

According to an embodiment, the data interface 210 may request frame data from the memory controller 160 at preset time intervals, receive input image data Din in units of frames, and store the received input image data Din in the buffer memory 230 .

The source of the input image data Din may be various. For example, the data interface 210 may be outputted from the CPU 100 , the memory 30 , the graphics processing unit 150 , or other components not shown (eg, a scaler, a post processor, etc.). The input image data Din may be received through a data bus.

To this end, the data interface 210 may include one or more direct memory access (DMA) (not shown) for reading the input image data Din by accessing the memory. According to an embodiment, the input image data Din may be R, G, and B data, but is not limited thereto.

The data interface 210 may buffer the input image data Din and store it in the buffer memory 230 , or process the input image data Din and store it in the buffer memory 230 .

According to an embodiment, the data interface 210 may blend or combine input image data Din received from two or more DMAs and store the synthesized image data Dp in the buffer memory 230 .

The control interface 220 may receive a control signal from another component (eg, CPU, etc.) external to the display controller 200 . For example, the control interface 220 may receive data size control information Scon, such as a maximum data size, a data size pattern, and/or a mode setting signal, from the CPU 100 and store it in the data size controller 240 . .

The mode setting signal is a signal for setting enable/disable of a data size variable control function according to an embodiment of the present invention. According to an embodiment, when the mode setting signal is the first value, the data size controller 240 controls the size of data (eg, the number of line data) transmitted to the display device to be variably adjusted, and the mode setting signal is the second value. When it is a value, the data size controller 240 may control the size (eg, the number of line data) of data transmitted to the display device to be fixed.

The mode setting signal may be set dynamically by a user setting or based on predetermined information.

The display driving circuit 260 converts the image data stored in the buffer memory 230 into a signal suitable for transmission to the display device 20 (eg, a signal according to a specific standard), and converts the converted signal into the display device 20 . send to

Image data to be transmitted to the display device 20 may include a plurality of frames, and each frame may include a plurality of line data. Each line data may include a plurality of pixel data.

For example, if the resolution (number of lines*number of pixels) of the display panel 25 is m*n, each frame includes m line data, and each line data includes n pixel data. According to an embodiment, each pixel data may be composed of R, G, and B data.

The timing controller 250 may output a control signal and a clock signal for controlling the overall operation timing of the display controller 200 .

According to an exemplary embodiment, the timing controller 250 transmits video control signals MIPI DSI COMMAND, which are signals for controlling display of image data including a plurality of lines and a plurality of frames, to the display driving circuit 260 . can provide

In addition, according to an embodiment, the timing controller 250 uses an input clock signal (not shown) necessary to receive the image data Dm from the buffer memory 230 to the display driving circuit 260 and the display device 20 . An output clock signal (not shown) required for transmission may be provided.

The display driving circuit 260 may read the image data Dm from the buffer memory 230 according to the data size CDS specified by the data size controller 240 and transmit the read image data Dm to the display device 20 .

According to an embodiment, the data size controller 240 designates the size CDS of data transmitted to the display device 20 as the 'number of lines', and the display driving circuit 260 controls the data size controller ( 240) may transmit line data of an assigned line number. Accordingly, the display driving circuit 260 may divide the image data in units of integer multiples of lines and transmit the image data to the display device 20 .

According to an embodiment, in order to determine the number of lines of data to be transmitted during one data transmission period, the data size controller 240 may vary the number of designated lines within a range that does not exceed a predetermined maximum number of lines.

For example, the data size controller 240 may generate a designated number of lines randomly or pseudo-randomly within the maximum number of lines for each data transmission section.

Image data is not transmitted in the idle period other than the data transmission period.

The data transmitters TX and 270 of the display driving circuit 260 may transmit data to the data receivers RX and 400 of the display device 20 according to the MIPI standard, and may be referred to as a master device or a host device. The data receiver 400 may also receive data from the data transmitter 270 according to the MIPI standard, and is also referred to as a slave device or a client device.

6 is a block diagram illustrating an embodiment 240a of the data size controller 240 shown in FIG. 5 . 5 and 6 , the data size controller 240a according to an embodiment of the present invention may include a register 241 and a random line generator 243 .

The register 241 may receive and store control information Scon necessary for generating the number of random lines from the control interface 220 .

The control information Scon may include the above-described maximum number of lines ML and a mode setting signal. The register 250 may also store resolution information of the display panel 25 .

The mode setting signal and the maximum number of lines ML may be set in the register 250 by the user or the CPU 100 .

The maximum number of lines ML may be predetermined and stored in the register 241 according to the resolution of the display panel 25 and the size of the buffer memory 230 .

According to an embodiment, in a state in which the mode setting signal is set to the first value, the random line generator 243 generates the specified number of lines randomly or pseudo-randomly within the maximum number of lines (ML). It can be output in data size (CDS). According to an embodiment, the random line generator 243 may be implemented as a random number generator that generates a random number according to a random number generation algorithm or a pseudo random number generation algorithm.

For example, when the maximum number of lines (ML) is 4, the random line generator 243 sequentially randomly generates the number of lines from 1 to 4 for transmission of one frame image, and the data size (CDS, eg, , 1, 3, 4, 2, 1, 2, ...).

Then, the display driving circuit 260 receives 1, 3, 4, 2, 1 from the buffer memory 230 according to the data size (CDS, for example, 1, 3, 4, 2, 1, 2, ...). Line data corresponding to , 2, ... may be sequentially output and transmitted to the display device 20 .

In a state in which the mode setting signal is set to the second value, the random line generator 243 may output a fixed number of lines as the data size CDS.

According to an embodiment, the control interface 220 may receive a number sequence table generated by a preset or a predetermined algorithm and store it in the register 241 .

8 is a table showing an embodiment of a numeric string table. Referring to this, the number sequence table may include a plurality of (2 or more) (eg, 4) number sequences and an index for designating each number sequence.

The number sequence may be a random number sequence composed of random numbers or pseudo-random numbers. Each number in the numeric string may be a value for designating the number of lines.

Accordingly, according to an embodiment, the random number sequence is a numeric sequence of a specific length (8 in the embodiment of FIG. 8 ) composed of a plurality of line numbers. In the embodiment of FIG. 8 , the random number sequence corresponding to index 1 is '111122222', and the random number sequence corresponding to index 2 is '11122221'.

The random line generator 243 may randomly generate a random number sequence index and fetch a random number sequence corresponding to the random number sequence index from the register 241 .

The random line generator 243 may provide the fetched random number sequence as a data size CDS to the display driving circuit 260 . In this case, the data size CDS may be a sequence composed of a plurality of values rather than a single value. The display driving circuit 260 outputs line data from the buffer memory 240 according to a data size sequence (ie, a random number sequence) provided from the random line generator 240 , and transmits the line data to the display device 20 .

When the random line generator 243 determines a data size sequence for one frame data, a value obtained by adding the numbers of the data size sequence may be equal to the number of lines m of the resolution of the display panel 25 .

Referring to FIG. 8 , when the random number sequence index is '1', the corresponding random number sequence is '11112222'. Accordingly, the display driving circuit 260 sets the number of line data according to '11112222', which is the number of lines designated by the random number sequence. can be variable. For example, in transmitting frame data, the display driving circuit 260 transmits one (1) line data in each of the first to fourth data transmission sections, and two (2) lines in each of the fifth to eighth data transmission sections. ) line data can be transmitted.

As another example, when the data size sequence (CDS) is a random number sequence ('11222211') corresponding to the random number sequence index 3 of FIG. 8, one (1) line data is transmitted in the first and second data transmission sections, respectively, , in the third to sixth data transmission sections, two (2) lines of data are transmitted, respectively, and in the eighth data transmission section, one (1) line data may be transmitted, respectively.

FIG. 7 is a block diagram showing another embodiment 240b of the data size controller 240 shown in FIG. 5 . 5 and 7 , the data size controller 240b may include a pattern storage unit 245, a pattern generator 247, and a data size determiner 249. have.

The pattern storage unit 245 may receive and store the above-described random number sequence table.

It is assumed that the random number sequence table stored in the pattern storage unit 245 is the same as in FIG. 8 .

The pattern generator 247 may generate a random pattern RP by using the random number sequence stored in the pattern storage unit 245 . According to an embodiment, the pattern generator 247 may randomly or pseudo-randomly shuffle the indexes of the random number sequence stored in the pattern storage unit 245 to generate a corresponding random pattern (RP). have.

According to an embodiment, the pattern generator 247 uses (eg, inverts or shifts) the random number sequence stored in the pattern storage unit 245 to generate a new random number sequence, and uses the newly generated random number sequence to generate a random pattern ( RP) can be printed.

9 is a table illustrating an example of a random pattern generated by the pattern generator 247 . Referring to this, the pattern generator 247 may generate inverted random number sequences 1', 2', 3', 4' corresponding to the random number sequence in which the original random number sequence shown in FIG. 8 is inverted. .

Referring to FIG. 9 , the inverted random number sequence of the first random number sequence (1:11112222) is the first inverted random number sequence (1':22221111), and the inverted random number sequence of the second random number sequence (2:11112222) is the second inversion It is a random number sequence (2':22211112).

The pattern generator 247 randomly mixes the indices of the original random number sequence (1, 2, 3, 4) and the inverted random number sequence (1', 2', 3', 4') and shuffled indexes (4, 6). ,1,7,2,5,8,3), and a corresponding random pattern can be generated.

The data size determiner 249 may determine and output the data size CDS according to the random pattern output from the pattern generator 247 .

According to an embodiment, when the mode setting signal is set to a first value (eg, '1'), the data size determiner 249 determines the data size CDS according to the random pattern output from the pattern generator 247 . is determined, and when the mode setting signal is set to a second value (eg, '0'), a fixed data size (CDS) may be determined.

The mode setting signal may be stored in the pattern storage unit 245 or in a separate register (not shown).

10 is a flowchart illustrating a method of operating a display controller according to an embodiment of the present invention. The method of operation according to an embodiment of the present invention shown in FIG. 10 may be performed by the display controller 200 shown in FIG. 5 .

5 and 10 , it is checked whether there is frame data to be transmitted (S110), and if there is frame data to be transmitted, first, the data size controller 240 determines the size of data to be transmitted (S120). As described above, the data size controller 240 may randomly change the data size (eg, the number of lines) or fix the data size according to the mode setting signal.

Next, data corresponding to the determined data size is read from the buffer memory 230 and transmitted to the display device 20 (S130).

Steps S120 and S130 may be repeatedly performed until transmission of the frame data is completed (S140).

That is, until the transmission of one frame data is completed (S140), the data size (eg, the number of lines) is determined each time (S120), and data corresponding to the determined data size (eg, the number of lines) is transmitted (S130) ) can be performed sequentially.

Assuming that each frame data includes 1024 lines of data, the number of data sizes can be 1, 2, and 3, and the average of the data sizes is 2, in order to transmit one frame data, steps S120 and S130 A step may be performed on average 512 (1024/2) times.

In another embodiment, before starting transmission of new frame data, a random pattern is generated, a data size sequence for the entire frame data is determined based on this, and then data can be transmitted according to the determined data size sequence. In this case, a value obtained by adding the number of the determined data size sequence may be equal to the number of lines (m) of the resolution of the display panel 25 .

11 is a flowchart illustrating a method of operating a display controller according to another embodiment of the present invention. The method of operation according to an embodiment of the present invention illustrated in FIG. 11 may be performed by the display controller illustrated in FIGS. 5 and 7 .

5, 7, and 11, first, a pattern is stored in the pattern storage unit (245 in FIG. 7). Here, the pattern may be the above-described original random number sequence. 11 , it is assumed that the stored pattern is the same as the random number sequence shown in FIG. 8 .

It is checked whether the random line generation function is enabled (S220). The random line generation function is an embodiment of the data size variable function, and may be selectively enabled or disabled according to a mode setting signal. Accordingly, by checking the value of the mode setting signal, it can be checked whether the random line generation function is enabled.

When the random line generation function is disabled, a fixed pattern having a fixed number of lines is generated (S235), and data is transmitted in units of a fixed number of lines (S270).

When the random line generation function is enabled, the data of the variable line number is transmitted by randomly varying the number of lines (S230 to S270).

Specifically, it is checked whether there is frame data to be transmitted (S230), and if there is frame data to be transmitted (Yes in S230), the pattern stored in step S210 is randomized (S240).

12 is a flowchart illustrating an embodiment of the randomization step ( S240 ) shown in FIG. 11 . The randomization step S240 of FIG. 12 may be performed by the pattern generator 247 of FIG. 7 . Referring to FIGS. 7, 11 and 12 , a pattern (eg, an original random number sequence) previously stored in the pattern storage unit ( 245 of FIG. 7 ) is read for randomization ( S310 ). Next, it is checked whether the shuffle function is enabled (S320).

According to an embodiment, the shuffle function enable signal may be stored in the pattern storage unit 245 of FIG. 7 or may be stored in a separate register (not shown).

If the shuffle function is enabled (Yes in S320), the stored random number sequence index is randomly or pseudo-randomly shuffled (S330), and a random index as shown in FIG. 8 is generated. (S340). If the shuffle function is not enabled (No in S320), the step (S330) of shuffling the index of the stored original random number sequence is omitted, and based on the index of the original random number sequence (eg, the original random number sequence) A random index is generated (in the order of the sequence or in the reverse order) (S340).

After performing the above-described randomization step (S240), a random pattern is obtained according to the random index (S250). Then, the size of data to be transmitted is determined based on the random pattern (S260).

Next, data corresponding to the determined data size is read from the buffer memory 230 and transmitted to the display device (S270).

Step S270 may be repeated until transmission of the frame data is completed (S280).

According to the embodiment shown in FIG. 11, before starting the transmission of new frame data, a stored pattern is randomized to generate a random pattern (S240, S250), and based on this, a data size sequence for the entire frame data is generated. After the determination (S260), data having a variable number of lines is sequentially transmitted according to the determined data size sequence (S270).

According to another embodiment, the operation of determining a data size (eg, number of lines) each time and transmitting data corresponding to the determined data size (eg, number of lines) is performed until transmission of one (1) frame data is completed. It can be done sequentially.

13 is a diagram illustrating comparison of data transmission timing according to a mode setting signal in a display controller according to an embodiment of the present invention. Specifically, FIG. 13A is a data transmission timing diagram in a mode in which the mode setting signal is set to a second value (eg, a random line generation function is disabled) in the display controller according to an embodiment of the present invention. and FIG. 13B is a data transmission timing diagram in a mode in which the mode setting signal is set to a first value (eg, a random line generation function is enabled) in the display controller according to an embodiment of the present invention. .

Referring to (a) of FIG. 13 , no data is transmitted in the idle period ⓑ, and one line data ⓐ is transmitted in the data transmission period between the idle periods ⓑ. is sent According to (a) of FIG. 13 , the number of lines transmitted in each data transmission section, that is, the data size is fixed.

That is, the duration of the data transmission section is fixed.

Accordingly, as the data transmission section and the idle section are repeated at the same interval, power noise is generated at the receiving side (ie, the display device) at regular intervals as shown in FIG. 2 .

On the other hand, referring to (b) of FIG. 13 , data is not transmitted in the idle period ⓑ, and line data transmitted in the data transmission period between the idle period ⓑ. The size, that is, the number of lines, is variable.

As shown in (b) of FIG. 13 , one line data ⓐ may be transmitted, two line data ⓒ may be transmitted, and three line data may be transmitted in each data transmission section. have.

The size of line data, ie, the number of lines, transmitted in each data transmission period is determined by the random line generator 240 as described above.

According to an embodiment of the present invention, since the duration of the data transmission section is variable, the interval between the data transmission section and the idle section is not constant. Accordingly, power noise generated at the receiving side (ie, the display device) is reduced.

For example, when it is assumed that the display controller transmits the same frame data to the display device, when the mode setting signal is set to the first value in the display controller, that is, when the size (number of lines) of line data is changed. Power noise generated in the display device is less than power noise generated in the display device when the mode setting signal is set to the first value, that is, when the size (number of lines) of line data is fixed.

Accordingly, according to an embodiment of the present invention, display noise in a display device is reduced, and thus display quality and performance of a device including the display device are improved.

The present invention can also be implemented as computer-readable codes on a computer-readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data readable by a computer system is stored.

Examples of the computer-readable recording medium include ROM, RAM, CD-ROM, magnetic tape, floppy disk, and optical data storage device.

In addition, the computer-readable recording medium is distributed in a computer system connected through a network, so that the computer-readable code can be stored and executed in a distributed manner. And functional programs, codes, and code segments for implementing the present invention can be easily inferred by programmers in the art to which the present invention pertains.

The content of the present invention has been described with reference to the embodiment shown in the drawings, but this is only exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. will be. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

1, 400: electronic system
10: SoC
20: display device
21: display driver
25: display panel
30: external memory
100: central processing unit (CPU)
110: ROM (read only memory; 110)
120: random access memory (RAM)
130: image signal processor (ISP)
150: graphics processing unit (GPU)
160: memory controller
170: post processor
180: system bus
200: display controller
210: data interface
220: control interface
230: buffer memory
240, 240a, 240b: data size controller
241: register
243: random line generator
245: pattern storage (Pattern Storage)
247: Pattern Generator
249: Data Size Determiner (Data Size Determiner)
250: timing controller
260: display driving circuit

Claims (20)

A display controller for controlling a display device, comprising:
a memory for storing frame data including line data of M (an integer greater than or equal to 2);
a data size controller for variably adjusting the size of data transmitted to the display device during each of the plurality of transmission sections, wherein a section for transmitting one of the frame data includes a plurality of transmission sections; and
and a display driving circuit for reading data corresponding to the data size from the memory and transmitting the data to the display device. The method of claim 1, wherein the data size controller is
register for storing the maximum number of lines; and
and a random line generator that randomly varies the specified number of lines within a range that does not exceed the maximum number of lines,
The display driving circuit reads line data from the memory according to the number of lines specified by the random line generator and transmits the read line data to the display device. The method of claim 2, wherein the display driving circuit
In the idle section, the line data is not transmitted, and in the data transmission section, line data corresponding to the specified number of lines is transmitted,
The duration of the data transmission section is variable according to the specified number of lines. 3. The method of claim 2, wherein the register is
store more mode setting signals,
When the mode setting signal is set to a first value, the number of designated lines is variable,
When the mode setting signal is set to a second value, the number of designated lines is fixed. 3. The method of claim 2, wherein the random line generator
A display controller that generates the specified number of lines according to a random number generation algorithm or a pseudo-random number generation algorithm. The method of claim 1, wherein the data size controller is
a pattern storage unit for storing a plurality of predetermined random number sequences;
a pattern generator for generating a random pattern by using the plurality of random number sequences stored in the pattern storage unit; and
and a data size determiner configured to determine a size of the data according to the random pattern. The method of claim 6, wherein the pattern generator
A display controller that randomly shuffles the plurality of random number sequences to generate the random pattern. The method of claim 6, wherein the data size determining unit
A display controller that varies the size of the data according to the random pattern in response to a mode setting signal. According to claim 1, wherein the display driving circuit
The display controller converts the frame data stored in the memory into a signal according to a predetermined standard, and transmits the converted signal to the display device. 10. The method of claim 9, wherein the predetermined standard is
MIPI ^® (Mobile Industry Processor Interface),
The display controller is a display controller operating in MIPI DSI COMMAND MODE. display device; and
a display controller for controlling the display device;
the display controller
a memory for storing frame data including line data of M (an integer greater than or equal to 2);
a data size controller for variably adjusting the size of data transmitted to the display device during each of the plurality of transmission sections, wherein a section for transmitting one of the frame data includes a plurality of transmission sections; and
and a display driving circuit for reading data corresponding to the data size from the memory and transmitting the data to the display device. 12. The method of claim 11, wherein the data size controller is
register for storing the maximum number of lines; and
and a random line generator that randomly varies the specified number of lines within a range that does not exceed the maximum number of lines,
The display driving circuit reads line data from the memory according to the number of lines specified by the random line generator and transmits the line data to the display device. 13. The method of claim 12, wherein the display driving circuit
In the idle section, the line data is not transmitted, and in the data transmission section, line data corresponding to the specified number of lines is transmitted,
The duration of the data transmission section is variable according to the number of designated lines. 13. The method of claim 12, wherein the register is
store more mode setting signals,
When the mode setting signal is set to a first value, the number of designated lines is variable,
When the mode setting signal is set to a second value, the number of designated lines is fixed. 15. The method of claim 14, wherein the power noise generated in the display device when the mode setting signal is set to the first value is smaller than the power noise generated in the display device when the mode setting signal is set to the second value. electronic system with 12. The method of claim 11, wherein the data size controller is
a pattern storage unit for storing a plurality of predetermined number sequences; and
and a data size determining unit configured to determine a size of the data based on the plurality of numeric strings. 17. The method of claim 16, wherein the data size controller is
Further comprising a pattern generator that randomly shuffles the plurality of numeric strings stored in the pattern storage unit to generate a random pattern,
The data size determining unit
An electronic system for determining a size of the data according to the random pattern. 12. The method of claim 11, wherein the display driving circuit
converting the frame data stored in the memory into ^{a signal according to a MIPI ®} (Mobile Industry Processor Interface) standard, and transmitting the converted signal to the display device;
The display controller is an electronic system operating in MIPI DSI COMMAND MODE. A method of operating a display controller for controlling a display device, the method comprising:
storing frame data including line data of M (an integer greater than or equal to 2) in a memory;
variably adjusting the number of lines designating the number of line data to be transmitted to the display device during each of the plurality of transmission periods, wherein a period for transmitting one of the frame data includes a plurality of transmission periods; and
and reading line data from the memory according to the variable number of lines and transmitting the line data to the display device. The method of claim 19, wherein the step of variably adjusting the number of lines comprises:
before starting the transmission of the frame data, determining a data size sequence for the one frame data;
The data size sequence is a number string consisting of a plurality of lines,
Each of the numeric strings corresponds to each of the plurality of transmission sections, the operating method of the display controller.

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