JP4005014B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a display device and, for example, to a technique effective when used for a device driven by a voltage averaging method using a simple matrix type liquid crystal display panel.

When a simple matrix type liquid crystal display panel is driven by the line sequential method and the voltage averaging method, the selection / non-selection voltage applied to the scanning line electrode and the signal line electrode is described in, for example, Japanese Patent Laid-Open No. 54-2096. The voltage is constant as determined by the voltage averaging method.
JP-A-54-2096

  In a signal line driving circuit for driving a simple matrix type liquid crystal display panel, serially captured image data are simultaneously output in parallel. When the AC signal is inverted for AC driving, the polarities of the display output signals supplied to the signal line electrodes of the liquid crystal display panel are simultaneously inverted. As the number of signal lines increases with higher definition and larger screens, the drive current concentrates on the power supply lines on the mounting board so that the liquid crystal drive circuit consisting of multiple elements sends the display output signals almost simultaneously. It will flow and generate large noise. In the liquid crystal display panel, since the lighting / non-lighting of the liquid crystal pixels is controlled by the effective voltage of the 1H period applied to the capacitance at the intersection of the scanning line electrode and the signal line electrode, the effective voltage changes due to the generation of the noise as described above. As a result, there arises a problem that unevenness of lighting / non-lighting is caused, or other input signals are distorted to cause malfunction in the mounting substrate.

  An object of the present invention is to provide a liquid crystal driving circuit and a liquid crystal display device that realizes improvement in display quality and stabilization of operation with a simple configuration.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the image data input serially in synchronism with the clock pulse is captured, and the liquid crystal drive circuit that outputs in parallel the display output signal formed based on the image data serially captured in accordance with the display timing signal. In addition, an output circuit and an output terminal are provided, and a plurality of liquid crystal drive circuits are connected in a tandem configuration, and the internal wiring and output circuit in the liquid crystal drive circuit are used as delay means for the display output signal for each liquid crystal drive circuit. The output timing is distributed over time.

  According to the above means, since the drive current is temporally distributed for each liquid crystal drive circuit, the peak current value flowing in the power supply line on the mounting board is reduced and the power supply is reduced even in high definition and large screen. It can prevent display quality degradation and malfunction due to noise.

  FIG. 1 is a schematic block diagram showing an embodiment of a liquid crystal display device using a liquid crystal driving circuit according to the present invention. In the drawing, a liquid crystal display panel, a liquid crystal driving circuit for forming a display output signal supplied to the signal lines (segments) thereof, and a control circuit for the liquid crystal display panel are exemplarily shown as representatives, and scanning necessary for the display of the liquid crystal display panel is shown. The line driving circuit is omitted because it is not directly related to the present invention.

  The signal line electrodes extended in the vertical direction of the liquid crystal display panel LCD are formed with high density for high definition. Therefore, in order to match the pitch of the output terminals of the liquid crystal driving circuit constituted by the semiconductor integrated circuit device and the pitch of the signal line electrodes of the liquid crystal display panel LCD, there is no particular limitation. Liquid crystal driving circuits for driving even-numbered ones are distributed up and down.

  For example, the lower liquid crystal drive circuits SDL1 to SDL5... Are driven to drive odd-numbered signal lines, and the upper liquid crystal drive circuits SDR1 to SDR5. To be driven. By allocating the drive circuit above and below the display panel in this way, the pitch of the signal lines of the liquid crystal display panel viewed from the liquid crystal drive circuit can be doubled, and the output terminal of the liquid crystal drive circuit and the liquid crystal display panel LCD connected thereto The pitch of the signal lines can be almost matched.

  Each of the liquid crystal driving circuits SDL1 to SDR5 in this embodiment has an input terminal and an output terminal. That is, serially input image data DATA, an alternating signal, a clock pulse TP, and the like are supplied from the input terminal. These signals DATA and TP are output as they are through the output circuit and the output terminal.

  A liquid crystal display panel LCD has about 600 to 1000 signal lines due to high definition, a large screen, etc., whereas a liquid crystal driving circuit constituted by a semiconductor integrated circuit device has about 80 to 160 outputs. Can only have a terminal. Therefore, a large number of liquid crystal drive circuits are used to drive one liquid crystal display panel LCD, and image data DATA input serially for one line is sequentially fetched by each liquid crystal drive circuit. That is, when the first-stage liquid crystal drive circuit SDL1 (SDR1) at the left end of the panel is enabled and the capture of the image data DATA corresponding thereto is completed, the next-stage liquid crystal drive circuit SDL2 (SDR2) is enabled and responds to it. The operation of taking in the image data DATA is repeated.

  In this embodiment, the liquid crystal driving circuit is not connected in parallel to the input signal lines formed on the mounting substrate as in the prior art, but is sequentially input in synchronization with the clock pulse TP through each liquid crystal driving circuit. Serial image data DATA and an alternating signal are supplied. Therefore, the lower liquid crystal drive circuits SDL1 to SDL5 will be described as an example. When serial image data is taken into the first-stage liquid crystal drive circuit SDL1, the input circuit and internal wiring and output circuit of the liquid crystal drive circuit SDL1 are signaled. It is used as a transmission path and transmitted to the next stage liquid crystal drive circuit SDL2. At this time, the internal wiring and the output circuit are used as a delay circuit, and the input signal transmitted to the liquid crystal drive circuit SDL2 in the next stage is not related to the signals DATA, TP, etc. of the signal bus output from the control circuit CONT. It will be delayed. However, since the relative time relationship between the image data DATA and the AC signal and the clock pulse TP is maintained, there is no problem with the capture and display output. In the following, input signals are transmitted in the order of the liquid crystal driving circuits SDL3, SDL4, SDL5..., And the preceding circuit is made to act as a delay circuit.

  For this reason, the serially input image data is sequentially taken into the liquid crystal drive circuits SDL2 to SDL5, etc., shifted by a time corresponding to the delay time in each of the liquid crystal drive circuits SDL1 to SDL5, and performs a parallel output operation. Since the display timing TP is similarly delayed, the first-stage liquid crystal drive circuit SDL1, the second-stage liquid crystal drive circuit SDL2,... Thus, a display output signal is output. The same applies to the upper liquid crystal drive circuits SDR1 to SDR5.

  As a result, the display drive current is distributed and output in units of the number of liquid crystal drive circuits as described above. Therefore, even if the number of signal lines increases due to high definition or large screen, the power supply lines on the mounting board The peak current that flows through is distributed and flows. Thereby, the peak current flowing through the power supply line can be greatly reduced.

  FIG. 2 is a schematic block diagram showing another embodiment of the liquid crystal display device using the liquid crystal driving circuit according to the present invention. In the figure, a liquid crystal display panel, a liquid crystal driving circuit for forming a display output signal supplied to the signal line, and a control circuit for the liquid crystal display panel are exemplarily shown as representatives, and a scanning line driving circuit necessary for the display of the liquid crystal display panel is shown. Are omitted because they are not directly related to the present invention. Further, as described above, the liquid crystal driving circuit provided on the upper side of the liquid crystal display panel LCD is also omitted.

  The liquid crystal driving circuit of this embodiment can only have about 80 to 160 display output signals, whereas the number of signal lines of the liquid crystal display panel LCD to be driven is 1000 due to high definition and large screen. There is a tendency that the number of liquid crystal driving circuits is increased, and the number of the liquid crystal driving circuits is increased. In the final stage circuit, there is a possibility that the display output may not be in time for one scanning timing period due to the added delay time. In other words, it is necessary to set the delay time for the liquid crystal drive circuit at the final stage with an upper limit of 1/2 of the period T of the serial capture signal of the display data. On the contrary, since the time width of the peak portion of the power supply noise in the conventional circuit is about 20 ns, it is necessary to set the total delay time of the final stage liquid crystal driving circuit so as to be equal to or larger than this. In this embodiment, the liquid crystal driving circuit is divided into a plurality of sets in consideration of the number of display outputs and the delay time conditions as described above.

  In this embodiment, the liquid crystal driving circuit is divided into two odd-numbered and even-numbered liquid crystal driving circuits. That is, the first, third, and fifth-stage liquid crystal drive circuits are configured to capture in parallel the image data DATA, the clock pulse TP, and the like output from the control circuit CONT as the first-stage circuit. The even-numbered liquid crystal drive circuits SDL2, SDL4, etc. are supplied with delay signals that are input through the liquid crystal drive circuits SDL1, SDL3, etc., which are the preceding stages.

  In this configuration, even if the number of liquid crystal drive circuits increases due to the high definition and large screen of the liquid crystal display panel LCD, the display output timing is divided into two. The range in which 1/2 of the period T of the captured signal is set as the upper limit and the time width of the peak portion of the power supply noise is set as the lower limit can be widened, and the delay time can be easily set in each liquid crystal driving circuit.

  FIG. 3 is a schematic block diagram showing still another embodiment of the liquid crystal display device using the liquid crystal driving circuit according to the present invention. In this embodiment, an example in which the display output timing is divided into three is shown. That is, three liquid crystal driving circuits SDL1 to SDL3 are arranged in a column for the input signal bus. As a result, the output timing of the liquid crystal driving circuit can be dispersed into three, and the peak current generated in the power supply line can be reduced to approximately 1/3. Hereinafter, if the number of liquid crystal drive circuits similarly arranged in a column is increased, the peak current value flowing through the power supply line is also reduced accordingly, and finally the embodiment of FIG. 1 has the smallest peak current. However, there is a limit due to delay time constraints.

  FIG. 4 shows a schematic block diagram of an embodiment of the liquid crystal driving circuit. In this embodiment, the input terminal is provided with an input protection circuit as an input circuit. Signals that pass through these protection circuits are supplied to internal logic / driving circuits (drivers) through internal wiring. The internal wiring is provided with a buffer (output) circuit and a function of sending a signal from the output terminal. Due to the signal propagation delay time in these internal wirings and the signal propagation delay time in the buffer circuit, the signal output from the output terminal is delayed with respect to each signal input from the input terminal.

  The input protection circuit protects the internal circuit from destruction caused by a steep current or static electricity entering from the input terminal, and stabilizes the shaping and amplitude of the distortion of the input waveform when a signal is transmitted to the internal logic or the drive circuit. That is, it is a circuit that has a role of electrically separating external and internal wiring and is commonly provided in semiconductor devices.

  There are three timing signals supplied from the input terminal: a line clock signal CL1, a data latch clock signal CL2, and an alternating signal M, which will be described later. The image data DATA is not particularly limited, but is 4-bit data. The For this reason, a total of seven input terminals are provided. Note that an input terminal to which a drive voltage formed by a drive voltage generation circuit, which will be described later, is input is regarded as a kind of power supply terminal and is omitted in FIG.

  As will be described later, the internal logic / drive circuit includes a line data latch circuit that performs serial / parallel conversion operation, a level shift circuit that shifts the output signal of the data latch circuit, and an output signal that passes through the level shift circuit. The output MOSFET (driver) is driven to output a driving voltage.

  FIG. 5 shows a schematic block diagram of another embodiment of the liquid crystal driving circuit. In the liquid crystal driving circuit, as shown in FIG. 1, the liquid crystal driving circuit is often arranged on the mounting substrate by being divided up and down the liquid crystal display panel. For this reason, when the input terminal and the output terminal are fixed as in the embodiment of FIG. 1, the liquid crystal driving circuit disposed on the upper side and the lower side of the display panel has an input terminal and an output terminal on one side. Are connected in order, and the wiring on the mounting board is minimized. On the other hand, on the other side, since the signal transmission direction, the input terminal, and the output terminal are reversed, the length of the wiring formed on the mounting board becomes long, and the input side and the output side cross each other. .

  In this embodiment, a bidirectional buffer is provided for each of the two sets of input / output terminals so that the input terminal and the output terminal can be used interchangeably. The bidirectional buffer is supplied with a shift direction control signal through an input protection circuit, and its signal transmission direction is determined. For example, if the shift direction control signal is at a high level, the input / output terminal L is used as an input terminal, and a bidirectional buffer provided corresponding thereto is operated as an input circuit. At this time, the bidirectional buffer operated as the input circuit also serves as the function of the input protection circuit. When the shift direction control signal is at a high level, a bidirectional buffer provided corresponding to the input / output terminal R is operated as an output circuit. Therefore, the input / output terminal R is used as an output terminal. With such a configuration, for example, the liquid crystal driving circuit provided on the lower side of FIG. 1 is operated.

  Conversely, if the shift direction control signal is at a low level, the input / output terminal R is used as an input terminal, and a bidirectional buffer provided corresponding thereto is operated as an input circuit. At this time, the bidirectional buffer operated as the input circuit also functions as an input protection circuit as described above. When the shift direction control signal is at a low level, a bidirectional buffer provided corresponding to the input / output terminal L is operated as an output circuit. Therefore, the input / output terminal L is used as an output terminal. With such a configuration, for example, the liquid crystal drive circuit provided on the upper side of FIG. 1 is operated.

  With such a configuration, the liquid crystal driving circuits can be connected in a column form with the shortest distance on the mounting substrate. Since the internal wiring formed in the semiconductor integrated circuit device is used as a signal transmission path, the print area formed on the mounting substrate can be reduced, and the wiring layout can be simplified. It will be possible.

  FIG. 6 shows an external view of the main part of one embodiment when the liquid crystal driving circuit according to the present invention is mounted on a liquid crystal display module. In this embodiment, although not particularly limited, a liquid crystal driving device based on a tape carrier system is mounted on a liquid crystal display panel and a printed board. The state where the input side outer lead terminal corresponding to the pixel data and the timing pulse is electrically connected by the wiring layer of the printed board is shown. In this way, a plurality of input terminals and output terminals of the liquid crystal driving circuit formed on the semiconductor chip are sequentially connected.

  FIG. 7 is a schematic overall block diagram of an embodiment of the liquid crystal display device according to the present invention. The liquid crystal display panel control device receives display data from a microprocessor CPU or the like, and generates clock pulses CL1 and CL2, display data Din, and a frame signal FLM necessary for the operation of the display panel.

  In this embodiment, when the polarity for alternating current is switched every frame (display period of one screen), polarity inversion is performed at a relatively low frequency, causing screen flickering due to alternating current. Therefore, the polarity is switched for each of a plurality of scanning lines in one frame, and the alternating frequency is increased to several hundred Hz to prevent flickering due to alternating current. For this reason, an AC signal generation circuit is provided, and the clock pulse CL1 corresponding to the selection timing is counted on the scanning line, and the polarity of the AC signal M is changed for each of the scanning lines.

  The series resistor and the operational amplifier are voltage generation circuits that form drive voltages V1 to V6 and supply them to the scan driver and the data driver. The liquid crystal display panel is composed of m scanning lines X1 to Xm and n signal lines Y1 to Yn. As a result, the liquid crystal display panel is composed of pixels such as m × n.

  The scanning line driving circuit is composed of a plurality of semiconductor integrated circuit devices, and a driving voltage V1 or V5 and V2 formed by a driving voltage generating circuit in response to a shift register that performs a shifting operation by a clock pulse CL1 and an output signal thereof. Alternatively, V6 is switched by an AC signal and output to the corresponding scanning line electrode to set the scanning line electrode to the selection / non-selection level.

  When the output signal of the shift register is set to the selection level, the drive voltage V1 is output to the corresponding scanning line electrode. At this time, the other scanning line driving voltage is set to the driving voltage V5 according to the non-selection level of the output signal of the shift register. Since the shift register sequentially shifts the selection level in synchronization with the clock pulse CL1, at the next timing, the next scanning line electrode is set to the selection level instead. In this way, the scanning line electrodes are sequentially selected. As described above, in the case of switching the polarity for each of a plurality of scanning lines in one frame, the AC signal M causes a selection level such as V2 instead of the driving voltage V1 and non-selection such as V6 instead of V5. To the level.

  The pixel data Din is serially input to the serial / parallel conversion circuit in synchronization with the clock pulse CL2. The pixel signal of the signal line electrode corresponding to one scanning line is serially input in synchronization with the clock pulse CL2 in the 1H period (within one cycle of the clock pulse CL1). Thus, the pixel signals for one scanning line captured serially are captured in parallel by the line data latch circuit as described above.

  The signal line drive circuit is composed of a plurality of liquid crystal drive circuits as described above, and is supplied to the line data latch circuit that performs the serial / parallel conversion operation as described above and the level shift circuit to provide the level. Shift. That is, the line data latch circuit is composed of a 5V system circuit, and outputs a high level such as 5V and a low level such as 0V. On the other hand, the driver is composed of a switch MOSFET, and outputs a voltage in a relatively large voltage range such as driving voltages V1, V3, V4 and V2 formed by the driving voltage generation circuit without level loss. The output signal of the latch circuit is level-shifted by a level shift circuit.

The effects obtained from the above embodiment are as follows. That is,
(1) An input terminal for a liquid crystal driving circuit that captures image data input serially in synchronization with a clock pulse and outputs a display output signal formed based on the image data serially captured in accordance with a display timing signal in parallel In addition to this, an output circuit and an output terminal are provided, a plurality of liquid crystal drive circuits are connected in a tandem form, and display output signals for each liquid crystal drive circuit using the internal wiring and output circuit in the liquid crystal drive circuit as delay means By distributing the output timing in terms of time, the peak current value flowing through the power supply line on the mounting board can be reduced even in high definition and large screens. An effect of preventing malfunction can be obtained.
(2) The input circuit and the output circuit are bidirectional buffers in which the signal transmission direction can be switched bidirectionally in accordance with the control signal, and the input terminal and the output terminal are determined in accordance with the bidirectional buffer. When the liquid crystal driving circuits are distributed and provided on both sides, an effect is obtained that the wiring for connecting the liquid crystal driving circuits in a column form on the mounting substrate can be formed in the shortest time.
(3) The liquid crystal drive circuit is divided into a plurality of sets corresponding to serial image data, and the input terminals of the first stage circuit in each set are connected in parallel to the input signal lines formed on the mounting board, By connecting the output circuit signal of the first stage circuit of each group in cascade so that it becomes the input signal of the next stage circuit, the period of the serial capture signal of the display data for high definition and large screen of the liquid crystal display panel In consideration of the upper limit delay time corresponding to the above and the time width of the peak portion of the power supply noise, the range of the lower limit can be widened.

  The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the display panel does not necessarily have to have a high definition or a large screen. When the number of signal lines is small as described above, there are advantages that an inexpensive device with a small power supply capability of the power supply device can be used, or that a thin wiring formed on the mounting substrate can be used.

  The liquid crystal display panel may have an active matrix configuration using TFTs (thin film transistors) in addition to the simple matrix configuration described above. In other words, the present invention can be widely used in a liquid crystal driving circuit and a liquid crystal display device that take in image data serially and output a display signal in parallel.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, the image data input serially in synchronism with the clock pulse is captured, and the liquid crystal drive circuit that outputs in parallel the display output signal formed based on the image data serially captured in accordance with the display timing signal. In addition, an output circuit and an output terminal are provided, and a plurality of liquid crystal drive circuits are connected in a tandem configuration, and the internal wiring and output circuit in the liquid crystal drive circuit are used as delay means for the display output signal for each liquid crystal drive circuit. By distributing the output timing in time, the peak current value flowing through the power supply line on the mounting board can be reduced even in higher definition and larger screens. Can be prevented.

  The input circuit and the output circuit are bi-directional buffers whose signal transmission directions can be switched in both directions according to the control signal, and the input terminal and the output terminal are determined in accordance with the bidirectional buffer. When the liquid crystal driving circuits are distributed and provided, the wiring for connecting the liquid crystal driving circuits in a columnar form on the mounting substrate can be formed in the shortest time.

  The liquid crystal drive circuit is divided into a plurality of sets corresponding to serial image data, and the input terminals of the first stage circuit in each set are connected in parallel to the input signal lines formed on the mounting board. By connecting the output circuit signal of the first-stage circuit in cascade so that it becomes the input signal of the next-stage circuit, it corresponds to the cycle of the serial capture signal of the display data for high definition and large screen of the liquid crystal display panel The range between the upper limit delay time and the lower limit can be widened in consideration of the time width of the peak portion of the power supply noise.

It is a schematic block diagram which shows one Example of the liquid crystal display device using the liquid crystal drive circuit which concerns on this invention. It is a schematic block diagram which shows another Example of the liquid crystal display device using the liquid crystal drive circuit based on this invention. It is a schematic block diagram which shows another one Example of the liquid crystal display device using the liquid crystal drive circuit based on this invention. 1 is a schematic block diagram showing an embodiment of a liquid crystal driving circuit according to the present invention. It is a schematic block diagram which shows another Example of the liquid-crystal drive circuit based on this invention. It is a principal part external view which shows one Example when the liquid crystal drive circuit based on this invention is mounted in the liquid crystal display module. 1 is a schematic overall block diagram showing an embodiment of a liquid crystal display device according to the present invention.

Explanation of symbols

  SDL1 to SDL5, SDR1 to SDR5 ... Liquid crystal drive circuit, CONT ... Control circuit, CPU ... Microprocessor.

Claims (3)

In a liquid crystal display device having a display area in which signal lines and scanning lines are arranged in a matrix,
A plurality of semiconductor integrated circuits to which a plurality of signal lines are connected are arranged around the display area,
The semiconductor integrated circuit forms a display output signal based on image data and outputs it to the display area,
The image data is sequentially supplied to each semiconductor integrated circuit through adjacent semiconductor integrated circuits,
The display timing signal for outputting the display output signal to the display area is sequentially supplied to each semiconductor integrated circuit through adjacent semiconductor integrated circuits,
The semiconductor integrated circuit has a buffer circuit, the buffer circuit, a liquid crystal display apparatus characterized by being arranged in the transmission path of the image data and the display timing signals. The liquid crystal display device, a liquid crystal display device according to claim 1, characterized in that the active matrix type. The liquid crystal display device, a liquid crystal display device according to claim 1, which is a simple matrix type.

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