JP2011128219A - Display device and method for driving display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device suppressing a temperature abnormality that chiefly occurs in an output buffer to a target value or lower, and also to provide a method for driving a display device. <P>SOLUTION: The liquid crystal display device 1 supplies data signals from source drivers 6 through the respective output buffers to data signal lines of a liquid crystal panel 2. Each source driver 6 is provided with: a temperature detecting circuit 20, which detects temperature abnormality that the temperature of the chip in the source driver 6 has risen to a setting or higher; and a start pulse signal wiring line 7a, which informs a controller 7 of detection of temperature abnormality when the temperature detecting circuit 20 detects temperature abnormality. The controller 7 is provided with a temperature abnormality eliminating means, which controls each source driver 6 and each gate driver 4 to eliminate temperature abnormality when the controller is informed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention includes a display panel, a plurality of source drivers and a plurality of gate drivers for driving the display panel, and a display control device for controlling display driving of the source driver and the gate driver. The present invention relates to a display device that supplies a data signal from a driver to each data signal line of a display panel via each output buffer, and a driving method of the display device, and more specifically, heat generated by driving a source driver. The present invention relates to a display device that detects an abnormality and controls operation so as not to exceed a certain temperature, and a display device driving method.

  Conventionally, active matrix liquid crystal panels have been widely used. An active matrix type liquid crystal panel has a plurality of data signal lines and a plurality of scanning signal lines intersecting the plurality of data signal lines on one transparent substrate of two transparent substrates sandwiching a liquid crystal layer. The pixel electrodes formed corresponding to the respective intersections are arranged in a matrix. Each pixel electrode is connected to a data signal line passing through an intersection corresponding to the pixel electrode via a TFT (Thin Film Transistor) as a switching element, and the gate terminal of the TFT passes through the intersection. Connected to the scanning signal line. On the other transparent substrate, a common electrode common to the plurality of pixel electrodes is formed as a common electrode.

  A liquid crystal display device including the liquid crystal panel includes a gate driver and a source driver as a drive circuit for displaying an image on the liquid crystal panel. The gate driver is also called a scanning signal line driving circuit, and is a driving circuit that applies a scanning signal for sequentially selecting the plurality of scanning signal lines to the plurality of scanning signal lines. The source driver is also called a data signal line drive circuit or a video signal line drive circuit, and is a drive circuit that applies a data signal for writing data to each pixel formation portion in the liquid crystal panel to the plurality of data signal lines.

  In the liquid crystal display device having the above configuration, the common voltage Vcom is applied to the common electrode facing the pixel electrode. In addition, a voltage corresponding to the value of the pixel corresponding to the pixel electrode is applied between each pixel electrode and the counter electrode, and the transmittance of the liquid crystal layer is changed according to the voltage application, whereby the liquid crystal panel is An image is displayed. At this time, the liquid crystal panel is AC driven in order to prevent deterioration of the liquid crystal material constituting the liquid crystal layer. That is, the source driver outputs the data signal so that the positive and negative polarities of the voltage applied between each pixel electrode and the counter electrode are inverted, for example, every frame.

  In general, in an active matrix type liquid crystal panel, there is a variation in characteristics of switching elements such as TFTs provided for each pixel. Therefore, an application based on the potential of the counter electrode, which is a data signal output from a source driver, is applied. Even if the positive and negative voltages are symmetrical, the transmittance of the liquid crystal layer is not completely symmetrical with respect to the positive and negative applied voltages. For this reason, in the frame inversion driving method in which the polarity of the voltage applied to the liquid crystal is inverted every frame, flickering occurs in the display of the liquid crystal panel.

  As a countermeasure against such flickering, a driving method is known in which the positive / negative polarity of the applied voltage is inverted for each horizontal scanning signal line while the positive / negative polarity is inverted for each frame. There is also known a dot inversion driving method in which the positive / negative polarity of the voltage applied to the liquid crystal layer forming the pixel is inverted for each scanning signal line and for each data signal line while being inverted for each frame.

  FIG. 21 shows source driver driving waveforms for outputting image data when the display panel is driven by the dot inversion driving method. In the dot inversion driving method, as shown in FIG. 21, the outputs of the positive data voltage Vpdata higher than the common voltage Vcom applied to the common electrode and the negative data voltage Vndata lower than the common voltage Vcom are output for each line. Has been repeated.

  On the other hand, the source driver is provided with a number of output buffers, each of which is connected to a data signal line and drives the load of the data signal line and the liquid crystal cell. Therefore, when the source driver outputs the potential of the positive data voltage Vpdata, the charging current from the high potential voltage VDD flows to the load, while the source driver outputs the potential of the negative data voltage Vndata. Causes a discharge current to flow to the low potential voltage VSS. Here, since the charging current and the discharging current pass through the internal resistance in the output buffer provided in the source driver, the amount of heat generation increases.

  Heat generated from the inside of the source driver is mainly generated from the output buffer. Therefore, in order to reduce the heat generation amount of the source driver, the heat generation from the output buffer, particularly the heat generation from the output portion of the output buffer, must be minimized. However, as shown in FIG. 21, when the data signal voltage swings between the positive data voltage Vpdata and the negative data voltage Vndata, heat generated by the internal resistance in the output buffer increases with the width of the swing. In addition, in a driving method in which the polarity is switched for each line, such as dot inversion driving, the number of times of charging / discharging increases, so that power consumption increases.

  As one method for preventing the increase in power consumption, for example, Patent Document 1 proposes a driving method using interlaced scanning (interlaced driving). In the interlace scanning disclosed in Patent Document 1, all odd-numbered (or even-numbered) scanning signal lines are scanned first, and then the remaining even-numbered (or odd-numbered) scanning signal lines are scanned.

  FIG. 22 shows source driver drive waveforms when interlaced scanning is performed. In interlaced scanning, rows of pixels with the same polarity are sequentially scanned, so that polarity inversion is performed at the timing when switching from odd-numbered line scanning to even-numbered line scanning is performed.

  FIG. 23 is a source driver drive waveform at the time when scanning of one frame in the case of performing interlaced driving, that is, scanning of both odd and even rows, is completed, and the dot inversion driving method shown in FIG. The same state as the source driver driving waveform in FIG. As described above, in interlaced driving, polarity inversion driving for each scanning line is possible and the number of polarity inversions can be suppressed. Therefore, the number of charging / discharging can be reduced, and an increase in power consumption can be suppressed.

  Here, if interlace driving is performed over the entire screen of the liquid crystal panel as in Patent Document 1, flickering is caused. Therefore, for example, Patent Document 2 proposes a driving method in which the display unit is divided into a plurality of areas in the column direction, and skipping scanning is performed for each area.

Japanese Patent Laid-Open No. 8-320674 (released on December 3, 1996) JP 11-352938 A (published December 24, 1999)

  As described above, in the conventional display device and the driving method of the display device, the driving method is devised so as to suppress the heat generation of the driving device.

  However, in the conventional display device and the driving method of the display device, even if the driving method is used due to reduction due to miniaturization of the driving device or increase in the number of driving elements (number of output terminals) arranged in the driving device. There is a problem in that the case where the heat generation of the drive device cannot be suppressed below the target value occurs.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a display device that can suppress a temperature abnormality mainly generated in an output buffer to a target value or less, and a method for driving the display device. There is.

  In order to solve the above problems, a display device of the present invention controls a display panel, a plurality of source drivers and a plurality of gate drivers for driving the display panel, and display driving of the source drivers and the gate drivers. A display control device that supplies a data signal from each source driver to each data signal line of the display panel via each output buffer. Each source driver includes a temperature of a chip of the source driver. Temperature abnormality detection means for detecting a temperature abnormality when the temperature exceeds the setting, and a temperature abnormality notification for notifying the display control device that a temperature abnormality has been detected when the temperature abnormality detection means detects a temperature abnormality And the display control device receives a notification from the temperature abnormality notification means when the temperature abnormality is detected. Temperature abnormality eliminating means for controlling each of the above source driver and the gate driver so as to eliminate is characterized in that is provided.

  In order to solve the above problems, a display device driving method of the present invention includes a display panel, a plurality of source drivers and a plurality of gate drivers for driving the display panel, and display of the source drivers and the gate drivers. A display control device that controls driving, and a display device driving method for supplying a data signal from each source driver to a data signal line of a display panel via each output buffer. A temperature abnormality detection step for detecting a temperature abnormality that has exceeded the set value, and a temperature abnormality that notifies the display control device that the temperature abnormality of the source driver has been detected when the temperature abnormality of the source driver is detected. When the notification process and the display control device are notified of the temperature abnormality of the source driver, the temperature abnormality is resolved. It is characterized in that it comprises as a temperature anomaly canceling step of controlling each of the above source driver and the gate driver.

  The source driver supplies a data signal to a plurality of data signal lines via each output buffer to drive the display device. Such a source driver has a problem that the amount of heat generated in each output buffer of the source driver is large, and a temperature abnormality due to the amount of generated heat cannot be suppressed to a target value or less.

  In this regard, in the display device of the present invention, each source driver has a temperature abnormality detection means for detecting a temperature abnormality that the temperature of the chip of the source driver has become equal to or higher than a setting, and the temperature abnormality detection means includes a temperature abnormality. Temperature abnormality notifying means for notifying the display control device that a temperature abnormality has been detected is detected, and the display control device has received a notification from the temperature abnormality notification means. In some cases, temperature abnormality eliminating means for controlling each source driver and each gate driver so as to eliminate the temperature abnormality is provided.

  For this reason, when the temperature abnormality detecting means detects a temperature abnormality, the temperature abnormality notifying means notifies the display control device, and the temperature abnormality eliminating means of the display control device performs a display operation to eliminate the temperature abnormality. It is possible to suppress the abnormality below the target value.

  Therefore, it is possible to provide a display device and a display device driving method that can suppress temperature abnormality mainly occurring in the output buffer below the target value. The target value can be set as appropriate.

  In the display device of the present invention, the temperature abnormality eliminating means can eliminate the temperature abnormality by controlling each of the source driver and each gate driver so as to reduce the display rewriting speed of the display panel.

  In the display device driving method of the present invention, in the temperature abnormality elimination step, it is possible to eliminate the temperature abnormality by controlling each of the source driver and each gate driver so as to slow down the display rewriting speed of the display panel. is there.

  That is, by reducing the display rewriting speed of the display panel, the operation speed of the source driver is lowered, and the switching cycle of the liquid crystal drive signal is lowered. As a result, heat generation at the time of switching the liquid crystal drive signal in the output buffer of the source driver is reduced.

  Therefore, the temperature abnormality elimination means specifically provides a display device and a display device driving method capable of suppressing the temperature abnormality mainly occurring in the output buffer below the target value by slowing down the display rewriting speed of the display panel. can do.

  In the display device according to the present invention, the temperature abnormality eliminating means may be configured to store the pixel for every two consecutive display scan lines with the same writing contents of the odd display scan lines and the even display scan lines. It is possible to eliminate the temperature abnormality by controlling each source driver and each gate driver to perform rewriting.

  In the display device driving method of the present invention, in the temperature abnormality elimination step, the writing contents of the odd display scan lines and the even display scan lines are made the same for the two consecutive display scan lines on the display panel. It is possible to eliminate the temperature abnormality by controlling each source driver and each gate driver so that the pixel is rewritten.

  That is, in the output buffer of the source driver, heat generation at the time of switching the liquid crystal drive signal is reduced by reducing the rewrite frequency.

  Therefore, in the present invention, the temperature abnormality eliminating means rewrites the pixels for every two consecutive display scanning lines with the same writing content of the odd display scanning lines and the even display scanning lines. The source drivers and the gate drivers are controlled as described above.

  As a result, in the output buffer of the source driver, the rewrite frequency is reduced to half.

  Therefore, it is possible to specifically provide a display device and a display device driving method that can suppress temperature abnormality mainly occurring in the output buffer to a target value or less.

  In the display device of the present invention, the temperature abnormality eliminating means writes data to the odd display scan lines (or even display scan lines) in the first frame, and even display scan lines (even numbers in the odd frames) in the next second frame. It is possible to eliminate the temperature abnormality by controlling each source driver and each gate driver so that writing is performed on an odd display scanning line when writing is performed on the display scanning line.

  In the driving method of the display device of the present invention, in the temperature abnormality eliminating step, writing is performed on the odd display scan lines (or even display scan lines) in the first frame, and even display scan lines (odd numbers are displayed in the next second frame). It is possible to eliminate the temperature abnormality by controlling each source driver and each gate driver so that writing is performed on the odd display scanning line when writing is performed on the even display scanning line in the frame.

  In the above-described method of rewriting a pixel for every two consecutive display scan lines with the same writing contents of the odd display scan lines and even display scan lines, for example, white is instantaneously displayed at a place where black is displayed. On the other hand, black may be displayed for a moment in a place where white is displayed.

  Therefore, in order to avoid this problem, in the present invention, the temperature abnormality eliminating means writes to the odd display scan line (or even display scan line) in the first frame, and even display scan line in the next second frame. The source driver and the gate driver are controlled so as to perform writing so as to perform writing to the even display scanning line in the odd frame, so as to eliminate the temperature abnormality.

  In this manner, by displaying the odd display scan lines and the even display scan lines separately for the first frame and the second frame, it is possible to prevent a part of the image from being expressed.

  In the display device according to the present invention, as described above, each source driver includes a temperature abnormality detection unit that detects a temperature abnormality when the temperature of the chip of the source driver exceeds a set value, and the temperature abnormality detection unit. A temperature abnormality notification means for notifying the display control device that a temperature abnormality has been detected when a temperature abnormality is detected is provided, and the display control device receives a notification from the temperature abnormality notification means. A temperature abnormality eliminating means for controlling each of the source driver and each gate driver so as to eliminate the temperature abnormality when received is provided.

  As described above, the display device driving method according to the present invention detects a temperature abnormality detecting step for detecting a temperature abnormality when the temperature of the chip of the source driver is equal to or higher than a setting, and detects a temperature abnormality of the source driver. In addition, a temperature abnormality notification step for notifying the display control device that the temperature abnormality of the source driver has been detected, and when the display control device is notified of the temperature abnormality of the source driver, the temperature abnormality is resolved. And a temperature abnormality eliminating step for controlling each of the source drivers and the gate drivers.

  Therefore, it is possible to provide a display device and a display device driving method that can suppress a temperature abnormality mainly occurring in the output buffer below the target value.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram illustrating a configuration of a liquid crystal panel according to an embodiment of a liquid crystal display device of the present invention. It is a circuit diagram which shows the structure of the temperature abnormality transmission circuit in the said liquid crystal display device. (A) is a timing chart showing the start pulse signal SSP input to the first-stage source driver and the start pulse signal SSPO1 output from the first-stage source driver on the time axis of the source clock signal SCLK, and (b). 5 is a timing chart showing a start pulse signal SSPOn-1 input to an nth stage source driver and a start pulse signal SSPOn output from an nth stage source driver on a time axis of a source clock signal SCLK. (A) is a timing chart showing the start pulse signal SSP input to the first-stage source driver and the start pulse signal SSPO1 output from the first-stage source driver on the time axis of the source clock signal SCLK, and (b). When the source driver detects a temperature abnormality, the start pulse signal SSPOn-1 input to the nth stage source driver and the start pulse signal SSPOn output from the nth stage source driver are represented by the source clock signal SCLK. It is a timing chart shown on a time axis. (A), (b) is a timing chart which shows the start pulse signal which becomes a 2 clock period when temperature abnormality occurs. (A) is a circuit diagram which shows an example of the temperature detection circuit in the said liquid crystal display device, (b) is a circuit diagram which shows the structure of the modification of (a). (A) is a circuit diagram which shows the structure of the test circuit in the said liquid crystal display device, (b) is a wave form diagram which shows the waveform in node ND_A shown to (a) when the temperature of a source driver is not high, ( (c) is a waveform diagram showing a waveform at the node ND_A shown in (a) when the temperature of the source driver becomes high. (A) is a front view of a liquid crystal panel in which a letter “A” is displayed on a display screen having 18 scanning signal lines, showing a method for eliminating temperature abnormality in the liquid crystal display device. It is a front view of the liquid crystal panel which shows the display method which rewrites a pixel for every two continuous display scanning lines by making the writing content of the odd display scanning line and the even display scanning line the same. (A) and (b) show a method for eliminating temperature abnormality in the liquid crystal display device. In the first frame, writing is performed on odd display scanning lines (or even display scanning lines), and in the second frame. It is a front view of a liquid crystal panel showing a display method for writing on even display scanning lines (or odd display scanning lines when writing to even display scanning lines in odd frames). In the above liquid crystal display device, the gray scale is simply divided into 64 from positive voltage 6V to voltage 12V. In the liquid crystal display device, the gradation is simply divided into 64 from negative voltage 0V to voltage 6V. It is a circuit diagram which shows the structure of the reference voltage generation circuit in the said liquid crystal display device. (A) is a block diagram showing a configuration of an output circuit of a source driver that performs dot inversion in the liquid crystal display device, and (b) shows an output amplitude when a temperature abnormality of the source driver is detected in the output circuit. It is a circuit diagram which shows the circuit structure for making it small. It is a circuit diagram which shows the structure of the pass transistor which connected each source and drain of Pch transistor and Nch transistor in the said liquid crystal display device. FIG. 3 is a block diagram illustrating a configuration of an output circuit of a source driver that performs dot inversion in the liquid crystal display device. (A)-(d) is a circuit diagram which shows each structure of switch SWA1, SWB1, SWA2, and SWB2 which changes the connection of operational amplifier and output terminal TA * TB in the output circuit shown in FIG. It is a circuit diagram which shows the operational amplifier circuit which comprises the operational amplifier in the said output circuit. It is a circuit diagram which shows the structure of the temperature abnormality avoidance transmission circuit in the said liquid crystal display device. It is a circuit diagram which shows the semiconductor integrated circuit for a liquid crystal drive which comprises the said source driver. (A), (b), (c) is a circuit diagram which shows the structure of each part of the voltage detection circuit in the said liquid crystal drive semiconductor integrated circuit. It is a wave form diagram which shows the drive waveform of the source driver which outputs image data at the time of driving a display panel by a dot inversion drive system. It is a wave form diagram which shows the drive waveform of the source driver which outputs image data at the time of performing interlace drive. It is a wave form diagram which shows the drive waveform of a source driver at the time of the scanning of one flame | frame when the interlace drive was performed.

[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 is a block diagram showing a main configuration of a liquid crystal display device 1 according to the present embodiment.

  A liquid crystal display device 1 as a display device according to the present embodiment is a TFT (Thin Film Transistor) type liquid crystal display device which is a typical example of an active matrix method. As shown in FIG. A liquid crystal panel 2, a gate driver unit 3, a source driver unit 5, a controller 7 as a display control device, a counter electrode 8, and a liquid crystal driving power source 9 are provided.

  The gate driver unit 3 includes a plurality of gate drivers 4, is supplied with a gate voltage from the liquid crystal driving power supply 9, and outputs a scanning signal for sequentially scanning the scanning signal lines in the liquid crystal panel 2.

  The source driver unit 5 includes a plurality of source drivers 6. The source driver unit 5 time-divides display data D input from the controller 7 and latches the data into a plurality of source drivers 6. Each source driver 6 performs D / A conversion on the time-divided display data D. As a result, a data signal for gradation display corresponding to the brightness of the display target pixel is output to the liquid crystal panel 2.

  The controller 7 outputs display data D and a control signal S1 which are digital signals to each source driver 6. Further, the controller 7 outputs an operation clock CLK to each gate driver 4 and outputs a gate start pulse signal GSP to the first stage gate driver 4 through the gate start pulse signal wiring 7b. The liquid crystal driving power source 9 generates an external reference voltage and outputs it to the gate driver unit 3, the source driver unit 5, and the counter electrode 8.

  The counter electrode 8 is a common electrode connected to each other, and is provided in the liquid crystal panel 2.

  Next, the configuration of the liquid crystal panel 2 will be described with reference to FIG. FIG. 2 is a circuit diagram showing a configuration of the liquid crystal panel 2.

  As shown in FIG. 2, the liquid crystal panel 2 is provided with a source signal line SL, a scanning signal line GL, a liquid crystal display element 10, and a counter electrode 8 as data signal lines.

  A plurality of source signal lines SL are provided in parallel with each other at a predetermined interval, and a plurality of scanning signal lines GL are provided in parallel with each other at a predetermined interval in a direction orthogonal to the source signal lines SL. Yes.

  The liquid crystal display element 10 is provided at each intersection of the source signal line SL and the scanning signal line GL, and includes a pixel capacitor 11, a pixel electrode 12, and a TFT 13. One end of the pixel capacitor 11 is coupled to the pixel electrode 12, and the other end of the pixel capacitor 11 is coupled to the counter electrode 8. The TFT 13 performs on / off control of voltage application to the pixel electrode 12. The source of the TFT 13 is connected to the source signal line SL, the gate of the TFT 13 is connected to the scanning signal line GL, and the drain of the TFT 13 is coupled to the pixel electrode 12.

  A scanning signal for sequentially turning on the TFTs 13 arranged in the column direction is supplied to the scanning signal line GL from the gate driver 4 shown in FIG. On the other hand, a gradation display voltage as a data signal is output to the source signal line SL from the source driver 6 shown in FIG. When the TFT 13 is in the ON state, the gradation display voltage from the source signal line SL is applied to the pixel electrode 12 and charges are accumulated in the pixel capacitor 11. Thereby, the light transmittance of the liquid crystal changes according to the gradation display voltage, and pixel display is performed.

Here, in the present embodiment, each source driver 6 shown in FIG. 1 is provided with a temperature detection circuit 20 as temperature abnormality detection means, and each source driver 6 has its own in the temperature detection circuit 20. The chip temperature is measured and notified to the controller 7 by a start pulse signal wiring 7a as temperature abnormality notification means.
(Configuration of temperature abnormality notification circuit)
The configuration of the temperature abnormality notification circuit 25 will be described below.

  In the present embodiment, when the temperature detection circuit 20 detects a temperature abnormality, each source driver 6 transmits the start pulse signal SSP using the start pulse signal wiring 7a. That is, in the present embodiment, the controller 7 is notified of the temperature abnormality using the start pulse signal SSP which is a cascade connection signal.

  3A and 3B, the start pulse signal SSP input in the source driver 6 and the start output from the source driver 6 to communicate with the source driver 6 of the next stage from the source driver 6 are shown. The timing of the pulse signal SSP is shown. FIG. 3A is a timing chart showing the start pulse signal SSP input to the first stage source driver 6 and the start pulse signal SSPO1 output from the first stage source driver 6 on the time axis of the source clock signal SCLK. is there. FIG. 3B shows that the start pulse signal SSPOn-1 input to the n-th stage source driver 6 and the start pulse signal SSPOn output from the n-th stage source driver 6 are represented by the source clock signal SCLK. It is a timing chart shown on the time axis.

  The start pulse signal SSP is connected to each source driver 6 and is a signal indicating the start timing of fetching the display data D in the source driver 6 at each stage.

  As shown in FIG. 3A, the start pulse signal SSP that is output from the controller 7 and is a data sampling start command of the source driver 6 is input to the source driver 6 at the first stage. Then, the first-stage source driver 6 outputs the start pulse signal SSPO1 to the second-stage source driver 6 at the timing when the data acquisition of the first-stage source driver 6 is completed. In the second stage source driver 6, the second stage source driver 6 starts to take in the display data D in response to the input of the start pulse signal SSPO 1. Similarly, as shown in FIG. 3B, the operation up to the n-th stage source driver 6 which is the final stage is performed, and the capture of the display data D is completed. A start pulse signal SSPOn indicating that the display data D has been captured is sent to the controller 7.

  The timing charts shown in FIGS. 3A and 3B show a normal state, and FIGS. 4A and 4B are timing charts when a temperature abnormality is detected.

  Here, as shown in FIG. 3A, the source driver 6 at the first stage monitors the start pulse signal SSP output from the controller 7 at the rising edge of the source clock signal SCLK, and the start pulse signal SSP is “H”. Is detected, sampling of the display data D is started, and the start pulse signal SSPO1 is set to “H” one clock before the sampling ends.

  As shown in FIG. 3B, the n-th stage source driver 6 monitors whether the start pulse signal SSPOn-1 becomes “H” at the rising edge of the source clock signal SCLK. Here, since the start pulse signal SSPOn-1 is delayed by the output load, "H" is detected at time Tb1. Since the time Tb1 is the time when the data sampling of the (n-1) th stage source driver 6 which is the previous stage source driver 6 is finished, the nth stage source driver 6 can continue to perform data sampling.

  The source driver 6 also recognizes that the start pulse signal SSPO and the start pulse signal SSPOn at the rising edge of the next source clock signal SCLK at the times Ta1 and Tb2 at which it is recognized that the start pulse signal SSPO and the start pulse signal SSPOn-1 become “H”. -1 status is monitored. In the case of FIGS. 3A and 3B, the start pulse signal SSPOn-1 is “L” at the times Ta1 and Tb2.

  Next, a timing chart when the source driver 6 detects a temperature abnormality will be described with reference to FIGS. FIG. 4A is the same timing chart as FIG. 3A, and FIG. 4B is a timing chart showing a state when the n-1 stage source driver 6 detects a temperature abnormality. .

  In FIG. 4A, as in FIG. 3A, the “H” period of the start pulse signal SSP that is the output of the controller 7 is one clock, but as shown in FIG. The “H” period of the start pulse signal SSPOn−1 in the n−1 stage source driver 6 is two clocks. This indicates that the n−1-th stage source driver 6 has detected a temperature abnormality and switched its operation.

  As shown in FIG. 4B, the start of sampling display data D is detected at time Tb1, and then it is detected that a temperature abnormality has occurred at time Tb2. The n-th stage source driver 6 switches to the operation corresponding to the temperature abnormality, and outputs the start pulse signal SSPOn in two clock periods. Then, the start pulse signal SSPOn in the final-stage n-th source driver 6 is transmitted to the controller 7.

  When the controller 7 detects that a temperature abnormality has occurred based on the signal of the start pulse signal SSPOn, as shown in FIG. 5A, the start pulse signal SSP also has a two-clock period. Therefore, as shown in FIG. 5B, the first source driver 6 and thereafter operate in a state where the operation is switched to the temperature abnormal operation.

The controller 7 repeats outputting the start pulse signal SSP in the “H” state for two clock periods during the determined frame. Thereafter, the start pulse signal SSP is returned to “H” for one clock period, and output is performed. At this time, if the temperature abnormality of all the source drivers 6 has been eliminated, the normal operation is performed. However, if even one source driver 6 having a temperature abnormality remains, the above operation is repeated, and the temperature again The operation corresponds to the abnormality.
(Temperature detection circuit)
Next, the structure of the temperature detection circuit 20 described above will be described with reference to FIGS. 6A and 6B are circuit diagrams showing an example of the temperature detection circuit 20, and FIG. 6A shows the configuration of the temperature detection circuit using two types of resistors. 6 (b) shows the configuration of the modified example of FIG. 6 (a).

  First, when it is necessary to form a circuit for detecting temperature on the integrated circuit, such as the source driver 6, a thermocouple cannot be used. For this reason, in this embodiment, as shown in FIGS. 6A and 6B, two types of devices such as resistors and diodes are used, and the temperature is detected using the difference in temperature characteristics between these two types of devices. Like to do.

  First, a temperature detection circuit 20 that uses two types of resistors and detects a temperature using a difference in temperature characteristics between the two types of resistors will be described with reference to FIG.

  As shown in FIG. 6A, the temperature detection circuit 20 includes two resistors R3 and R4 and a comparator 21 connected in series between a power supply voltage node Vcc and a ground node. The node ND located between the two resistors R3 and R4 is connected to the minus terminal of the comparator 21, while the reference voltage VREF is supplied to the plus terminal of the comparator 21.

  Here, the resistor R3 is a poly resistor formed by depositing polysilicon, and the resistor R4 is a diffused resistor formed by diffusing impurities from the semiconductor surface.

  In the temperature detection circuit 20 having such a configuration, since the temperature characteristics of the resistor R3 and the resistor R4 are different, the potential of the node ND varies depending on the temperature. At this time, if the potential of the node ND at the desired temperature is set to the reference voltage VREF, it can be detected that the temperature is higher (or lower) than the desired temperature.

Here, as shown in FIG. 6B, the temperature detection circuit 20 may have a configuration in which the resistor R4 shown in FIG. 6A is replaced with a diode D4. Even in this configuration, since the temperature characteristics of the resistor R3 and the diode D4 are different, temperature detection similar to the above can be performed.
(Temperature detection method using delay)
In this embodiment, a simple temperature detection method using the source driver 6 circuit is possible without providing the dedicated temperature detection circuit 20 as shown in FIGS. is there. Such a temperature detection method will be described with reference to FIGS. 7 (a), 7 (b), and 7 (c). FIG. 7A is a block diagram showing a configuration of the source driver 6 that enables the temperature detection method, and FIG. 7B shows a node shown in FIG. 7A when the temperature of the source driver is not high. FIG. 7C is a waveform diagram showing a waveform at the node ND_A shown in FIG. 7A when the temperature of the source driver becomes high.

  As shown in FIG. 1, the source driver 6 sequentially transfers the start pulse signal SSP from the controller 7, and finally returns the start pulse signal SSPOn to the controller 7.

  Further, the liquid crystal display device 1 has a period during which no display is performed, which is called a vertical blanking period. In the present embodiment, the state of the source driver 6 is detected using the start pulse signal SSP using this vertical blanking period.

  Specifically, the source driver 6 is provided with a temperature detection test circuit 40 as temperature abnormality detection means as shown in FIG. The temperature detection test circuit 40 includes an input terminal SSPin, an output terminal SSPout, inverters 41 and 42, a resistor 43, and switches 44 and 45, as shown in FIG.

  The input terminal SSPin is a terminal to which the start pulse signal SSP or the start pulse signals SSPO1 to SSPOn-1 shown in FIG. Are terminals output from each source driver 6.

  In the above temperature detection test circuit 40, since the switches 44 and 45 are normally connected to the switch terminal I and the switch terminal A, the signal input from the input terminal SSPin is processed by the normal circuit 46 and output. Output to terminal SSPout.

  The controller 7 instructs the source driver 6 to connect the output terminal SSPout and the input terminal SSPin to the temperature detection test circuit 40 during the vertical blanking period.

  When a connection command to the temperature detection test circuit 40 comes from the controller 7, the switches 44 and 45 are connected to the switch terminal I and the switch terminal B, and the connection from the input terminal SSPin to the output terminal SSPout is from the normal circuit 46. The circuit is switched to a circuit composed of the inverters 41 and 42 and the resistor 43.

  Since the drive capability of the inverters 41 and 42 shown in FIG. 7A is reduced when the temperature is high, if there is a source driver 6 that is at a high temperature, the delay time increases at that point and the controller 7 returns to the controller 7. The start pulse signal SSPOn is slower than usual. The delay is measured by the controller 7 and when the delay more than the setting occurs, the source driver 6 may be switched to the operation at the time of abnormal high temperature. The resistor 43 is for adjusting the delay time, and its value can be changed as appropriate.

  Instead of measuring the delay by the controller 7, it may be measured whether the inverter 41 can drive the resistor 43 in the temperature detection test circuit 40 of the source driver 6. The controller 7 outputs a short pulse from the start pulse signal SSP and checks whether the pulse is fed back from the start pulse signal SSPOn. In this case, the value of the resistor 43 shown in FIG. 7A is increased, or the drive capability of the inverter 41 is decreased to increase the delay of the node ND_A.

  FIG. 7B shows a waveform when the temperature is not high. When the temperature is not high, a pulse close to a square wave is input from the input terminal SSPin. The waveform of the node ND_A, which is the output of the inverter 41, is delayed. However, when the drive capability of the inverter 42 is sufficiently large, when the inversion voltage of the inverter 42 is exceeded, the delayed waveform of the node ND_A is shaped at the output terminal SSPout to form a square wave. Output in a form close to. For this reason, a delay time occurs, but a pulse is output.

  Next, FIG. 7C shows a waveform when the temperature becomes high. The input signal from the input terminal SSPin is the same, but the driving capability of the inverters 41 and 42 is reduced because the temperature has increased. The inverter 41 is particularly susceptible to temperature because the delay time is increased as described above. For this reason, the output delay time of the inverter 41 is increased, and the input pulse is inverted before the output exceeds the inverted voltage of the inverter 42. For this reason, no pulse is output to the output terminal SSPout which is the output of the inverter 42.

As described above, the temperature detection test circuit 40 of the source driver 6 whose delay has been increased cannot drive a signal during the “H” (or “L”) period of the pulse, and cannot output a pulse. For this reason, when the temperature detection test circuit 40 shown in FIG. 7A is connected, a pulse is output from the controller 7 to the input terminal SSPin, and by monitoring whether the pulse is fed back from the output terminal SSPout, The presence or absence of the source driver 6 in which the temperature abnormality has occurred can be confirmed.
(Countermeasures for abnormal temperature)
Next, various examples of operation contents to be switched when the source driver 6 becomes abnormal in high temperature are shown. These (Example 1) to (Example 14) can be applied in combination as appropriate.
(Example 1: Slow down the overall operation speed)
In order to suppress heat generation due to the operation of the source driver 6, the controller 7 reduces the operation speed of the source driver 6 to reduce the switching cycle of the liquid crystal drive signal. The source driver 6 charges and discharges the panel capacitance by switching the liquid crystal drive signal. At this time, since a large current flows through the source driver 6, if the drive signal switching is reduced, the current decreases and the temperature also decreases.

  For example, when the frame frequency is 60 Hz and a temperature abnormality is detected, the controller 7 causes the gate start pulse as a vertical synchronization signal in the gate start pulse signal wiring 7b to set the frame frequency to 30 Hz which is ½. By switching the output timing of the signal GSP from 60 Hz to 30 Hz, all signals related to display are halved.

  With this configuration, the switching period of the liquid crystal drive signal of the source driver 6 becomes ½, and the temperature of the source driver 6 decreases.

  The above driving is performed once every several frames, and is repeated until the temperature abnormality of the source driver 6 is eliminated. For example, once every 10 seconds, that is, in a plurality of frames for 10 seconds, the switching cycle is halved by one frame, and this driving is repeated until the temperature abnormality of the source driver 6 is eliminated.

Note that the interval at which the above driving is performed varies depending on the liquid crystal display device 1, and may be set at an interval causing no problem in the actual liquid crystal display device 1.
(Example 2: The writing contents of the odd display scan lines and the even display scan lines are the same, and the pixel is rewritten for every two consecutive display scan lines.)
In order to reduce the drive period of the source driver 6 without reducing the frame frequency, the source driver 6 changes the output not every time the gate driver 4 drives the scanning signal line GL, for example, two lines. What is necessary is just to reduce the frequency | count that the output of the source driver 6 changes for every scanning signal line GL.

  Specifically, scanning is performed as usual, but the source driver 6 outputs the gradation data for the first display scanning line, and then holds the output as it is for the scanning period of the next second display scanning line. Data sampling for the second display scan line is not performed. Therefore, the second display scan line has the same display as the data of the first display scan line. That is, the pixel is rewritten every two display scanning lines.

  As a result, the number of times of display on one screen display scan line is halved. However, this driving method may be performed within a range that has little influence on display, for example, one frame out of 60 frames.

  As a specific example, for example, a case where the character “A” is displayed on 18 display screens as shown in FIG. 8A will be described.

  In the above driving, the scanning signal line GL is driven as usual, but the output of the source driver 6 changes only for every two consecutive scanning signal lines GL. That is, the gate start pulse signal GSP of the gate start pulse signal wiring 7b is outputted as usual, but the latch timing in the latch circuit 83 for latching the gradation data in the liquid crystal driving semiconductor integrated circuit 70 shown in FIG. The controller 7 controls the latch timing signal for controlling the data so that data sampling for the next line is not performed, that is, is not latched.

For this reason, as shown in FIG. 8B, all the pixels in the display scanning line “1” are displayed in white, and therefore the display of the display scanning line “2” is also all white. Hereinafter, similarly, the same pattern is displayed for every two scanning scanning lines. In the next frame, the display returns to that shown in FIG.
(Example 3: When writing to odd display scan lines (or even display scan lines) in the first frame, and even display scan lines (writing to even display scan lines in odd frames) in the next second frame Write to odd display scan line)
In the above (example 2), for example, white is displayed at a place where black is displayed in a horizontal bar “A” or the like. On the other hand, black is displayed for a moment at a place where white is displayed as indicated by a display scanning line “18” shown in FIG.

  In order to prevent this, the operation of the gate driver 4 is changed to separately scan the even-numbered scan signal line GL and the odd-numbered scan signal line GL.

  The operation of the source driver 6 is the same as in (Example 2), and the source driver 6 outputs the gradation data for one display scanning line and then holds the output as it is for the scanning period of the next display scanning line. Data sampling for the next display operation line is not performed.

  On the other hand, as shown in FIG. 9A, the gate driver 4 scans the odd scanning signal lines GL and displays the odd scanning signal lines GL in the first frame. In the next frame, as shown in FIG. 9B, the even scanning signal lines GL that have not been scanned in the previous frame are scanned.

  Specifically, as the control of the controller 7, for example, in the first frame, a horizontal synchronization signal is sent to the gate driver 4 so as to select only the odd display scanning lines. Further, a latch timing signal is sent to the source driver 6 so as to latch the gradation data of the odd lines in order to output the gradation data for the odd display scanning lines. Then, control is performed so that data sampling for the next even line is not performed, that is, is not latched.

  In the second frame, the controller 7 sends a selection signal to the gate driver 4 so as to select only the even display scanning lines. Then, a latch timing signal is sent to the source driver 6 so as to latch the gradation data of the even lines in order to output the gradation data of the even lines. Then, control is performed so that data sampling for the next odd-numbered line is not performed, that is, is not latched.

  With this driving method, the number of display lines per screen is halved, but once every few frames (2 frames), the process is repeated until the temperature abnormality of the source driver 6 is eliminated.

  The interval at which the above driving is performed varies depending on the liquid crystal display device 1, and may be set at an interval causing no problem in the actual liquid crystal display device 1.

  In the above description, the remaining display in the previous frame is not shown, but when the odd display scan line is scanned, the display of the even display scan line displayed in the previous frame remains. For this reason, when the display of the same pattern is repeated (still image), the display is not affected.

When displaying a moving image, since the pattern to be displayed changes for each frame, if there is a display scanning line that is not scanned, the display is likely to be affected, so (Example 2) may be used.
In (Example 2), an unintended pattern appears on the still screen, and the display is likely to be affected. Therefore, (Example 3) may be used for the still image.
(Example 4: Manipulating gradation data to suppress output amplitude)
The heat generated in the output buffer of the source driver 6 increases as the output amplitude increases. An example of the output voltage of the source driver 6 capable of outputting 64 gradations is shown in FIGS. In FIG. 10 and FIG. 11, for simplicity, the common voltage applied to the counter electrode 8 is set to 6V without considering γ correction, and the positive voltage 6V to the voltage 12V and the negative voltage 0V to the voltage 6V. Are simply divided into 64 parts. FIG. 10 is a diagram showing gray scales simply divided into 64 from positive voltage 6V to voltage 12V, and FIG. 11 shows gray scales divided simply into 64 from negative voltage 0V to voltage 6V. FIG.

  In this case, as shown in FIG. 10 and FIG. 11, for example, “gradation 1” indicated by data (decimal) “0” is the same as the common voltage regardless of whether the polarity is positive or negative. 6V is output. Since the voltage applied to the liquid crystal pixel is the difference between the common voltage and the output voltage from the source driver 6, no voltage is applied in this case. Therefore, when the display panel is normally black, the display color is black.

  In the case of “gradation 64” indicated by data (decimal) “63”, 12 V is output when the polarity is positive, and 0 V is output when the polarity is negative. In this case, the maximum voltage applied to the liquid crystal pixels is 6V, and when the display panel is normally black, the display color is white.

  In the case of dot inversion display, if white is continuously displayed, the output of the source driver 6 is inverted to 12V and 0V for each scanning line due to polarity inversion. When such display is performed, a large amount of current is consumed in the output buffer of the source driver 6 to generate heat. Therefore, when a temperature abnormality is detected, the operation is changed so as to reduce the amplitude of the output of the source driver 6. More specifically, by operating the data fetched by the source driver 6, data (decimal) “56” or more “gradation 57” in which the upper 3 digits of 6-digit data (binary) are all “1”. ”To“ gradation 64 ”are all fixed to data (decimal)“ 56 ”. As a result, the maximum output voltage of the source driver 6 is 11.25V, the minimum is 0.75V, and the amplitude voltage is 12V to 10.50V.

  Thus, heat generation can be suppressed by suppressing the maximum value of the amplitude voltage.

As described above, when the amplitude of the output buffer is suppressed, there is little influence on the display due to the absence of the gradation difference between whites, but the white color becomes dark overall. Therefore, correction for brightening a backlight (not shown) is performed for display correction.
(Example 5: Shorting the reference voltage to lower the output amplitude)
In order to change the amplitude of the output, a switching circuit is provided in the reference voltage generation circuit for creating the gradation voltage. FIG. 12 shows a reference voltage generation circuit.

  As shown in FIG. 12, the reference voltage generation circuit 50 is a ladder resistor circuit in which a plurality of resistors 51 are connected in series, and a switch 52 that is a switching circuit is connected between the resistors 51. . In this reference voltage generation circuit 50, for example, 12V is applied to the reference power supply terminal VA, 6V is applied to the reference power supply terminal VB, and 0V is applied to the reference power supply terminal VC. Further, the voltage 6V between the reference power supply terminal VA and the reference power supply terminal VB is divided by each resistor 51 from “resistor R1” to “resistor R63” to create “gradation 64” from positive “gradation 1”. To do. Similarly, the voltage 6V between the reference power supply terminal VB and the reference power supply terminal VC is divided by the resistors 51 from “resistor R1” to “resistor R63”, and negative “gradation 1” to “gradation 64” are divided. create.

  In the switch 52, normally, the switch terminal A and the switch terminal I are short-circuited, and the voltage of each gradation is output. However, when a temperature abnormality is detected, the switch 52 is configured such that the switch terminal B and the switch terminal I are short-circuited, and the switch terminal B outputs from “gradation 56” to “gradation 64”. Are short-circuited to the switch terminal B of the switch 52 connected to each other. As a result, when a temperature abnormality is detected, the output voltages from “gradation 56” to “gradation 64” are all the same voltage as “gradation 56”.

As described above, by providing the switch 52 in the reference voltage generation circuit 50 shown in FIG. 12, the same effect as in Example 1 can be generated without manipulating the gradation data.
(Example 6: By switching the use of the positive amplifier and the negative amplifier, a voltage with a large amplitude is not output)
FIG. 13A shows an outline of an output circuit 60 as an output buffer of the source driver 6 that performs dot inversion. As shown in FIG. 13A, the output circuit 60 of the source driver 6 is composed of a first operational amplifier and operational amplifiers 61 and 62 as the first operational amplifier.

  In dot inversion, the polarities of adjacent source signal lines SL are opposite to each other. In the case of the output circuit 60 shown in FIG. 13, the positive side of the polarity is set to a voltage from 6 V to 12 V at the output of the DAC (Digital Analog Converter) (positive), while the negative side of the polarity is set to the DAC (negative) output. The voltage is from 0V to 6V.

  A full dynamic range operational amplifier that outputs an output corresponding to the entire input voltage has a large circuit scale. Therefore, in the source driver 6 for dot inversion driving, as shown in FIG. Two operational amplifiers 62 (dynamic range from about 1V to 12V) and negative operational amplifier 62 (dynamic range from 0V to about 11V) are prepared and shared by two outputs.

  In the output circuit 60, when the output terminal TA outputs the positive side, the output terminal TB outputs the negative side. Therefore, the switch SWA is turned on and the switch SWB is turned off by the switch control signal REV. The positive operational amplifier 61 is connected to the output terminal TA, and the negative operational amplifier 62 is connected to the output terminal TB. Conversely, when the output terminal TA outputs the negative side, the switch SWB is turned on and the switch SWA is turned off. In this case, the positive operational amplifier 61 is connected to the output terminal TB, the negative operational amplifier 62 is connected to the output terminal TB, and the polarity is inverted. The positive-side operational amplifier 61 is connected to the positive-side DAC (positive).

  Since the positive-side DAC (positive) outputs a voltage from 6V to 12V, the input of the positive-side operational amplifier 61 only enters from the voltage 6V to the voltage 12V. For this reason, the dynamic range from 1 V to 12 V is sufficient. Further, since the negative DAC (negative) outputs a voltage from 0V to 6V, the input of the negative operational amplifier 62 is input only from the voltage 0V to the voltage 6V. For this reason, a voltage range of 0V to 11V is sufficient for the dynamic range.

  Next, the output circuit 60 for reducing the output amplitude when a temperature abnormality is detected will be described with reference to FIG. FIG. 13B is a circuit diagram showing a circuit for reducing the output amplitude when a temperature abnormality is detected.

  As shown in FIG. 13B, in the output circuit 60 of the present embodiment, in addition to the output circuit 60 shown in FIG. 13A, the positive DAC (positive) and the first DAC as the first DAC circuit. The switches SWC and SWD are connected between the negative DAC (negative) as the DAC circuit 2 and the operational amplifiers 61 and 62, and the switches SWC and SWD are also provided for the switch control signal REV. Yes. The switches SWC and SWD are switched by an operation change output signal TE_IN that detects a temperature abnormality shown in FIG.

  In the output circuit 60 having the above configuration, the switch SWC is normally turned on, the positive operational amplifier 61 is connected to the positive DAC (positive), and the negative operational amplifier 62 is connected to the negative DAC (negative). . Further, the switch control signal REV to the switches SWA and SWB remains the switch control signal REV because the switch SWC is on.

  Next, when a temperature abnormality is detected, the switch SWC is turned off and the switch SWD is turned on. Thus, the positive DAC (positive) is connected to the negative operational amplifier 62, and the negative DAC (negative) is connected to the positive operational amplifier 61. Since the switch SWC is turned off and the switch SWD is turned on via the inverting circuit 63, the switch control signal REV to the switches SWA and SWB becomes an inverted signal of the switch control signal REV. The relationship between the DAC (negative) and the output terminal TA · TB is the same as that in FIG.

  As described above, when the connection is changed, the positive DAC (positive) is output using the negative operational amplifier 62. However, since the dynamic range of the negative operational amplifier 62 is from 0V to about 11V, the output from about 11V to 12V of the positive DAC (positive) is output to the output terminal TA at about 11V.

  Similarly, since the negative DAC (negative) is output using the positive operational amplifier 61, the DAC (negative) voltage from 0V to about 1V is output to the output terminal TA · TB as approximately 1V.

As a result, the output of the source driver 6 can be set to a voltage of about 1 V to about 11 V, and the output amplitude can be set to about 10 V.
(Example 7: Switch the polarity switch to one channel to suppress output)
As shown in FIG. 14, the switches SWA and SWB shown in FIG. 13A can be constituted by a pass transistor 64 in which the sources and drains of the Pch transistor and the Nch transistor are connected to each other.

  The pass transistor 64 becomes conductive when the pass transistor control signal PTC is “H”. Either one of the Pch transistor and the Nch transistor can conduct a signal, but only one transistor cannot pass a voltage corresponding to the threshold value of the transistor. For example, in the case of a Pch transistor, since the gate voltage is GND, a voltage equal to or lower than Vthp (Vthp is a threshold value of the Pch transistor) cannot pass. Similarly, in the case of only the Nch transistor, since the gate voltage is VLS, a voltage higher than VLS−Vthn (Vthn is a threshold value of the Nch transistor) cannot pass. Therefore, as shown in FIG. 14, by using both the Pch transistor and the Nch transistor, it is possible to pass a voltage from 0 V (GND level) to VLS (power supply level).

  Here, as shown in FIGS. 15 and 16 (a), (b), (c), and (d), in the output circuit 60, switches SWA1 and SWB1 that change the connection between the operational amplifiers 61 and 62 and the output terminals TA and TB. -It is preferable to provide SWA2 and SWB2. Here, it is assumed that the switches SWA1 and SWA2 are turned on when the switch control signal REV is “H”, while the switches SWB1 and SWB2 are turned on when the switch control signal REV is “L”.

  When the switch control signal REV is “H”, the switches SWA1 and SWA2 are turned on, and the positive operational amplifier 61 is connected to the output terminal TA, while the negative operational amplifier 62 is connected to the output terminal TB. At this time, when a temperature abnormality is detected, the connection of the switch SW2 shown in FIGS. 16A, 16B, 16C, and 16D is switched from the switch terminal A to the switch terminal B by the operation change output signal TE_IN. In the switch SWA1, since the inverted signal of the switch control signal REV is “L”, the Pch transistor is turned on, but the gate of the Nch transistor is turned to the ground GND and turned off. On the other hand, in the switch SWA2, the Nch transistor is turned on and the Pch transistor is turned off. There is no effect on turning off the switches SWB1 and SWB2.

  The output of the positive operational amplifier 61 is output to the output terminal TA through the switch SWA2. As described above, since only the Nch transistor is ON, the switch SWA2 is not output in the vicinity of 12V from the voltage 6V in the output range to the voltage 12V. Assuming that the threshold value Vthn is 1.0V, the output range changes from the voltage 6V to the voltage 11V. On the other hand, the negative-side operational amplifier 62 is output to the output terminal TB through the switch SWA1. Since the switch SWA1 is ON only for the Pch transistor, the voltage up to the threshold value Vthp is not output. When the threshold value Vthp is 1.0V, the output voltage is changed from 1V to 6V.

  The same applies when the switch control signal REV is “L” and the switches SWB1 and SWB2 are turned on.

As described above, by changing the configuration of the switch for switching the output, the output amplitude can be changed from the voltage 1V to the voltage 11V, and the output amplitude can be set to about 10V.
(Example 8: Reduce the power supply voltage of the operational amplifier)
If there is no problem even if the power supply of the operational amplifiers 61 and 62 is lower than the input voltage, the power supply voltage of the operational amplifiers 61 and 62 may be lowered when a temperature abnormality is detected. For example, the input voltage is changed from 0V to 12V. On the other hand, the power supply voltage is changed from 1V to 11V. As a result, the output amplitude can be changed from 1V to 11V, and the output amplitude can be reduced to about 10V.
(Example 9: Decreasing the amplitude by reducing the slew rate)
In the source driver 6, the output voltage changes every 1H (one horizontal period) of the liquid crystal display device 1. Therefore, the slew rate is set so that the target voltage can be output within 1H. When the slew rate is small, the target voltage can be reached within 1H when the voltage change is small, but when the voltage change is large, the target voltage cannot be reached within 1H.

  Therefore, when the drive voltage of the source driver 6 is 0V to 12V, the slew rate is set so that it can be changed by 12V or more at 1H, but this slew rate is adjusted so that it can only be changed by about 11V, for example.

  As a result, when the output amplitude is large (11 V or more), the amplitude is limited, and as a result, the output amplitude can be reduced.

As described above, when the amplitude of the output circuit 60 is suppressed, there is little influence on the display due to the absence of the gradation difference between whites, but the white color becomes dark overall. Therefore, correction for brightening the backlight may be performed for display correction.
(Example 10: Decreasing the slew rate by reducing the bias current)
Operational amplifiers 61 and 62 are used for the output circuit 60 of the source driver 6. The operational amplifiers 61 and 62 operate using a bias current (constant current), and the slew rate is determined based on the bias current. That is, when the bias current is reduced, the driving capability of the operational amplifiers 61 and 62 is reduced and the slew rate is also reduced. This can be used to adjust the slew rate.

  FIG. 17 is a diagram showing an example of an operational amplifier circuit 65 that constitutes the operational amplifiers 61 and 62. In the operational amplifier circuit 65 shown in FIG. 17, the differential amplification stage is constituted by the constant currents Ia and Ib, the transistors QP1 and QP2 constituting the differential input, and the transistors QP1 and QP2 and the transistors QN1 and QN2 constituting the current mirror. Has been.

  In the above operational amplifier circuit 65, the switch SW20 is normally turned on, and the bias current I1 of the differential amplification stage is Ia + Ib. The output VO of the differential amplifier stage is output from the output terminal Vout by an amplifier stage composed of a constant current I2, an output transistor QN3, and a feedback capacitor Cc.

  At this time, the slew rate of the operational amplifier circuit 65 is approximated to ΔVout / Δt = I1 / Cc if the feedback capacitance Cc is sufficiently large and I1 << I2.

When the switch SW20 is turned off when the device is at a high temperature, the bias current I1 becomes Ia, and the slew rate can be reduced to Ia / I1.
(Example 11: Decreasing the slew rate by increasing the resistance value of the output switch)
As shown in FIG. 15, the source driver 6 that performs dot inversion includes an operational amplifier 61 as a third operational amplifier that is a positive polarity amplifier, and an operational amplifier 62 as a third operational amplifier that is a negative polarity amplifier. Switches SWA1, SWB1, SWA2, and SWB2 for switching output terminals TA and TB of the operational amplifiers 61 and 62 are provided. The switches SWA1, SWB1, SWA2, and SWB2 are composed of transistors as shown in FIGS. 16 (a), (b), (c), and (d). When the resistance value of this transistor is increased, the slew rate can be reduced. This can be used to adjust the slew rate.
(Example 12: Decreasing the slew rate by increasing the impedance of the output buffer)
The transistor QN3 of the operational amplifier circuit 65 as an output buffer constituting the operational amplifier 61 (or the operational amplifier 62) shown in FIG. 17 operates as an output impedance. Therefore, if W (channel width) / L (channel width), which is the transistor size, is reduced, the impedance increases and the charging time of the output load is delayed. This reduces the slew rate of the operational amplifier circuit. For example, if the transistor QN3 shown in FIG. 17 is composed of two transistors having the same channel width L and is operated at one side at a high temperature, the channel width W of the transistor can be reduced and the slew rate can be reduced.

This can be used to adjust the slew rate.
(Example 13: Decreasing the slew rate by increasing the protective resistance)
An integrated circuit such as a driver is provided with a protection circuit for preventing current entry at a terminal in order to prevent the inside of the integrated circuit from being destroyed by external electrical noise. Further, a part of the protection circuit is provided with a protection resistor between the terminal and the internal circuit. Normally, a small protective resistor that does not affect the output slew rate is used. However, if this protective resistor is increased, the slew rate is decreased.

  By utilizing this fact, the slew rate can be adjusted.

In addition, as a protective resistor, a plurality of protective resistors having different resistance values are prepared and can be switched at any time, and a single protective resistor composed of a variable resistor is prepared. It is possible to switch.
(Example 14: Decreasing the slew rate by increasing the power supply resistance)
When a resistor is inserted in the power supply of the output transistor of the operational amplifier circuit 65 constituting the operational amplifier 61 (or operational amplifier 62), the current is limited and the slew rate is lowered. This can be used to adjust the slew rate.

  In the case of the operational amplifier circuit 65 shown in FIG. 17, it is preferable to insert a resistor between the transistor QN3 and the ground GND.

  As described above, the liquid crystal display device 1 according to the present embodiment includes a liquid crystal panel 2 as a display panel, a plurality of source drivers 6 and a plurality of gate drivers 4 for driving the liquid crystal panel 2, a source driver 6, And a controller 7 as a display control device for controlling the display drive of the gate driver 4, and a data signal is supplied from each source driver 6 to a source signal line SL as a data signal line of the liquid crystal panel 2 through each output buffer. To do. Each source driver 6 includes a temperature detection circuit 20 as a temperature abnormality detection means for detecting a temperature abnormality when the temperature of the chip of the source driver 6 exceeds a set value, and the temperature detection circuit 20 detects a temperature abnormality. When detected, a start pulse signal wiring 7a is provided as temperature abnormality notification means for notifying the controller 7 that a temperature abnormality has been detected, and the controller 7 has received a notification from the temperature detection circuit 20. Sometimes, a temperature abnormality eliminating means for controlling each source driver 6 and each gate driver 4 so as to eliminate the temperature abnormality is provided.

  In the driving method of the liquid crystal display device 1 according to the present embodiment, the temperature abnormality detection step of detecting the temperature abnormality that the temperature of the chip of the source driver 6 has exceeded the set value and the temperature abnormality of the source driver 6 are detected. In addition, a temperature abnormality notification step for notifying the controller 7 that a temperature abnormality of the source driver 6 has been detected, and each time so as to eliminate the temperature abnormality when the controller 7 receives a notification of the temperature abnormality of the source driver 6. And a temperature abnormality elimination step for controlling the source driver 6 and each gate driver 4.

  That is, the source driver 6 drives the liquid crystal display device 1 by supplying data signals to the plurality of source signal lines SL via the respective output buffers. Such a source driver 6 has a problem that the amount of heat generated in each output buffer of the source driver 6 is large and a temperature abnormality due to the amount of heat generated cannot be suppressed to a target value or less. .

  In this regard, in the liquid crystal display device 1 of the present embodiment, when the temperature detection circuit 20 detects a temperature abnormality, the controller 7 is notified by the start pulse signal wiring 7a, and the temperature abnormality eliminating means of the controller 7 has the temperature abnormality. Since the display operation for eliminating the above is performed, it is possible to suppress the temperature abnormality to a target value or less.

  Therefore, it is possible to provide the liquid crystal display device 1 that can suppress the temperature abnormality mainly occurring in the output buffer below the target value, and the driving method of the liquid crystal display device 1. The target value can be set as appropriate.

  Further, in the liquid crystal display device 1 of the present embodiment, the temperature abnormality eliminating means controls each source driver 6 and each gate driver 4 so as to reduce the display rewriting speed of the liquid crystal panel 2 to eliminate the temperature abnormality. Is possible.

  Further, in the driving method of the liquid crystal display device 1 of the present embodiment, in the temperature abnormality eliminating step, the temperature abnormality is corrected by controlling the source drivers 6 and the gate drivers 4 so as to reduce the display rewriting speed of the liquid crystal panel 2. It can be resolved.

  That is, by reducing the display rewriting speed of the liquid crystal panel 2, the operation speed of the source driver 6 is lowered, and the switching cycle of the liquid crystal drive signal is lowered. As a result, heat generation during switching of the liquid crystal drive signal in the output buffer of the source driver 6 is reduced.

  Therefore, the liquid crystal display device 1 that can suppress the temperature abnormality mainly generated in the output buffer below the target value by the temperature abnormality eliminating means slowing down the display rewriting speed of the liquid crystal panel 2 and the driving method of the liquid crystal display device 1 Can be specifically provided.

  Further, in the liquid crystal display device 1 of the present embodiment, the temperature abnormality elimination means performs two display scans on the liquid crystal panel 2 with the same writing contents in the odd display scan lines and the even display scan lines. Each source driver 6 and each gate driver 4 are controlled so as to rewrite the pixels for each line, thereby eliminating the temperature abnormality.

  Further, in the driving method of the liquid crystal display device 1 of the present embodiment, in the temperature abnormality elimination step, two consecutive writings with the same writing contents of the odd display scan lines and the even display scan lines are made to the liquid crystal panel 2. Each source driver 6 and each gate driver 4 are controlled so as to rewrite the pixels for each display scanning line, thereby eliminating the temperature abnormality.

  That is, in the output buffer of the source driver 6, heat generation at the time of switching the liquid crystal drive signal is reduced by reducing the rewrite frequency.

  Therefore, in the present embodiment, the temperature abnormality eliminating means rewrites the pixel for every two consecutive display scanning lines with the same writing contents of the odd display scanning lines and the even display scanning lines. Each source driver 6 and each gate driver 4 are controlled to perform the above.

  Thereby, in the output buffer of the source driver 6, the rewrite frequency is reduced to half. Therefore, it is possible to specifically provide the liquid crystal display device 1 and a driving method of the liquid crystal display device 1 that can suppress temperature abnormality mainly occurring in the output buffer below the target value.

  Further, in the liquid crystal display device 1 of the present embodiment, the temperature abnormality eliminating means writes in the odd display scan lines (or even display scan lines) in the first frame, and even display scan lines in the next second frame. Each source driver 6 and each gate driver 4 are controlled so as to perform writing so as to perform writing to the odd display scanning line when writing is performed to the even display scanning line in the odd frame.

  Further, in the driving method of the liquid crystal display device 1 of the present embodiment, in the temperature abnormality elimination step, writing is performed on the odd display scanning lines (or even display scanning lines) in the first frame, and even in the next second frame. The source driver and each gate driver are controlled so as to perform writing on the display scan line (or odd display scan line when writing is performed on the even display scan line in the odd frame), thereby eliminating the temperature abnormality.

  In the above-described method of rewriting a pixel for every two consecutive display scan lines with the same writing contents of the odd display scan lines and even display scan lines, for example, white is instantaneously displayed at a place where black is displayed. On the other hand, black may be displayed for a moment in a place where white is displayed.

  Therefore, in order to avoid this problem, in this embodiment, a partial image is expressed by displaying the odd display scan lines and the even display scan lines separately in the first frame and the second frame. It can be prevented from being lost.

  In the present embodiment, each source driver 6 notifies the controller 7 when the temperature detection circuit 20 detects a temperature abnormality. However, the present invention is not limited to this. It is also possible to only inform the source driver 6.

  In this case, as shown in FIG. 18, each source driver 6 measures its own chip temperature in the temperature detection circuit 20, and the temperature abnormality avoidance transmission circuit 30 sets the temperature when the temperature reaches a preset temperature or more. In addition to changing its own operation so as to lower the temperature, it is possible to output a signal notifying that the temperature has exceeded the set value and notifying other source drivers 6. In this case, the source driver 6 that has received this signal changes its own operation to the operation when the temperature measured by its own temperature detection circuit 20 is equal to or higher than the setting even if the temperature is not higher than the setting. The reason for this is to make the display constant by making the operations of all the source drivers 6 the same.

  As described above, when the temperature of one source driver 6 becomes equal to or higher than the set value, as a method for notifying other source drivers 6, for example, by providing a dedicated terminal, it is possible to share temperature abnormality information.

  Specifically, as shown in FIG. 18, each source driver 6 is provided with a dedicated terminal TE. The dedicated terminals TE of the source drivers 6 are connected to each other by a dedicated line 34, and the connected dedicated line 34 is grounded via a pull-down resistor 35 such as a pull-down transistor. Each source driver 6 includes a temperature abnormality avoidance transmission circuit 30 as shown in FIG. 18, and this temperature abnormality avoidance transmission circuit 30 includes a dedicated terminal TE, a Pch transistor 31, an inverter circuit 32, and a buffer circuit. 33.

  The temperature abnormality input signal TE_OUT of the inverter circuit 32 is a signal from the temperature detection circuit 20 and is normally “L”, and becomes “H” when a temperature abnormality is detected.

  Since the gate of the Pch transistor 31 is normally “H”, the Pch transistor 31 is normally off. Therefore, the dedicated terminal TE is set to “L” by the external pull-down resistor 35. Here, when the temperature abnormality input signal TE_OUT of the inverter circuit 32 becomes “H”, the gate of the Pch transistor 31 becomes “L”, and the Pch transistor 31 is turned on. Since the on-resistance value of the Pch transistor 31 is sufficiently smaller than the resistance value of the pull-down resistor 35, the dedicated terminals TE of all the source drivers 6 are set to “H”. When the dedicated terminal TE becomes “H”, the operation change output signal TE_IN of the buffer circuit 33 becomes “H”. The operation change output signal TE_IN is a signal indicating a change in operation in response to a temperature abnormality signal.

  As a result of the above operation, the temperature abnormality detected by one source driver 6 is transmitted to all the source drivers 6, and the operations of all the source drivers 6 are changed.

  Thereafter, when the temperature detection circuits 20 of all the source drivers 6 do not detect the set temperature or more, the temperature abnormality input signal TE_OUT of the inverter circuit 32 returns to “L”, so that the Pch transistor 31 is turned off and the dedicated terminal TE is Becomes “L”. Therefore, the operation change output signal TE_IN of the buffer circuit 33 also becomes “L”, the operation change of the source driver 6 is canceled, and the normal operation is restored.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIG. 19 and FIG. Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted.

  The present embodiment exemplifies another temperature abnormality notification circuit, and the point that the temperature abnormality is transmitted using the reference power source (V0) input to the reference voltage generation circuit that creates the gradation voltage is described above. This is different from the first embodiment.

  First, FIG. 19 shows a conceptual diagram of a liquid crystal driving semiconductor integrated circuit 70 constituting the source driver 6 capable of outputting m gray scale output voltages from n liquid crystal driving signal output terminals.

  As shown in FIG. 19, a liquid crystal driving semiconductor integrated circuit 70 constituting the source driver 6 includes a clock input terminal 71, a gradation data input terminal 72 having a plurality of signal input terminals, a LOAD signal input terminal 73, A reference power supply V0 terminal 74, a reference power supply V1 terminal 75, a reference power supply V2 terminal 76, a reference power supply V3 terminal 77, and a reference power supply V4 terminal 78 are provided. Further, n liquid crystal drive signal output terminals 79-1 to 79-n (hereinafter, the liquid crystal drive signal output terminals are referred to as “signal output terminals”. Furthermore, the liquid crystal drive signal output terminals 79-1 to 79- When n is generically referred to, it is referred to as “signal output terminal 79”). In addition, the liquid crystal driving semiconductor integrated circuit 70 includes a reference voltage generating circuit 81, a pointer shift register circuit 82, a latch circuit 83, a hold circuit 84, and a D / A converter (Digital Analog Converter: hereinafter referred to as DAC) circuit. 85 and an output buffer 86.

  The pointer shift register circuit 82 includes n-stage shift registers 82-1 to 82-n. The latch circuit 83 includes n latch circuits 83-1 to 83-n, the hold circuit 84 includes n hold circuits 84-1 to 84-n, and the DAC circuit 85 includes n The DAC circuit 85-1 to 85-n. In addition, the output buffer 86 is composed of output buffers 86-1 to 86-n composed of operational amplifiers.

  The pointer shift register circuit 82 selects one of the latch circuits 83-1 to 83-n according to the clock input signal input from the clock input terminal 71. Then, the gradation output data input from the gradation data input terminal 72 is selected and stored in the latch circuit 83.

  The latch circuit selection signal output from the pointer shift register circuit 82 is transferred from the first latch circuit 83-1 to the nth latch circuit 83-n by the clock input signal input from the clock input terminal 71. Select sequentially. Therefore, when n clocks are input, data can be stored in all the latch circuits 83-1 to 83-n. The latch circuits 83-1 to 83-n can store different values of data. The data stored in the latch circuits 83-1 to 83-n is transferred to the corresponding n number of hold circuits 84-1 to 84-n by the data LOAD signal, and the data is stored in the DAC circuits 85-1 to 85-n. Digital input data.

  The DAC circuits 85-1 to 85-n selectively output m types of gradation voltage values based on the input digital data. The m kinds of gradation voltage values are created by the voltage input from the reference power supply V0 terminal 74 to the reference power supply V4 terminal 78 and the reference voltage generation circuit 81.

  In the output buffer 86, the m kinds of gradation voltage values are impedance-converted and output as gradation voltages from the signal output terminals 79-1 to 79-n as liquid crystal panel driving signals.

  Further, the power supply voltage of the output buffer 86 is VLS, and the relationship between the power supply voltage VLS and the voltage input from the reference power supply V0 terminal 74 to the reference power supply V4 terminal 78 is VLS> V0> V1> V2> V3> V4. To do.

  The reference voltage V0 to the reference voltage V4 described above are connected by a common signal line between the plurality of source drivers 6 mounted.

  In this embodiment, in addition to the liquid crystal driving semiconductor integrated circuit 70 constituting the source driver 6, a reference voltage change detection circuit 90 shown in FIGS. 20A is a circuit diagram showing a configuration of the reference voltage change detection circuit 90, and FIG. 20B is a circuit diagram showing a circuit for changing the reference voltage input to the reference voltage change detection circuit 90. FIG. 20C is a circuit diagram showing a circuit for creating a reference voltage Vref input to one side of the comparator 91 of the reference voltage change detection circuit 90.

  First, in the present embodiment, as shown in FIG. 20B, an Nch transistor 92 and a resistor 93 are connected in series to the reference power supply V0 terminal 74. A function of changing the reference voltage V0 inputted to the reference power supply V0 terminal 74 of the reference voltage generating circuit 81 for generating the gradation voltage to a voltage different from the voltage used for display when the driver 6 detects a temperature abnormality. Have.

  The temperature abnormality input signal TE_OUT input to the gate of the Nch transistor 92 is a signal that becomes “H” when a temperature abnormality occurs. The temperature abnormality input signal TE_OUT becomes “H” and the Nch transistor 92 is turned on. Then, the reference voltage V0 of the reference power supply V0 terminal 74 is set to be lower than the reference voltage Vref. That is, the reference voltage V0 of the reference power supply V0 terminal 74 is changed to a voltage lower than the voltage used for display.

  Then, the reference voltage V0 changed to a voltage lower than the voltage used for the display is input as one input signal of the comparator 91 constituting the reference voltage change detection circuit 90 shown in FIG. A reference voltage Vref is input to the other input signal of the comparator 91. This reference voltage Vref is a resistor 94 provided between the power supply voltage VLS and the ground GND as shown in FIG. Created in. That is, the resistor 94 divides between the power supply voltage VLS and the ground GND, and creates the reference voltage Vref having a relationship of Vref> V0.

  In the reference voltage change detection circuit 90, as shown in FIG. 20A, the comparator 91 compares both the reference voltage Vref and the reference voltage V0 and switches to the operation when a temperature abnormality occurs. A change output signal TE_IN is output.

  Usually, since the temperature abnormal input signal TE_OUT is “L”, the Nch transistor 92 is off, and V0> Vref, so that the operation change output signal TE_IN which is the output of the comparator 91 is “L”. For this reason, the operation of the source driver 6 is a normal operation.

  Next, when a temperature abnormality occurs in the source driver 6, the temperature abnormality input signal TE_OUT becomes “H”, the Nch transistor 92 is turned on, and V0 <Vref. For this reason, the operation change output signal TE_IN that is the output of the comparator 91 becomes “H”, and the operation of the source driver 6 is switched to the operation when the temperature abnormality occurs.

  Here, the reference voltage V0 input to the reference power supply V0 terminal 74 is common to all the source drivers 6. Therefore, when one source driver 6 detects a temperature abnormality, a voltage drop of the reference voltage V0 occurs in all the source drivers 6. For this reason, a temperature abnormality is detected for all the source drivers 6 by setting the resistance value so that the reference voltage V0 of all the source drivers 6 becomes smaller than the reference voltage Vref by the Nch transistor 92 and the resistor 93. It is possible to switch to the operation at the time.

  When the temperature abnormality is not detected, the temperature abnormality input signal TE_OUT returns to “L”, so that the operation of the source driver 6 returns to the normal operation.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.

  The present invention can be applied to a source driver and a display device that drive a display device by supplying data signals to a plurality of data signal lines through output buffers. Specifically, as a display device, for example, it can be used for an active matrix liquid crystal display device, and an electrophoretic display, a twist ball display, a reflective display using a fine prism film, a digital mirror device, etc. In addition to displays using light modulation elements, organic EL light-emitting elements, inorganic EL light-emitting elements, displays using light-emitting luminance variable elements such as LEDs (Light Emitting Diodes), field emission displays (FED) It can also be used for plasma displays.

1 Liquid crystal display device (display device)
2 Liquid crystal panel (display panel)
3 Gate Driver 4 Gate Driver 5 Source Driver 6 Source Driver 7 Controller (Display Control Device)
7a Start pulse signal wiring (temperature abnormality elimination means, temperature abnormality notification means)
7b Gate start pulse signal wiring (temperature abnormality elimination means)
8 Counter electrode 9 Liquid crystal drive power supply 10 Liquid crystal display element 11 Pixel capacity 12 Pixel electrode 13 TFT
20 Temperature detection circuit (temperature abnormality detection means)
21 Comparator 30 Temperature Abnormality Avoidance Transmission Circuit 31 Pch Transistor 32 Inverter Circuit 33 Buffer Circuit 34 Dedicated Line 35 Pull-down Resistor 40 Temperature Detection Test Circuit (Temperature Abnormality Detection Means)
41/42 Inverter 43 Resistor 44/45 Switch 46 Normal circuit 50 Reference voltage generating circuit 51 Resistor 52 Switch 60 Output circuit (output buffer)
61 operational amplifier 62 operational amplifier 64 pass transistor 65 operational amplifier circuit (output buffer)
70 Liquid Crystal Drive Semiconductor Integrated Circuit 71 Clock Input Terminal 72 Gradation Data Input Terminal 73 LOAD Signal Input Terminals 74 to 78 Reference Power Supply V0 Terminal to Reference Power Supply V4 Terminal 79 Liquid Crystal Drive Signal Output Terminal 81 Reference Voltage Generation Circuit 82 Pointer Shift Register circuit 83 Latch circuit 84 Hold circuit 85 D / A converter circuit 86 Output buffer 90 Reference voltage change detection circuit 91 Comparator 92 Nch transistor 93 Resistor 94 Resistor

A / B switch terminal Cc feedback capacitor D4 diode GL scanning signal line GND ground GSP gate start pulse signal ND node ND_A node I switch terminal Ia / Ib constant current QP1, QP2 transistor QN1, QN2 transistor QN3 transistor R3 / R4 resistance REV switch control Signal SCLK Source clock signal SL Source signal line (data signal line)
SSP start pulse signal SSPOn start pulse signal SSPin input terminal SSPout output terminal SW20 switch SWA / SWB switch SWA1 / SWB1 switch SWA2 / SWB2 switch SWC / SWD switch TA / TB output terminal Tb1 / Tb2 time TE dedicated terminal TE_OUT temperature abnormal input signal TE_IN Operation change output signal VA / VB Reference power supply terminal Vcc Power supply voltage node VLS Power supply voltage VREF Reference voltage Vthp Threshold Vthn Threshold Vout Output terminal VLS Power supply voltage

Claims (8)

A display panel, a plurality of source drivers and a plurality of gate drivers for driving the display panel, and a display control device for controlling display driving of the source drivers and the gate drivers, each output from the source driver In a display device for supplying a data signal to a data signal line of a display panel via a buffer,
Each of the source drivers has a temperature abnormality detecting means for detecting a temperature abnormality that the temperature of the chip of the source driver has exceeded a set value, and a temperature abnormality when the temperature abnormality detecting means detects a temperature abnormality. A temperature abnormality notifying means for notifying the display control device of the detection is provided;
The display control device is provided with temperature abnormality eliminating means for controlling each source driver and each gate driver so as to eliminate the temperature abnormality when receiving a notification from the temperature abnormality notifying means. Characteristic display device.   2. The display device according to claim 1, wherein the temperature abnormality eliminating means controls the source driver and each gate driver so as to reduce a display rewriting speed of the display panel to eliminate the temperature abnormality.   The temperature abnormality eliminating means rewrites the pixels every two consecutive display scanning lines with the same writing contents of the odd display scanning lines and the even display scanning lines. 3. The display device according to claim 1, wherein the temperature abnormality is resolved by controlling the source driver and each gate driver.   In the first frame, the temperature abnormality eliminating means writes to the odd display scanning line (or even display scanning line), and in the next second frame writes to the even display scanning line (odd frame even writing scan line). 4. The display device according to claim 1, wherein the temperature abnormality is resolved by controlling each of the source drivers and each of the gate drivers so that writing is performed on an odd-numbered display scanning line. A display panel, a plurality of source drivers and a plurality of gate drivers for driving the display panel, and a display control device for controlling display driving of the source drivers and the gate drivers, each output from the source driver In a driving method of a display device for supplying a data signal to a data signal line of a display panel via a buffer,
A temperature abnormality detection step for detecting a temperature abnormality that the temperature of the chip of the source driver is higher than a setting;
A temperature abnormality notification step of notifying the display control device that a temperature abnormality of the source driver is detected when a temperature abnormality of the source driver is detected;
The display control device includes a temperature abnormality elimination step of controlling each source driver and each gate driver so as to eliminate the temperature abnormality when the notification of the temperature abnormality of the source driver is received. A driving method of a display device.   6. The display device drive according to claim 5, wherein in the temperature abnormality elimination step, the temperature abnormality is eliminated by controlling each of the source driver and each gate driver so as to slow down a display rewriting speed of the display panel. Method.   In the temperature abnormality eliminating step, each of the display panels is rewritten so that the pixels are rewritten every two consecutive display scan lines with the same writing contents of the odd display scan lines and the even display scan lines. 7. The method of driving a display device according to claim 5, wherein the temperature abnormality is resolved by controlling the source driver and each gate driver.   In the temperature abnormality eliminating step, writing is performed on the odd display scanning lines (or even display scanning lines) in the first frame, and writing is performed on the even display scanning lines (odd display scanning lines in the odd frames) in the next second frame. 8. The display device drive according to claim 5, wherein the source driver and the gate driver are controlled so as to eliminate the temperature abnormality so as to perform writing to an odd display scanning line). Method.

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