WO2023176670A1

WO2023176670A1 - Voltage sensing circuit, display driver, display device, and comparator

Info

Publication number: WO2023176670A1
Application number: PCT/JP2023/008992
Authority: WO
Inventors: 弘土
Original assignee: ラピステクノロジー株式会社
Priority date: 2022-03-17
Filing date: 2023-03-09
Publication date: 2023-09-21

Abstract

In the present invention, first, a differential current pair corresponding to a difference between a reference voltage and a sensed voltage is generated. Next, the differential current pair is converted into a first current based on a first voltage and a second current based on a second voltage, and voltage, which is generated at a first output end by extracting the second current from the first output end while supplying the first current to the first output end, is outputted as a first signal. The differential current pair is further converted into a third current based on the first voltage and a fourth current based on the second voltage, and voltage, which is generated at a second output end by extracting the fourth current from the second output end while supplying the third current to the second output end, is outputted as a second signal. Then, whether the sensed voltage has changed from a reference state or not is determined on the basis of the first and second signals. Note that, in the reference state, the first current is set to be higher than the second current, and the third current is set to be lower than the fourth current.

Description

Voltage detection circuit, display driver, display device and comparator

The present invention relates to a voltage detection circuit, a display driver including the voltage detection circuit, a display device, and a comparator.

Currently, active matrix drive type display devices that use liquid crystal or organic EL for the display panel are generally known as main display devices.

The display panel has a plurality of data lines each extending in the vertical direction of a two-dimensional screen and a plurality of gate lines each extending in the horizontal direction of the two-dimensional screen on an insulating transparent substrate such as glass or plastic. are arranged in an intersecting manner. Further, a pixel portion connected to the data line and the gate line is formed at each intersection of the plurality of data lines and the plurality of gate lines. Each pixel section is equipped with a TFT (thin film transistor) switch and a pixel electrode, and when the TFT switch is turned on by a gate signal supplied to the gate line, the gradation data signal supplied to the data line is sent to the pixel electrode via the TFT. Supplied.

A display panel of a liquid crystal display device has a structure in which a liquid crystal device is sealed between a semiconductor substrate on which a thin film semiconductor circuit is formed and a counter substrate on which a counter electrode is formed over the entire surface. A liquid crystal display device performs gradation display by controlling the transmittance of a backlight provided on the back surface of a display panel using a voltage applied to the liquid crystal. Color display is achieved by assigning three primary colors of RGB to each pixel and synthesizing the three primary colors using a combination of an LED backlight and a color filter or color conversion layer.

On the other hand, the display panel of an organic EL display device is composed of a semiconductor substrate on which a thin film semiconductor circuit and an organic EL element are formed in each pixel section, and in each pixel section, a grayscale data signal supplied to a pixel electrode is converted into a current. A pixel circuit for supplying the organic EL element to the organic EL element is formed. In an organic EL display device, gradation display is performed by controlling the emission intensity of the organic EL element by a current supplied to the organic EL element of each pixel portion. Color display is realized by emitting light from an organic EL element in three primary colors of RGB assigned to each pixel, or by color synthesis of the three primary colors by combining the light emission from a monochromatic organic EL element and a color filter.

In addition to the display panel described above, such a display device includes a gate driver that supplies a horizontal scanning signal to the gate line to sequentially turn on the TFT switch for each pixel row, and an analog voltage that corresponds to the brightness level of each pixel. A data driver is included that supplies a grayscale signal having a value to a data line in data pulses for one horizontal scanning period.

FIG. 1 is a block diagram schematically showing the configuration of an active matrix display device.

The display device shown in FIG. 1 has gate lines GL1 to GLr wired horizontally on an insulating substrate, data lines DL1 to DLm wired vertically, and a matrix at the intersection of each gate line and data line. a display panel 150 including a pixel section 154 arranged in a pixel section 154, a gate driver 110 that drives each gate line, a data driver 120 that drives each data line, and a controller 130 that adjusts the output timing of the gate driver 110 and the data driver 120. Consists of. Note that the description of the TFT switch, pixel electrode, display device, etc. included in the pixel portion 154 is omitted.

The gate driver 110 is supplied with the signal group GS from the controller 130, and outputs a scanning signal to be supplied to each gate line based on the signal group GS.

The data driver 120 is supplied with a signal group VDS, which is a collection of CLK, control signals, video data signals, etc., from the controller 130, and outputs gradation signals to be supplied to each data line based on the signal group VDS.

Incidentally, in recent years, it has become common for the gate driver 110 to have a thin film transistor circuit configuration that is integrally formed with a pixel portion and wiring in the display panel 150. Further, the data driver 120 is usually formed of a silicon LSI, and is mounted on the end of the display panel 150 using COG (Chip On Glass) or COF (Chip On Film). When the data driver 120 is composed of a plurality of individual ICs, a signal group VDS corresponding to the data line that each IC is responsible for driving is supplied from the controller 130 to each data driver IC. Note that when the data driver 120 is a single IC or a small number of ICs, the controller 130 may be built into the data driver 120. In that case, the signal group supplied to the controller 130 from the outside is directly transmitted to the data driver 120. supplied to

Furthermore, in recent years, display panels have become increasingly high-resolution, and as pixel pitches have been reduced, wiring widths and wiring spacing have also been reduced. This also increases the risk of failure of the display panel.

Therefore, there is an increasing demand for a display panel equipped with a gate driver, data driver, and controller to be equipped with a function to detect abnormalities and failures. In particular, in-vehicle display panels are required to have a function that quickly detects abnormalities in the display panel in order to avoid display sticking, that is, freezing of images.

Therefore, a configuration has been proposed in which a data driver has a built-in circuit that detects and determines defects and defective states of the display panel without requiring an external inspection device (see, for example, FIGS. 1 and 4 of Patent Document 1). ).

In Patent Document 1, a switching circuit between a normal operation mode and a test mode is provided for each output. The switching circuit includes a determination circuit that compares the signal voltage supplied to the data line with a preset reference voltage in the test mode, and determines whether it is normal or abnormal based on the comparison result.

Specifically, the determination circuit shown in FIG. 4 of Patent Document 1 has two reference voltages (1/4·VCC, 3/4·VCC) with respect to the output power supply voltage VCC, and an output voltage monitor line. It includes two comparators (COMP1, COMP2) that compare the signal voltages supplied via the two comparators. The determination circuit synchronizes the results of comparing the signal voltage and two reference voltages by two comparators with the reference clock CK by the serial I/O 74 as a determination signal indicating whether the signal voltage is normal or abnormal. Output. That is, this determination circuit uses two reference voltages to determine whether the signal voltage is normal or abnormal, depending on which voltage level range the signal voltage is in with respect to the two reference voltages.

Japanese Patent Application Publication No. 2000-275610

In the determination circuit described in Patent Document 1, at least two comparators (COMP1, COMP2) and the input section of the serial I/O 74 process a relatively high signal voltage that can drive a display panel, so Consists of voltage circuit. Further, in accordance with this, a high voltage circuit is also required for a circuit that generates a reference clock that synchronizes the outputs of the two comparators.

Therefore, in realizing the determination circuit, the high voltage circuit occupies a large area, resulting in an increase in cost due to an increase in chip size.

In particular, the automotive semiconductor device (including a data driver for display) described in Patent Document 1 requires a large number of abnormality detection circuits that detect whether there are abnormalities in various signals. Therefore, if a large number of detection circuits for detecting an abnormality in a high voltage signal are each composed of a high voltage circuit, the chip size of the semiconductor device will increase, resulting in an increase in cost.

Furthermore, a common comparator used in the determination circuit has a problem in that highly accurate voltage detection is difficult due to variations in threshold voltage of transistors forming the circuit.

SUMMARY OF THE INVENTION Therefore, the present invention provides a voltage detection circuit that detects whether the voltage of a detection target has changed from a reference state with high speed response and high accuracy while suppressing the scale of the device, a display driver including the voltage detection circuit, and a display device. , and a comparator.

The voltage detection circuit according to the present invention is a voltage detection circuit that detects that the detection voltage of a detection target has changed from a reference state having a voltage value within a predetermined voltage range including a reference voltage, a differential stage that outputs a differential current pair corresponding to a difference between the detection voltage and the first and second voltages; and a coupling circuit that outputs first and second signals from the first and second coupling points based on first to fourth currents generated by performing current mirror conversion on the second voltage, respectively; The coupling circuit has one of a source type (current source type) and a sink type (current sink type) based on the first voltage. 3, and the other of the differential current pair is converted into the second and fourth currents that are the other of a source type and a sink type based on the second voltage, and A voltage generated at the first connection point where the second current is coupled is generated as the first signal, and the second current is coupled with the third current and the fourth current. generates a voltage generated at a coupling point of the coupling circuit as the second signal, and in the coupling circuit, in the reference state, the first current is larger than the second current and the fourth current is larger than the third current. The current is set to be larger than the current.

The display driver according to the present invention generates a gradation signal corresponding to the brightness level of each pixel based on a video data signal and applies it to each of the first to kth (k is an integer of 2 or more) data lines of the display panel. A display driver that supplies first to kth gradation signals, and a display mode for displaying an image on the display panel, and whether or not the gradation signals supplied to the first to kth data lines are normal. and a setting section configured to set a voltage value of a gray scale signal corresponding to a predetermined brightness level as a reference voltage; a selection unit that selects one of the grayscale signals and obtains the voltage value of the selected one of the grayscale signals as a detection voltage; and a reference in which the detection voltage has a voltage value within a predetermined voltage range that includes the reference voltage. a voltage detection circuit that detects whether the voltage has changed from a state, and the voltage detection circuit includes a differential stage that outputs a differential current pair corresponding to a difference between the reference voltage and the detection voltage; first to fourth circuits having first and second voltages and first and second coupling points, and generating current mirror transforms of the differential current pair with respect to the first and second voltages, respectively; a coupling circuit that outputs first and second signals from the first and second coupling points based on the current of the current, and a coupling circuit that outputs first and second signals from the first and second coupling points; a determination circuit that outputs a determination signal indicating the determination result, and the coupling circuit connects one of the differential current pairs to a source type (current source) based on the first voltage converting the first and third currents into one of a type) and a sink type (current sink type), and converting the other of the differential current pair into the other of a source type and a sink type based on the second voltage. converting the second and fourth currents into the second and fourth currents, and generating a voltage generated at the first coupling point where the first current and the second current are coupled as the first signal; , a voltage generated at the second coupling point where the third current and the fourth current are coupled is generated as the second signal; The current is set to be larger than the second current, and the fourth current is set to be larger than the third current.

A display device according to the present invention includes a display panel having first to k-th (k is an integer of 2 or more) data lines, each of which has a plurality of pixel portions formed therein, and a display panel that has a display panel having first to k-th (k is an integer of 2 or more) data lines, each of which has a plurality of pixel portions formed therein; a display driver that generates gradation signals corresponding to levels and supplies the first to k-th gradation signals to each of the first to k-th (k is an integer of 2 or more) data lines of the display panel; , the display driver has a display mode for displaying an image on the display panel, and a detection mode for detecting whether or not the gradation signals supplied to the first to k-th data lines are normal. a setting unit configured to set a voltage value of a grayscale signal corresponding to a predetermined luminance level as a reference voltage; and a setting unit configured to select one of the first to kth grayscale signals in the detection mode. , a selection unit that acquires the voltage value of the selected grayscale signal as a detection voltage; and a selection unit that controls the selection unit to periodically select one of the first to kth grayscale signals one by one. a control unit; and a voltage detection circuit that detects that the detection voltage has changed from a reference state having a voltage value within a predetermined voltage range that includes the reference voltage, and the voltage detection circuit includes and a differential stage that outputs a differential current pair corresponding to the difference between the detection voltage and the detection voltage, and a differential stage that outputs a differential current pair corresponding to the difference between the first and second voltages and the first and second coupling points, and a coupling circuit that outputs first and second signals from the first and second coupling points based on first to fourth currents generated by performing current mirror conversion on the first and second voltages, respectively; , a determination circuit that determines whether or not the detected voltage has fluctuated from the reference state based on the first and second signals and outputs a determination signal indicating the determination result, and the coupling circuit includes: , converting one of the differential current pair into the first and third currents of one of a source type (current source type) and sink type (current sink type) based on the first voltage; converting the other of the differential current pair into the second and fourth currents that are the other of a source type and a sink type based on the second voltage, and the first current and the second current are combined. The voltage generated at the first coupling point where the third current and the fourth current are coupled is generated as the first signal, and the voltage produced at the second coupling point where the third current and the fourth current are coupled is generated as the first signal. generated as the second signal, and in the coupling circuit, the first current is larger than the second current and the fourth current is larger than the third current in the reference state. It is set.

A comparator according to the present invention is a comparator that receives an input voltage and a reference voltage and outputs a comparison result indicating whether the input voltage is greater than the reference voltage, It has a differential stage that outputs a differential current pair corresponding to the difference, a first voltage and a second voltage, and an output terminal, and current mirrors the differential current pair with respect to the first and second voltages, respectively. a circuit unit that outputs the comparison result signal from the output terminal based on the first and second currents that are converted and generated; The first current is one of a source type (current source type) and a sink type (current sink type) based on the voltage of A voltage generated at the output terminal where the first current and the second current are combined is generated as the comparison result signal.

In the present invention, a differential current pair corresponding to the difference between a high voltage detection voltage to be detected and a reference voltage is generated, and this differential current pair is converted into a source current and a sink current based on a low voltage, respectively. Then, both currents are combined at the output end, and based on the voltage generated at the output end, it is determined whether the detection voltage of the high voltage to be detected has changed from the reference state based on the reference voltage.

This makes it possible to output detection results at high speed with high sensitivity and precision in accordance with the input detection voltage.

FIG. 1 is a block diagram schematically showing the configuration of an active matrix display device. FIG. 2 is a circuit diagram showing the configuration of a voltage detection circuit 50 according to a first embodiment. 5 is a diagram showing an aspect of a detection result by a voltage detection circuit 50. FIG. 3 is a circuit diagram showing an example of an internal configuration of a differential stage 10. FIG. 3 is a circuit diagram showing another example of the internal configuration of the differential stage 10. FIG. 3 is a circuit diagram showing the configuration of a coupling circuit 30A as another example of the coupling circuit 30. FIG. 3 is a circuit diagram showing the configuration of a coupling circuit 30B as another example of the coupling circuit 30. FIG. 5 is a circuit diagram showing a configuration of a voltage detection circuit 50_1 including a coupling circuit 30C as another example of the voltage detection circuit 50. FIG. It is a figure which shows the aspect of the 1st detection result (O1, O2, JD1) by voltage detection circuit 50_1. It is a figure which shows the aspect of the 2nd detection result (O3, O4, JD2) by voltage detection circuit 50_1. FIG. 2 is a block diagram showing the configuration of a display device 200 according to a second embodiment of the present invention. 2 is a block diagram showing the internal configuration of a data driver 120_1 included in the display device 200. FIG. FIG. 7 is a circuit diagram showing the configuration of a comparator 51 according to a third embodiment of the present invention.

FIG. 2A is a circuit diagram showing an example of the configuration of the voltage detection circuit 50 according to the first embodiment of the present invention. Note that the voltage detection circuit 50 is a voltage detection circuit that detects whether or not the detection voltage has changed from a preset reference state of the detection voltage to be detected by comparing it with a reference voltage. It is a circuit.

As shown in FIG. 2A, the voltage detection circuit 50 includes a differential stage 10, a coupling circuit 30, and a determination circuit 40.

The differential stage 10 outputs a differential current pair (Is1, Is2) corresponding to the difference between the reference voltage (Vref) and the high voltage detection voltage (Vdet) to be detected.

The coupling circuit 30 converts the differential current pair (Is1, Is2) into a first system current pair (I1, I2) and a second system current pair (I3, I4). In FIG. 2A, currents I1 and I3 are source type currents, that is, current source type currents, based on the logic power supply voltage VDD, and currents I2 and I4 are sink type currents, that is, current sinking type currents, based on the ground voltage VSS. It is. Then, the coupling circuit 30 couples the source type and sink type current pairs of the first system current pair (I1, I2) and the second system current pair (I3, I4), and connects each connection point (n5, n6) outputs low voltage first and second logic signals O1 and O2.

In addition, in the coupling circuit 30, in the reference state, the first current (I1) of the source type in the current pair (I1, I2) of the first system is set to be larger than the second current (I2) of the sink type. It is configured. Further, in the coupling circuit 30, the fourth current (I4) of the sink type in the current pair (I3, I4) of the second system is made larger than the third current (I3) of the source type in the reference state. It is configured.

As shown in FIG. 2B, the determination circuit 40 determines whether the detection voltage (Vdet) is in a reference state (a predetermined voltage including the reference voltage Vref) based on the first and second logic signals O1 and O2 output from the coupling circuit 30. (within the range). That is, as shown in FIG. 2B, the determination circuit 40 is normal when the first and second logic signals O1 and O2 have different logical values (the detection voltage Vdet is the reference state), and abnormal when they have the same logical value. (The detected voltage Vdet deviates from the reference state). That is, the determination circuit 40 receives the 2-bit logic signals O1 and O2 and converts them into a 1-bit logic signal JD indicating normality (one of H or L) or abnormality (the other of H or L). Note that since it is possible to determine normality or abnormality even with the 2-bit logic signals O1 and O2, the voltage detection circuit of the present invention may have a configuration that does not include the determination circuit 40.

Here, in the voltage detection circuit 50, when a high voltage signal is to be detected, the differential stage 10 is formed of a high voltage element corresponding to a high voltage range (AVSS to AVDD), and the coupling circuit 30 and the determination circuit Reference numeral 40 is formed of a low voltage element corresponding to a low voltage range (VSS to VDD) based on a logic power supply.

Below, the voltage detection circuit 50 shown in FIGS. 2A and 2B will be described in detail.

Note that the voltage detection circuit 50 detects whether the detected voltage Vdet is maintained at a reference state in which the voltage value is included within a predetermined voltage range that includes the reference voltage Vref (normal) or not (abnormal). That is, when the reference state is defined as when the detection voltage Vdet is substantially the same as the reference voltage Vref, a state in which the detection voltage Vdet deviates from the reference voltage Vref by a predetermined value or more is detected as abnormal. For convenience of explanation, the following descriptions of each embodiment will be made assuming that the reference state is when the reference voltage Vref and the detection voltage Vdet are equal. Further, in the embodiments of the present invention, the configuration of a voltage detection circuit that performs a detection operation on a high voltage signal higher than the logic power supply voltage will be described.

As shown in FIG. 2A, the differential stage 10 has an AVDD power supply terminal receiving a high potential analog power supply voltage AVDD and an AVSS power supply terminal receiving an analog ground voltage AVSS. This is a high voltage circuit made up of voltage elements. The coupling circuit 30 is a low-voltage circuit composed of a low-voltage voltage element that operates between a VDD power supply terminal receiving a low-potential logic power supply voltage VDD and a VSS power supply terminal receiving a logic ground voltage VSS.

In each embodiment, the relationship among the analog power supply voltage AVDD, the analog ground voltage AVSS, the logic power supply voltage VDD, and the logic ground voltage VSS will be explained using an example of AVDD>VDD>VSS≧AVSS.

In FIG. 2A, the differential stage 10 is composed of, for example, an operational amplifier, receives a reference voltage Vref for a high voltage signal and a detection voltage Vdet to be detected, and generates a differential signal according to the difference voltage between the reference voltage Vref and the detection voltage Vdet. Generate output currents Is1 and Is2. Differential stage 10 supplies differential output current Is1 to coupling circuit 30 via node n1, and supplies differential output current Is2 to coupling circuit 30 via node n2.

The coupling circuit 30 has N-channel

MOS type transistors

21, 22, 33-35 and P-channel MOS type transistors 23-25.

The transistor 21 has its drain and gate connected to the node n1, and its source connected to the VSS power supply terminal. The transistor 22 has its own gate connected to the gate of the transistor 21, and its own source connected to the VSS power supply terminal. Further, the transistor 22 has its own drain connected to the drain and gate of the transistor 23. The source of transistor 23 is connected to the VDD power supply terminal. The

transistors

24 and 25 have their respective sources connected to the VDD power supply terminal, and their respective gates connected to the gate of the transistor 23 via the node n3.

The transistor 33 has its drain and gate connected to the node n2, and its source connected to the VSS power supply terminal.

The

transistors

34 and 35 have their respective sources connected to the VSS power supply terminal, and their respective gates connected to the gate of the transistor 33 via the node n2. The transistor 34 has its own drain connected to the drain of the transistor 24 via the node n5. The transistor 35 has its own drain connected to the drain of the transistor 24 via the node n5.

Here, a signal having the voltage generated at the node n5 is supplied from the above-described node n5 to the determination circuit 40 as the above-described logic signal O1. Furthermore, a signal having the voltage generated at the node n6 is supplied from the above-described node n6 to the determination circuit 40 as the above-described logic signal O2.

With this configuration, the differential output current Is1 supplied from the differential stage 10 becomes a folded current with respect to the logic ground voltage VSS by the current mirror (21, 22) composed of N-channel transistors. The folded current is folded back against the logic power supply voltage VDD by current mirrors (23, 24) and (23, 25) composed of P-channel transistors, and the two source type currents I1 and I3 are generated. In addition, the differential output current Is2 of the differential stage 10 is folded back to the logic ground voltage VSS by current mirrors (33, 34) and (33, 35) composed of N-channel transistors, and is sent to two sink systems. Type currents I2 and I4 are generated.

Generally speaking, in a source type and sink type current pair, one of the differential output currents Is1 and Is2 is generated by folding back an odd number of current mirror sections, and the other is generated by folding back an even number of current mirror sections. generated.

Here, the source type current I1 and the sink type current I2 are defined as a first system current pair, and the source type current I3 and sink type current I4 are defined as a second system current pair. At this time, the source type current I1 of the current pair of the first system is sent to the node n5, and the sink type current I2 is extracted from the node n5, so that both currents (I1, I2) are combined at the node n5. The logic signal O1 having the voltage generated at the node n5 is output.

In addition, the source type current I3 of the current pair of the second system is sent to the node n6, and the sink type current I4 is extracted from the node n6, so that both currents (I3, I4) are combined at the node n6. , a logic signal O2 having the voltage generated at the node n6 is output.

Each of the logic signals O1 and O2 is a source type current obtained by current-mirror-converting one and the other of the differential output currents Is1 and Is2, in which one increases and the other decreases, respectively, with respect to the power supply voltage VDD and the ground voltage VSS. Since it is generated by the combination of the current and the sink type current, the state quickly changes to the logic power supply voltage VDD or logic ground voltage VSS representing the detection result (logical value), resulting in a high-speed response.

By the way, in the coupling circuit 30, the current driving capability (current amount) of the

transistors

24, 25, 34, and 35 that generate the currents I1 to I4, respectively, is determined when the potential relationship between the reference voltage Vref and the detection voltage Vdet is in the reference state. ,
I1>I2 and I3<I4
It is set so that In the reference state, the voltage at the junction of the sink type current and the source type current is pulled towards the one with the larger current drive capability (current amount), and becomes stable at the logic power supply voltage VDD or the logic ground voltage VSS. Furthermore, the current that actually flows is the smaller of the combined sink type and source type currents.

Note that the current difference between the currents I1 and I2 and the current difference between the currents I3 and I4 in the reference state are determined by taking into account the tolerance range of the detection voltage Vdet, which is considered to be the reference state, and manufacturing variations in the transistors that constitute the voltage detection circuit. is set.

As a result, in a reference state where the detection voltage Vdet is approximately equal to the reference voltage Vref (Vref-dV1≦Vdet≦Vref+dV2), the voltage at the first output terminal (node n5) of the coupling circuit 30 is H: high level (VDD), The voltage at the second output terminal (node n6) becomes L: low level (VSS). Note that dV1 indicates the lower limit width allowable as the amount of deviation toward the low voltage side with respect to the reference voltage Vref, and dV2 indicates the upper limit width allowable as the amount of deviation toward the high voltage side.

Therefore, at this time, the coupling circuit 30 outputs a high level (H) logic signal O1 and a low level (L) logic signal O2, as shown in FIG. 2B.

On the other hand, when the detection voltage Vdet is lower than the allowable lower limit voltage preset with respect to the reference voltage Vref (Vdet<Vref-dV1), the coupling circuit 30 outputs the low level (L) logic signal O1 and the low level (L) logic signal O1. L) logic signal O2 is output. Further, when the detection voltage Vdet is higher than the allowable upper limit voltage preset with respect to the reference voltage Vref (Vdet>Vref+dV2), the coupling circuit 30 outputs the high level (H) logic signal O1 and the high level (H) logic signal O1. ) outputs the logic signal O2.

The determination circuit 40 receives the logic signals O1 and O2 output from the coupling circuit 30, determines whether the detection voltage Vdet has fluctuated from the reference state based on the logic signals O1 and O2, and outputs the determination signal JD. .

That is, as shown in FIG. 2B, the determination circuit 40 determines that when the logic signals O1 and O2 are at low level (L) and high level (H), respectively, they are equivalent to the reference state, that is, are normal. Further, when the logic signals O1 and O2 are both at low level (L), the determination circuit 40 detects that the detection voltage Vdet is lower than the reference state and determines that there is an abnormality. Further, when the logic signals O1 and O2 are both at high level (H), the determination circuit 40 detects that the detection voltage Vdet is higher than the reference state and determines that there is an abnormality.

Note that the voltage detection circuit 50 includes a control switch that receives a control signal instructing activation and deactivation, and activates (operating state) or deactivates (stops state) itself according to the control signal. It's okay. Examples of the control switch include a first switch pair that blocks the differential output currents Is1 and Is2 output from the differential stage 10 from being supplied to the coupling circuit 30 in the off state, and a first switch pair that blocks the coupling circuit 30 from being supplied to the coupling circuit 30 in the on state. A second switch pair is used that fixes the first and second output terminals (nodes n5, n6) of the device to the same logical value as the reference state (the potential of the VDD power supply terminal or the VSS power supply terminal). That is, when the control signal indicates activation, the first switch pair is set to the on state and the second switch pair is set to the off state, and when the control signal indicates deactivation, the first switch pair is set to the on state and the second switch pair is set to the off state. The second switch pair is set to the off state, and the second switch pair is set to the on state.

Thereby, current consumption of the voltage detection circuit 50 can be minimized by activating the voltage detection circuit 50 only during a predetermined detection operation period.

Next, the setting of the current driving capacity (current amount) for the currents I1 to I4 in the reference state in the coupling circuit 30 will be explained.

The ratio of the current amounts of the currents I1 to I4 in the reference state can be set, for example, by the channel width ratio of the input side transistor and the output side transistor of the current mirror, which determines the current mirror ratio of the current mirror.

Here, in the differential stage 10, when the detection voltage Vdet is in a reference state equivalent to the reference voltage Vref, the differential output currents Is1 and Is2 are as follows.
Is1=Is2
Then,
When the detection voltage Vdet is higher than the reference voltage Vref,
Is1>Is2
Then,
When the detection voltage Vdet is lower than the reference voltage Vref,
Is1<Is2
becomes.

Here, the current mirror ratio of the N-channel current mirrors (21, 22) and (33, 34) is 1, that is, the ratio of the channel width W of the input side transistor and the output side transistor is the same channel width (W = Wn). Set to . Furthermore, the current mirror ratio of the P-channel type current mirrors (23, 25) is set to 1, that is, the ratio of the channel widths W of the input side transistor and the output side transistor is set to be the same (W=Wp). For convenience, the description will be made assuming that the channel lengths of the transistors of the same conductivity type in the coupling circuit 30 are the same.

On the other hand, the current mirror ratio of the P-channel current mirror (23, 24) is greater than 1, that is, the channel width of the transistor 24 on the output side is larger than the channel width of the transistor 23 on the input side (W=Wp). (W=Wp+).

As a result, the amounts of currents I1 and I2 in the standard state are:
I1>I2
becomes.

The current mirror ratio of the N-channel current mirror (33, 35) is also larger than 1, that is, the channel width ratio of the output side transistor 35 is larger than the channel width of the input side transistor 33 (W=Wn). W=Wn+). As a result, the amount of currents I3 and I4 in the reference state is
I3<I4
becomes.

Note that the current amounts of the currents I1 and I2 in the reference state are set, for example, when the detection voltage Vdet is the allowable lower limit voltage (Vref - dV1) set in advance with respect to the reference voltage Vref. The amount is
I1=I2
Set it so that

Similarly, the current amounts of the currents I3 and I4 in the reference state are set such that when the detection voltage Vdet is the allowable upper limit voltage (Vref+dV2) set in advance with respect to the reference voltage Vref, the current amounts of the currents I3 and I4 are set as follows.
I3=I4
Set it so that

In this case, if the detection voltage Vdet is within the range from the allowable upper limit voltage to the allowable lower limit voltage including the reference voltage Vref, it can be determined as a reference state, and if it is outside the range from the allowable upper limit voltage to the allowable lower limit voltage, it is determined to be an abnormal state. It can be judged. That is, by setting the ratio of the current amounts of the above-described currents I1 to I4 in the reference state, an arbitrary allowable range can be provided for the determination of the reference state of the detection voltage Vdet. As a result, it is possible to realize a voltage detection circuit that has a sufficient margin against manufacturing variations in transistors constituting the voltage detection circuit and characteristic fluctuations due to environmental temperature.

Next, the effects of the voltage detection circuit 50 shown in FIG. 2A will be explained.

The voltage detection circuit 50 generates two current pairs by converting one and the other of the differential output currents Is1 and Is2 of the differential stage 10 into source type and sink type current pairs, respectively. Then, the source type and sink type currents are combined for each system, and two systems of logic signals O1 and O2 are taken out from the connection point.

When a voltage difference occurs between the reference voltage Vref and the detection voltage Vdet, the differential stage 10 increases the amount of one of the differential output currents Is1 and Is2 and decreases the amount of the other. Therefore, the voltages at the first and second coupling points (nodes n5, n6) of the coupling circuit 30 quickly change to the logic power supply voltage VDD or the logic ground voltage VSS. That is, the logical signals O1 and O2 taken out from the coupling circuit 30 can quickly determine the logic of the detection result.

Therefore, according to the voltage detection circuit 50 shown in FIG. 2A, the influence of manufacturing variations of transistors, etc. is small, and the detection results (O1, O2 ) can be quickly determined. Further, the voltage detection circuit 50 shown in FIG. 2A realizes an analog/digital conversion circuit that converts the state of the detection voltage Vdet with respect to the reference voltage Vref into a 2-bit digital signal (O1, O2).

Further, according to the voltage detection circuit 50, the detection voltage Vdet is within a normal voltage range without using two reference voltages indicating the allowable lower limit voltage and the allowable upper limit voltage, respectively, as shown in FIG. 4 of Patent Document 1. Since it is possible to determine whether or not there is a signal, the circuit configuration can be simplified.

Further, in the voltage detection circuit 50 shown in FIG. 2A, only the differential stage 10 may be configured with a high voltage (high breakdown voltage) transistor for the detection voltage of high voltage (AVDD to AVSS). In other words, the other configurations of the coupling circuit 30 and the determination circuit 40 can be configured with low voltage (low breakdown voltage) transistors that operate at low voltage (VDD to VSS), so the voltage detection circuit can be configured with a small circuit area and This can be achieved with low power consumption.

In addition, in FIG. 2A, the potential relationship of the power supply voltage is AVDD>VDD>VSS≧AVSS... (1)
An example of the configuration is shown. For example, by reversing the potential relationship,
AVSS≧VSS>VDD>AVDD… (2)
In this case, the conductivity types of the transistors in the coupling circuit 30 in FIG. 2A may be exchanged. Each of the embodiments including FIG. 2A will be described using the potential relationship configuration in (1) above.

FIG. 3 is a circuit diagram showing a specific example of the differential stage 10 shown in FIG. 2A. Note that the coupling circuit 30 and the determination circuit 40 are the same as those shown in FIG. 2A, and their explanation will be omitted.

In the example shown in FIG. 3, the differential stage 10 includes a P-channel differential pair (11, 12) that differentially inputs the reference voltage Vref and the detection voltage Vdet, and supplies current to the tail of the differential pair. It is composed of a current source transistor 13.

Specifically, the P-channel type differential pair (11, 12) is a P-channel type differential pair whose gate is supplied with the reference voltage Vref and whose drain is connected to the input end (node n1) of the current mirror (21, 22). and a P-channel transistor 12 whose gate is supplied with the detection voltage Vdet and whose drain is connected to the input terminal (node n2) of the current mirrors (33, 34) and (33, 35). .

Differential output currents Is1 and Is2 are output from each drain of

transistors

11 and 12, respectively. The sources of

transistors

11 and 12 are commonly connected and form the tail of a P-channel differential pair (11, 12).

The current source transistor 13 is composed of a P-channel transistor whose gate is supplied with a bias voltage BIASP, whose source is connected to the AVDD power supply terminal, and whose drain is connected to the tail of the P-channel differential pair (11, 12). Ru.

According to the configuration shown in FIG. 3, the threshold voltage of the P-channel differential pair (11, 12) from the analog power supply voltage AVDD is |Vtp| It becomes possible to detect the detection voltage Vdet in the voltage range [AVSS to (AVDD-|Vtp|)] excluding the range of .

Note that the clamp circuit or clamp element that maintains the voltage of each node n1 and n2 connecting between the differential stage 10 and the coupling circuit 30 within the low voltage range [VDD to VSS] based on the logic power supply voltage VDD is used as a differential It may be provided between the P-channel type differential pair (11, 12) of the stage 10 and the

transistors

21 and 33 of the coupling circuit 30.

FIG. 4 is a circuit diagram showing another specific example of the differential stage 10 shown in FIG. 2A. Note that the coupling circuit 30 and the determination circuit 40 are the same as those shown in FIG. 2A, and their explanation will be omitted.

In the example shown in FIG. 4, the differential stage 10 includes an N-channel differential pair (11a, 12a) that differentially inputs a reference voltage Vref and a detection voltage Vdet, and a current that supplies current to the tail of the differential pair. It is composed of a source transistor 13a, a P-channel type current mirror (14, 15), and a P-channel type current mirror (16, 17).

Specifically, the N-channel type differential pair (11a, 12a) is an N-channel type differential pair whose gate is supplied with the reference voltage Vref and whose drain is connected to the input end (node n7) of the current mirror (14, 15). and an N-channel transistor 12a whose gate is supplied with the detection voltage Vdet and whose drain is connected to the input end (node n8) of the current mirror (16, 17).

The current mirror (14, 15) includes P-

channel transistors

14 and 15 whose gates and sources are connected to each other. The drain and gate of transistor 14 are connected to node n7, and the source is connected to the AVDD power supply terminal. The drain of the transistor 15 is connected to the node n1, and the source is connected to the AVDD power supply terminal. The current mirror (16, 17) includes P-

channel transistors

16 and 17 whose gates and sources are connected to each other. The drain and gate of transistor 16 are connected to node n8, and the source is connected to the AVDD power supply terminal. The drain of the transistor 17 is connected to the node n2, and the source is connected to the AVDD power supply terminal.

Here, the differential output current Is1 is output from the drain of the transistor 11a, and is supplied to the node n1 via the P-channel type current mirror (14, 15). Further, the differential output current Is2 is output from the drain of the transistor 12a, and is supplied to the node n2 via the P-channel type current mirror (16, 17). The sources of the transistors 11a and 12a are commonly connected and form the tail of an N-channel differential pair (11a, 12a).

The current source transistor 13a is an N-channel transistor whose gate is supplied with the bias voltage BIASN, whose source is connected to the AVSS power supply terminal, and whose drain is connected to the tail of the N-channel differential pair (11a, 12a). Ru.

When the configuration shown in FIG. 4 is adopted as the differential stage 10, the voltage range [(AVSS+Vtn) to AVDD excluding the range of the threshold voltage Vtn of the N-channel differential pair (11a, 12a) from the analog power supply voltage AVSS ] can be detected as the detection voltage Vdet.

FIG. 5 is a circuit diagram showing the configuration of a coupling circuit 30A as a modification of the coupling circuit 30 shown in FIG. 2A. The coupling circuit 30A in FIG. 5 has a configuration that allows adjustment of the detection sensitivity, that is, adjustment of the upper and lower limit voltages of the allowable voltage range for determination using the detection voltage Vdet as a reference state.

Incidentally, in the coupling circuit 30A shown in FIG. 5, for convenience of explanation, changed portions are extracted from the coupling circuit 30 shown in FIG. 2A. In other words, the coupling circuit 30A includes a circuit made up of transistors 21 to 23 and 33, similar to the coupling circuit 30 shown in FIG. 2A, and the description of these transistors 21 to 23 and 33 is omitted in FIG. There is.

In the coupling circuit 30A shown in FIG. 5, a circuit 24A is used in place of the transistor 24 shown in FIG. 2A, and a circuit 35A is used in place of the transistor 35 shown in FIG. 2A. It is the same as shown in 2A.

In FIG. 5, a voltage that generates source type currents I1 and I3 is supplied to node n3, and a voltage that generates sink type currents I2 and I4 is supplied to node n2. In addition, the setting of the current amount of currents I1 to I4 is as follows in the standard state.
I1>I2 and I3<I4
It is set so that

The coupling circuit 30A includes a P-channel transistor 25 in which a source-type current I3 in a reference state is set to a fixed value, and an N-channel transistor 34 in which a sink-type current I2 is set to a fixed value. Furthermore, the coupling circuit 30A includes

circuits

24A and 35A that can variably adjust the amounts of the source type current I1 and the sink type current I4 in the reference state.

The

circuits

24A and 35A will be explained below.

The circuit 24A has a configuration in which a plurality of sets of P-channel transistors and switches connected in series are provided in parallel between the VDD power supply terminal and the node n5. That is, the logic power supply voltage VDD is supplied to each source of each of the plurality of parallel P-channel type transistors 24a_1, 24a_2, . . . , and each gate is commonly connected to the node n3. As a result, each of the transistors 24a_1, 24a_2, . . . generates a mirror current according to the voltage of the node n3. Each of the plurality of parallel switches 26a_1, 26a_2, . . . is controlled to be turned on or off by an external current amount control signal CNTA.

Therefore, in the circuit 24A, the combined current of at least one transistor connected to the switch turned on by the current amount control signal CNTA becomes the current amount of the current I1. That is, by controlling each of the plurality of switches 26a_1, 26a_2, . . . , it is possible to optimally and variably adjust the amount of current I1 relative to current I2. Thereby, the allowable lower limit voltage for determining the detection voltage Vdet as the reference state can be adjusted.

The circuit 35A has a configuration in which a plurality of sets of N-channel transistors and switches connected in series are provided in parallel between the VSS power supply terminal and the node n6. That is, the logic ground voltage VSS is supplied to each source of each of the plurality of parallel N-channel type transistors 35a_1, 35a_2, . . . , and each gate is commonly connected to the node n2. As a result, each of the transistors 35a_1, 35a_2, . . . generates a mirror current according to the voltage of the node n2. Each of the plurality of parallel switches 36a_1, 36a_2, . . . is controlled to be turned on or off by a current amount control signal CNTA.　　　

Therefore, in the circuit 35A, the combined current of at least one transistor connected to the switch turned on by the current amount control signal CNTA becomes the current amount of the current I4. That is, by controlling each of the plurality of switches 36a_1, 36a_2, . . . , it is possible to optimally and variably adjust the amount of current I4 relative to current I3. Thereby, it is possible to adjust the allowable upper limit voltage for determining the detection voltage Vdet as the reference state.

FIG. 6 is a circuit diagram showing a coupling circuit 30B as yet another modification of the coupling circuit 30 shown in FIG. 2A. The coupling circuit 30B in FIG. 6 is also configured to be able to adjust the upper and lower limit voltages of the allowable voltage range that is determined using the detection voltage Vdet as a reference state.

Incidentally, in the coupling circuit 30B shown in FIG. 6 as well, like the coupling circuit 30A, changes from the coupling circuit 30 shown in FIG. 2A are excerpted and shown. That is, like the coupling circuit 30 shown in FIG. 2A, the coupling circuit 30B includes a circuit made up of transistors 21 to 23 and 33, and the illustrations of these transistors 21 to 23 and 33 are omitted in FIG. There is.

In the coupling circuit 30B shown in FIG. 6, a circuit 24B is used instead of the transistor 24 shown in FIG. 2A, and a circuit 35B is used instead of the transistor 35 shown in FIG. 2A. It is the same as shown in 2A.

In FIG. 6, a voltage that generates source type currents I1 and I3 is supplied to node n3, and a voltage that generates sink type currents I2 and I4 is supplied to node n2. In addition, the amount of currents I1 to I4 is as follows in the standard state:
I1>I2 and I3<I4
It is set so that

The coupling circuit 30B includes a transistor 25 in which a source type current I3 is set to a fixed value in a reference state, a transistor 34 in which a sink type current I2 is set to a fixed value, a source type current I1 and a sink type current in the reference state. It includes

circuits

24B and 35B that can variably adjust the amount of current I4.

The transistor 25 and the transistor 34 have the same configuration as the transistor 25 and the transistor 34 of the coupling circuit 30 shown in FIG. 2A. The

circuits

24B and 35B will be explained below.

The circuit 24B has a configuration in which a P-channel transistor 24b_1 and a variable current source 24b_2 are provided in parallel between the VDD power supply terminal and the node n6. The transistor 24b_1 has a source supplied with the logic power supply voltage VDD, a gate connected to the node n3, generates a mirror current according to the voltage of the node n3, and sends it out from the drain.

The current amount of the variable current source 24b_2 is controlled by an external current amount control signal CNTB. The combined current of the transistor 24b_1 and the variable current source 24b_2 is set as the amount of current I1. That is, by controlling the current amount of the variable current source 24b_2, it is possible to optimally set the current amount of the current I1 relative to the current I2. Thereby, the allowable lower limit voltage for determining the detection voltage Vdet as the reference state can be adjusted.

The circuit 35B has a configuration in which an N-channel transistor 35b_1 and a variable current source 35b_2 are provided in parallel between the VSS power supply terminal and the node n6. The transistor 35b_1 has a source supplied with the logic ground voltage VSS, a gate connected to the node n2, generates a mirror current according to the voltage of the node n2, and outputs it from the source.

The current value of the variable current source 35b_2 is controlled by an external current amount control signal CNTB. The combined current of the transistor 35b_1 and the variable current source 35b_2 is set as the current amount of the current I4. That is, by controlling the current of the variable current source 35b_2, it is possible to optimally set the amount of current I4 relative to current I3. Thereby, it is possible to adjust the allowable upper limit voltage for determining the detection voltage Vdet as the reference state.

In addition, in FIGS. 2A, 5, and 6, the settings of the current amount of current I1 and current I2, and current I3 and current I4 are determined by the size of the transistor that generates current I1 and current I4, and the parallel arrangement of transistors. Although an example in which adjustment is performed by the number of stages has been shown, such an adjustment function may be provided in the generation circuit of the current I2 or the current I3.

Next, a specific example of the determination circuit 40 will be explained. The determination circuit 40 receives the 2-bit logic signals O1 and O2 output from the coupling circuit 30 and outputs a 1-bit determination signal JD. The determination circuit 40 can be realized, for example, by an exclusive OR circuit (referred to as an EXOR circuit).

That is, the EXOR circuit receives the detection voltage Vdet and the reference voltage Vref at two input terminals. As a result, the EXOR circuit has a logic value H indicating normality (detection voltage Vdet is in the reference state) when logic signals O1 and O2 are different, and a logic value H indicating abnormality (detection voltage Vdet deviates from the reference state) when they are the same. A determination signal JD indicating the value L is output.

Note that the determination circuit 40 configured with an EXOR circuit expresses the presence or absence of a variation in the detection voltage Vdet from the reference state using binary values, but cannot determine the direction of variation in the detection voltage Vdet. Therefore, if it is desired to also obtain the fluctuation direction (increase direction, decrease direction) of the detection voltage Vdet as a determination result, the logic signals O1 and O2 output from the coupling circuit 30 may be directly output as 2-bit signals. Alternatively, in addition to the determination signal JD of the determination circuit 40, two logic signals O1 and O2 may be output.

FIG. 7 is a circuit diagram showing the configuration of a voltage detection circuit 50_1 as another example of the configuration of the voltage detection circuit 50. Note that the voltage detection circuit 50_1 shown in FIG. 7 employs a coupling circuit 30C in place of the coupling circuit 30 shown in FIG. 2A, and the other configuration is the same as that shown in FIG. 2A except that a determination circuit 40a is newly added. is the same as

Furthermore, in the coupling circuit 30C, the transistors 21 to 25 and 33 to 35 are the same as those shown in the coupling circuit 30 shown in FIG. 2A.

However, in the coupling circuit 30C, a circuit consisting of

transistors

24, 25, 34, and 35, which is also included in the coupling circuit 30 in FIG. In addition, a second converter CV2 and a determination circuit 40a are added.

The second conversion unit CV2 includes P-channel

MOS type transistors

24a and 25a and N-channel

MOS type transistors

34a and 35a. The

transistors

24a and 25a have their respective sources connected to the VDD power supply terminal, and their respective gates connected to the gate of the transistor 23 via the node n3. The

transistors

34a and 35a have their respective sources connected to the VSS power supply terminal, and their respective gates connected to the gate of the transistor 33 via the node n2. The drain of the transistor 34a is connected to the drain of the transistor 24a via the node n5a. The transistor 35a has its own drain connected to the drain of the transistor 25a via a node n6a.

Here, a signal having the voltage generated at the node n5a described above is supplied to the determination circuit 40a as the logic signal O3. Furthermore, a signal having the voltage generated at the node n6a is supplied from the above-described node n6a to the determination circuit 40a as the logic signal O4.

With this configuration, in the coupling circuit 30C, first, the differential output current Is1 supplied from the differential stage 10 becomes a folded current with respect to the logic ground voltage VSS by the current mirror (21, 22). At this time, in the first conversion unit CV1, the folded current is folded back to the logic power supply voltage VDD by current mirrors (23, 24) and (23, 25), and the two source type currents I1, I3 is generated. Further, in the first converting unit CV1, the differential output current Is2 supplied from the differential stage 10 is folded back to the logic ground voltage VSS by current mirrors (33, 34) and (33, 35), Two sink type currents I2 and I4 are generated.

At this time, in the first conversion unit CV1, the source type current I1 is sent to the node n5, and the sink type current I2 is extracted from the node n5, so that both currents (I1, I2) are combined at the node n5, A logic signal O1 having the voltage generated at the node n5 is output. Further, in the first conversion unit CV1, the source type current I3 is sent to the node n6, and the sink type current I4 is extracted from the node n6, so that both currents (I3, I4) are combined at the node n6, A logic signal O2 having the voltage generated at the node n6 is output.

Note that the current drive capability (current amount) of each of the

transistors

24, 25, 34, and 35 of the first conversion unit CV1 that generates the currents I1 to I4, respectively, is based on the first criterion based on the potential relationship between the reference voltage Vref and the detection voltage Vdet. When the condition is
I1>I2 and I3<I4
It is set so that

As a result, the detection voltage Vdet falls within the following first range centered around the reference voltage Vref:
Vref-dV1≦Vdet≦Vref+dV2
dV1: First allowable lower limit width dV2: First allowable upper limit width If included, the voltage at the first output terminal (node n5) of the coupling circuit 30C is H: high level (VDD), second output terminal The voltage at (node n6) becomes L: low level (VSS). Further, when the detection voltage Vdet is lower than the first allowable lower limit voltage preset with respect to the reference voltage Vref (Vdet<Vref-dV1), the first output terminal (node n5) and the second output terminal (node Both voltages of n6) become L: low level (VSS). Further, when the detection voltage Vdet is higher in potential than the first allowable upper limit voltage preset with respect to the reference voltage Vref (Vdet>Vref+dV2), the first output terminal (node n5) and the second output terminal (node n6) Both voltages become H: high level (VDD).

As a result, the detection voltage Vdet becomes
Vref-dV1≦Vdet≦Vref+dV2
In this case, the first conversion unit CV1 outputs a logic signal O1 indicating a high level and a logic signal O2 indicating a low level, as shown in FIG. 8A.

Also, the detection voltage Vdet is Vdet<Vref-dV1
In this case, the first conversion unit CV1 outputs logic signals O1 and O2, both of which are at a low level, as shown in FIG. 8A.

Also, the detection voltage Vdet is Vdet>Vref+dV2
In this case, the first conversion unit CV1 outputs logic signals O1 and O2, both of which are at a high level, as shown in FIG. 8A.

The determination circuit 40 determines whether the detected voltage Vdet is within a first range (Vref-dV1≦Vdet≦Vref+dV2), as shown in FIG. 8A, based on the logic signals O1 and O2 output from the first conversion unit CV1. A determination signal JD1 indicating the determination result is output.

In this way, the first conversion unit CV1 and the determination circuit 40 determine whether the voltage value of the detection voltage Vdet is within a predetermined first range centered on the reference voltage Vref, as shown in FIG. 8A. Alternatively, a determination signal JD1 is generated indicating whether it is outside the first range.

On the other hand, in the second conversion unit CV2, the folded current corresponding to the differential output current Is1 folded back by the current mirror (21, 22) is converted to the logic power supply voltage by the current mirror (23, 24a) and (23, 25a). It is turned back to VDD, and two source type currents I1a and I3 are generated. Further, in the second conversion unit CV2, the differential output current Is2 supplied from the differential stage 10 is reflected back to the logic ground voltage VSS by the current mirrors (33, 34a) and (33, 35a), Two sink type currents I2 and I4a are generated.

At this time, in the second conversion unit CV2, the source type current I1a is sent to the node n5a, and the sink type current I2 is extracted from the node n5a, so that both currents (I1a, I2) are combined at the node n5a, A logic signal O3 having the voltage generated at the node n5a is output. Further, in the second conversion unit CV2, the source type current I3 is sent to the node n6a, and the sink type current I4a is extracted from the node n6a, so that both currents (I3, I4a) are combined at the node n6a, A logic signal O2 having the voltage generated at the node n6a is output.

Note that the current drive capability (current amount) of the

transistors

24a, 25a, 34a, and 35a of the second conversion unit CV2 that generate the currents I1a, I2, I3, and I4a, respectively, is determined by the potential relationship between the reference voltage Vref and the detection voltage Vdet. In the reference state,
I1a>I1>I2, and I3<I4<I4a
It is set so that

For example, the channel width of the transistor 25a of the second conversion unit CV2 is made the same as the channel width Wp of the transistor 25 of the first conversion unit CV1, and the channel width of the transistor 34a of the second conversion unit CV2 is made the same as the channel width Wp of the transistor 25 of the first conversion unit CV1. channel width Wn. Further, the channel width of the transistor 24a of the second conversion unit CV2 is set to a channel width Wp++ wider than the channel width Wp+ of the transistor 24 of the first conversion unit CV1, and the channel width of the transistor 35a of the second conversion unit CV2 is set to be wider than the channel width Wp+ of the transistor 24 of the first conversion unit CV1. The channel width Wn++ is wider than the channel width Wn+ of the transistor 35 of CV1.

As a result, the detection voltage Vdet falls within the following second range centered around the reference voltage Vref:
Vref-dV3≦Vdet≦Vref+dV4
dV3 (dV3>dV1): second permissible lower limit width dV4 (dV4>dV2): second permissible upper limit width If the voltage at the third output terminal (node n5a) of the coupling circuit 30C is H: The voltage at the high level (VDD) and the fourth output terminal (node n6a) is L: low level (VSS). Further, when the detection voltage Vdet is lower than the second allowable lower limit voltage preset with respect to the reference voltage Vref (Vdet<Vref-dV3), the third output terminal (node n5a) and the fourth output terminal (node The voltages of n6a) are both L: low level (VSS). Further, when the detection voltage Vdet is higher in potential than the second allowable upper limit voltage preset with respect to the reference voltage Vref (Vdet>Vref+dV4), the third output terminal (node n5a) and the fourth output terminal (node n6a) Both voltages become H: high level (VDD).

As a result, the detection voltage Vdet becomes
Vref-dV3≦Vdet≦Vref+dV4
In this case, the second conversion unit CV2 outputs a logic signal O1 indicating a high level and a logic signal O2 indicating a low level, as shown in FIG. 8B.

Also, the detection voltage Vdet is Vdet<Vref-dV3
In this case, the second conversion unit CV2 outputs logic signals O1 and O2, both of which are at a low level, as shown in FIG. 8B.

Also, the detection voltage Vdet is Vdet>Vref+dV4
In this case, the second conversion unit CV2 outputs logic signals O1 and O2, both of which are at high level, as shown in FIG. 8B.

The determination circuit 40a determines whether the detected voltage Vdet is within a second range (Vref-dV3≦Vdet≦Vref+dV4), as shown in FIG. 8B, based on the logic signals O3 and O4 output from the second conversion unit CV2. A determination signal JD2 indicating the determination result is output.

In this way, according to the second conversion unit CV2 and the determination circuit 40a, the voltage value of the detection voltage Vdet is within the second range, which is wider than the first range, centered on the reference voltage Vref, as shown in FIG. 8B. A determination signal JD2 is generated indicating whether the second range is included in the second range or outside the second range.

That is, as shown in FIG. 8B, the voltage detection circuit 50_1 detects the first range along with the determination result (JD1) indicating whether the voltage value of the detection voltage Vdet is included within the first range centered on the reference voltage Vref. It is possible to obtain a determination result (JD2) indicating whether or not the second range is included in the second range, which is wider than the first range.

In the above embodiment, the source type current I1 (I1a) in the reference state is made larger than the sink type current I2, and the sink type current I4 (I4a) is made larger than the source type current I3. , the source type current I1 (I1a) may be made smaller than the sink type current I2, and the sink type current I4 (I4a) may be made smaller than the source type current I3.

In short, the voltage detection circuit according to the present invention includes at least the following differential stage and coupling circuit, and may further include a determination circuit.

The differential stage (10, 11 to 17, 11a to 13a) outputs a differential current pair (Is1, Is2) corresponding to the difference between the reference voltage (Vref) and the detection voltage (Vdet) to be detected.

The coupling circuit (30, 30A to 30C) has first and second voltages (VDD, VSS) and first and second coupling points (n5, n6), and has a differential current pair (Is1, Is2). Based on the first to fourth currents (I1 or I1a, I2, I3, I4 or I4a) generated by performing current mirror conversion on the first and second voltages (VDD, VSS), The first and second signals (O1 or O3, O2 or O4) are output from the second connection point (n5 or n5a, n6 or n6a). The coupling circuit also connects one of the differential current pair (Is1) to the first and third currents (I1 or I1a, I3) of a source type (current source type) based on the first voltage (VDD). converting the other of the differential current pair (Is2) into second and fourth currents (I2, I4 or I4a) of sink type based on the second voltage (VSS); The voltage generated at the first coupling point (n5 or n5a) where (I1 or I1a) and the second current (I2) are coupled is generated as the first signal (O1 or O3), and the third The voltage generated at the second coupling point (n6 or n6a) where the current (I3) and the fourth current (I4 or I4a) are coupled is generated as a second signal (O2 or O4). Furthermore, the coupling circuit is such that the first current (I1 or I1a) is larger than the second current (I2) and the fourth current (I4 or I4a) is larger than the third current (I3) in the reference state. It is set to be.

The determination circuit (40, 40a) determines whether the detection voltage (Vdet) is fluctuating from the reference state (first range or second range) based on the first and second signals (O1 or O3, O2 or O4). A judgment signal (JD, JD1, JD2) indicating the judgment result is output.

FIG. 9 is a block diagram showing the configuration of a display device 200 as a second embodiment of the present invention.

As shown in FIG. 9, the display device 200 includes gate lines GL1 to GLr (r is an integer of 2 or more) wired horizontally on an insulating substrate, and data lines DL1 to DLk (k is an integer greater than or equal to 2), the display panel 150 includes a display panel 150 having pixel portions 154 arranged in a matrix at the intersections of each gate line and a data line, and a controller 130. Note that a gate driver 110 that drives each gate line and a data driver 120_1 that drives each data line are connected to the display panel 150, and the controller 130 controls the output timing of these gate drivers 110 and data driver 120_1. adjust.

The gate driver 110 is supplied with the signal group GS from the controller 130, and outputs a scanning signal to be supplied to each gate line based on the signal group GS. Note that the gate driver 110 generally has a thin film transistor circuit configuration that is integrally formed with a pixel portion and wiring in the display panel 150.

The data driver 120_1 is supplied with a video data signal VDS including a clock signal, various control signals, video data signals, etc. from the controller 130, and based on the video data signal VDS, gradation voltages are supplied to the data lines DL1 to DLk. Output a signal.

Note that the data driver 120_1 is usually formed of a silicon LSI, and is mounted at the end of the display panel 150 using COG (Chip On Glass) or COF (Chip On Film). When the data driver 120_1 is composed of a plurality of individual ICs, a video data signal VDS containing various control signals related to the data lines each of which is responsible for driving is supplied from the controller 130 to each data driver IC. When the data driver 120_1 is a single IC or a small number of ICs, the controller 130 may be built into the data driver 120_1. In that case, a group of signals supplied to the controller 130 from the outside is directly sent to the data driver 120_1. Supplied.

FIG. 10 is a block diagram showing an example of the internal configuration of the data driver 120_1.

As shown in FIG. 10, the data driver 120_1 includes output units 80_1 to 80_k that drive loads (data line loads) 90_1 to 90_k, each including a plurality of pixel units 154, via data lines DL1 to DLk.

Furthermore, the data driver 120_1 includes at least the following voltage detection circuit 50, selection switch group 54, reference voltage setting section 55, grayscale voltage generation section 70, and control section 60.

The voltage detection circuit 50 detects whether there is an abnormality in the output voltage of each of the output units 80_1 to 80_k. The selection switch group 54 selects one from the output voltage group output from the output units 80_1 to 80_k and supplies the selected output voltage to the voltage detection circuit 50 as the detection voltage Vdet. The reference voltage setting section 55 sets a reference voltage Vref and supplies it to the voltage detection circuit 50. The control unit 60 generates pixel data PD1 to PDk representing the brightness level of each pixel every horizontal scanning period based on the digital data signal (including video data and control signal) VDS supplied from the outside, and are supplied to the corresponding output units 80_1 to 80_k. Further, the control section 60 supplies a control signal ctla for controlling the voltage detection circuit 50, a control signal ctlb for controlling the selection switch group 54, and a control signal ctlc for controlling the reference voltage setting section 55, respectively.

Each of the output units 80_1 to 80_k receives the pixel data PD assigned to each output unit by the control unit 60, and includes a level shifter (LS) that converts the pixel data from a low voltage at the logic power supply level to a high voltage for driving the load. , converting the grayscale voltage group generated by the grayscale voltage generation unit 70 into a corresponding grayscale voltage signal based on the pixel data signal converted from the grayscale voltage group generated by the grayscale voltage generation unit 70 to a high voltage. It includes a digital-to-analog conversion circuit (DAC), an AMP that amplifies and outputs the gray-scale voltage signal, and an output SW that controls supply or cutoff of the gray-scale voltage signal output from the AMP to the load.

The first to kth gradation voltage signals output from the output units 80_1 to 80_k are supplied to loads 90_1 to 90_k via output pads P1 to Pk.

The selection switch group 54 is composed of switches 54_1 to 54_k that select one of the k grayscale voltage signals output from each output section and supply it to the voltage detection circuit 50 as a detection voltage Vdet. . Selection control and deactivation control (turning off all switches 54_1 to 54_k) of the selection switch group 54 are controlled by a control signal ctla from a control unit 60.

The voltage detection circuit 50 is the voltage detection circuit shown in FIG. 2A, FIG. 3, FIG. 4, etc., including the differential stage 10, the coupling circuit 30, and the determination circuit 40. The detection operation of the voltage detection circuit 50 is controlled by a control signal ctlb from the control section 60.

The reference voltage setting section 55 inputs a gradation voltage to be used as a reference voltage for voltage detection from the gradation voltage group generated by the gradation voltage generation section 70, and sets the gradation voltage specified by the control signal ctlc from the control section 60. The adjusted voltage is supplied to the voltage detection circuit 50 as a reference voltage Vref.

The control unit 60 outputs grayscale voltage signals corresponding to the video data to the data lines DL1 to DLk, and selects a display mode in which video is displayed on the display panel 150, and a display mode in which the grayscale voltage signals are output to the data lines DL1 to DLk according to the video data, and the grayscale voltage signals supplied to the first to kth data lines. Controls the detection mode for detecting whether the modulation signal is normal or not. In the display mode, each output SW of the output units 80_1 to 80_k is turned on, and grayscale voltage signals are supplied from each amplifier AMP to the data lines DL1 to DLk. Note that in the display mode, the voltage detection circuit 50 and selection switch group 54 are inactivated. On the other hand, the detection mode is generally set to a period that does not overlap with the display mode. Below, in the detection mode, the operation of the voltage detection circuit 50 and the control unit 60 to detect a voltage abnormality of the gradation signal output from each of the output units 80_1 to 80_k will be described.

At this time, the control unit 60 first supplies the voltage detection circuit 50 with a control signal ctlb instructing execution of the detection operation, and outputs a grayscale voltage having the same voltage value as the reference voltage Vref. Pixel data PD1 to PDk are designated to output signals. Next, the control unit 60 controls the selection switch group 54 to sequentially select the k grayscale voltage signals output from the output units 80_1 to 80_k one by one. As a result, one gradation voltage signal selected by the selection switch group 54 is supplied to the voltage detection circuit 50 as the detection voltage Vdet, and the voltage detection circuit 50 detects that the detection voltage Vdet is in the reference state (same as the reference voltage Vref). (or a voltage value in the vicinity thereof) is determined. Then, a determination signal JD indicating the determination result is fed back to the control section 60. The control unit 60 receives the determination signal JD and has an abnormality avoidance processing function such as activating means for notifying an abnormality or stopping the data driver 120_1 when an abnormality is determined.

Note that the gradation voltage signal taken out as the detection voltage Vdet from each output section is preferably the voltage at the connection point between the output terminal of the amplifier AMP and the output SW. In that case, by turning on the output SW and performing a detection operation, it is possible to detect an abnormality on the load side (such as a short circuit between loads). Further, by performing the detection operation with the output SW turned off, it is possible to detect an abnormality in the data driver 120_1. Furthermore, by performing these processes together, even if there is no abnormality in the wiring connecting the data driver 120_1 and the loads 90_1 to 90_k, it is possible to determine which one is abnormal.

Furthermore, it is preferable that the voltage abnormality detection operation as described above be performed when the display device 200 is powered on or during a blanking period from one screen display operation to the next one screen display operation. Alternatively, the output units 80_1 to 80_k may be divided into a plurality of output groups, and the output groups targeted for detection operation may be sequentially switched for each blanking period.

As described above in detail, the data driver 120_1 shown in FIG. 10 only has one shared voltage detection circuit 50 for multiple output units (80_1 to 80_k) that drive multiple loads (90_1 to 90_k). Accordingly, voltage abnormality detection can be performed for a plurality of grayscale voltage signals output from each output section.

In addition, in the voltage detection circuit 50, for detecting high voltage signals, only the differential stage 10 is composed of high voltage elements, and the coupling circuit 30 and the judgment circuit 40 are composed of low voltage elements, thereby realizing space saving. It becomes possible to do so. Further, since the voltage detection circuit 50 can determine whether the voltage to be detected is normal or abnormal in one detection operation, it can be realized with a simple circuit configuration that does not require a complicated control circuit.

Note that although FIG. 10 illustrates the operation of detecting a voltage abnormality in the gradation voltage signal output from each output section of the data driver included in the display device, the device that is the target of voltage abnormality detection is based on the data of the display device. Not limited to drivers. In short, the selection switch group 54 and the voltage detection circuit 50 may be provided in an electronic device that handles a plurality of control voltages, setting voltages, etc. other than voltages for driving loads such as gradation voltage signals for display. . Particularly for detection voltages in a high voltage range, by employing the voltage detection circuit of the present invention, it is possible to save area.

FIG. 11 is a circuit diagram showing the configuration of a comparator 51 according to a third embodiment of the present invention.

The comparator 51 compares a high voltage reference voltage Vref and a high voltage detection voltage Vdet, and outputs a comparison result indicating whether the detection voltage Vdet is larger (or smaller) than the reference voltage Vref to the low voltage. A comparison result signal O1 expressed by the level of the logic power supply voltage is output.

Note that the configuration of the comparator 51 shown in FIG. 11 is obtained by omitting the

transistors

25 and 35 from the voltage detection circuit 50 shown in FIG. 2A, and the other circuit configurations are the same as that shown in FIG. 2A. However, in the comparator 51, the current driving capabilities of the transistor 24 and the transistor 34 are the same.

The comparator 51 includes the following differential stage 10 and coupling circuit 30D.

The differential stage 10 generates a differential current pair (Is1, Is2) corresponding to the difference between the reference voltage Vref and the detection voltage Vdet. The differential stage 10 is a high-voltage circuit that receives a high-potential analog power supply voltage AVDD and an analog ground voltage AVSS, and is configured of high-voltage elements that operate at a voltage between the AVDD and AVSS.

The coupling circuit 30D includes N-

channel MOS transistors

21, 22, 33, and 34 and P-

channel MOS transistors

23 and 24.

The transistor 21 has its drain and gate connected to the node n1, and its source connected to the VSS power supply terminal. The transistor 22 has its own gate connected to the gate of the transistor 21, and its own source connected to the VSS power supply terminal. Further, the transistor 22 has its own drain connected to the drain and gate of the transistor 23. The source of transistor 23 is connected to the VDD power supply terminal. The transistor 24 has its source connected to the VDD power supply terminal, and its gate connected to the gate of the transistor 23 via the node n3. The transistor 33 has its drain and gate connected to the node n2, and its source connected to the VSS power supply terminal. The transistor 34 has its source connected to the VSS power supply terminal, and its gate connected to the gate of the transistor 33 via the node n2. The transistor 34 has its own drain connected to the drain of the transistor 24 via the node n5. A signal having the voltage generated at the node n5 is outputted from the node n5 as the above-mentioned comparison result signal O1.

In such a configuration, when the detection voltage Vdet is at a lower potential than the reference voltage Vref (Vdet<Vref), the coupling circuit 30D outputs a logic signal O1 at a low level (VSS). On the other hand, when the detection voltage Vdet is higher in potential than the reference voltage Vref (Vdet>Vref), the coupling circuit 30D outputs the comparison result signal O1 at a high level (VDD).

Here, in the configuration shown in FIG. 11, one and the other of the differential output currents Is1 and Is2 of the differential stage 10 are converted into a source type current pair and a sink type current pair, the current pairs are combined, and the connecting point A comparison result signal O1 representing the comparison result is generated from the comparison result signal O1. At this time, when a voltage difference occurs between the reference voltage Vref and the detection voltage Vdet, one of the differential output currents Is1 and Is2 increases, and the other current decreases. Therefore, the voltage at the output end (node n5) of the coupling circuit 30D quickly changes to the logic power supply voltage VDD or the logic ground voltage VSS.

That is, the comparison result signal O1 output from the coupling circuit 30D is quickly determined to a level representing the result of the comparison with the reference voltage Vref in response to the input of the detection voltage Vdet.

Furthermore, according to the configuration shown in FIG. 11, only the differential stage 10 is formed of high voltage elements, especially when comparing a high voltage signal with a reference voltage and outputting the comparison result as a low voltage signal at a logic level. Since it is only necessary to do so, it is possible to save area.

10

Differential stage

30, 30A to

30C Coupling circuit

40, 40a Judgment circuit 50, 50_1 Voltage detection circuit 51 Comparator 60 Judgment circuit 120_1 Data driver 200 Display device

Claims

A voltage detection circuit that detects that a detection voltage of a detection target has changed from a reference state having a voltage value within a predetermined voltage range including a reference voltage,
a differential stage that outputs a differential current pair corresponding to the difference between the reference voltage and the detection voltage;
first to fourth circuits having first and second voltages and first and second coupling points, and generating current mirror transforms of the differential current pair with respect to the first and second voltages, respectively; a coupling circuit that outputs first and second signals from the first and second coupling points based on the current,
The coupling circuit converts one of the differential current pair into the first and third currents of one of a source type and a sink type based on the first voltage, and converts the other of the differential current pair into the second and fourth currents of the other of a source type and a sink type based on the second voltage, and the first current and the second current are combined. A voltage generated at the coupling point is generated as the first signal, and a voltage generated at the second coupling point where the third current and the fourth current are coupled is generated as the second signal. generate,
The coupling circuit is characterized in that the first current is set to be larger than the second current and the fourth current is set to be larger than the third current in the reference state. Voltage detection circuit.
The method further includes a determination circuit that determines whether or not the detected voltage has fluctuated from the reference state based on the first and second signals output from the coupling circuit and outputs a determination signal indicating the determination result. The voltage detection circuit according to claim 1.
The determination circuit determines that the detection voltage is in the reference state when the first and second signals have different logical values, while determining that the first and second signals have the same logical value. 3. The voltage detection circuit according to claim 1, wherein the voltage detection circuit determines that the detected voltage has fluctuated from the reference state when the detected voltage has the same value as the reference state.
The coupling circuit operates in a first voltage range consisting of the first voltage and the second voltage,
The differential stage operates in a second voltage range consisting of one of the first voltage and the second voltage and a third voltage,
The voltage detection circuit according to claim 1, wherein the second voltage range is set larger than the first voltage range.
The differential stage is formed of a high voltage element that operates at a high power supply voltage higher than a low power supply voltage consisting of the first voltage and the second voltage,
4. The voltage detection circuit according to claim 1, wherein the coupling circuit is formed of a low voltage element that operates with the low power supply voltage.
The coupling circuit generates the first current and the third current by performing current mirror conversion of the one of the differential current pair twice based on the second voltage and the first voltage, respectively, and generates the first current and the third current, respectively. Any one of claims 1 to 5, wherein the second current and the fourth current are respectively generated by one-time current mirror conversion of the other of the differential current pair based on the second voltage. 1. The voltage detection circuit according to 1.
The coupling circuit is
a first transistor circuit that receives the first voltage and outputs a current corresponding to the one of the differential current pair as the first current to the first coupling point;
a second transistor circuit that receives the second voltage and outputs a current corresponding to the other of the differential current pair as the second current to the first coupling point;
a third transistor circuit that receives the first voltage and outputs a current corresponding to the one of the differential current pair as the third current to the second coupling point;
a fourth transistor circuit that receives the second voltage and outputs a current corresponding to the other of the differential current pair as the fourth current to the second connection point;
At least one of the first transistor circuit and the second transistor circuit includes a plurality of transistors whose activation and inactivation are individually controlled and connected in parallel, and the active transistor circuit of the plurality of transistors is connected in parallel. generating a composite current as the first current or the second current by combining the currents output from each of the transistors controlled by the transistor;
At least one of the third transistor circuit and the fourth transistor circuit includes a plurality of transistors whose activation and inactivation are individually controlled and connected in parallel, and the active transistor circuit of the plurality of transistors is connected in parallel. The voltage according to any one of claims 1 to 6, characterized in that the third current or the fourth current is a composite current obtained by combining the currents output from each of the transistors controlled to the voltage. Detection circuit.
The coupling circuit is
a first transistor circuit that receives the first voltage and outputs a current corresponding to the one of the differential current pair as the first current to the first coupling point;
a second transistor circuit that receives the second voltage and outputs a current corresponding to the other of the differential current pair as the second current to the first coupling point;
a third transistor circuit that receives the first voltage and outputs a current corresponding to the one of the differential current pair as the third current to the second coupling point;
a fourth transistor circuit that receives the second voltage and outputs a current corresponding to the other of the differential current pair as the fourth current to the second connection point;
The first transistor circuit includes a first transistor that outputs a current obtained by current mirror-converting one of the differential current pairs, and a first transistor that is connected in parallel with the first transistor and whose current value can be variably controlled. a current source, generating a composite current as the first current by combining the current output from the first current source and the current output from the first transistor,
The fourth transistor circuit includes a second transistor that outputs a current obtained by current mirror-converting the other of the differential current pair, and a second transistor that is connected in parallel with the second transistor and whose current value can be variably controlled. a current source, and a composite current obtained by combining the current output from the second current source and the current output from the second transistor is generated as the fourth current. The voltage detection circuit according to any one of Items 1 to 6.
A gradation signal corresponding to the luminance level of each pixel is generated based on the video data signal, and the 1st to kth gradations are applied to each of the 1st to kth (k is an integer of 2 or more) data lines of the display panel. A display driver that supplies a signal,
a display mode for displaying an image on the display panel; and a detection mode for detecting whether or not the gradation signals supplied to the first to k-th data lines are normal;
a setting unit that sets a voltage value of a grayscale signal corresponding to a predetermined brightness level as a reference voltage;
In the detection mode, a selection unit that selects one of the first to kth grayscale signals and obtains a voltage value of the selected one of the grayscale signals as a detection voltage; a voltage detection circuit that detects whether or not there is a change from a reference state having a voltage value within a predetermined voltage range including the reference voltage;
The voltage detection circuit is
a differential stage that outputs a differential current pair corresponding to the difference between the reference voltage and the detection voltage;
first to fourth circuits having first and second voltages and first and second coupling points, and generating current mirror transforms of the differential current pair with respect to the first and second voltages, respectively; a coupling circuit that outputs first and second signals from the first and second coupling points based on the current;
a determination circuit that determines whether the detected voltage has fluctuated from the reference state based on the first and second signals and outputs a determination signal indicating the determination result;
The coupling circuit converts one of the differential current pair into the first and third currents of one of a source type and a sink type based on the first voltage, and converts the other of the differential current pair into the second and fourth currents of the other of a source type and a sink type based on the second voltage, and the first current and the second current are combined. A voltage generated at the coupling point is generated as the first signal, and a voltage generated at the second coupling point where the third current and the fourth current are coupled is generated as the second signal. generate,
The coupling circuit is characterized in that the first current is set to be larger than the second current and the fourth current is set to be larger than the third current in the reference state. display driver.
The display driver according to claim 9, further comprising a control unit that controls the selection unit to sequentially select the first to kth gradation signals one by one at a predetermined timing.
10. The voltage detection circuit operates only during a period when the first to kth grayscale signals are not being supplied to the first to kth data lines of the display panel. Display driver as described in .
a display panel having first to kth (k is an integer of 2 or more) data lines, each of which has a plurality of pixel portions formed therein;
A gradation signal corresponding to the luminance level of each pixel is generated based on the video data signal, and the first to kth gradation signals are applied to each of the first to kth (k is an integer of 2 or more) data lines of the display panel. a display driver that supplies a grayscale signal;
The display driver is
It has a display mode for displaying an image on the display panel, and a detection mode for detecting whether or not the gradation signals supplied to the first to kth data lines are normal, and corresponds to a predetermined brightness level. a setting section that sets the voltage value of the grayscale signal obtained as a reference voltage;
In the detection mode, a selection unit that selects one of the first to kth grayscale signals and obtains the voltage value of the selected one of the grayscale signals as a detection voltage;
a control unit that controls the selection unit to periodically select the first to kth gradation signals one by one;
a voltage detection circuit that detects whether or not the detection voltage varies from a reference state having a voltage value within a predetermined voltage range including the reference voltage;
The voltage detection circuit is
a differential stage that outputs a differential current pair corresponding to the difference between the reference voltage and the detection voltage;
first to fourth circuits having first and second voltages and first and second coupling points, and generating current mirror transforms of the differential current pair with respect to the first and second voltages, respectively; a coupling circuit that outputs first and second signals from the first and second coupling points based on the current;
a determination circuit that determines whether the detected voltage has fluctuated from the reference state based on the first and second signals and outputs a determination signal indicating the determination result;
The coupling circuit converts one of the differential current pair into the first and third currents of one of a source type and a sink type based on the first voltage, and converts the other of the differential current pair into the second and fourth currents of the other of a source type and a sink type based on the second voltage, and the first current and the second current are combined. A voltage generated at the coupling point is generated as the first signal, and a voltage generated at the second coupling point where the third current and the fourth current are coupled is generated as the second signal. generate,
The coupling circuit is characterized in that the first current is set to be larger than the second current and the fourth current is set to be larger than the third current in the reference state. Display device.
A comparator that receives an input voltage and a reference voltage and outputs a comparison result indicating whether the input voltage is greater than the reference voltage,
a differential stage that outputs a differential current pair corresponding to a difference between the reference voltage and the input voltage;
has a first and second voltage and an output terminal, and is based on the first and second currents generated by performing current mirror conversion of the differential current pair with respect to the first and second voltages, respectively; a circuit unit that outputs the comparison result signal from an output end,
The circuit unit converts one of the differential current pair into the first current of either a source type or a sink type based on the first voltage, and converts the other of the differential current pair into the first current that is of one of a source type and a sink type based on the first voltage. The voltage generated at the output terminal where the first current and the second current are combined is determined by the comparison result. A comparator characterized by generating a signal.
The circuit section operates in a first voltage range consisting of the first voltage and the second voltage,
The differential stage operates in a second voltage range consisting of one of the first voltage and the second voltage and a third voltage,
14. The comparator according to claim 13, wherein the second voltage range is set larger than the first voltage range.
The differential stage is formed of a high voltage element that operates at a high power supply voltage higher than a low power supply voltage consisting of the first voltage and the second voltage,
15. The comparator according to claim 13, wherein the coupling circuit is formed of a low voltage element that operates on the low power supply voltage.