KR102250763B1 - Direct testing for peripheral circuits in flat panel devices - Google Patents

Abstract

A method of testing a flat panel display comprising an array of pixels and peripheral circuitry configured to provide signals to the pixels is disclosed. The method includes applying at least one test signal to a peripheral circuit, acquiring one or more voltage images of the peripheral circuit, and detecting a defect in the peripheral circuit based on the obtained voltage image.

Description

Direct testing of peripheral circuits of flat panel devices {DIRECT TESTING FOR PERIPHERAL CIRCUITS IN FLAT PANEL DEVICES}

Cross-reference to related applications

This application claims the benefit of U.S. Provisional Application No. 61/888,731 filed Oct. 9, 2013, filed Nov. 14, 2006, filed Nov. 15, 2005, and is generally deposited in the United States Claims priority to Provisional Application No. 60/737,090 and is generally related to deposited US Pat. No. 7,714,589, all of which are incorporated herein by reference in their entirety.

The present invention relates generally to inspection of thin film transistor (TFT) arrays used in liquid crystals, organic light emitting diodes and related displays, and more particularly to inspection of TFT arrays including integrated driving circuits.

An important part of the manufacturing cost associated with a liquid crystal display (LCD) panel occurs when a liquid crystal (LC) material is injected between an upper-color filter and a lower-TFT backplane. Therefore, prior to this manufacturing step, it is useful to identify and correct any defects in the TFT backplane (hereinafter, also referred to as "panel"). As such, an important part of the institutional cost associated with organic light-emitting diode (OLED) displays occurs when OLED materials are deposited on the TFT backplane. The problem with inspecting an LCD or OLED panel prior to the deposition of an LC material or OLED material is that without the LC material or OLED material, the display is not functional and does not produce an image for inspection. Prior to the deposition of an LC or OLED material, the only signal present in a given pixel, when driven by an external power source, is the electric field generated by the voltage on the electrode of that pixel. Typically, techniques for testing arrays on a panel use the electrical properties of a pixel electrode, such as an electric field or pixel voltage that is regulated by a change in drive voltage on a transistor gate or data line.

Array panel testers, created by Photon Dynaamics, Inc (PDI)/Orbotech's Voltage Imaging® Optical System (VIOS), as described in U.S. Patent No. 4,983,911, are being tested, for example, using electro-optic transducers. It converts the electric field of the device into optical information recorded by an optical sensor in the VIOS test head. A panel test machine (also known as a pattern generator) is a VIOS detector and pixel array that detects the electric field associated with the signal from the pixel array before the LC material is injected into the panel or the OLED material is deposited on the TFT backplane. In order to drive the signal used in the inspection of the panel, the panel is electrically driven using mechanical contact to the pads on the periphery of the panel.

Most of the latest liquid crystal displays (LCD) and organic light emitting diode (OLED) display panels contain integrated gate driving (IGD) circuits that are manufactured as part of the TFT panel manufacturing process, whereas displays are paneled almost at the end of the panel manufacturing process. It has a separate gate driver IC attached to it. Typically, the IGD circuit is formed around the active pixel array area on the panel. IGD technology lowers cost, reduces bezel size and weight, and increases robustness compared to displays with external, tab-bonded gate driver ICs. However, panel testing is primarily concerned with imaging portions of the array, not areas of the IGD circuit.

Therefore, in order to ensure proper functionality of the panel prior to injection of LC material or deposition of OLED material, maximize production, and lower unit cost, there is a need for a better method for detecting defects in the IGD circuit as well as the active array area.

The nature and advantages of the embodiments of the present invention will be better understood with reference to the following detailed description and the accompanying drawings.

One inventive aspect is a method of testing a flat panel display comprising an array of pixels and peripheral circuitry configured to provide signals to the pixels. The method includes applying at least one test signal to a peripheral circuit, acquiring one or more voltage images of the peripheral circuit, and detecting a defect in the peripheral circuit based on the obtained voltage image.

Another inventive aspect is a system configured to test a flat panel display comprising an array of pixels and peripheral circuitry configured to provide signals to the pixels. The system includes a probe assembly configured to apply at least one test signal to a peripheral circuit, a voltage imaging system configured to obtain one or more voltage images of the peripheral circuit, and a processor configured to detect a defect in the peripheral circuit based on the obtained voltage image. Includes.

1 shows a schematic high-level block diagram of an array portion of a panel being tested using a plurality of signal lines, a plurality of shorting bars and a VIOS test head.
2 shows an IGD circuit including a plurality of shifts in the panel.
3A is a timing diagram of a plurality of applied signals applied to the IGD circuit of FIG. 2.
3B shows a timing diagram of a plurality of output signals generated by the IGD circuit of FIG. 2.
4A shows a schematic and simulated voltage image of a portion of an array including line defects associated with IGD circuit defects in the panel.
4B shows a schematic and simulated voltage image of a portion of the array containing block defects associated with IGD circuit defects in the panel.
5 shows a schematic high-level block diagram of an IGD circuit of a panel being tested using a VIOS test head while the panel is being driven using a plurality of signal lines, in accordance with an embodiment of the present invention.
6 shows a schematic image of an exemplary shift register in the IGD circuit of the panel.
7 is a schematic high-level flow diagram of a method for testing a flat panel display including an active array and peripheral circuits including a plurality of unit cells formed on and periodically arranged in a panel, according to an embodiment of the present invention.
8 shows a schematic high-level flow diagram of the method steps shown in FIG. 7, according to another embodiment of the present invention.
9 shows a schematic high-level flow diagram of a method 900 according to an embodiment of the present invention.
10 shows a schematic high-level flow diagram of a system 1000 in accordance with some embodiments of the present invention.

A method according to an embodiment of the present invention includes an inspection technique for a TFT display panel including an integrated driving circuit. 1 illustrates a plurality of signal lines 150, 152, 154, 156, a plurality of shorting bars 1082 and 1081, and an array region 102 according to an embodiment of the present invention. A schematic high-level block diagram of an array portion 102 of a panel being tested using a VIOS test head 103 disposed thereon, hereinafter referred to as "pixel of array" is shown. The panel further includes an IGD circuit 104 disposed around the array portion 102 at one or both ends of the gate line (FIG. 1 shows an IGD portion on one side of the active region). The IGD circuit 104 includes a clock signal (CK1), a clock signal (CK2), a supply voltage (Vdd), and an enable signal (Vst), respectively, to the IGD circuit 104 It may be connected to a first signal line 150, a second signal line 152, a third signal line 154, and a fourth signal line 156 that may be used to supply to. Eventually, the IGD circuit 104 supplies its output signal to the N gate lines (N gate lines, 114-1, 114-2 to 114-N), and the IGD circuit and the N gate lines " It is driven as intended during panel operation, ie, one gate line is driven at a time in response to the clock signals (CK1, CK2) and the enable signal (Vst).

The panel may further include shorting bars 1081 and 1082 for driving the plurality of data lines 106 in parallel. The data lines are separated into a set of "odd" and "even" lines, which are contact pads, DO ("data odds") through shorting bars 1081 and 1082, respectively. )" 110) and ("data even" 112). The pixels of the array portion 102 connected together to the same shorting bar are simultaneously turned on when the intersecting data line and the gate line are activated together, that is, where the data is "high". Similarly, a panel may have one or more shorting bars (not shown) connected to one or more gate pads (not shown), allowing the IGD circuit to be bypassed when one or more gate shorting bars directly drive multiple gate lines in parallel. Poetry) may also be included. The shorting bar can be separated from the panel during later stages of the panel fabrication process.

In order to test the TFT array electrically, a pattern of an electrical driving signal is applied, and a detection means such as Photon Dynamics' voltage imaging system (VIOS) observes any pixel that does not respond to the pattern of the signal while observing the array portion of the panel ( 102). The pattern of the electrical driving signal is applied to the array portion 102 through the IGD circuit 104 or one or more gate shorting bars, and is also applied to the data lines through the data shorting bars or individual data lines. As described in more detail in US Pat. No. 7,714,589 to M. Jun, et al, under the designation "Array Test Using the Shorting Bar and High Frequency Clock Signal for the Inspection of TFT-LCD With Integrated Driver IC." The displayed display pattern is compared with the expected display pattern to detect the defect.

Figure 2 is an exemplary implementation of a periodic circuit 104 comprising a plurality of N shift registers 204-N (collectively and alternatively referred to hereinafter as shift register 204) in a panel. An example IGD is shown: It will be understood that the following "IGD circuit", "IGD circuit element" and "shift register" include respective connections to the corresponding gate line 114 in the array portion 102. Figure 3A Fig. 2 shows a timing chart of a plurality of input signals applied to the IGD circuit 104 of Fig. 2. Fig. 3B shows a timing chart of a plurality of output signals generated by the IGD circuit 104 of Fig. 2, 3A and 3B, each shift register 204 is a pair of clock signals (CK1 350, CK2 352) phase-shifted by 180 degrees and a supply voltage (Vdd 354). When the signal Vst 356 is applied to the input terminal EN-1 of the shift register 204-1, the shift register 204-1 is transferred to the gate line 114-1 (not shown). ) To generate an output pulse 314-1 that appears to be supplied to the output pulse 314-1, which is synchronized to the clock signals CK1 and CK2, in other words, the signal Vst is driving. Enable the start of the pattern. The output pulse of the shift register 204-1 is received as the enable signal EN-2 to the shift register 204-2, and in turn, the output pulse 314-2 is To the gate line 114-2 (not shown), and subsequently to the shift register 204-N. Thus, the output pulse 314 corresponds to the stream of input clock signals CK1 and CK2. , Are generated sequentially in time, which is an example of an “as intended” operation.

4A shows a schematic and simulated voltage image 404 of an array portion 102 including a line defect 410 associated with a defect in the IGD circuit 104 of the panel, as observed by a VIOS test head. Show. The “line-type” fault 410 is the result of a fault in the associated shift register 434 of the IGD circuit 104, and a voltage that is substantially different from the other (i.e., faultless) gate line 114 It is detected as a result of one of the N gate lines 114 with a voltage condition. Fig. 4B shows a "block-type" defect associated with another type of IGD circuit 104 defect in the panel. A schematic and simulated voltage image 406 of the array portion 102 including 420. Block defect 420 is followed by a gate line with N gate lines 114 and defective shift register 444. This is the result of a defective shift register 444 associated with one of the gate lines that must be driven, both of which have a substantially different voltage state than the normal gate line voltage driven prior to the defective gate line. ) May correspond to, for example, one of the shift registers 204 shown in Fig. 2. The line defect 410 and block defect 420 are determined by the moving VIOS test head 103 referenced in Fig. 1. It is located above portion 102.

A defect in the array portion 102, which may be hidden by a defect in the IGD circuit 104, can be detected by driving the gate line using a conventional shorting bar, whereby the IGD circuit is avoided, so that the gate line ( 114) provides a normal voltage level to drive.

The techniques described above have significant improvements in the detection of IGD defects, but still have significant limitations with respect to, for example, finding a specific defect element of the IGD, i.e., the defective element in the shift register with the defect, because the IGD defect. This is because, depending on the exact nature, can have a wide variety of characteristics. Some IGD defects can lead to a change (increase or decrease) in voltage across the entire area of the panel downstream of the defect, while other IGD defects can lead to a change in voltage across the band-limited area (i.e. The voltage increases to normal for some gate index (N) below). Other IGD defects may be characterized by one or more isolated lines with voltages lower (or higher) than normal voltages. In addition, in some cases, the effect of IGD defects on the array portion 102 may be insignificant and difficult to detect.

According to an embodiment of the present invention, a new IGD defect detection method provides a direct voltage image of a structure within an IGD region. In other words, in some embodiments, the new IGD defect detection method, unlike inferring the IGD defect from the direct voltage image of the array portion 102 (i.e., indirect IGD defect detection), the voltage image directly from the peripheral circuit portion. Get The new IGD defect detection method provides more accurate detection and finding of defective IGD circuit elements (e.g., this method allows you to determine which shift register is defective), as well as the location of the defect within the defective shift register. It also provides the ability to decide where to do it. In addition, the new IGD defect detection method can identify which shift register many elements (eg, about 10 or more transistors) are defective. In one embodiment, the peripheral circuit portion may include a plurality of interface connections disposed between the plurality of shift registers 204 and the array portion 102. In one embodiment, the plurality of interface connections may include a portion of the gate signal line 114 and a signal line between the shift registers, which may be disposed between the shift register 204 and the array portion 102. .

5 is a diagram of the IGD circuit 104 of the panel being tested using the VIOS test head 503 while the panel is being driven using a plurality of signal lines 150, 152, 154, according to an embodiment of the present invention. A schematic high-level block diagram is shown. The features shown in FIG. 5 are similar to those shown in FIG. 1. Some differences are discussed below.

When a signal is applied to the IGD circuit 104, the conductive elements contained within the IGD circuit 104 receive a voltage, which causes the electric field to diverge from the surface of the display in the area of the IGD circuit. These electric fields can be imaged using a VIOS test head 503 placed (at least in part) directly above (at least in part) the peripheral area of the panel containing the IGD, which is how the pixels in the active area are tested before the LC material is injected into the panel. It is similar to whether or not. However, the VIOS test head 503 is positioned in a manner that does not interfere with probe contacts and associated hardware connecting a plurality of signals to the panel.

One aspect of the implementation of direct Voltage Iamging in the IGD circuit is the ability to prevent mechanical interference between the probe assembly and the VIOS test header moving across the surface of the panel.

In one embodiment, the VIOS test head 503 is on a cushion of air at a predetermined distance above the panel, without interference of a mechanical probe assembly and associated hardware (not shown) applied to connect a plurality of signals to the panel. And at least one air injector block 520 applied to float the VIOS test head 503. In addition, the air injection block 520 is a part of the physical area (but not the imaging area of the VIOS test head 503), and the area of the VIOS test head 503 is an area to be imaged (for example, in this case, the IGD circuit (104)). Consequently, this can result in probing the hardware of the probe assembly that is minimally separated from the IGD circuit (or equivalently, the panel active area), which can lead to insufficient use of the substrate area. In one embodiment, the air injection block 520 of the VIOS test head 503 is adapted to provide a detection surface adjacent to or immediately adjacent to the other side 515 of the VIOS test head 503 to the VIOS test head 503. It can be arranged along at least one side. In one embodiment, the air injection block 520 may be oriented along a longitudinal axis 517 oriented substantially parallel to the gate line 114 of the panel. In addition, the VIOS test head 503 EH, the panel plate is rotated, so that the effective area imaged by a detection modulator in the VIOS test head is an air injection block 520 that interferes with the acquisition of a voltage image at the edge of the panel. It can be ensured that it extends farthest towards the edge of the panel, without the occlusion area caused by ).

In one embodiment, the panel is mechanically probed, and does not interfere, and when a mechanical probe assembly (including its own probe pins) contacts a plurality of contact pads 530, it is connected to the probe assembly. Thus, a plurality of contact pads 530 that do not interfere with the movement of the VIOS test head 503 may be included. For example, the plurality of contact pads 530 may be disposed in at least one row on one side of the panel away from the IGD circuit 104 and the array portion 102. In one embodiment, the plurality of contact pads 530 may be disposed around the outside of the array portion 102 on a side substantially perpendicular to the direction of the data line 106. That is, the horizontal axis 540 of at least one row of the contact pad 530 is substantially perpendicular to the horizontal direction of the data lane 106. In one embodiment, the probe assembly may be applied to minimize mechanical interference with the VIOS test head 503. For example, the probe assembly may use a small probe pin and a small probe pin holder.

In one embodiment, during VIOS testing, the IGD circuit 104 drives using the pattern(s) used for steady state, or used for “as intended” operation referred to in FIGS. 3A and 3B. Can be. In another embodiment, during VIOS testing, the IGD circuit 104 may be driven using a special pattern used to highlight certain types of defects. For example, a short in the channel of a TFT in a given shift register is kept high using at least one signal line 150, 152, 154 and/or 156 where the source of the TFT drives the IGD circuit 104. As such, it can be detected when the gate of the TFT is driven low. Different patterns can be designed to detect different types of defects.

6 shows a schematic image 604 of an exemplary shift register of the IGD circuit of the panel, showing that the structure of the IGD circuit 104 is generally more complex than the structure of the array portion 102. However, as shown in FIG. 2, the IGD circuit 104 has a periodicity that is an integer multiple of the gate line (a typical integer such as 1 or 2), and is periodic in a direction perpendicular to the gate line 114. For example, the layout design pattern for an even indexed shift register (e.g., shift register 204-2) is compared to an odd indexed shift register (e.g., shift register 204-1), which is parallel to the gate line 114. If flipped 180 degrees along the axis, the integer multiple could be 2. The cyclically arranged unit cells corresponding to the shift register 204 in the peripheral circuit structure are complex. Therefore, an algorithm different from that used for defect detection of the array portion 102 is needed.

FIG. 7 is a schematic high-level flowchart 700 of a method for testing a flat panel display including an active array and a peripheral circuit including a plurality of unit cells formed on and periodically arranged in a panel, according to an embodiment of the present invention. ). Referring to FIGS. 2 and 5, after registering the VIOS test head 503 on the panel by means of an alignment reference mark executed for this purpose around the panel, the VIOS test head 503 is It is located above the IGD area (720). A plurality of signals are applied to the panel, and the VIOS test head 503 may acquire a voltage image of the IGD region caused by the applied signal. The voltage image is used to determine the functionality of the IGD region.

In some embodiments, depending on the resulting registration data and layout information related to the position of the periodic circuit on the panel (e.g., the position of the shift register 204 on the panel), within the periphery of the panel (e.g., IGD circuit 104). Regions of interest (ROI's) in a voltage image associated with a plurality of unit cells (eg, N shift registers 204), each periodically arranged, may be determined 730. In some embodiments, the ROI's of the voltage image are determined 730 according to the spatial period of the periodic circuit on the panel, as determined from the layout information or the voltage image. The resulting display pattern may be formed. The defect is detected 740 according to the difference between the resulting display pattern and the expected or reference display pattern, and further, it is detected according to a threshold level, which will be described in more detail below.

The location of the defect blob in the IGD circuit element ROI may be used to classify the defect 750 based on comparison with the layout information of the panel. This can be done by subdividing the layout information into various zones, which corresponds to a characteristic of the shift register 204 (eg, a transistor or a group of transistors), and maps a defective cell (shift register) to the layout information. Thus, it is determined which zone corresponds to the defect. The classification accuracy increases with the adjustment of the effective resolution of VIOS.

FIG. 8 shows a schematic high-level flow diagram 800 of method steps 730 and 740 shown in FIG. 7, according to another embodiment of the present invention. After registration and acquisition of the voltage image, an ROI (eg, a unit cell closest to the registration point) corresponding to the first IGD circuit element or unit cell may be determined 810. The determination of the first unit cell may be according to a preset shift with respect to the registration point, or a part of the image including the reference point and the first element and a reference or "golden" image (e.g., a known non-defective unit cell or It can be done by correlation of the stored voltage image of the shift register and registration mark).

Thereafter, the periodicity of the periodically arranged unit cells (eg, the shift register 204) may be determined (820). Determination of periodicity is, for example, a repetitive direction of a unit cell that is periodically repeated of the ROI corresponding to a first IGD circuit element or unit cell that is successively fast Fourier transformed (e.g., perpendicular to the horizontal axis of the gate line 114). Direction). A preset pitch (eg, determined using layout information) between unit cells or IGD circuit elements may also be used.

In the next step, ROIs corresponding to IGD circuit elements or unit cells (eg, second, third and/or subsequent unit cells) after the first unit cell may be determined 830. The determination of the first and subsequent ROIs may be performed by slicing the ROI of the IGD circuit into N sub-ROIs according to the ROI or golden image of the first unit cell and the periodicity detected in the previous step 820.

The reference ROI for the IGD circuit can be configured 840 later. This reference ROI can be formed according to the golden image, or can be constructed by averaging all or part of the IGD circuit element ROIs. This criterion may be, for example, in the form of a median projection peak (or valley) intensity. For example, the reference ROI may be constructed exclusively from any given unit cell or from a close proximity (eg, nearest neighbor) unit cell element of any given unit cell or IGD circuit element. Constructing a reference ROI from a unit cell element in close proximity can be referred to as local averaging, which can be used to minimize the effect of long-distance changes. Alternatively, in one embodiment, global averaging across a plurality of unit cells may be used. In one embodiment, an outlier unit cell (eg, a defective unit cell with a compromised voltage image) may be rejected when forming a reference.

The reference ROI thus formed may be compared 850 (eg, subtracted) with each of a plurality of unit cells or an IGD circuit element in order to detect a defect. As an example, it is possible to compare the intensity of each projection peak or band and the intensity of a reference (eg, Idian) projection peak. The comparison can be made according to the sensor pixel-by-sensor pixel subtraction. Low pass filtering may be used to minimize the effect of noise in the image data. A cell whose difference from a reference or neighbor exceeds a preset threshold or a series of preset thresholds at any location within the cell for any given pixel of the ROI is identified as a defective cell. The preset threshold is an absolute number, in relation to the strength of the reference ROI, or the individual IGD ROIs that make up the reference ROI-the latter approach is called "adaptive thresholding"-to change between Can be set accordingly. Other "thresholding" approaches are also conceivable. Defective pixels are grouped into connected elements called blobs. Defective blobs may be ignored based on their size (eg, blobs formed less than any number of connected sensor pixels are ignored) or other criteria.

9 shows a schematic high-level flow diagram of a method 900 according to an embodiment of the present invention. Using method 900, defects in a periodic circuit, such as the IGD circuit of the FPD, can be detected. In accordance with the present method, a voltage imaging system such as a VIOS test head, discussed elsewhere herein, is used to capture a voltage image of a periodic circuit, which, if functioning properly, allows one or more nodes of the periodic circuit to capture a known voltage state. It is driven with an electrical input signal configured to cause it to appear. One or more aspects of other methods discussed herein may be used in method 900.

The voltage imaging system may be aligned (or registered) with the periodic circuit 910. For example, the voltage imaging system can be aligned using an optical feature recognition control system. For example, the optical feature recognition control system can be configured to match a physical feature of the periodic circuit with a feature pattern stored in memory. For example, one or more alignment fiducial marks or another pattern may be created as part of a physical periodic circuit. An indication of the mark or pattern is stored in the memory and the voltage imaging system is aligned so that the voltage imaging system produces an image of a physical mark or pattern that is positioned and matched with the indication of the mark or pattern in the memory.

Alternatively, the periodic circuit is physically positioned such that the alignment fiducial mark or other pattern is within the area of the view of the optical feature recognition system. Then, the position of the mark or pattern is registered with high accuracy using an optical feature recognition system. Using the known offset between the voltage imaging system and the optical feature recognition system, an offset between the alignment mark or pattern and the first portion of the periodic circuit to be inspected by the voltage imaging system is determined. Based on the offset, the voltage imaging system is positioned on the first portion of the periodic circuit.

Other alignment mechanisms and schemes are used additionally or alternatively. For example, the user may input information indicating alignment information for positioning the voltage imaging system, or information indicating positioning for alignment may be stored in a memory.

In addition, the separation period of the periodic circuit is determined (920). For example, the spacing period may be determined based on one or more voltage images of a periodic circuit obtained using a voltage imaging system. One or more images can be analyzed by the processor to determine the period of the periodic circuit. For example, a fast Fourier transform (FFT) is performed on the data of the voltage image, so that the separation period of the periodic circuit may be determined as a direction in which the determined separation period represents the length of the repeated unit cells of the periodic circuit. In some embodiments, the data of the voltage image includes a section along the direction of the repeated cells of the periodic circuit.

Other methods of determining the periodicity of the periodic circuit may additionally or alternatively be used. For example, the user may input information indicating the separation period, or information indicating the separation period may be stored in a memory.

The period of the periodic circuit may be used to determine the dimensions for each of the plurality of portions of interest (ROI's). For example, the length of each ROI or the pitch of the ROI's may be equal to or coincide with one spacing period of the periodic circuit. In some embodiments, the length of each ROI or the pitch of the ROI's may be equal to or coincide with an integer of the spacing period of the periodic circuit.

The location of each ROI may be determined based on the length or pitch of the information and the alignment information. After the location of the ROI's is determined, at least one voltage image is connected 930 to each ROI. In some embodiments, one or more voltage images of the periodic circuit are connected that are used to determine the spacing period of the periodic circuit. In some embodiments, one or more voltage images for the ROI's are acquired using a voltage imaging system by having the voltage imaging system acquire one or more new voltage images.

In addition, the method includes accessing 940 a reference image. For example, in some embodiments, the reference image is stored in memory in communication with the processor. For example, using a voltage imaging system, a voltage image of a known good portion of a periodic circuit can be captured, and a reference image can be generated based on the captured voltage image and stored in a memory.

In some embodiments, the reference image may be generated based on the voltage image of the device being tested. For example, the voltage images of all or part of the ROI's may be averaged to generate a reference image. Alternatively, the average height of the projection can be used to generate the reference image.

When the reference image is connected, the voltage image of each ROI is compared 950 with the reference image.

Based on the comparison, each ROI may be evaluated 960 operationally or defectively. For example, ROI's whose voltage images of the ROI's differ by more than a threshold from the reference image may be evaluated as including one or more defects. Further, ROI's in which the voltage image of the ROI's differ from the reference image by less than a threshold can be operatively evaluated.

10 shows a schematic high-level schematic diagram of a system 1000 in accordance with some embodiments of the present invention. The system 1000 includes a processor 1010, an electronic memory 1020, a voltage imaging system 1030, a probe assembly 1040, an input device 1050, and And an output device 1060.

The processor 1010 is in electrical communication with each of the memory 1020, voltage imaging system 1030, probe assembly 1040, input device 1050, and output device 1060. The processor 1010 includes a memory 1020, a voltage imaging system 1030, a probe assembly 1040, an input device 1050, respectively, to cause the system 1000 to perform the method steps and actions discussed herein. And an output device 1060. Processor 1010 may be configured to execute instructions stored in memory 1020, which instructions are configured to cause system 1000 to perform the method steps and actions discussed herein.

The input device 1050 is configured to be used by a user to communicate information with the processor 1010. For example, the input device 1050 may include a keyboard.

The output device 1060 is configured to receive information from the processor 1010 and communicate the received information to a user. For example, the output device 1060 may include a display.

Electronic memory 1020 may store computer readable instructions that are executed to cause processor 1010 or system 1000 to perform the methods and actions discussed herein. In addition, the electronic memory 1020 may store other information for functions such as various memories discussed elsewhere herein.

Voltage imaging system 1030 may be configured to perform the methods and actions performed by the various voltage imaging systems discussed herein. For example, voltage imaging system 1030 may include a VIOS test head.

The probe assembly 1040 may be configured to perform the methods and actions performed by the various probe assemblies discussed herein.

With the introduction of direct Voltage Imaging of the IGD circuit, according to an embodiment of the present invention, inspection of the array portion 102 can be done entirely using a shorting bar to avoid the IGD circuit 104. Therefore, for an area to be inspected including both a part of the IGD circuit and a part of the array part 102, two sets of Voltage Images can be obtained. In one embodiment, the two sets of Voltage Images are one Voltage Image obtained as a full-gate pattern and another obtained as an avoidance pattern using the IGD circuit 104 as intended. Subsequent image processing may be allocated to the ROI corresponding to the region in which the pattern is intended (eg, the entire gate pattern for IGD, the avoidance pattern for the active region).

Embodiments of the present invention can be applied to detect defects in a TFT integrated data driver circuit when such a data driver is executed during production. In an embodiment of the present invention, a voltage measurement technique other than an Electro-Optical Transducer-based one may be used. One example of such an alternative technique is voltage measurement by secondary electrons generated after exposing the panel structure to an electron beam.

It can be understood that the embodiments of the present invention are not limited to finding defects in the IGD circuit, but can also be applied to finding defects in a complex circuit structure that repeats cyclically located in a peripheral portion of a panel outside the array portion 102. .

The above embodiments of the present invention are illustrative and not limiting. Various alternative and equivalent examples are possible. While the present invention has been described with respect to an integrated gate driving circuit by way of example, it can be understood that the present invention is not limited by the type of periodic circuit around the flat panel. While the present invention has been described with respect to an LCD display and an OLED display by way of example, it can be understood that the present invention is not limited by the type of display panel technology. While the present invention has been described with respect to a Voltage Imaging® optical system (VIOS) by way of example, it will be understood that the invention is not limited by the type of voltage imaging technique used. Further, the present invention is not limited to testing of thin film transistor arrays, and can be used to test devices such as other circuits on a flat panel, microelectronic circuits, circuit boards, solar panels, semiconductor circuits, and the like. Other additions, subtractions, or modifications are to be understood in light of the present disclosure, and are intended to be within the scope of the disclosure.

Claims (20)

A method of testing a flat panel display comprising an array of pixels and peripheral circuitry configured to provide signals to the pixels,
The peripheral circuit includes a plurality of unit cells periodically arranged,
The above method,
Applying at least one test signal to the peripheral circuit;
Acquiring one or more voltage images of the peripheral circuit, each voltage image being one of the unit cells;
Determining a region of interest in the voltage image associated with each of the periodically arranged unit cells;
Detecting a defect in the peripheral circuit based on the obtained voltage image; And
Classifying the defect based on the comparison with the layout information of the panel, using the position of the defect blob in the region of interest
Including a method for testing a flat panel display. delete The method of claim 1, further comprising determining a period of the periodically arranged unit cells. 4. The method of claim 3, wherein the period is determined based on the one or more voltage images. 5. The method of claim 4, wherein the period is determined based on a fast Fourier transform of the one or more voltage images. The flat panel of claim 1, further comprising comparing each voltage image with a reference, and detecting a defect comprises detecting a difference between one or more voltage images and the reference. How to test the display. 7. The method of claim 6, further comprising determining the reference. 8. The method of claim 7, wherein the reference is determined based on the voltage image. 9. The method of claim 8, wherein the reference is determined based on an average of the voltage images. The method of claim 1,
The peripheral circuit,
A plurality of shift registers; And
A plurality of interface connection units positioned between the plurality of shift registers and the array of pixels
A method for testing a flat panel display, comprising: a. A system configured to test a flat panel display comprising an array of pixels and peripheral circuitry configured to provide signals to the pixels,
The peripheral circuit includes a plurality of unit cells periodically arranged,
The system,
A probe assembly configured to apply at least one test signal to the peripheral circuit;
A voltage imaging system configured to acquire one or more voltage images of the peripheral circuit, each voltage image being one of the unit cells; And
Including a processor,
The processor,
Determining a portion of interest in the voltage image associated with each of the periodically arranged unit cells,
Detecting a defect in the peripheral circuit based on the obtained voltage image, and
Classifying the defect using the location of the defect blob within the interested part, based on the comparison with the layout information of the panel
A system configured to test a flat panel display. delete 12. The system of claim 11, wherein the processor is further configured to determine a period of the periodically arranged unit cells. 14. The system of claim 13, wherein the period is determined based on the one or more voltage images. 15. The system of claim 14, wherein the period is determined based on a fast Fourier transform of the one or more voltage images. The flat panel of claim 11, wherein the processor is further configured to compare each voltage image with a reference, and detecting the fault comprises detecting a difference between the one or more voltage images and the reference. A system configured to test the display. 17. The system of claim 16, wherein the processor is further configured to determine the reference. 18. The system of claim 17, wherein the reference is determined based on the voltage image. 19. The system of claim 18, wherein the reference is determined based on an average of the voltage images. The method of claim 11,
The peripheral circuit,
A plurality of shift registers; And
A plurality of interface connection units positioned between the plurality of shift registers and the array of pixels
A system configured to test a flat panel display, comprising: a.

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