KR102632426B1 - Method for identifying defects on a substrate, and apparatus for identifying defective driver circuits on a substrate - Google Patents

Abstract

A method for identifying a defect on a substrate overlying a plurality of pixels of a display is described. The method includes providing a clock signal for driving a portion of a display to a driver circuit provided on a substrate; imaging at least one portion of the driver circuit synchronized with a clock signal to obtain at least one image of the at least one portion of the driver circuit; and identifying defects in the driver circuitry within the at least one image.

Description

Method for identifying defects on a substrate, and apparatus for identifying defective driver circuits on a substrate

[0001] Embodiments of the present disclosure relate to testing of substrates, particularly large area substrates for display manufacturing. Embodiments relate to defect identification. Embodiments of the present disclosure relate generally to test systems for large area substrates on which electronic devices are formed, and more specifically to locating driver defects for such electronic devices. will be. In particular, embodiments provide a method for identifying a defect on a substrate over which a plurality of pixels of a display are located, a computer-readable medium containing a program for the corresponding method, and an apparatus for identifying a defective driver circuit on the substrate. It's about.

[0002] In many applications, it is necessary to inspect the substrate to monitor its quality. For example, glass substrates on which layers of coating material are deposited are manufactured for the display market. Since defects may arise during the processing of the substrates, such as during the coating of the substrates or structuring the coated layers, inspection of the substrate is necessary to examine the defects and to monitor the quality of the displays.

[0003] Displays are often manufactured on large area substrates with continuously growing substrate sizes. Additionally, displays such as TFT displays continue to improve. For example, display bezels are becoming narrower, OLED displays are increasingly being used for laptops, desktop PC monitors and TVs in addition to mobile devices, and the first μ-LED displays are commercially available. It is available.

[0004] Active matrix liquid crystal displays (LCDs) and OLED displays are commonly used in applications such as computer and television monitors, cell phone displays, personal digital assistants (PDAs), and an increasing number of other devices. It is used in Typically, an active matrix LCD and/or OLED display comprises two flat plates or flat panels, between which a layer of liquid crystal materials or OLED material is sandwiched, respectively. The plates are typically made of glass, polymer, or other material suitable for having electronic devices formed on the plates. A display typically includes an array of thin film transistors (TFTs) each coupled to a pixel. Each pixel is activated by providing signals to data and gate lines and driver circuits, such as transistors, and activation of the pixel can be provided by simultaneously addressing the appropriate data and gate lines. The TFTs can be switched on or off to create an electric field between the individual TFT and a portion of the color filter. TFTs can be switched on or off to drive current through the OLED or μ-LED. Due to the high pixel densities, proximity of gate lines and data lines, and complexity of forming TFTs, there is a high probability of defects during the manufacturing process.

[0005] As described above, a TFT array can be used in LCD displays. However, OLED and μ-LED displays and other displays can also be based on a TFT array backplane, where the pixel electrodes are charged to activate the pixels of the display.

[0006] In order to reduce the manufacturing costs of the display and narrow the bezel of the display, a gate driver, ie a driver circuit, can be fabricated on a substrate with a TFT array and also tested with a test device. For example, US 2008/0284760 describes a method for identifying a defective driver circuit on a substrate on which a plurality of pixels are located. The method includes testing at least some of the plurality of pixels to determine operability of the pixels for some of the plurality of pixels, locating malfunctioning pixels within the plurality of pixels, and an associated It includes testing the driver circuit and locating defects within the driver circuit.

[0007] To further improve the number of defects that can be identified, further improvements in test methods and test apparatuses would be advantageous.

[0008] In view of the above, there is provided a method for identifying a defect on a substrate, a computer readable medium comprising a program for identifying a defect on a substrate, and a defective driver circuit on the substrate having a plurality of pixels positioned thereon. A device for identifying is provided. Additional aspects, advantages and features are apparent from the dependent claims, detailed description and accompanying drawings.

[0009] According to one embodiment, a method is provided for identifying a defect on a substrate overlying a plurality of pixels of a display. The method includes providing a clock signal for driving a portion of a display to a driver circuit provided on a substrate; imaging at least one portion of the driver circuit synchronized with a clock signal to obtain at least one image of the at least one portion of the driver circuit; and identifying defects in the driver circuitry within the at least one image.

[0010] According to one embodiment, a computer-readable medium is provided that includes a program for identifying a defect on a substrate over which a plurality of pixels are located, the program, when executed by a processor, Carry out the method according to the instructions.

[0011] According to one embodiment, an apparatus is provided for identifying a defective driver circuit on a substrate having a plurality of pixels positioned thereon. The device includes a detector configured to generate a voltage contrast image of a driver circuit on a substrate; and a controller that provides a clock signal to activate the driver circuitry on the substrate and a synchronization signal to synchronize image generation.

[0012] In such a way that the above-enumerated features of the disclosure may be understood in detail, a more specific description of the disclosure briefly summarized above may be made with reference to the embodiments, some of which are appended to the present disclosure. Illustrated in the drawings. However, it should be noted that the accompanying drawings illustrate exemplary embodiments only and therefore should not be considered limiting in scope, but may permit other equally effective embodiments.
[0013] Figure 1A illustrates an example large area flat panel substrate having gate drivers and an array of thin film transistors (TFTs) each coupled to a pixel that can be tested in accordance with embodiments described herein. .
[0014] Figure 1B is a schematic diagram of a driver circuit to be tested according to embodiments of the present disclosure.
[0015] Figure 2 illustrates a portion of a substrate to be tested with a method according to embodiments of the disclosure or with a device according to embodiments of the disclosure.
[0016] Figure 3 shows a timeline of signals illustrating methods for identifying a defect on a substrate overlying a plurality of pixels of a display, in accordance with the present disclosure.
[0017] Figure 4 shows a charged particle beam device according to embodiments of the present disclosure.
[0018] Figure 5 illustrates an electron beam test device that can be used for electron beam testing according to one embodiment of the present disclosure.
[0019] Figure 6 is a flow diagram of example operations for identifying whether a defect exists in a pixel or a driver circuit, according to one embodiment of the present disclosure.
[0020] To facilitate understanding, identical reference numbers have been used, where possible, to indicate identical elements that are common to the drawings. It is contemplated that elements and features of one embodiment may advantageously be incorporated into other embodiments without further recitation.

[0021] Detailed reference will now be made to exemplary embodiments, one or more examples of which are illustrated in the drawings. Each example is provided as an illustration and not as a limitation. For example, features illustrated or described as part of one embodiment may be used on or in conjunction with other embodiments to give rise to further embodiments. The intent is that this disclosure includes such modifications and variations.

[0022] Within the following description of the drawings, like reference numbers refer to like components. Only differences with respect to individual embodiments are described. The structures shown in the drawings are not necessarily drawn to scale, but rather are shown to provide a better understanding of the embodiments.

[0023] Embodiments of the present disclosure provide techniques and apparatus for determining whether a driver circuit, such as a gate driver, provided on a substrate is defective. Modern display manufacturing can involve driver circuits on a substrate, ie the substrate on which the TFT array is fabricated. This may be referred to as gate driver on array (GOA), especially since gate drivers are easier to fabricate on the substrate. A signal driver that can be fabricated on a substrate can similarly be tested with methods and devices according to embodiments of the present disclosure.

[0024] Methods, and corresponding devices, for testing a display substrate, particularly during the manufacture of a display, ie before the manufacturing process is completed, typically include testing of substrate pixels. Additionally, test methods and test devices may be provided for testing the driver circuit on the board. Embodiments of the present disclosure provide the option of synchronized testing of driver circuitry. For example, methods and apparatus are provided for synchronized testing of gate driver circuits on an array of display panels. Determining malfunctioning pixels on large-area substrates such as liquid crystal display (LCD) panels or OLED panels can be based on the pixel, the driver circuit for that pixel, the line (gate line or signal line), or a combination thereof. Additionally, it is advantageous to locate driver circuit defects.

[0025] Figure 1A illustrates a section of a flat panel substrate 110 with a plurality of pixels 12. The flat panel substrate 110 is typically a flat, rectangular piece of glass, a polymeric material, or other suitable material on which electronic devices can be formed, and typically has a large surface area. One or more thin film transistors (TFTs) 18 and, for example, one or more capacitors may be associated with each pixel 12 . Flat panel substrate 110 further includes data lines 14 and gate lines 16. Additionally, common lines and also other lines may be provided if necessary. The pixels 12, thin film transistors 18, data lines 14, and gate lines 16 may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), It may be formed on a flat panel substrate 110 by photolithography methods, or other suitable fabrication processes.

[0026] The driver circuit may be connected to a data line or a gate line, especially a gate line. Driver circuits 20, for example gate driver circuits, are connected to individual lines, for example gate line 16. During testing of flat panel substrate 110, driver circuits 20 may be operated to drive pixels 12. Driver circuits 20, which are gate driver circuits, may be operated in combination with the operation of data lines, that is, signal lines. The data lines may be operated by an external driver circuit, by biasing one or more shorting bars, or by other operating methods.

[0027] Pixels 12 can be tested, for example, by voltage contrast measurements to determine the charge provided on the pixel. For example, transistor 18 of pixel 12 can be opened by applying +15 V to the gate of transistor 18, a voltage of 5 V can be provided to the pixel electrode through the signal line, and the transistor can be - It can be closed with a gate voltage of 15V, and a voltage of -10V can be provided to the signal line to keep the transistor closed. A charge of 5V should be maintained across the closed transistor on the pixel electrode, without faults such as shorts or opens. Depending on the measured voltage value deviating from the expected value for one or more pixels of a row and/or column of the display, identification of the defect and even its type may be possible. A wide variety of patterns and test algorithms can be provided to detect line defects, defects in transistor 18, or other defects. Defects on flat panel substrates may include pixel defects, line defects and/or defects in driver circuitry. Pixel defects may include shorts to pixel gate lines and shorts to pixel data lines. Line defects may include line-to-line shorts (eg, data line-to-data line or gate line-to-gate line), cross-shorts (eg, data line-to-gate line), and open line defects. Other flat circuit panels, such as printed circuit boards and multi-chip modules, can also be tested according to various embodiments described herein.

[0028] According to embodiments of the present disclosure, a voltage contrast image of the driver circuit or at least a portion of the driver circuit may be provided. Accordingly, in addition to testing of pixels in particular, an image of the driver circuit can be provided. According to embodiments of the present disclosure, a method is provided for identifying the presence of a defect on a substrate, i.e., a defect on a substrate over which a plurality of pixels of a display are located. The method may optionally include testing at least some of the plurality of pixels to determine operability of the pixels for some of the plurality of pixels. The method includes providing a clock signal for driving a portion of a display to a driver circuit provided on a substrate; imaging at least one portion of the driver circuit synchronized with a clock signal to obtain at least one image (which may be reduced to the size of a single pixel) of the at least one portion of the driver circuit; and locating or determining the presence of a defect in the driver circuit within the at least one image. Imaging at least one portion of the driver circuit includes at least one of electron beam imaging, voltage image capture, charge sensing using an electro-optical sensing device, or electrodes capacitively coupled to the driver circuit.

[0029] Figure 1B shows a schematic diagram of the driver circuit 20, for example a gate driver. As described in more detail with respect to Figure 2, multiple driver circuits may be provided on the substrate. A plurality of gate drivers can be operated as a shift register, and the gate drivers are operated in sequence. For example, the gate drivers may be operated at the product of the display's repetition frequency and gate line number, for example, 60 Hz × 1080 for a full HD display.

[0030] The driver circuit 20 includes a terminal 21 for an operating voltage, and an input terminal 22, a clock terminal 24, an output terminal 26, and a reset terminal 27. A combination of a signal at the input terminal and a signal at the clock terminal can activate the driver circuit. The output terminal can, for example, drive the gate lines of the display and further activate subsequent driver circuitry. The reset terminal can be used to disable active driver circuitry. According to embodiments of the present disclosure, at least a clock terminal is provided. Embodiments may include the terminals described above and may also include additional terminals. A plurality of transistors may be included in the driver circuit 20. FIG. 1B illustrates the transistor 120 by way of example. In one example, transistor 120 may operate as a diode.

[0031] For example, in addition to pixels on a substrate, testing driver circuits on a substrate may include voltage contrast imaging. For example, as described below, a scanning electron microscope (SEM) image including voltage contrast may be provided. Imaging of parts of the driver circuit may make it possible to identify some defects that may potentially occur. According to embodiments of the present disclosure, imaging of at least one portion of the driver circuit is synchronized with a clock signal of the driver circuit. Accordingly, the operation of the driver circuit and the imaging of the driver circuit are synchronized.

[0032] According to some embodiments, which may be combined with other embodiments described herein, imaging of the driver circuit may be provided with a predetermined delay during or relative to the operation of the driver circuit. . Delay operation may, for example, be provided immediately after operation of the driver circuit or even immediately before operation of the driver circuit. Imaging is synchronized with a clock signal, for example a clock signal for the driver circuit. Considering the above, embodiments of the present disclosure have the advantage of enabling identification of defect types that may occur only during operation or at predetermined timing with respect to operation of the driver circuit. Accordingly, according to some embodiments, a defect is identified when the display is dynamically driven and the defective gate driver is activated.

[0033] According to some embodiments, which may be combined with other embodiments described herein, at least a portion of the gate driver is imaged at the time the gate driver is active. For example, the transistor 120, which acts as a diode, may have a defect that appears only during operation of the driver circuit. For example, the driver circuit is operated upon receiving an input signal and a clock signal at input terminal 22 and clock terminal 24.

[0034] Although the test procedures described herein are exemplarily described using an electron beam or charged particle emitter, specific embodiments described herein include optical devices, charge sensing, optical devices, capacitively coupled electrode arrangements, , or other test applications configured to test electronic devices on large substrates in vacuum conditions, or at or near atmospheric pressure.

[0035] Figure 2 shows a substrate 110 with a plurality of pixels of a display positioned thereon. Figure 2 shows schematic pixel examples 212 next to an array of driver circuits. Based on the ability to fabricate an array of driver circuits, for example a GOA, in a small edge region of the display, for example a region of less than 5 mm or even less than 2 mm, the manufacturing of displays becomes possible. However, driver circuits provided on the substrate are advantageously tested with the TFT array on the substrate.

[0036] The array of driver circuits includes driver circuits 20-1, 20-2, 20-3, and 20-4. For example, the driver circuits may be drivers manufactured simultaneously with or subsequent to manufacturing the TFT array. For example, gate drivers can be made of amorphous silicon or LTPS or a metal oxide such as IGZO (InGaZnO). Accordingly, some of the transistors in the driver circuit may be relatively large to provide the desired current. The driver circuits 20-1, 20-2, 20-3, and 20-4 shown in FIG. 2 exemplarily include first zones 221, second zones 222, and third zones ( 223). Each of the zones may include one or more transistors, capacitors and/or connection lines.

[0037] The driver circuits 20-1, 20-2, 20-3, and 20-4 are connected to an array as shift registers. One or more clock signals 124 are provided. Additionally, a start signal 122 may be provided. The start signal may be provided, for example, on the input terminal 22 of the first driver circuit 20-1 and optionally the second driver circuit 20-2. The input terminals 22 of the subsequence driver circuits, for example driver circuits 20-3, 20-4, etc., are connected to the output terminals 26 of one of the previous driver circuits. In the example shown in Figure 2, driver circuits N and N+2 (N is an integer) are linked together. According to other modifications, the driver circuits (N and N+3, N and N+4, N and N+5, N and N+6) can be interlinked. The arrangement of the interlinked driver circuits depends on the display size, the number of clock signals provided for the display, and other parameters that may vary from display manufacturer to display manufacturer.

[0038] During operation, for example, starting from the first driver circuit 20-1, the driver circuits are operated sequentially. For example, subsequent operation of the top-down driver circuits of Figure 2 is based on, among other things, one or more clock signals 124, a start signal 122, and the output of the previous driver circuit being used as input to an additional driver circuit. do. In addition to the shift register defined by the plurality of driver circuits, output is provided for pixels, shown as schematic pixel illustrations 212 in FIG. 2 . In the example shown in Figure 2, the output to the gate line is provided separately from the output to the shift register. However, output terminal 26 can also be connected to a gate line to drive pixels.

[0039] Embodiments of the present disclosure provide the ability to test a driver circuit of a plurality of driver circuits, and particularly testing synchronized with activation of the driver circuit. For example, testing of the driver circuit may be synchronized to at least one of one or more clock signals. Sensing voltages may involve a non-contact test in which no contact is made to measure the voltage. In one embodiment, contact is made only at driver circuit input pads, shorting bars, other conductive contact points or contact pads disposed on the TFT array around the perimeter of the pixel array, and combinations thereof. A variety of devices can be used to sense voltages or charge. Examples include electron beams, electro-optical sensors, and electrodes in close proximity to the surface of the pixels and/or drivers capacitively coupled to the pixel or driver. For electron beam testing, the primary beam can be deflected to specific areas of the driver circuit. SEM images may be acquired, where voltage contrast measurements are provided, for example as described in relation to FIG. 4 .

[0040] If the sensed voltage in the driver circuit or section of the driver circuit is approximately equal to the expected voltage (i.e., within measurement tolerances), the driver circuit or section of the driver circuit may be considered operable. In this case, the driver circuit or part of the driver circuit is not defective. If a pixel or multiple pixels associated with an individual driver circuit are non-functional, the pixel (or lines associated with the pixel) may be inferred to be defective. Appropriate steps may be taken to repair the pixel or lines associated with the pixel.

[0041] If the sensed voltage in the driver circuit or a region of the driver circuit differs from the expected voltages, the driver may be considered inoperable and a fault in the driver circuit may be identified and reported, for example. In some embodiments, a defective driver circuit may be repaired. Repair may include severing inappropriate connections (e.g., shorts) within the driver circuit, depositing conductive material to close the open circuit, and connecting a redundant driver structure to the circuit. Cutting of connections, repair of connections, and/or joining of connections may be made possible by a laser.

[0042] Figure 3 shows a diagram illustrating timing, i.e. synchronized timing of signals for methods for identifying a defect on a substrate over which a plurality of pixels of a display are located. The operating voltage (VSS) is shown as illustrated by reference numeral 321. The start signal 122 starts the operation of a plurality of driver circuits. One or more clock signals 124, for example a first clock signal and a second clock signal, sequentially drive the driver circuits G1 to G7, for example from the top downwards in FIG. 2 (or alternatively from the bottom upwards). ) to operate. In synchronization with the operation of the driver circuits, an image of the operated driver circuit is taken. This is shown as signal 300, which is an image synchronization signal. For example, on the first trigger of signal 300, an image of driver circuit G1 is taken, on a second trigger of signal 300, an image of driver circuit G2 is taken, and so on. Imaging of the driver circuit or a portion of the driver circuit is synchronized with the operation of the driver circuit. For example, there may be a predetermined delay to the start of operation of the driver circuit, or there may be some other predetermined time relationship. According to embodiments of the present disclosure, synchronized imaging of the operation of the driver circuit is associated with a predetermined temporal relationship. In particular, imaging occurs in a time period that overlaps with the operation of the driver circuit.

[0043] The example diagram shown in FIG. 3 further indicates that the time for imaging the driver circuit or one or more portions of the driver circuit is about 50 μs. For example, a display driven with an operating frequency of 60 Hz results in a typical time when an individual driver circuit, for example a gate driver, of a plurality of driver circuits is active. For example, for dynamic driving of the display during testing, the clock time may be approximately 50 μs to 100 μs. Accordingly, high-speed imaging of the driver circuit or one or more portions of the driver circuit is advantageous for embodiments of the present disclosure. According to some embodiments, which may be combined with other embodiments described herein, the driver circuit is imaged within 500 μs or less, especially within 300 μs or less. For example, imaging may occur for less than 60 μs.

[0044] According to some embodiments, the resolution of the image of one or more portions of the driver circuits may be 50 μm or less, particularly 20 μm or less, such as about 15 μm. Accordingly, fast imaging is advantageous for synchronized imaging of the driver circuit, resolution and predetermined clock time advantageous for identification of defects within the driver circuit. As shown in FIG. 2, each of the driver circuits 20-1 to 20-4 includes a first zone 221, a second zone 222, and a third zone 223. According to some embodiments, which may be combined with other embodiments described herein, imaging at least one portion of the driver circuit includes imaging two or more separate portions of the driver circuit. For example, only the first, second and third zones are imaged. Additionally, only one of the regions may be imaged. In particular, portions of the driver circuit may not be imaged according to some embodiments. Accordingly, image generation can be limited to specific regions of interest. Limiting the areas to be imaged can increase imaging speed for a particular driver circuit. In particular, for image generation using a scanning electron beam, it is advantageous to limit the areas of the driver circuit that are imaged during testing to reduce charging of the driver circuit.

[0045] According to some embodiments, which may be combined with other embodiments described herein, a voltage contrast image is generated in one or more zones of a driver circuit. For example, a voltage contrast image may be provided with a scanning charged particle beam. As shown in FIG. 2, the first feature 231 includes a first driver circuit 20-1, a second driver circuit 20-2, a fourth driver circuit 20-4, and a fifth driver circuit ( 20-5), the voltage, for example, the expected voltage, can be indicated. The first feature 231 may not be visible at the expected voltage at the third driver circuit 20-3. Accordingly, a portion of the second region 222 of the third driver circuit 20-3 may be marked as defective.

[0046] According to some embodiments, which may be combined with other embodiments described herein, identifying defective features in a driver circuit involves comparing, in particular, one of the corresponding features in neighboring driver circuits. It can be based on comparison to the above. According to some embodiments that can be combined with other embodiments described herein, an imaging device for testing a display has a wide field of view, such as a field of view with a dimension of 200 mm or more, such as a field of view with a dimension of 400 mm or more. May include field of view. Imaging operations at high resolution and wide field of view may provide reduced uniformity of the image, for example, uniformity of contrast, uniformity of distortion, or uniformity of other imaging characteristics across the entire field of view. Accordingly, comparison of regions or features of neighboring driver circuits may result in similar imaging characteristics. Accordingly, fault identification based on comparison with neighboring driver circuits may advantageously be provided in accordance with some embodiments of the present disclosure. As another example, the second feature 232 is shown only in the third driver circuit 20-3 and is one or more of a plurality of neighboring driver circuits, e.g., the next neighbor or plurality within 10 or less neighboring driver circuits. A comparison with neighbors may indicate that the second feature 232 corresponds to defective features within the first region 221 of the third driver circuit 20-3.

4 shows an electron beam (e-beam) test device, such as a charged particle beam microscope (e.g., a charged particle beam microscope), for locating defects in, e.g., pixel and/or driver circuitry, associated with malfunctioning pixels of a large-area substrate, such as a TFT array. 400) is an example. In the test device, power to a charged particle beam gun, such as an e-beam gun, can be supplied from a power supply. The controller may also be used (e.g., via executable software) in an effort to scan the electron beam at individual pixels of a pixel array fabricated on the TFT array or to scan for the generation of a voltage contrast image, such as an SEM image. ) can control the operation of deflection elements (eg, deflection coils or plates). A detector may be provided to detect voltage from signal particles, such as backscattering or secondary electrons.

[0048] Figure 4 shows a charged particle beam device or charged particle beam microscope 400. According to some embodiments, which may be combined with other embodiments described herein, the charged particle beam device or charged particle beam microscope has a field of view with a dimension of 200 mm or more. Those skilled in the art will recognize that, for example, a scanning electron microscope for high resolution imaging for the semiconductor industry may not be an appropriate device for testing large area substrates at high speeds given the limited size field of view of such devices. An electron beam (dotted line) may be generated by the electron beam source 412. Within gun chamber 410, additional beam shaping elements such as suppressors, extractors and/or anodes may be provided. The electron beam source may include a TFE emitter. The gun chamber can be evacuated to a pressure of 10 ^-8 mbar to 10 ^-9 mbar. Although reference is made in the examples to scanning electron beam devices, charged particle beam devices may generally be used.

[0049] In a further vacuum chamber 420 of the column of the charged particle beam microscope 400, a condenser lens may be provided. Additional electro-optical elements may be provided in the additional vacuum chamber. Additional electro-optical elements may be selected from the group consisting of: stigmator, correction elements for chromatic aberration and/or spherical aberrations.

[0050] The primary electron beam or primary charged particle beam may be focused onto the substrate 110 by an objective lens 424. Substrate 110 is positioned at a substrate position on substrate support 435 . Upon impact of the electron beam onto the substrate 110, signal electrons, such as secondary and/or backscattered electrons, and/or x-rays are emitted from the substrate 110, which are transmitted to the detector 440. ) can be detected by. According to some embodiments, which may be combined with other embodiments described herein, a voltage contrast filter such as grid 441 may be provided. The grid 441 may be biased with a potential, allowing electrons above a certain voltage to pass through the grid while pushing the electrons with energy below the corresponding voltage. According to further embodiments, which may be combined with other embodiments described herein, a voltage is applied to the substrate to create a field on secondary electrons for energy filtering, i.e. to create a voltage contrast image. may be provided (the provided voltages may be shifted).

[0051] In example embodiments described in connection with FIG. 4, a concentrator lens 423 is provided. As shown in Figure 4, objective lens 424 can have a magnetic lens component with pole pieces and a coil. The objective lens focuses the primary electron beam onto the substrate 110. The objective lens may be, for example, a combined electrostatic-magnetic lens with an axial gap or a radial gap, or the objective lens may be an electrostatic retarding field lens.

[0052] Additionally, a scanning deflector assembly may be provided. The scanning deflector assembly may be, for example, a magnetic and/or electrostatic scanning deflector assembly configured for high pixel rates. The scanning deflector assembly may be a single stage assembly. Alternatively, a 2-stage or even 3-stage deflector assembly could also be provided for scanning. Each stage may be provided at a different position along the optical axis.

[0053] According to some embodiments, which may be combined with other embodiments described herein, the magnetic scanning deflector 471 and the electrostatic scanning deflector 472 may be combined. The combination of magnetic scanning deflectors and electrostatic scanning deflectors enables, for example, the wide field of view provided by magnetic scanning deflectors. Additionally, within a wider field of view, sub-regions of the field of view can be scanned at a faster rate with an electrostatic scanning deflector. Accordingly, fast image acquisition can be provided by a combination of magnetic scanning deflectors and electrostatic scanning deflectors. According to some embodiments, a magnetic scanning deflector can steer the beam into a sub-region. The electrostatic scanning deflector can, for example, scan the beam within a sub-region with a resolution of less than 20 μm, such as 5 μm. After the sub-region has been scanned, the magnetic scanning deflector can steer the beam into further separation, which in turn is scanned by the electrostatic scanning deflector. Accordingly, the precision of a magnetic scanning deflector can be combined with the lack of magnetic hysteresis (and corresponding reduced scanning speed) of an electrostatic deflector. The charged particle beam microscope 400 shown in FIG. 4 includes a detector 440. Detector 440 includes a scintillator arrangement and, for example, a light multiplier.

[0054] According to embodiments of the present disclosure, a charged particle beam device and/or a test system including a charged particle beam device includes a controller 430, where the controller controls the charged particle beam device with a signal line 432. It is connected to and provides a synchronization signal, specifically triggering imaging of areas on the substrate. The synchronization signal is synchronized with the clock signal to enable imaging at least one portion of the driver circuit to obtain at least one image of the at least one portion of the driver circuit.

[0055] A controller of a charged particle beam device and/or test system may include a central processing unit (CPU), memory, and, for example, support circuits. To enable control of a charged particle beam device, a CPU may be any type of general-purpose computer processor that may be used in an industrial environment to control various components and sub-processors. The memory is coupled to the CPU. The memory or computer-readable medium may be one or more readily available memory devices, such as random access memory, read-only memory, floppy disk, hard disk, or any other form of digital storage, local or remote. Support circuits may be coupled to the CPU to support the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and related subsystems, etc. Inspection process instructions and/or instructions for synchronized imaging of at least a portion of the driver circuitry are generally stored in memory as software routines, typically known as recipes. Software routines may also be stored and/or executed by a second CPU located remotely from the hardware being controlled by the CPU. The software routine, when executed by the CPU, transforms the general purpose computer into a special purpose computer (controller) that controls the charged particle beam device and, in accordance with any of the embodiments of the present disclosure, synchronized driver circuit imaging, For example, it can provide synchronized gate driver imaging. Although the methods and/or processes of this disclosure are discussed as being implemented as software routines, some of the method operations disclosed herein may be performed by a software controller as well as in hardware. Accordingly, embodiments may be implemented in software running on a computer system, in hardware as an application-specific integrated circuit or other type of hardware implementation, or in a combination of software and hardware. The controller may execute or perform a method, in accordance with embodiments of the present disclosure, for identifying a defect on a substrate over which a plurality of pixels of a display are located, for example, for display manufacturing.

[0056] According to embodiments described herein, methods of the present disclosure may be performed using computer programs, software, computer software products, and interrelated controllers, which operate with corresponding components of the device. It can have a communicating CPU, memory, user interface, and input/output devices.

[0057] FIG. 5 illustrates an external view of an example electron beam test system 500 (e-beam test system) that may be used for electron beam testing in connection with one or more embodiments of the present disclosure. The electron beam test system 500 is an integrated system requiring minimal space, up to 1.25 meters x 1.5 meters and exceeding 1.25 meters x 1.5 meters, for example up to 2.94 meters x 3.37 meters and exceeding 2.94 meters x 3.37 meters. It is possible to test large glass panel substrates. Electron beam test system 500 may include a load lock chamber 504 and a test chamber 550. Additionally, optionally, a prober storage assembly and/or a prober transport assembly may be provided.

[0058] According to some embodiments, large area substrates may have a size of at least 1.375 m2. The size may be from about 1.375 m2 (1100 mm x 1250 mm - GEN 5) to about 9 m2, more specifically from about 2 m2 to about 9 m2 or even up to 12 m2. The substrates or substrate receiving regions on which structures, devices and methods according to embodiments described herein are provided may be large-area substrates as described herein. For example, large-area substrates or carriers include GEN 5, which corresponds to approximately 1.375㎡ substrates (1.1m × 1.25m), GEN 7.5, which corresponds to approximately 4.39㎡ substrates (1.95m × 2.25m), and approximately 5.7㎡ substrates ( It could be a GEN 8.5 corresponding to 2.2 m x 2.5 m), or even a GEN 10.5 corresponding to about 10.5 m2 boards (2.94 m x 3.37 m). Even larger generations, such as GEN 11 and GEN 12 and corresponding substrate areas, can be implemented similarly.

[0059] A prober storage assembly may be provided, for example, may accommodate one or more probers or may include probe bars proximate the test chamber 550 for easy use and retrieval. You can. According to advantageous embodiments that can be combined with other embodiments described herein, test chamber 550 includes a prober bar that is adaptable to various configurations or designs of displays on a large area substrate. Accordingly, specific probers for display layout on the substrate can be avoided, and prober storage assembly can also be avoided.

[0060] The electron beam test system 500 may further include four or more electron beam test (EBT) columns 525, such as 10 or more EBT columns. EBT columns may be placed on the upper surface of test chamber 550. During electron beam testing, specific voltages can be applied to the TFTs by using one or more probers, and the electron beam from the EBT column is directed to the individual pixels under investigation and/or to contact pads for the driver circuit. Secondary electrons emitted from pixels or contact pads can be sensed to determine TFT or driver circuit voltages, respectively.

[0061] According to some embodiments, which may be combined with other embodiments described herein, testing of a large area substrate may include the operation of two or more electron beam test columns. In certain implementations, the operation of neighboring test columns can be synchronized to reduce crosstalk between neighboring columns. Accordingly, it may be advantageous to operate each column, for example every 50 μs, for testing of the driver circuits synchronized with the driver circuit operation.

[0062] FIG. 6 shows a flow chart illustrating a method 600 for identifying a defect on a substrate overlying a plurality of pixels of a display. As described above, in operation 602, at least some of the plurality of pixels may be tested to determine operability of pixels for some of the plurality of pixels. Optional pixel testing may be provided before or after testing of the driver circuitry. Testing both one or more driver circuits and one or more pixels has the advantage that driver testing can be provided with the same test equipment as pixel testing. At operation 604, a clock signal is provided on the substrate to drive a portion of the display with driver circuitry. At least one portion of the driver circuit is imaged, and in operation 606 the imaging is synchronized with a clock signal to obtain at least one image of the at least one portion of the driver circuit. At operation 608, a defect in the driver circuitry is identified within at least one image.

[0063] According to some embodiments, which may be combined with other embodiments described herein, identifying a fault within a driver circuit includes detecting a voltage that is different from an expected voltage, and in particular, the expected voltage may require an additional driver. derived from the circuit. According to some modifications, identifying the defect may further include locating the defect. According to some embodiments, which may be combined with other embodiments described herein, the method may further include repairing a defect in the driver circuit.

[0064] Although the foregoing relates to embodiments of the disclosure, other and additional embodiments of the disclosure may be devised without departing from the basic scope of the disclosure, and The scope is determined by the claims below.

Claims (20)

A method for identifying a defect on a substrate over which a plurality of pixels of a display are located, comprising:
providing a clock signal for driving a portion of the display to a driver circuit provided on the substrate;
imaging at least one portion of the driver circuit synchronized with the clock signal to obtain at least one image of the at least one portion of the driver circuit; and
comprising identifying a defect in the driver circuit within the at least one image,
A method for identifying defects on a board. According to claim 1,
further comprising testing at least some of the plurality of pixels to determine operability of pixels for some of the plurality of pixels,
A method for identifying defects on a board. According to clause 2,
Testing some of the plurality of pixels includes using one of electron beam testing, voltage image capture, charge sensing using an electro-optical sensing device, or electrodes capacitively coupled to the plurality of pixels. doing,
A method for identifying defects on a board. According to claim 1,
Imaging at least one portion of the driver circuit includes using one of electron beam imaging, voltage image capture, charge sensing using an electro-optical sensing device, or an electrode capacitively coupled to the driver circuit. ,
A method for identifying defects on a board. According to claim 1,
Identifying a fault in the driver circuit includes detecting a voltage that is different from an expected voltage.
A method for identifying defects on a board. According to clause 5,
The expected voltage is derived from an additional driver circuit,
A method for identifying defects on a board. According to claim 1,
Identifying the defect includes locating the defect,
A method for identifying defects on a board. According to claim 1,
Imaging the at least one portion of the driver circuit includes imaging an area on the substrate to image the at least one portion of the driver circuit in synchronization with the clock signal.
A method for identifying defects on a board. According to claim 1,
Imaging at least one portion of the driver circuit includes imaging two or more separate portions of the driver circuit.
A method for identifying defects on a board. The method according to any one of claims 1 to 8,
Imaging at least one portion of the driver circuit includes imaging two or more separate portions of the driver circuit.
A method for identifying defects on a board. According to claim 10,
Portions of the driver circuit are not imaged,
A method for identifying defects on a board. The method according to any one of claims 1 to 9,
Imaging of at least one portion of the driver circuit is synchronized to acquire the image while the driver circuit is active.
A method for identifying defects on a board. The method according to any one of claims 1 to 9,
The driver circuit is connected to a data line or gate line,
A method for identifying defects on a board. The method according to any one of claims 1 to 9,
further comprising repairing a defect in the driver circuit,
A method for identifying defects on a board. A device for identifying a defective driver circuit on a substrate on which a plurality of pixels are located, comprising:
a detector configured to generate a voltage contrast image of a driver circuit on the substrate; and
A controller that provides a clock signal to activate the driver circuit on the board and a synchronization signal to synchronize image generation,
The device is,
further comprising a computer-readable medium including a program for identifying defects on the substrate over which the plurality of pixels are located,
The program, when executed by a processor, performs the method according to any one of claims 1 to 9,
A device for identifying defective driver circuits on a board. A device for identifying a defective driver circuit on a substrate on which a plurality of pixels are located, comprising:
a detector configured to generate a voltage contrast image of a driver circuit on the substrate; and
A controller that provides a clock signal to activate driver circuitry on the substrate and a synchronization signal to synchronize image generation,
A device for identifying defective driver circuits on a board. According to claim 16,
A charged particle beam gun for generating a primary charged particle beam; and
further comprising one or more scanning deflectors configured to deflect the primary charged particle beam over a portion of the driver circuit.
A device for identifying defective driver circuits on a board. According to claim 17,
The detector further comprises a voltage contrast filter for generating a voltage contrast image based on signal electrons generated by impact of the deflected primary charged particle beam on the substrate.
A device for identifying defective driver circuits on a board. According to claim 16,
wherein the controller provides the synchronization signal to image at least one portion of the driver circuit in synchronization with the clock signal to obtain at least one image of the at least one portion of the driver circuit,
A device for identifying defective driver circuits on a board. According to clause 19,
Imaging the at least one portion of the driver circuit includes imaging an area on the substrate to image the at least one portion of the driver circuit.
A device for identifying defective driver circuits on a board.