KR102188570B1 - Method of nanowire Semiconductor Device - Google Patents

Method of nanowire Semiconductor Device Download PDF

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Publication number
KR102188570B1
KR102188570B1 KR1020180145648A KR20180145648A KR102188570B1 KR 102188570 B1 KR102188570 B1 KR 102188570B1 KR 1020180145648 A KR1020180145648 A KR 1020180145648A KR 20180145648 A KR20180145648 A KR 20180145648A KR 102188570 B1 KR102188570 B1 KR 102188570B1
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South Korea
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conductive layer
nanowire
layer
semiconductor device
forming
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KR1020180145648A
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Korean (ko)
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KR20190111725A (en
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잉 홍
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홍잉
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Priority to PCT/KR2019/002515 priority Critical patent/WO2019182264A1/en
Priority to CN201980021545.1A priority patent/CN111902944A/en
Publication of KR20190111725A publication Critical patent/KR20190111725A/en
Priority to US17/028,342 priority patent/US11342183B2/en
Application granted granted Critical
Publication of KR102188570B1 publication Critical patent/KR102188570B1/en
Priority to US17/695,336 priority patent/US11699588B2/en

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    • H01L29/41725—Source or drain electrodes for field effect devices

Abstract

나노와이어 반도체 소자의 제조 방법에 대해 기술한다. 제조 방법은: 기판에 촉매층을 형성하는 단계; 상기 촉매층 위에 제1도전층, 반도체 실리콘층 그리고 제2도전층 순으로 적층된 다층막을 형성하는 단계; 상기 다층막을 패터닝하여 상기 기판 상에 수직 나노와이어를 형성하는 단계; 열처리에 의해 상기 나노와이어를 결정화하는 단계; 상기 나노와이어를 덮는 절연층을 형성하는 단계; 상기 나노와이어의 반도체 실리콘층에 의한 채널영역을 감싸는 게이트를 형성하는 단계; 그리고 상기 게이트, 제1도전층, 그리고 제2도전층에 전기적으로 연결되는 메탈패드를 형성하는 단계;를 포함한다.A method of manufacturing a nanowire semiconductor device will be described. The manufacturing method includes: forming a catalyst layer on a substrate; Forming a first conductive layer, a semiconductor silicon layer, and a second conductive layer on the catalyst layer in that order; Forming vertical nanowires on the substrate by patterning the multilayer film; Crystallizing the nanowires by heat treatment; Forming an insulating layer covering the nanowires; Forming a gate surrounding the channel region by the semiconductor silicon layer of the nanowire; And forming a metal pad electrically connected to the gate, the first conductive layer, and the second conductive layer.

Description

수직 나노와이어 반도체 소자 및 그 제조 방법{Method of nanowire Semiconductor Device}Vertical nanowire semiconductor device and its manufacturing method TECHNICAL FIELD [Method of nanowire Semiconductor Device]

본 개시는 나노와이어 반도체 소자 및 그 제조 방법에 관한 것으로 상세하게는 버티컬 반도체 나노와이어를 이용하는 반도체 소자 및 그 제조 방법에 관한 것이다.The present disclosure relates to a nanowire semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device using a vertical semiconductor nanowire and a method of manufacturing the same.

고성능의 반도체는 전자 제품의 품질을 향상하며, 비용 면에서의 이익도 수반한다. 반도체 소자는 높은 이동도와 신뢰도를 가지는 것이 필요하고, 특히 일정한 특성을 가짐으로써 특성 산포를 줄이는 것이 필요하다.High-performance semiconductors improve the quality of electronic products and come with cost benefits. A semiconductor device needs to have high mobility and reliability, and in particular, it is necessary to reduce the distribution of characteristics by having certain characteristics.

최근의 스마트폰들의 모바일 디바이스는 AM-OLED 디스플레이가 주로 적용한다. 이러한 AM-OLED 디스플레이의 화소 스위칭 소자로서는 높은 집적도 하에서도 높은 전하 이동도(mobility)와 높은 신뢰도(reliability)를 가지는 저온 다결정 실리콘 박막 트랜지스터(LTPS TFT)가 적합하다.AM-OLED displays are mainly applied to mobile devices of recent smartphones. As the pixel switching device of such an AM-OLED display, a low temperature polycrystalline silicon thin film transistor (LTPS TFT) having high charge mobility and high reliability even under a high degree of integration is suitable.

저온 다결정 실리콘 박막트랜지스터(LTPS TFT)의 제조에는 실리콘의 결정화 위해 ELA (Excimer Laser Annealing)가 주로 적용 된다. 이러한 LTPS TFT의 단점은 대면적 디스플레이에 적용했을 때 일정 수준의 결정립 균일성(crystal grain uniformity) 유지에 어려움이 있고, 수율(yield)이 낮다.ELA (Excimer Laser Annealing) is mainly applied to the manufacture of low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) to crystallize silicon. The disadvantage of the LTPS TFT is that it is difficult to maintain a certain level of crystal grain uniformity when applied to a large-area display, and the yield is low.

모범적인 실시 예들은 MIC 기술을 이용하여 <111> 배향된 고품질 Si 나노와이어의 형성방법을 제시한다.Exemplary embodiments suggest a method of forming high quality Si nanowires oriented <111> using MIC technology.

모범적인 실시 예들은 Si 나노와이어를 이용하는 반도체 소자 및 그 제조 방법을 제시한다.Exemplary embodiments propose a semiconductor device using Si nanowires and a method of manufacturing the same.

모범적인 실시 예에 따른 반도체 소자의 제조 방법:은Method of manufacturing a semiconductor device according to an exemplary embodiment: silver

기판에 종자층을 형성하는 단계;Forming a seed layer on the substrate;

상기 촉매층 위에 제1도전층, 반도체 실리콘층 그리고 제2도전층 순으로 적층된 다층막을 형성하는 단계;Forming a first conductive layer, a semiconductor silicon layer, and a second conductive layer on the catalyst layer in that order;

상기 다층막을 패터닝하여 상기 기판 상에 수직 나노와이어를 형성하는 단계;Forming vertical nanowires on the substrate by patterning the multilayer film;

열처리에 의해 상기 나노와이어를 결정화하는 단계;Crystallizing the nanowires by heat treatment;

상기 나노와이어를 덮는 절연층을 형성하는 단계;Forming an insulating layer covering the nanowires;

상기 나노와이어의 반도체 실리콘층에 의한 채널영역을 감싸는 게이트를 형성하는 단계; 그리고Forming a gate surrounding the channel region by the semiconductor silicon layer of the nanowire; And

상기 게이트, 제1도전층, 그리고 제2도전층에 전기적으로 연결되는 메탈패드를 형성하는 단계;를 포함한다.And forming a metal pad electrically connected to the gate, the first conductive layer, and the second conductive layer.

모범적인 실시 예에 따르면, 상기 기판 위의 수직 나노와이어를 덮는 것으로 상기 제1도전층, 제2도전층 및 게이트에 대응하는 다수의 컨택홀을 가지는 ILD층을 형성하는 단계; 상기 ILD층 위에 상기 게이트, 제1도전층 및 제2도전층에 각각 대응하는 다수의 메탈 패드를 형성하는 단계;를 더 포함할 수 있다.According to an exemplary embodiment, forming an ILD layer having a plurality of contact holes corresponding to the first conductive layer, the second conductive layer and the gate by covering the vertical nanowires on the substrate; The method may further include forming a plurality of metal pads corresponding to the gate, the first conductive layer, and the second conductive layer, respectively, on the ILD layer.

모범적인 실시 예에 따르면, 상기 촉매층은 NiOx, NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, NixGey 으로 이루어지는 그룹에서 선택된 적어도 어느 하나의 물질로 형성할 수 있다.According to an exemplary embodiment, the catalyst layer may be formed of at least one material selected from the group consisting of NiOx, NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, and NixGey.

모범적인 실시 예에 따르면, 상기 제1도전층, 제2도전층 및 반도체 나노와이어는 Si, SiGe, Ge 중 어느 하나의 물질을 포함할 수 있다.According to an exemplary embodiment, the first conductive layer, the second conductive layer, and the semiconductor nanowire may include any one of Si, SiGe, and Ge.

모범적 실시 예에 따르면, 상기 제1도전층, 제2도전층은 실리콘 도전층이며, 상기 반도체 나노와이어를 실리콘 나노와이어 일 수 있다.According to an exemplary embodiment, the first conductive layer and the second conductive layer may be a silicon conductive layer, and the semiconductor nanowire may be a silicon nanowire.

모범적인 실시 예에 따르면, 상기 다중층은 P형 채널과 N형 실리콘 도전층을 가지는 제1다층막과 N형 채널과 P형 실리콘 도전층을 가지는 제2다층막;을 포함할 수 있다.According to an exemplary embodiment, the multilayer may include a first multilayer film having a P-type channel and an N-type silicon conductive layer, and a second multilayer film having an N-type channel and a P-type silicon conductive layer.

모범적인 실시 예에 따르면, 상기 제1적층 구조물과 제2적층 구조물을 동시에 패터닝하여 제1나노와이어와 제2나노와이어를 형성할 수 있다.According to an exemplary embodiment, the first and second nanowires may be formed by simultaneously patterning the first and second laminated structures.

상기 제조 방법에 따른 반도체 소자:는A semiconductor device according to the manufacturing method:

기판:Board:

상기 기판에 형성되는 소스 또는 드레인 영역의 제1도전층;A first conductive layer in a source or drain region formed on the substrate;

상기 제1도전층 위에 수직으로 직립되어 있는 채널 영역의 반도체 나노와이어;A semiconductor nanowire in a channel region vertically standing on the first conductive layer;

상기 나노와이어의 상단에 마련되는 드레인 또는 소스 영역의 제2도전층;A second conductive layer in a drain or source region provided on an upper end of the nanowire;

상기 수직의 나노와이어를 감싸는 게이트; 그리고A gate surrounding the vertical nanowires; And

상기 채널과 게이트의 사이에 개재되는 게이트 절연층;을 구비한다.And a gate insulating layer interposed between the channel and the gate.

모범적인 실시 예에 따르면, 상기 제1도전층, 제2도전층 및 반도체 나노와이어는 Si, SiGe, Ge 중 어느 하나의 물질을 포함할 수 있다.According to an exemplary embodiment, the first conductive layer, the second conductive layer, and the semiconductor nanowire may include any one of Si, SiGe, and Ge.

모범적 실시 예에 따르면, 상기 제1도전층, 제2도전층은 실리콘 도전층이며, 상기 반도체 나노와이어는 단결정립 실리콘 나노와이어 일 수 있다.According to an exemplary embodiment, the first conductive layer and the second conductive layer may be a silicon conductive layer, and the semiconductor nanowire may be a single crystal grain silicon nanowire.

모범적인 실시 예에 따르면, 상기 제2도전층 위에 메탈층이 형성되며, 제2도전층과 메탈층의 사이에 NiSi2 컨택층이 마련될 수 있다.According to an exemplary embodiment, a metal layer may be formed on the second conductive layer, and a NiSi 2 contact layer may be provided between the second conductive layer and the metal layer.

모범적인 실시 예에 따르면, 상기 기판 위에 반도체 나노와이어를 덮는 것으로 상기 제1도전층, 제2도전층 및 게이트에 대응하는 다수의 컨택홀을 가지는 ILD층이 형성되고, 상기 ILD층 위에는 게이트, 제1도전층 및 제2도전층에 대응하는 메탈패드가 형성될 수 있다.According to an exemplary embodiment, an ILD layer having a plurality of contact holes corresponding to the first conductive layer, the second conductive layer, and the gate is formed by covering the semiconductor nanowire on the substrate, and a gate and a second conductive layer are formed on the ILD layer. Metal pads corresponding to the first conductive layer and the second conductive layer may be formed.

모범적인 실시 예에 따르면, 상기 나노와이어는 원형 또는 다각형의 단면을 가질 수 있다.According to an exemplary embodiment, the nanowire may have a circular or polygonal cross section.

모범적인 실시 예에 따르면, 상기 제1도전층과, 제2도전층은 상기 실리콘 나노와이어의 하부로부터 해당 컨택홀 각각의 직하부까지 연장될 수 있다.According to an exemplary embodiment, the first conductive layer and the second conductive layer may extend from a lower portion of the silicon nanowire to a portion directly under each corresponding contact hole.

상기 반도체 나노와이어 및 제1, 2도전층은 <111> 방향으로 결정이 배향될 수 있다.The semiconductor nanowires and the first and second conductive layers may have crystals oriented in a <111> direction.

모범적인 실시 예는 <111> 방향으로 결정이 성장된 반도체 나노와이어 채널을 제작하는 방법과 이를 응용하여 CMOS를 제작하는 방법을 제시한다. 이러한 모범적인 실시 예는 대면적 기판에 고성능 LSI, 메모리, 센서 등을 제작하여 SOP(System on panel)을 실현할 수 있다. 이러한 모범적 실시 예에 따르면, 기도전층을 형성하기 위한 이온주입(Ion implantation) 공정이 따로 필요 없고 기존의 활성화(activation) 과정도 필요 없다. 따라서 모범적 실시 예에 따라 높은 이동도와 신뢰도가 높고 제품간 특성 산포가 적은 높은 수율의 반도체 소자의 획득이 가능하다.An exemplary embodiment presents a method of fabricating a semiconductor nanowire channel in which a crystal is grown in the <111> direction, and a method of fabricating a CMOS by applying the same. This exemplary embodiment can realize a system on panel (SOP) by fabricating a high-performance LSI, memory, sensor, etc. on a large-area substrate. According to this exemplary embodiment, there is no need for an ion implantation process for forming a conductive layer, and there is no need for a conventional activation process. Therefore, according to an exemplary embodiment, it is possible to obtain a high-yield semiconductor device with high mobility, high reliability, and small product-to-product characteristic distribution.

도1내지 도12는 모범적 실시 예에 따른 수직 나노와이어 반도체 소자의 제조공정의 흐름을 보인다.
도13은 모범적 실시 예에 따른 수직 나노와이어 반도체 소자의 기본 구조를 설명하는 도면이다.1 to 12 show the flow of a manufacturing process of a vertical nanowire semiconductor device according to an exemplary embodiment.
13 is a diagram illustrating a basic structure of a vertical nanowire semiconductor device according to an exemplary embodiment.

이하, 첨부도면을 참조하여 본 발명 개념의 바람직한 실시 예들을 상세히 설명하기로 한다. 그러나, 본 발명 개념의 실시 예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명 개념의 범위가 아래에서 상술하는 실시 예들로 인해 한정 되어는 것으로 해석되어서는 안 된다. 본 발명 개념의 실시 예들은 당 업계에서 평균적인 지식을 가진 자에게 본 발명 개념을 보다 완전하게 설명하기 위해서 제공되는 것으로 해석되는 것이 바람직하다. 동일한 부호는 시종 동일한 요소를 의미한다. 나아가, 도면에서의 다양한 요소와 영역은 개략적으로 그려진 것이다. 따라서, 본 발명 개념은 첨부한 도면에 그려진 상대적인 크기나 간격에 의해 제한되어지지 않는다. 제1, 제2 등의 용어는 다양한 구성 요소들을 설명하는 데 사용될 수 있지만, 상기 구성 요소들은 상기 용어들에 의해 한정되지 않는다. 상기 용어들은 하나의 구성 요소를 다른 구성 요소로부터 구별하는 목적으로만 사용된다. 예를 들어, 본 발명 개념의 권리 범위를 벗어나지 않으면서 제 1 구성 요소는 제 2 구성 요소로 명명될 수 있고, 반대로 제 2 구성 요소는 제 1 구성 요소로 명명될 수 있다.Hereinafter, preferred embodiments of the concept of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the concept of the present invention may be modified in various forms, and the scope of the concept of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the inventive concept are preferably interpreted as being provided in order to more fully explain the inventive concept to a person having average knowledge in the art. Identical symbols mean the same elements all the time. Furthermore, various elements and areas in the drawings are schematically drawn. Accordingly, the inventive concept is not limited by the relative size or spacing drawn in the accompanying drawings. Terms such as first and second may be used to describe various components, but the components are not limited by the terms. These terms are only used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the inventive concept, a first component may be referred to as a second component, and conversely, a second component may be referred to as a first component.

본 출원에서 사용한 용어는 단지 특정한 실시 예들을 설명하기 위해 사용된 것으로서, 본 발명 개념을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함한다. 본 출원에서, “포함한다” 또는 “갖는다” 등의 표현은 명세서에 기재된 특징, 개수, 단계, 동작, 구성 요소, 부분품 또는 이들을 조합한 것이 존재함을 지정하려는 것이지, 하나 또는 그 이상의 다른 특징들이나 개수, 동작, 구성 요소, 부분품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다.Terms used in the present application are only used to describe specific embodiments, and are not intended to limit the concept of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, expressions such as "include" or "have" are intended to designate the existence of features, numbers, steps, actions, components, parts, or a combination thereof described in the specification, but one or more other features or It is to be understood that it does not preclude the possibility of the presence or addition of numbers, actions, components, parts or combinations thereof.

달리 정의되지 않는 한, 여기에 사용되는 모든 용어들은 기술 용어와 과학 용어를 포함하여 본 발명 개념이 속하는 기술 분야에서 통상의 지식을 가진 자가 공통적으로 이해하고 있는 바와 동일한 의미를 지닌다. 또한, 통상적으로 사용되는, 사전에 정의된 바와 같은 용어들은 관련되는 기술의 맥락에서 이들이 의미하는 바와 일관되는 의미를 갖는 것으로 해석되어야 하며, 여기에 명시적으로 정의하지 않는 한 과도하게 형식적인 의미로 해석되어서는 아니 될 것임은 이해될 것이다.Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. In addition, commonly used terms as defined in the dictionary should be construed as having a meaning consistent with what they mean in the context of the technology to which they are related, and in an excessively formal sense unless explicitly defined herein. It will be understood that it should not be interpreted.

어떤 실시 예가 달리 구현 가능한 경우에 특정한 공정 순서는 설명되는 순서와 다르게 수행될 수도 있다. 예를 들어, 연속하여 설명되는 두 공정이 실질적으로 동시에 수행될 수도 있고, 설명되는 순서와 반대의 순서로 수행될 수도 있다.When a certain embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the described order.

첨부 도면에 있어서, 예를 들면, 제조 기술 및/또는 공차에 따라, 도시된 형상의 변형들이 예상될 수 있다. 따라서, 본 발명의 실시 예들은 본 명세서에 도시된 영역의 특정 형상에 제한된 것으로 해석되어서는 아니 되며, 예를 들면 제조 과정에서 초래되는 형상의 변화를 포함하여야 한다. 여기에 사용되는 모든 용어 "및/또는"은 언급된 구성 요소들의 각각 및 하나 이상의 모든 조합을 포함한다. 또한, 본 명세서에서 사용되는 용어 "기판"은 기판 그 자체, 또는 기판과 그 표면에 형성된 소정의 층 또는 막 등을 포함하는 적층 구조체를 의미할 수 있다. 또한, 본 명세서에서 "기판의 표면"이라 함은 기판 그 자체의 노출 표면, 또는 기판 위에 형성된 소정의 층 또는 막 등의 외측 표면을 의미할 수 있다. 또한 "상부" 나 "상"이라고 기재된 것은 접촉하여 바로 위에 있는 것뿐만 아니라 비접촉으로 위에 있는 것도 포함할 수 있다.In the accompanying drawings, for example, depending on manufacturing techniques and/or tolerances, variations of the illustrated shape can be expected. Accordingly, the embodiments of the present invention should not be construed as being limited to a specific shape of the region shown in the present specification, but should include, for example, a change in shape resulting from a manufacturing process. All terms "and/or" as used herein include each and every combination of one or more of the recited elements. In addition, the term "substrate" as used herein may refer to a substrate itself, or a laminate structure including a substrate and a predetermined layer or film formed on the surface thereof. In addition, in the present specification, "the surface of the substrate" may mean an exposed surface of the substrate itself, or an outer surface of a predetermined layer or film formed on the substrate. In addition, what is described as "top" or "top" may include not only those directly above in contact but also non-contact above.

이하, 첨부된 도면을 참고하면서 모범적인 실시 예에 따른 수직 나노와이어 트랜지스터를 포함하는 CMOS 소자의 제조 방법의 설명한다. Hereinafter, a method of manufacturing a CMOS device including a vertical nanowire transistor according to an exemplary embodiment will be described with reference to the accompanying drawings.

모범적 실시 예에 따른 나노와이어 트랜지터는, 기판, 상기 기판에 형성되는 소스 또는 드레인 영역의 제1도전층, 상기 제1도전층 위에 수직으로 직립되어 있는 채널 영역의 반도체 나노와이어, 상기 나노와이어의 상단에 마련되는 드레인 또는 소스 영역의 제2도전층, 상기 수직의 나노와이어를 감싸는 게이트; 그리고 상기 채널과 게이트의 사이에 개재되는 게이트 절연층;을 구비한다.The nanowire transistor according to an exemplary embodiment includes a substrate, a first conductive layer in a source or drain region formed on the substrate, a semiconductor nanowire in a channel region vertically standing on the first conductive layer, and the nanowire. A second conductive layer in the drain or source region provided on the top, and a gate surrounding the vertical nanowires; And a gate insulating layer interposed between the channel and the gate.

이러한 모범적 실시 예에 따른 나노와이어 트랜지스터의 제조 방법은, 기판에 촉매층을 형성하는 단계, 상기 촉매층 위에 제1도전층, 반도체 실리콘층 그리고 제2도전층 순으로 적층된 다층막을 형성하는 단계, 상기 다층막을 패터닝하여 상기 기판 상에 나노와이어를 형성하는 단계, 열처리에 의해 상기 나노와이어을 결정화하는 단계, 상기 제1도전층을 덮는 절연층을 형성하는 단계, 상기 나노와이어의 반도체층에 의한 채널영역을 감싸는 게이트를 형성하는 단계; 그리고 상기 게이트, 제1도전층, 그리고 제2도전층에 전기적으로 연결되는 메탈패드를 형성하는 단계;를 포함한다.The method of manufacturing a nanowire transistor according to this exemplary embodiment includes forming a catalyst layer on a substrate, forming a multilayer film stacked on the catalyst layer in order of a first conductive layer, a semiconductor silicon layer, and a second conductive layer, and the multilayer film Patterning to form a nanowire on the substrate, crystallizing the nanowire by heat treatment, forming an insulating layer covering the first conductive layer, surrounding the channel region by the semiconductor layer of the nanowire Forming a gate; And forming a metal pad electrically connected to the gate, the first conductive layer, and the second conductive layer.

이하에서 위와 같은 모범적 실시 예에 기초하여 CMOS의 제조방법을 설명한다. 이하의 기술내용의 이해를 통해서 수직 실리콘 나노와이어 트랜지스터의 구조 및 그 제조 방법도 쉽게 도출해 낼 수 있을 것이다. 이하의 실시 예에서 반도체 물질로서 비정질 실리콘을 이용하여 CMOS 소자를 제조 방법을 예시적으로 설명된다.Hereinafter, a method of manufacturing a CMOS will be described based on the exemplary embodiment as described above. The structure of the vertical silicon nanowire transistor and its manufacturing method can be easily derived through understanding the following technical content. In the following embodiments, a method of manufacturing a CMOS device using amorphous silicon as a semiconductor material will be exemplarily described.

도1에 도시된 바와 같이 기판(100)에 버퍼층(101) 및 촉매층(102)을 순차 형성한다. As shown in FIG. 1, a buffer layer 101 and a catalyst layer 102 are sequentially formed on the substrate 100.

상기 버퍼층(101)은 선행 공정을 통해 이미 형성되어 있는 적층 구조물의 상부 절연층(top-most dielectric layer)에 의해 제공될 수 있다. 상기 버퍼층(101)은 예를 들어 SiO2, SiNx, SiONx 또는 AlOx 등의 절연물질로 형성될 수 있다.The buffer layer 101 may be provided by a top-most dielectric layer of a multilayer structure already formed through a preceding process. The buffer layer 101 may be formed of an insulating material such as SiO 2 , SiNx, SiONx or AlOx.

상기 버퍼층(101) 위에 촉매층(102)은 Ni 계 산화물로서, NiOx, NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, NixGey 으로 이루어지는 그룹에서 선택된 적어도 어느 하나의 물질을 포함할 수 있다.The catalyst layer 102 on the buffer layer 101 is a Ni-based oxide, and contains at least one material selected from the group consisting of NiOx, NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, and NixGey. Can include.

도2에 도시된 바와 같이, 상기 촉매층(102) 위에 비정질 상태의 제1실리콘 도전층(103), 실리콘 반도체층(104) 및 제2실리콘 도전층(105), 그리고 제2실리콘 도전층(105) 위의 메탈층(106)을 포함하는 다층막(ML)을 형성한다. 예를 들어 상기 다층막(ML)은 p형 실리콘 채널과 그 상하의 n형 실리콘 도전층을 가지는 PMOS 트랜지스터를 얻기 위한 n+ a-Si/p a-Si/ n+ a-Si/TiN의 적층구조를 가질 수 있다.2, a first silicon conductive layer 103, a silicon semiconductor layer 104 and a second silicon conductive layer 105, and a second silicon conductive layer 105 in an amorphous state on the catalyst layer 102. ) To form a multilayer film ML including the metal layer 106 above. For example, the multilayer film ML may have a stacked structure of n+ a-Si/p a-Si/ n+ a-Si/TiN for obtaining a PMOS transistor having a p-type silicon channel and an n-type silicon conductive layer above and below it. have.

도3에 도시된 바와 같이, 상기 기판 상에서 제1트랜지스터, 예를 들어 PMOS 트랜지스터 영역으로 정의된 제1트랜지스터(TR1)의 영역에 PR(photoresist) 마스크를 적용하여 다층막(ML)을 패터닝한다. 다층막(ML)의 패터닝은 전통적인 포토리소그래피법을 따룰 수 있다. 이러한 다층막(ML) 패터닝에 의해 제1트랜지스터(TR1)의 영역에만 제1다층막(ML1)이 잔류하고, 나머지 부분에서는 기판(100) 상의 촉매층(102)이 노출되어 있다. As shown in FIG. 3, a photoresist (PR) mask is applied to a region of the first transistor TR1 defined as a first transistor, for example, a PMOS transistor region, on the substrate to pattern the multilayer film ML. Patterning of the multilayer film (ML) may follow a traditional photolithography method. By this patterning of the multilayer film ML, the first multilayer film ML1 remains only in the region of the first transistor TR1, and the catalyst layer 102 on the substrate 100 is exposed in the remaining part.

도4에 도시된 바와 같이, 상기 기판(100) 상에서 제2트랜지스터(TR2)의 영역으로 정의된 부분에 제2트랜지스터, 예를 들어 NMOS 트랜지스터를 형성하기 위한 제2다층막(ML2)을 형성한다. 제2다층막(ML2)은 p+ a-Si/n a-Si/ p+ a-Si/TiN 의 적층 구조를 가질 수 있다. 이러한 제2다층막(ML2)은 제1다층막(ML1)의 형성 과정과 유사한 과정을 통해서 얻을 수 있으며, 하부로부터 제1실리콘 도전층(107), 실리콘 반도체층(108), 제2실리콘 도전층(109) 및 메탈층(110)가 적층된 구조를 가진다.As shown in FIG. 4, a second multilayer film ML2 for forming a second transistor, for example, an NMOS transistor, is formed on the substrate 100 in a portion defined as a region of the second transistor TR2. The second multilayer film ML2 may have a stacked structure of p+ a-Si/n a-Si/ p+ a-Si/TiN. The second multilayer film ML2 can be obtained through a process similar to the process of forming the first multilayer film ML1, and the first silicon conductive layer 107, the silicon semiconductor layer 108, and the second silicon conductive layer ( 109) and the metal layer 110 are stacked.

도5에 도시된 바와 같이 제1다층막(ML1)과 제2다층막(ML2)를 동시에 패터닝하여 수직의 제1트랜지스터와 제2트랜지스터를 위한 제1실리콘 나노와이어(W1)와 제2실리콘 나노와이어(W2)를 상기 제1, 제2실리콘 도전층(103, 107)위에 형성한다. 여기에서, 패터닝은 실리콘 반도체층(104, 108)까지만 진행되고 그 하부의 제1실리콘 도전층(103, 107)은 패터닝에서 제외된다. 따라서 제1실리콘 도전층(103, 107)은 제1, 제2실리콘 나노와이어(W1, W2)의 바깥으로 연장되어 후술하는 ILD 층의 해당 컨택홀의 직하부까지 연장된다.As shown in Fig. 5, the first and second silicon nanowires (W1) and the second silicon nanowires (W1) and the second silicon nanowires ( W2) is formed on the first and second silicon conductive layers 103 and 107. Here, the patterning proceeds only up to the silicon semiconductor layers 104 and 108, and the first silicon conductive layers 103 and 107 below the silicon semiconductor layers 103 and 107 are excluded from the patterning. Accordingly, the first silicon conductive layers 103 and 107 extend outward of the first and second silicon nanowires W1 and W2 to extend directly under the corresponding contact hole of the ILD layer to be described later.

상기 제1, 제2실리콘 나노와이어(W1, W2)는 원기둥의 형태를 가질 수 있으며, 다른 실시 예에 따르면, 사각기둥 또는 그 이상의 다각형 기둥의 형상을 가질 수 있으며, 이러한 실리콘 나노와이어의 특정한 구조나 형상은 다양한 모범적 실시 예들의 기술적 범위를 제한하지 않는다.The first and second silicon nanowires (W1, W2) may have the shape of a cylinder, and according to another embodiment, may have a shape of a square pillar or a polygonal pillar of more than that, a specific structure of such a silicon nanowire B shape does not limit the technical scope of the various exemplary embodiments.

도6에 도시된 바와 같이 저온 열처리를 통해 MIC(metal induced crystallization)를 수행하여 제1, 제2실리콘 와이어(W1, W2)를 결정화한다. 이 결정화 과정에서 촉매층의 Ni 이 Si 와 반응하여 NiSi2 가 생성되며, 이는 제1, 제2실리콘 와이어(W1, W2)의 최상부로 제2실리콘도전층(106, 109) 에 도달하여 제2실리콘 도전층과 메탈층간의 NiSi2 컨택층(102')을 형성하게 된다.As shown in FIG. 6, metal induced crystallization (MIC) is performed through low-temperature heat treatment to crystallize the first and second silicon wires W1 and W2. In this crystallization process, Ni in the catalyst layer reacts with Si to generate NiSi 2 , which reaches the top of the first and second silicon wires (W1, W2) to the second silicon conductive layers (106, 109), A NiSi 2 contact layer 102' between the conductive layer and the metal layer is formed.

결정화된 나노와이어는 (111) 방향으로 결정 배향성을 가진다. 이러한 열처리 후에, HNO3 또는 HF 등을 이용한 습식 크리닝에 의해 단결정립 실리콘 나노와이어의 외주면에 존재할 수 있는 NiSi2 를 제거할 수 있다.The crystallized nanowires have crystal orientation in the (111) direction. After such heat treatment, NiSi 2 that may exist on the outer peripheral surface of the single crystal silicon nanowire may be removed by wet cleaning using HNO 3 or HF.

도7에 도시된 바와 같이, 상기 기판(100)의 제1실리콘 도전층(103, 107) 위에 제1절연층(111)을 소정 두께로 형성한다. 이는 폴리이미드(PI) 등 유기 절연체 혹은 고밀도 플라즈마 산화물(HDP oxide)막을 형성하고 에치백하는 방법으로 제작할 수 있다. 이때에 제1, 제2실리콘 나노와이어(W1, W2)의 하부 일부만 덮이며, 그 두께는 후속 과정에서 형성될 게이트의 하단 경계의 위치에 따라 설정된다.As shown in FIG. 7, a first insulating layer 111 is formed on the first silicon conductive layers 103 and 107 of the substrate 100 to a predetermined thickness. This can be produced by forming an organic insulator such as polyimide (PI) or a high-density plasma oxide (HDP oxide) film and etching back. At this time, only a portion of the lower portion of the first and second silicon nanowires W1 and W2 is covered, and the thickness is set according to the position of the lower boundary of the gate to be formed in a subsequent process.

도8에 도시된 바와 같이, 상기 제1, 제2실리콘 나노와이어(W1, W2)의 측면에 게이트 절연층(112)과 게이트(113)를 형성 한다. 이 과정은 절연물질과 게이트 물질의 증착 및 패터닝 공정을 수반한다. 여기에서 게이트 절연층(112)은 SiO2로 형성될 수 있으며, 게이트(113)는 MoW로 형성될 수 있다. 이때에 게이트 절연층(112)과 게이트(113)는 미완성 상태로서 상기 제1, 제2실리콘 나노와이어(W1, W2)의 상단 부분도 덮고 있다. 그리고 게이트(113)의 하부에는 게이트(113)의 외부 접속을 위한 터미널로서의 패드(113a)가 마련되는데, 이것은 기판(100)의 평면에 나란한 방향으로 소정 길이 연장된다.As shown in FIG. 8, a gate insulating layer 112 and a gate 113 are formed on the side surfaces of the first and second silicon nanowires W1 and W2. This process involves deposition and patterning of an insulating material and a gate material. Here, the gate insulating layer 112 may be formed of SiO 2 , and the gate 113 may be formed of MoW. At this time, the gate insulating layer 112 and the gate 113 are in an unfinished state and cover upper portions of the first and second silicon nanowires W1 and W2 as well. Further, a pad 113a as a terminal for external connection of the gate 113 is provided under the gate 113, which extends a predetermined length in a direction parallel to the plane of the substrate 100.

도9에 도시된 바와 같이, 상기 기판(100)의 위에 제2절연층(114)를 평탄화 막으로서 소정 두께로 형성한다. 제2절연층(114)의 상면은 제1, 제2실리콘 나노와이어(W1, W2)의 컨택층(102')의 아래에 위치한다. 이러한 제2절연층(114)은 제1, 제2실리콘 나노와이어(W1, W2)의 상부에 존재하는 게이트 절연층(112)과 게이트(113)의 불필요 부분의 제거를 위한 마스크로서 사용된다. 이와 같이 높이 또는 두께가 조절된 제2절연층(114)은 폴리이미드(PI) 등의 유기물 절연체 혹은 HDP 산화물 (oxide) 막을 형성하고 에치백하는 방법으로 제작할 수 있다.9, a second insulating layer 114 is formed on the substrate 100 to have a predetermined thickness as a planarization film. The upper surface of the second insulating layer 114 is located under the contact layer 102 ′ of the first and second silicon nanowires W1 and W2. The second insulating layer 114 is used as a mask for removing unnecessary portions of the gate insulating layer 112 and the gate 113 existing on the first and second silicon nanowires W1 and W2. The second insulating layer 114 whose height or thickness is adjusted as described above may be manufactured by forming an organic insulator such as polyimide (PI) or an HDP oxide film, followed by etching back.

도10에 도시된 바와 같이, 상기 제2절연층(114)에 덮이지 않은 게이트(113)과 게이트 절연층(112)의 노출 부분을 등방성 식각(isotropic etch)에 의해 제거하여 제1, 제2실리콘 나노와이어(W1, W2)의 상부의 제2실리콘 도전층(106, 110)과 그 하부의 컨택층(102')을 완전히 노출시킨다. 이러한 과정에서 미완성의 게이트(113)가 완성된다.As shown in FIG. 10, the gate 113 that is not covered by the second insulating layer 114 and the exposed portion of the gate insulating layer 112 are removed by isotropic etching to remove the first and second insulating layers. The second silicon conductive layers 106 and 110 above the silicon nanowires W1 and W2 and the contact layer 102' below the second silicon conductive layers 106 and 110 are completely exposed. In this process, the unfinished gate 113 is completed.

도11에 도시된 바와 같이, 상기 기판(100)에 다수의 컨택홀(115a, 115b, 115c)(116a, 116b, 116c)을 가지는 ILD(115)를 형성한다. 상기 ILD(115)는 제1실리콘 나노와이어(W1)에 의한 제1트랜지스터 및 제2실리콘 나노와이어(W2)에 의한 실리콘 나노와이어 트랜지스터에 의한 CMOS 반도체 소자를 덮는 것이다.As shown in FIG. 11, an ILD 115 having a plurality of contact holes 115a, 115b, 115c) (116a, 116b, 116c) is formed in the substrate 100. The ILD 115 covers a CMOS semiconductor device made of a first transistor made of a first silicon nanowire W1 and a silicon nanowire transistor made of a second silicon nanowire W2.

도12에 도시된 바와 같이 상기 ILD(115) 위에 상기 (115a, 115b, 115c)(116a, 116b, 116c)을 통해 그 하부의 제1, 제2트랜지스터의 제1, 2반도체 도전층 및 게이트에 전기적으로 연결되는 금속 패드(117a, 117b, 117c)(118a, 118b, 118c)를 형성한다.As shown in Fig. 12, through the (115a, 115b, 115c) (116a, 116b, 116c) on the ILD (115), the first and second semiconductor conductive layers and gates of the lower first and second transistors are Metal pads 117a, 117b, 117c and 118a, 118b, 118c that are electrically connected are formed.

이와 같은 공정에 후속하여 적용대상 전자 소자의 설계에 따라 추가 공정이 수행될 수 있다.Following this process, an additional process may be performed according to the design of the electronic device to be applied.

위의 실시 예를 통해 예시적으로 설명된 나노와이어 반도체 소자는 도13에 개략적으로 도시된 바와 같이 기판에 나란하게 배치되는 소스와 드레인의 사이에 수직의 채널인 단결정립 실리콘 나노와이어와 이를 에워싸는 게이트를 구비한다. 여기에서, 상기 실리콘 나노와이어는 (111) 방향으로 성장된 결정 구조를 가진다.The nanowire semiconductor device exemplarily described through the above embodiment is a single crystal grained silicon nanowire that is a vertical channel between a source and a drain disposed parallel to the substrate as schematically shown in FIG. 13, and a gate surrounding it. It is equipped with. Here, the silicon nanowires have a crystal structure grown in the (111) direction.

상기 실리콘 나노와이어의 결정 성장은 MIC에 의존하면, 결정화 촉매층으로는 수 나노미터 두께의 NiOx, NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, NixGey 등으로 형성되는 비정질막을 적용할 수 있다. 이러한 촉매층의 형성은 ALD 방법으로 증착 할 수 있다. 위의 실시 예의 설명에서 채널에 해당하는 실리콘 반도체층은 n 타입 또는 p 타입의 불순물로 도핑될 수 있고, 다른 실시 예에 따르면, 진성 실리콘으로 형성될 수 도 있다.When the crystal growth of the silicon nanowires depends on the MIC, the crystallization catalyst layer is amorphous formed of several nanometers thick NiOx, NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, NixGey, etc. Membrane can be applied. The formation of such a catalyst layer can be deposited by the ALD method. In the description of the above embodiment, the silicon semiconductor layer corresponding to the channel may be doped with n-type or p-type impurities, and according to another embodiment, may be formed of intrinsic silicon.

비정질 실리콘을 결정화를 위한 MIC 열처리는 보통 가열로(furnace)에서 진행 할 수 있고 전자기장이 있는 가열로(furnace)에서 진행할 수 있다. 채널을 제공하는 수직의 실리콘 나노와이어의 경우 결정화 유도한 NiSi2는 제2실리콘 도전층의 최상면에 까지 올라가서 표면까지 올라가 메탈층과 접촉하여 컨택층으로서의 기능을 가지게 된다. 모범적 실시 예에서 설명되는 실리콘 나노와이어는 트랜지스터뿐 아니, 메모리 소자, 다이오드의 제조에도 적용할 수 있다.MIC heat treatment for crystallization of amorphous silicon can usually be performed in a furnace and can be performed in a furnace with an electromagnetic field. In the case of a vertical silicon nanowire providing a channel, the crystallization-induced NiSi 2 rises to the top surface of the second silicon conductive layer, rises to the surface, and contacts the metal layer to function as a contact layer. The silicon nanowires described in the exemplary embodiment can be applied not only to transistors, but also to manufacturing memory devices and diodes.

위의 실시 예의 설명에서 하나의 트랜지스터가 하나의 나노와이어를 포함하는 것으로 기술되었으나, 다른 실시 예에 따르면 하나의 다수 트랜지스터가 다수의 나노와이어를 포함함으로써 하나의 트랜지스터가 멀티 채널의 구조를 가질 수 있다.In the description of the above embodiments, one transistor has been described as including one nanowire, but according to another embodiment, one transistor may have a multi-channel structure because one transistor includes a plurality of nanowires. .

또한, 위와 같은 반도체 소자에 있어서, 제1도전층과 제2도전층 각각에 대한 도핑타입(type)을 달리하여 p+-i-n+ 혹은 n+-i-p+ 구조의 터널링 효과 트랜지스터(tunneling field effect transistor)를 제작할 수 있다. In addition, in the above semiconductor device, a tunneling field effect transistor having a p+-i-n+ or n+-i-p+ structure by different doping types for each of the first conductive layer and the second conductive layer. ) Can be produced.

전술할 실시 예에서 반도체 물질로 실리콘을 적용한 예가 설명되었으나, 실리콘 외에 SiGe, Ge 등으로 형성될 수 있다.In the above-described embodiment, an example of applying silicon as a semiconductor material has been described, but may be formed of SiGe, Ge, etc. in addition to silicon.

본 발명의 다른 실시 예에 따르면, 위와 같은 방법에 기초하여 다결정 실리콘 기판 혹은 이종 기판 위에 실리콘 솔라 셀을 제작 할 수도 있으며, 3D 적층 구조를 제작하여 3D 적층 메모리를 제작 할 수 있고, 다양한 소자를 하나의 기판 위에 집적(integration)할 수 있다. According to another embodiment of the present invention, a silicon solar cell may be manufactured on a polycrystalline silicon substrate or a heterogeneous substrate based on the above method, and a 3D stacked memory may be manufactured by fabricating a 3D stacked structure. Can be integrated on the substrate of.

본 발명의 실시 예에 따른 반도체 소자 제조 방법은 이해를 돕기 위하여 도면에 도시된 실시 예를 참고로 설명되었으나, 이는 예시적인 것에 불과하며, 당해 분야에서 통상적 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시 예가 가능하다는 점을 이해할 것이다. 따라서, 본 발명의 진정한 기술적 보호 범위는 첨부된 특허청구범위에 의해 정해져야 할 것이다.The method of manufacturing a semiconductor device according to an embodiment of the present invention has been described with reference to the embodiment shown in the drawings for better understanding, but this is only an example, and various modifications and equivalents therefrom are those of ordinary skill in the art. It will be appreciated that other embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the appended claims.

Claims (13)

기판에 촉매물질로 촉매층을 형성하는 단계;
상기 촉매층 위에 제1도전층, 반도체층, 제2도전층, 그리고 메탈층 순으로 적층된 다층막을 형성하는 단계;
상기 다층막을 패터닝하되, 반도체층, 제2도전층 및 메탈층이 포함된 수직의 나노와이어를 형성하는 단계;
저온 열처리에 의한 MIC(metal induced crystallization) 과정에 의해 상기 나노와이어를 결정화하되, 상기 촉매층에 접촉된 제1도전층에서 시작된 결정성장이 상기 제2도전층까지 도달되게 하여 상기 제1도전층과 제2도전층의 결정화에 의한 활성화를 유도하고 제1도전층 위에 단결정립 결정 구조를 가지는 나노와이어를 형성함과 아울러, 그리고 상기 MIC 과정에서 생성된 촉매물질의 반응물질이 상기 제2도전층과 메탈층과의 사이에 도달시켜 상기 제2도전층과 메탈층 사이의 컨택층을 형성하는 단계;
상기 나노 와이어를 덮는 절연층을 형성하는 단계;
상기 나노 와이어의 반도체층에 의한 채널영역을 감싸는 게이트를 형성하는 단계; 그리고
상기 게이트, 제1도전층, 그리고 제2도전층에 전기적으로 연결되는 메탈패드를 형성하는 단계;를 포함하는 나노와이어 반도체 소자의 제조 방법.Forming a catalyst layer on a substrate with a catalyst material;
Forming a first conductive layer, a semiconductor layer, a second conductive layer, and a metal layer on the catalyst layer in that order;
Patterning the multilayer film, forming a vertical nanowire including a semiconductor layer, a second conductive layer, and a metal layer;
The nanowires are crystallized by a metal induced crystallization (MIC) process by low temperature heat treatment, and the crystal growth started in the first conductive layer in contact with the catalyst layer reaches to the second conductive layer. 2 Induces activation by crystallization of the conductive layer and forms a nanowire having a single crystal grain structure on the first conductive layer, and the reactant material of the catalyst material generated in the MIC process is mixed with the second conductive layer and the metal. Forming a contact layer between the second conductive layer and the metal layer by reaching between the layer;
Forming an insulating layer covering the nanowires;
Forming a gate surrounding the channel region by the semiconductor layer of the nanowire; And
Forming a metal pad electrically connected to the gate, the first conductive layer, and the second conductive layer; a nanowire semiconductor device manufacturing method comprising a. 제1항에 있어서,
상기 기판 위에, 상기 수직의 나노와이어를 덮는 것으로 상기 제1도전층, 제2도전층 및 게이트에 대응하는 다수의 컨택홀을 가지는 ILD층을 형성하는 단계; 그리고
상기 ILD층 위에 상기 게이트, 제1도전층 및 제2도전층에 각각 대응하는 다수의 메탈 패드를 형성하는 단계;를 더 포함하는, 나노와이어 반도체 소자의 제조 방법. The method of claim 1,
Forming an ILD layer having a plurality of contact holes corresponding to the first conductive layer, the second conductive layer, and the gate by covering the vertical nanowires on the substrate; And
Forming a plurality of metal pads respectively corresponding to the gate, the first conductive layer, and the second conductive layer on the ILD layer; further comprising, a method of manufacturing a nanowire semiconductor device. 제1항 또는 제2항에 있어서,
상기 촉매물질은 NiOx, NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, NixGey 으로 이루어지는 그룹에서 선택된 적어도 어느 하나의 물질인, 나노와이어 반도체 소자의 제조 방법.The method according to claim 1 or 2,
The catalyst material is at least one material selected from the group consisting of NiOx, NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, NixGey, a method of manufacturing a nanowire semiconductor device. 제1항 또는 제2항에 있어서,
상기 제1도전층, 제2도전층 및 나노와이어는 Si, SiGe, Ge 중 어느 하나의 물질을 포함하는, 나노와이어 반도체 소자의 제조 방법.The method according to claim 1 or 2,
The first conductive layer, the second conductive layer and the nanowire include any one of Si, SiGe, Ge, a method of manufacturing a nanowire semiconductor device. 제4항에 있어서,
상기 다층막은 p형 채널과 n형 도전층을 가지는 제1다층막과 n형 채널과 p형 도전층을 가지는 제2다층막;을 포함하는, 수직 나노와이어 반도체 소자의 제조 방법.The method of claim 4,
The multilayer film includes a first multilayer film having a p-type channel and an n-type conductive layer and a second multilayer film having an n-type channel and a p-type conductive layer. 제5항에 있어서,
상기 제1다층막과 제2다층막을 동시에 패터닝하여 PMOS 반도체 소자를 위한 제1나노와이어와 NMOS 반도체 소자를 위한 제2나노와이어를 형성하는, 수직 나노와이어 반도체 소자의 제조 방법.The method of claim 5,
A method of manufacturing a vertical nanowire semiconductor device, wherein the first multilayer film and the second multilayer film are simultaneously patterned to form a first nanowire for a PMOS semiconductor device and a second nanowire for an NMOS semiconductor device. 제1항에 있어서,
상기 다층막은 p형 채널과 n형 도전층을 가지는 제1다층막과 n형 채널과 p형 도전층을 가지는 제2다층막;을 포함하는, 수직 나노와이어 반도체 소자의 제조 방법.The method of claim 1,
The multilayer film includes a first multilayer film having a p-type channel and an n-type conductive layer and a second multilayer film having an n-type channel and a p-type conductive layer. 제1항 또는 제2항의 제조 방법에 의해 제조되는 수직의 나노와이어 반도체 소자에 있어서,
기판:
상기 기판에 형성되는 소스 또는 드레인 영역의 제1도전층;
상기 제1도전층 위에 위치하는 수직의 채널 영역으로서의 단결정립 반도체 나노와이어;
상기 수직의 단결정립 반도체 나노 와이어 위에 형성되는 드레인 또는 소스 영역의 제2도전층;
상기 제2도전층 위에 형성되는 컨택층; 그리고
상기 컨택층 위에 마련되는 메탈층;을 포함하는, 수직 나노와이어 반도체 소자.In the vertical nanowire semiconductor device manufactured by the manufacturing method of claim 1 or 2,
Board:
A first conductive layer in a source or drain region formed on the substrate;
A single crystal grain semiconductor nanowire as a vertical channel region positioned on the first conductive layer;
A second conductive layer in a drain or source region formed on the vertical single crystal grain semiconductor nanowire;
A contact layer formed on the second conductive layer; And
A vertical nanowire semiconductor device comprising; a metal layer provided on the contact layer. 제8항에 있어서,
상기 촉매물질은 NiOx, NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, NixGey 으로 이루어지는 그룹에서 선택된 적어도 어느 하나의 물질인, 수직 나노와이어 반도체 소자.The method of claim 8,
The catalyst material is at least one material selected from the group consisting of NiOx, NiCxOy, NiNxOy, NiCxNyOz, NiCxOy:H, NiNxOy:H, NiCxNyOz:H, NixSiy, NixGey, vertical nanowire semiconductor device. 제8항에 있어서,
상기 제1도전층, 제2도전층 및 반도체 나노와이어는 Si, SiGe, Ge 중 어느 하나의 물질을 포함하는, 수직 나노와이어 반도체 소자.The method of claim 8,
The first conductive layer, the second conductive layer, and the semiconductor nanowire include any one of Si, SiGe, and Ge, a vertical nanowire semiconductor device. 제9항에 있어서,
상기 제1도전층, 제2도전층 및 반도체 나노와이어는 Si, SiGe, Ge 중 어느 하나의 물질을 포함하는, 수직 나노와이어 반도체 소자.The method of claim 9,
The first conductive layer, the second conductive layer, and the semiconductor nanowire include any one of Si, SiGe, and Ge, a vertical nanowire semiconductor device. 제8항에 있어서,
상기 반도체 나노와이어는 PMOS 반도체 소자를 위한 제1나노와이어와 NMOS 반도체 소자를 위한 제2나노와이어를 포함하는, 수직 나노와이어 반도체 소자.The method of claim 8,
The semiconductor nanowire includes a first nanowire for a PMOS semiconductor device and a second nanowire for an NMOS semiconductor device. 제12항에 있어서,
상기 PMOS 반도체 소자와 NMOS 반도체 소자 각각은 다수의 나노와이어에 의한 멀티 채널의 구조를 가지는, 수직 나노와이어 반도체 소자..The method of claim 12,
Each of the PMOS semiconductor device and the NMOS semiconductor device has a multi-channel structure of a plurality of nanowires.
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