JP2009016600A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the malfunction of a thin film transistor for achieving a high-speed operation is suppressed. <P>SOLUTION: The semiconductor device by this invention includes: a transparent substrate (112) provided with a front surface (112a) and a back surface (112b); a first semiconductor layer (120) supported by the front surface (112a) of the transparent substrate (112); an insulating layer (114) selectively provided on the first semiconductor layer (120); and a second semiconductor layer (130) including the active layer (132) of the thin film transistor (140), wherein the active layer (132) faces the first semiconductor layer (120) through the insulating layer (114). The first semiconductor layer (120) contains a gettering element and a catalyst element accelerating the crystallization of the second semiconductor layer, and the active layer (132) overlaps with the first semiconductor layer (120) when viewed from the normal direction of the back surface (112b) of the transparent substrate (112). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, a technique for manufacturing a semiconductor layer having a crystal structure (hereinafter referred to as a crystalline semiconductor layer) by crystallizing an amorphous semiconductor layer formed over an insulating substrate such as a glass substrate has been widely studied. . The crystalline semiconductor layer is, for example, a polycrystalline semiconductor layer or a microcrystalline semiconductor layer. The crystalline semiconductor layer has higher carrier mobility than the amorphous semiconductor layer, and a thin film transistor (TFT) manufactured using the crystalline semiconductor layer uses the amorphous semiconductor layer. It can operate at higher speed than the fabricated TFT.

  As a method for crystallizing an amorphous semiconductor layer, there is known a CGS (Continuous Grain Silicon) method in which a catalytic element (for example, nickel) serving as a crystallization catalyst is added to an amorphous semiconductor layer and heat treatment is performed. ing. By the CGS method, crystallization can be performed at a low temperature below the strain point of glass. The average crystal grain size of a crystalline semiconductor layer (for example, a polycrystalline silicon layer) obtained by the CGS method is larger than the average crystal grain size of a crystalline semiconductor layer obtained by irradiation with an excimer laser beam, and has a high mobility. Can be realized.

  However, when a TFT is formed using a crystalline semiconductor layer manufactured by the CGS method, the off-current of the TFT may increase suddenly if the catalytic element remains in the channel region. For this reason, it is known that a gettering region for gettering the catalytic element is provided to suppress a sudden increase in off-current (for example, see Patent Document 1).

  Hereinafter, a conventional method for manufacturing a crystalline semiconductor layer disclosed in Patent Document 1 will be described with reference to FIG.

  First, as illustrated in FIG. 6A, the semiconductor layer 620 is formed on the insulating substrate 612. For example, the insulating substrate 612 is a glass substrate, and the semiconductor layer 620 is an amorphous silicon layer. The amorphous silicon layer is formed by plasma CVD (Chemical Vapor Deposition) or LPCVD (Low Pressure CVD). Thereafter, a nickel acetate film 615 is formed over the semiconductor layer 620.

  Next, as shown in FIG. 6B, the semiconductor layer 620 is crystallized by heat treatment. During the heat treatment, nickel acetate in the nickel acetate film 615 is thermally decomposed into nickel, which promotes crystallization of the semiconductor layer 620. After that, the semiconductor layer 620 is irradiated with an excimer laser beam to perform laser annealing treatment. Thereby, the catalyst element is dispersed. Since an oxide film is formed on the surface of the semiconductor layer 620 in the previous step, the oxide film is removed by hydrofluoric acid treatment.

  Next, as illustrated in FIG. 6C, a resist layer 632 is formed over the semiconductor layer 620. The resist layer 632 is made of, for example, silicon nitride.

  Next, as shown in FIG. 6D, a mask 634 is formed by etching the resist layer 632. After that, phosphorus is implanted as a gettering element into a region 622 of the semiconductor layer 620 that is not covered with the mask 634. The region 622 into which phosphorus is implanted is referred to as a gettering region.

  Next, as shown in FIG. 6E, the catalytic element in the semiconductor layer 620 is gettered into the gettering region 622 by heat treatment. Accordingly, the concentration of the catalytic element in the region covered with the mask 634 in the semiconductor layer 620 decreases.

  Next, as illustrated in FIG. 6F, etching is performed using a mask 634 to remove part of the region other than the gettering region 622 from the semiconductor layer 620 together with the gettering region 622. In this manner, the semiconductor layer 620 having a low catalyst element concentration can be formed. This semiconductor layer 620 is used as an active layer of the TFT.

  It is also known to perform gettering by providing a semiconductor layer separately from the semiconductor layer used as the active layer of the TFT (see, for example, Patent Documents 2 and 3).

  Hereinafter, a conventional method for manufacturing a crystalline semiconductor layer disclosed in Patent Document 2 will be described with reference to FIG.

  First, as shown in FIG. 7A, the first semiconductor layer 720 is formed on the insulating substrate 712. For example, the insulating substrate 712 is a glass substrate, and the first semiconductor layer 720 is an amorphous silicon layer. Next, a mask 734 is formed over the first semiconductor layer 720. The mask 734 is made of, for example, silicon oxide. The mask 734 is provided with an opening, and a part of the first semiconductor layer 720 is exposed from the opening of the mask 734.

  Next, a nickel acetate film 715 is formed over the first semiconductor layer 720 and the mask 734. Nickel is a catalyst element for promoting crystallization, whereby the catalyst element is imparted to the first semiconductor layer 720.

  Next, as shown in FIG. 7B, heat treatment is performed to crystallize the first semiconductor layer 720. During the heat treatment, nickel in the nickel acetate film 715 moves laterally in the first semiconductor layer 720 from a portion corresponding to the opening of the mask 734. Thereby, crystallization of the first semiconductor layer 720 is promoted.

  Next, as illustrated in FIG. 7C, a silicon oxide film 736 is formed over the region of the first semiconductor layer 720 exposed from the opening of the mask 734. Thereafter, a second semiconductor layer 730 covering the mask 734 and the silicon oxide film 736 is formed. The second semiconductor layer 730 contains phosphorus as a gettering element.

  Next, as shown in FIG. 7D, heat treatment is performed, and at least a part of the catalytic element in the first semiconductor layer 720 is transferred from the first semiconductor layer 720 to the second semiconductor layer 730 through the silicon oxide film 736. The catalyst element in the first semiconductor layer 720 is gettered to the second semiconductor layer 730. As a result, the concentration of the catalytic element in the first semiconductor layer 720 decreases.

  Next, as shown in FIG. 7E, the second semiconductor layer 730 and the mask 734 are removed. In this manner, the first semiconductor layer 720 having a low catalytic element concentration can be formed. The first semiconductor layer 720 is used as an active layer of the TFT.

  Next, a conventional method for manufacturing a semiconductor device disclosed in Patent Document 3 will be described with reference to FIG.

  First, as shown in FIG. 8A, the first semiconductor layer 820 is formed on the insulating substrate 812. The insulating substrate 812 is a glass substrate, and the first semiconductor layer 820 is an amorphous silicon layer. The first semiconductor layer 820 is formed by a sputtering method. The first semiconductor layer 820 contains argon as a gettering element.

  Next, as illustrated in FIG. 8B, a first insulating layer 814 is formed on the first semiconductor layer 820. The first insulating layer 814 is made of silicon oxide. The first insulating layer 814 is formed by a plasma CVD method.

  Next, as illustrated in FIG. 8C, the second semiconductor layer 830 is formed on the first insulating layer 814. The second semiconductor layer 830 is an amorphous silicon layer. The second semiconductor layer 830 is formed by a plasma CVD method.

  Next, as shown in FIG. 8D, nickel is added to the second semiconductor layer 830 as a catalyst element. Nickel is applied to the entire surface of the second semiconductor layer 830. Thereafter, heat treatment is performed. By this heat treatment, the second semiconductor layer 830 is crystallized, and nickel present in the second semiconductor layer 830 is gettered to the first semiconductor layer 820.

  Next, as shown in FIG. 8E, the second semiconductor layer 830 is irradiated with a laser beam. Thereby, the crystallinity of the second semiconductor layer 830 is improved. An excimer laser beam is used as the laser beam.

  Next, as illustrated in FIG. 8F, part of the second semiconductor layer 830 is removed, and element isolation is performed. The second semiconductor layer 830 thus formed is used as an active layer of the TFT. Thereafter, a second insulating layer 816 is formed over the second semiconductor layer 830.

  Next, as illustrated in FIG. 8G, a metal layer 842 is formed on the second insulating layer 816. The metal layer 842 functions as a gate electrode of the TFT.

  Next, as illustrated in FIG. 8H, an impurity element is implanted into a region of the second semiconductor layer 830 that is not covered with the metal layer 842. The impurity element is implanted, for example, by an ion doping method. The TFT 840 is manufactured as described above.

  Further, when light enters the active layer of the TFT, the TFT may malfunction accordingly. In particular, when an active matrix substrate of a liquid crystal display device is manufactured using a semiconductor device, the TFT is likely to malfunction due to backlight light. In order to prevent such a malfunction of the TFT, it is known to provide a light shielding film (for example, see Patent Document 4).

FIG. 9 shows a liquid crystal display device 900 disclosed in Patent Document 4. The liquid crystal display device 900 is provided with a conductive light-shielding film 950 extending below both the TFT 940 and the auxiliary capacitance wiring 942. The conductive light-shielding film 950 is made of a metal or a metal compound, and forms a capacitor with the semiconductor layer 920 that is electrically connected to the pixel electrode 944. Therefore, the conductive light shielding film 950 not only functions as a light shielding film for the semiconductor layer 920 but also reduces the leakage current of the TFT 940.
JP-A-10-223533 JP-A-11-354448 JP 2003-100629 A JP 2000-47254 A

  In the manufacturing method disclosed in Patent Document 1, the gettering region is removed after crystallization using a catalytic element. In the manufacturing method disclosed in Patent Document 2, the second semiconductor layer including the gettering region is removed after crystallization using a catalytic element. Thus, in the manufacturing methods disclosed in Patent Document 1 and Patent Document 2, since the semiconductor layer containing the gettering element or a part thereof is removed, the number of manufacturing steps and manufacturing time of the crystalline semiconductor layer are removed. Therefore, a TFT that operates at high speed cannot be easily manufactured.

  Further, in the manufacturing method disclosed in Patent Document 3, crystal growth in which the catalytic element moves in the horizontal direction and gettering in which the catalytic element moves in the vertical direction proceed simultaneously. For this reason, if the insulating layer provided between the first semiconductor layer and the second semiconductor layer is thick, crystal growth takes precedence over gettering, and crystalline silicon having a large grain size can be obtained while gettering is obtained. There is a possibility that the ring is not performed sufficiently. In addition, if the insulating layer provided between the first semiconductor layer and the second semiconductor layer is thin, gettering takes precedence over crystal growth. There is a possibility that the diameter becomes small or a region that is not sufficiently crystallized remains in the semiconductor layer. As described above, in the manufacturing method of Patent Document 3, a problem occurs whether the insulating layer is thick or thin, and a margin for variation in the thickness of the insulating layer is small.

  Further, as in the liquid crystal display device disclosed in Patent Document 4, if a light shielding layer is produced in order to prevent malfunction of the TFT, the number of production steps and production time increase.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which malfunction of a thin film transistor that realizes high-speed operation is suppressed, and a simple manufacturing method thereof.

  A semiconductor device according to the present invention includes a transparent substrate having a front surface and a back surface, a first semiconductor layer supported on the front surface of the transparent substrate, an insulating layer selectively provided on the first semiconductor layer, and a thin film transistor And a second semiconductor layer including an active layer facing the first semiconductor layer with the insulating layer interposed therebetween, wherein the first semiconductor layer includes a gettering element, A catalyst element that promotes crystallization of the second semiconductor layer, and the active layer overlaps the first semiconductor layer when viewed from the normal direction of the back surface of the transparent substrate.

  In one embodiment, the concentration of the catalytic element in the first semiconductor layer is higher than the concentration of the catalytic element in the second semiconductor layer.

  In one embodiment, the active layer has a source region, a channel region, and a drain region, and the first semiconductor layer has a higher electrical conductivity than the channel region of the active layer, The first semiconductor layer functions as a gate for controlling the conductivity of the channel region.

  In one embodiment, the second semiconductor layer further includes a connection part in contact with the first semiconductor layer, and the source region and the drain region of the active layer, and the connection part contain the same impurity element. is doing.

  The method for manufacturing a semiconductor device according to the present invention includes a step of preparing a transparent substrate having a front surface and a back surface, and a first semiconductor layer supported on the front surface of the transparent substrate, the first semiconductor containing a gettering element. A step of forming a layer, a step of selectively forming an insulating layer on the first semiconductor layer, a step of forming a second semiconductor layer covering the first semiconductor layer and the insulating layer, and promoting crystallization A step of applying a catalytic element to the second semiconductor layer, and a step of applying a thermal annealing treatment after applying the catalytic element to the second semiconductor layer, wherein the second semiconductor layer is crystallized. And at least part of the catalytic element in the second semiconductor layer is moved to the first semiconductor layer, and after the thermal annealing treatment, the method of the back surface of the transparent substrate in the second semiconductor layer is performed. From the line direction Comprising a step of a portion overlapping with the first semiconductor layer to form a thin film transistor used as the active layer when the.

  In one embodiment, the step of forming the thin film transistor includes selectively removing a part of the second semiconductor layer, so that a portion of the second semiconductor layer that becomes the active layer of the thin film transistor and the first semiconductor layer are formed. A step of separating the semiconductor layer.

  According to the present invention, it is possible to provide a semiconductor device that suppresses a malfunction of a thin film transistor that realizes a high-speed operation and a simple manufacturing method thereof.

  Hereinafter, embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments.

  First, an embodiment of a semiconductor device according to the present invention will be described with reference to FIG.

  The semiconductor device 100 of the present embodiment is selectively provided on the transparent substrate 112 having the front surface 112a and the back surface 112b, the first semiconductor layer 120 supported by the front surface 112a of the transparent substrate 112, and the first semiconductor layer 120. The first insulating layer 114 and the second semiconductor layer 130 including the active layer 132 of the TFT 140 are provided. The active layer 132 faces the first semiconductor layer 120 with the first insulating layer 114 interposed therebetween. A base coat layer 113 is provided between the transparent substrate 112 and the first semiconductor layer 120. The source region 132a and the drain region 132b of the active layer 132 contain an impurity element and are electrically connected to the source electrode 144 and the drain electrode 146, respectively. The gate electrode 142 faces the channel region 132c of the active layer 132 with the second insulating layer 116 interposed therebetween.

  The first semiconductor layer 120 contains a gettering element and a catalyst element that promotes crystallization of the second semiconductor layer 130. Further, when viewed from the normal direction of the back surface 112b of the transparent substrate 112, the entire active layer 132 overlaps the first semiconductor layer 120, and the active layer 132 extends from the back surface 112b of the transparent substrate 112 in parallel to the normal direction. Light traveling in the direction is blocked by the first semiconductor layer 120. Thereby, the malfunction of the TFT 140 is prevented.

The concentration of the catalytic element in the first semiconductor layer 120 is higher than the concentration of the catalytic element in the second semiconductor layer 130. For example, the concentration of the catalytic element in the first semiconductor layer 120 is 1 × 10 ^{19 to} 9 × 10 ¹⁹ atoms / cm ³ , and the concentration of the catalytic element in the second semiconductor layer 130 is 8 × 10 ¹⁸ to 1 × 10. ¹⁹ atoms / cm ³ . Note that secondary ion mass spectrometry (SIMS) or inductively coupled plasma mass spectrometry (ICP-MS) is used to measure the concentration of the catalytic element.

  Further, in the semiconductor device 100 of the present embodiment, the second semiconductor layer 130 further has a connection portion 135. The connection part 135 contains the same impurity element as the source region 132 a and the drain region 132 b, and the bottom gate voltage input electrode 150 is electrically connected to the first semiconductor layer 120 through the connection part 135.

  In addition, the first semiconductor layer 120 has a higher electrical conductivity than the channel region 132c of the active layer 132 by containing the gettering element. When a voltage is applied from the bottom gate voltage input electrode 150 to the first semiconductor layer 120 via the connection portion 135, the conductivity of the channel region 132c of the active layer 132 can be controlled. Thus, the first semiconductor layer 120 also functions as a bottom gate electrode, and the TFT 140 is a double gate transistor. Note that the structure of the semiconductor device 100 can be easily verified by a cross-sectional structure analysis using an electron microscope or the like.

  Hereinafter, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. 2A to 2F are schematic cross-sectional views showing the manufacturing process of the semiconductor device 100 of the present embodiment, respectively.

  First, as shown in FIG. 2A, a transparent substrate 112 having a front surface 112a and a back surface 112b is prepared, a base coat layer 113 is formed on the front surface 112a of the transparent substrate 112, and then a first coat is formed on the base coat layer 113. A semiconductor layer 120 is formed. The first semiconductor layer 120 is, for example, an n-type amorphous silicon layer containing phosphorus. This phosphorus functions as a gettering element.

  Next, as illustrated in FIG. 2B, the first insulating layer 114 is selectively formed on the first semiconductor layer 120. The first insulating layer 114 is provided with an opening, and the first semiconductor layer 120 is exposed from the opening of the first insulating layer 114.

  Next, as shown in FIG. 2C, a second semiconductor layer 130 that covers the first semiconductor layer 120 and the first insulating layer 114 is formed. Note that a portion of the second semiconductor layer 130 that becomes the active layer of the TFT 140 is a portion that faces the first semiconductor layer 120 with the first insulating layer 114 interposed therebetween, and this portion is referred to as a facing portion 132. In addition, a portion of the second semiconductor layer 130 that is continuous with both the facing portion 132 and the first semiconductor layer 120 is referred to as a continuous portion 134. The facing portion 132 of the second semiconductor layer 130 overlaps the first semiconductor layer 120 when viewed from the normal direction of the back surface 112 b of the transparent substrate 112.

Next, as illustrated in FIG. 2D, a nickel acetate film 115 is formed on the second semiconductor layer 130. Nickel is a catalytic element for promoting crystallization, whereby the catalytic element is imparted to the second semiconductor layer 130. The concentration of the catalytic element in the second semiconductor layer 130 is 2 × 10 ^{19 to} 9 × 10 ²⁰ atoms / cm ³ .

Next, as shown in FIG. 2E, thermal annealing is performed. Thereby, the second semiconductor layer 130 is crystallized. At this time, the catalytic element present in the facing portion 132 of the second semiconductor layer 130 moves in the lateral direction and promotes crystallization of the second semiconductor layer 130. When the catalytic element reaches the continuous portion 134, the catalytic element moves from the continuous portion 134 to the first semiconductor layer 120 containing the gettering element. Accordingly, the concentration of the catalytic element in the first semiconductor layer 120 is 1 × 10 ^{19 to} 9 × 10 ¹⁹ atoms / cm ³ , and the concentration of the catalytic element in the second semiconductor layer 130 is 8 × 10 ¹⁸ to 1 × 10. ¹⁹ atoms / cm ³ . As described above, the second semiconductor layer 130 is crystallized by the thermal annealing treatment, and at least a part of the catalytic element in the second semiconductor layer 130 moves to the first semiconductor layer 120.

  Next, as shown in FIG. 2F, a TFT 140 is formed using the facing portion 132 of the second semiconductor layer 130 as an active layer. Specifically, first, a connection portion 135 separated from the facing portion 132 of the second semiconductor layer 130 is formed by removing a part of the continuous portion 134 of the second semiconductor layer 130. The facing part 132 becomes an active layer of the TFT. After that, the second insulating layer 116 that covers the active layer 132, the connection portion 135, and the first insulating layer 114 is formed, and the gate electrode 142 is formed at a position facing the active layer 132 with the second insulating layer 116 interposed therebetween. After that, an interlayer film 118 that covers the second insulating layer 116 and the gate electrode 142 is formed, and contact holes are formed in the second insulating layer 116 and the interlayer film 118. A source electrode 144, a drain electrode 146, and a bottom gate voltage input electrode 150 are formed in the contact hole. The semiconductor device 100 is manufactured as described above.

  According to the manufacturing method of this embodiment, since gettering is performed together with crystallization by thermal annealing, the manufacturing process and manufacturing time can be shortened. Note that in general, a crystalline semiconductor layer requires a larger number of steps and a longer manufacturing time than an amorphous semiconductor layer. In particular, when a crystalline semiconductor layer is manufactured by the CGS method, the manufacturing method disclosed in Patent Documents 1 and 2 described above with reference to FIGS. 6 and 7 contains a gettering element after gettering. The semiconductor layer or a part thereof is removed. In contrast, in the present embodiment, the first semiconductor layer 120 containing the gettering element is not removed, and the crystalline semiconductor layer can be manufactured in a shorter time than the conventional manufacturing method.

  Further, in the manufacturing method disclosed in Patent Document 3 described above with reference to FIG. 8, the catalyst element in the second semiconductor layer 830 moves not only in the horizontal direction but also in the vertical direction during the thermal annealing process. Gettering is performed by vertical movement. In contrast, in the manufacturing method of the present embodiment, the catalytic element in the facing portion 132 of the second semiconductor layer 130 moves in the lateral direction until reaching the continuous portion 134, and the first semiconductor is passed through the continuous portion 134. Move to layer 120. Since the opposing portion 132 crystallized by moving the catalytic element in the lateral direction is used as the active layer of the TFT 140, the TFT 140 can realize high-speed operation.

  In the present embodiment, the first semiconductor layer 120 containing a gettering element is used as a light shielding layer and a bottom gate. For this reason, the manufacturing process and manufacturing time for separately manufacturing the light shielding layer and the bottom gate can be shortened.

  In the above description, the catalyst element is nickel (Ni), but the present invention is not limited to this. The catalytic element may be Co, Sn, Pb, Pd, Fe, or Cu, or a plurality of these elements.

  In the above description, the gettering element is phosphorus (P), but the present invention is not limited to this. As the gettering element, an element belonging to Group B of the periodic table that imparts n-type other than phosphorus may be used. Moreover, you may use the element which belongs to periodic table group 3 B with the element which belongs to the said periodic table group 5 B as a gettering element. Note that by using phosphorus or boron as the gettering element, the visible light transmittance of the first semiconductor layer 120 is reduced, so that the light-shielding property of the first semiconductor layer 120 can be improved. When the first semiconductor layer 120 is used as a bottom gate electrode, it is preferable to use an element belonging to Group B of the periodic table as a gettering element in order to achieve low resistance.

  Gettering is performed due to the difference in the solid solubility of the catalytic element. Comparing the solid solubility of the catalytic element with respect to the semiconductor layer, the solid solubility of the amorphous semiconductor layer is higher than that of the polycrystalline semiconductor layer, and the amorphous semiconductor layer is doped with an impurity element. The solid solubility of the semiconductor layer is higher than that of an amorphous semiconductor layer not doped with an impurity element. Since the catalytic element moves from the low solid solubility region to the high solid solubility region in the thermal annealing treatment step, the longer the thermal annealing treatment time, the more the catalytic element from the second semiconductor layer 130 becomes. On the contrary, the catalyst element that has moved to the semiconductor layer 120 and has moved from the second semiconductor layer 130 to the first semiconductor layer 120 does not move from the first semiconductor layer 120 to the second semiconductor layer 130. Further, the catalyst element does not move from the second semiconductor layer 130 to the first semiconductor layer 120 in various processes other than the thermal annealing process.

  Next, the manufacturing method of this embodiment will be described in more detail with reference to FIGS.

  First, as shown in FIG. 3A, a transparent substrate 112 having a front surface 112 a and a back surface 112 b is prepared, and a base coat layer 113 is formed on the front surface 112 a of the transparent substrate 112. The transparent substrate 112 is, for example, a glass substrate. The base coat layer 113 is formed by sequentially depositing a silicon oxynitride film and a silicon oxide film by, for example, a plasma enhanced chemical vapor deposition (PE-CVD) method.

Next, as shown in FIG. 3B, the first semiconductor layer 120 is formed on the base coat layer 113. The first semiconductor layer 120 is an n-type amorphous silicon layer containing phosphorus, and this phosphorus functions as a gettering element. The n-type amorphous silicon layer is formed, for example, by a PE-CVD method using SiH ₄ (silane), PH ₃ (phosphine), and NH ₃ mixed gas. The ratio of PH ₃ is about 0.5% of SiH ₄ , and the phosphorus concentration in the first semiconductor layer 120 is 1 × 10 ¹⁹ to 1 × 10 ²² / cm ³ .

  Next, as illustrated in FIG. 3C, the first insulating layer 114 having a thickness of 30 nm to 100 nm (for example, 70 nm) is formed on the first semiconductor layer 120. The first insulating layer 114 is made of a silicon oxide film, a silicon nitride film, or a laminated film thereof, and is formed by a PE-CVD method. Thereafter, an opening is formed by a photolithography method in a region of the first insulating layer 114 that does not correspond to the active layer 132 of the TFT 140. The size of the opening is 1.0 μm □ to 8.0 μm □ (for example, 5 μm □), and a part of the first semiconductor layer 120 is exposed from the opening of the first insulating layer 114.

  Next, as shown in FIG. 3D, a second semiconductor layer 130 covering the first insulating layer 114 and the first semiconductor layer 120 is formed. The second semiconductor layer 130 is an amorphous silicon layer, for example, and is formed by a PE-CVD method. By forming the second semiconductor layer 130 in this way, a part of the second semiconductor layer 130 is in contact with the first semiconductor layer 120. The facing portion 132 of the second semiconductor layer 130 faces the first semiconductor layer 120 via the insulating layer 114, and the continuous portion 134 of the second semiconductor layer 130 is connected to both the facing portion 132 and the first semiconductor layer 120. It is continuous.

  Next, as illustrated in FIG. 3E, a nickel acetate film 115 is formed on the second semiconductor layer 130. The nickel acetate film 115 is formed by spin-coating a nickel acetate aqueous solution having a concentration of 1 to 10 ppm (weight percentage). Thereby, nickel which is a catalytic element is applied to the surface of the second semiconductor layer 130.

  Next, as shown in FIG. 3F, thermal annealing is performed. The thermal annealing treatment is performed, for example, at a temperature of 500 to 650 ° C. for 30 to 180 minutes. Thereby, the second semiconductor layer 130 to which the catalytic element is applied is crystallized by solid phase growth. In addition, since the first semiconductor layer 120 contains a gettering element, the catalytic element that promotes crystallization of the second semiconductor layer 130 during the thermal annealing process is transmitted from the continuous portion 134 of the second semiconductor layer 130 to the first semiconductor. Move to layer 120.

  As a result of the thermal annealing treatment, as shown in FIG. 4G, the second semiconductor layer 130 is crystallized, and at least a part of the catalytic element is gettered to the first semiconductor layer 120.

  Next, as shown in FIG. 4H, a laser annealing process is performed on the second semiconductor layer 130. Thereby, the crystallinity of the second semiconductor layer 130 is further improved. For example, a pulse laser beam having a wavelength of 308 nm is used as the laser beam.

  Next, as shown in FIG. 4I, the second semiconductor layer 130 is patterned. This patterning is performed by a photolithographic method, whereby a part of the continuous portion 134 is removed, and the second semiconductor layer 130 has a facing portion 132 that becomes an active layer of the TFT 140 and a connecting portion that contacts the first semiconductor layer 120. 135. Further, if necessary, the first insulating layer 114 and the first semiconductor layer 120 may be patterned by a photolithography method.

  Next, as illustrated in FIG. 4J, the second insulating layer 116 that covers the active layer 132, the connection portion 135, and the first insulating layer 114 is formed. The second insulating layer 116 is made of, for example, silicon oxide or a laminated film of silicon oxide and silicon nitride, and is formed by a PE-CVD method. The second insulating layer 116 functions as a gate insulating layer of the TFT 140.

  Next, as illustrated in FIG. 4K, the gate electrode 142 is formed on the second insulating layer 116. The gate electrode 142 is formed by forming a gate electrode layer made of a laminated film of tungsten and tantalum nitride by sputtering and patterning the gate electrode layer by photolithography.

  Next, as shown in FIG. 4L, a doping process is performed by self-alignment using the gate electrode 142 as a doping mask. In the case of manufacturing an n-channel TFT, phosphorus is used as a dopant (impurity element). On the other hand, when a p-channel TFT is manufactured, boron is used as a dopant. A dopant is implanted into the source region 132a and the drain region 132b of the active layer 132 by the doping process. Further, the dopant is also implanted into the connection portion 135 by this doping process.

Note that the amount of dopant in the connecting portion 135 and the laser annealing conditions may be equal to the N-type impurity concentration regions in the source region and the drain region. Dopant concentration is 1 × 10 ¹⁹ ~1 × 10 ²² months / cm ³ or so, in the laser annealing, wavelength 308 nm, an excimer laser beam energy 250~450mJ / cm ² is irradiated. For this reason, the characteristics of the source region 132a, the drain region 132b, and the connection portion 135 are substantially equal. Depending on the characteristics required for the TFT, the tapered portion of the gate electrode 142 and a photoresist are used as a doping mask for further doping to form an LDD (Lightly Doped Drain) structure or a GOLD (Gate Overlapped LDD) structure. May be.

  Next, as shown in FIG. 5M, an interlayer film 118 covering the second insulating layer 116 and the gate electrode 142 is formed. The interlayer film 118 is made of, for example, a laminated film of silicon oxide and silicon nitride, and is formed by PE-CVD. Alternatively, the formation method of the interlayer film 118 is not limited to the PE-CVD method, and the interlayer film 118 may be formed by spin-coating an SOG (Silicon on Glass) material.

  Next, as shown in FIG. 5 (n), heat treatment is performed to activate the dopant. The heat treatment is performed at a temperature of 500 to 700 ° C. for 30 to 120 minutes, for example.

  Next, as shown in FIG. 5 (o), a part of the second insulating layer 116 and the interlayer film 118 is removed by photolithography to form a contact hole. A part of the active layer 132 and a part of the connection part 135 are exposed through the contact hole formed in this way.

  Next, as shown in FIG. 5P, a source electrode 144, a drain electrode 146, and a bottom gate voltage input electrode 150 are formed in the contact hole. The source electrode 144 and the drain electrode 146 are in contact with the active layer 132, and the bottom gate voltage input electrode 150 is in contact with the connection portion 135. These electrodes 144, 146, and 150 are formed by forming an electrode layer made of a laminated film of titanium and aluminum by a sputtering method and patterning the electrode layer by a photolithography method.

  By activating the dopant implanted into the connection part 135, the connection part 135 has a higher electrical conductivity than the channel region 132 c of the active layer 132. For this reason, the first semiconductor layer 120 is electrically connected to the bottom gate voltage input electrode 150 through the connection portion 135, and the voltage is applied from the bottom gate voltage input electrode 150 to the first semiconductor layer 120 through the connection portion 135. Is applied, the conductivity of the channel region 132c of the active layer 132 can be controlled. Thus, the first semiconductor layer 120 functions as a bottom gate electrode.

  When metal or metal compound is used as the bottom gate electrode, the thermal conductivity of the metal or metal compound is larger than that of the silicon oxide film or silicon film, so the portion where the bottom gate electrode is disposed and the portion where it is not disposed The degree of diffusion of heat given by the laser beam in the laser annealing process differs greatly. For this reason, the crystallinity of the semiconductor layer is likely to vary, and as a result, the transistor characteristics may vary. On the other hand, when the bottom gate is formed of a semiconductor layer, variation in crystallinity due to the presence or absence of the bottom gate electrode can be suppressed.

  In the above description, the bottom gate voltage input electrode 150 is formed together with the source electrode 144 and the drain electrode 146, but the present invention is not limited to this. The bottom gate voltage input electrode 150 may not be formed. In the above description, the connecting portion 135 is formed by removing a part of the continuous portion 134, but the present invention is not limited to this. All of the continuous part 134 may be removed.

  In the above description, the impurity element is implanted, but the present invention is not limited to this. The implantation of the impurity element may be omitted. In this case, the annealing process for improving the activation rate of the impurity element may be omitted.

  In the above description, an element belonging to Group 5B or Group 3B of the periodic table is used as the gettering element, but the present invention is not limited to this. A rare gas element may be used as the gettering element.

  According to the present invention, it is possible to easily manufacture a semiconductor device in which malfunction of a TFT that realizes high-speed operation is suppressed. In addition, such a semiconductor device is suitably used for a display device such as a liquid crystal, an organic EL (Electroluminescence), or an FED (Field Emission Display).

It is a schematic diagram showing an embodiment of a semiconductor device according to the present invention. (A)-(f) is typical sectional drawing which shows the manufacturing process of the semiconductor device of this embodiment, respectively. (A)-(f) is typical sectional drawing for demonstrating the manufacturing process of the semiconductor device of this embodiment, respectively. (G)-(l) is typical sectional drawing for demonstrating the manufacturing process of the semiconductor device of this embodiment, respectively. (M)-(p) is typical sectional drawing for demonstrating the manufacturing process of the semiconductor device of this embodiment, respectively. (A)-(f) is typical sectional drawing for demonstrating the conventional manufacturing method of a crystalline semiconductor layer, respectively. (A)-(e) is typical sectional drawing for demonstrating another conventional manufacturing method of a crystalline semiconductor layer, respectively. (A)-(h) is typical sectional drawing for demonstrating the conventional manufacturing method of a semiconductor device, respectively. (A) is typical sectional drawing of the conventional liquid crystal display device, (b) is typical sectional drawing along the cross section different from (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 112 Transparent substrate 113 Base coat layer 114 1st insulating layer 116 2nd insulating layer 120 1st semiconductor layer 130 2nd semiconductor layer 140 TFT

Claims (6)

A transparent substrate having a front surface and a back surface;
A first semiconductor layer supported on the front surface of the transparent substrate;
An insulating layer selectively provided on the first semiconductor layer;
A semiconductor device comprising: an active layer of a thin film transistor; and a second semiconductor layer including an active layer facing the first semiconductor layer with the insulating layer interposed therebetween,
The first semiconductor layer contains a gettering element and a catalytic element that promotes crystallization of the second semiconductor layer,
The semiconductor device, wherein the active layer overlaps the first semiconductor layer when viewed from the normal direction of the back surface of the transparent substrate.   2. The semiconductor device according to claim 1, wherein a concentration of the catalytic element in the first semiconductor layer is higher than a concentration of the catalytic element in the second semiconductor layer. The active layer has a source region, a channel region, and a drain region,
The first semiconductor layer has a higher electrical conductivity than the channel region of the active layer;
The semiconductor device according to claim 1, wherein the first semiconductor layer functions as a gate that controls conductivity of the channel region. The second semiconductor layer further includes a connection part in contact with the first semiconductor layer,
The semiconductor device according to claim 3, wherein the source region and the drain region of the active layer, and the connection portion contain the same impurity element. Preparing a transparent substrate having a front surface and a back surface;
Forming a first semiconductor layer supported on the front surface of the transparent substrate, the first semiconductor layer containing a gettering element;
Selectively forming an insulating layer on the first semiconductor layer;
Forming a second semiconductor layer covering the first semiconductor layer and the insulating layer;
Applying a catalyst element for promoting crystallization to the second semiconductor layer;
A step of performing a thermal annealing process after applying the catalytic element to the second semiconductor layer, crystallizing the second semiconductor layer and at least part of the catalytic element in the second semiconductor layer; Moving to one semiconductor layer;
Forming a thin film transistor using, as the active layer, a portion of the second semiconductor layer that overlaps the first semiconductor layer when viewed from the normal direction of the back surface of the transparent substrate after the thermal annealing treatment; A method for manufacturing a semiconductor device including:   The step of forming the thin film transistor separates the first semiconductor layer from the portion of the second semiconductor layer that becomes the active layer of the thin film transistor by selectively removing a part of the second semiconductor layer. The manufacturing method of the semiconductor device of Claim 5 including the process to carry out.

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