KR102175341B1 - Light emitting device, method for fabricating the same, and light emitting device package - Google Patents

Abstract

The light emitting device disclosed in the embodiment includes: a first conductive type semiconductor layer; A second conductive type semiconductor layer disposed on the first conductive type semiconductor layer; And an active layer including a plurality of well layers and a plurality of barrier layers between the first conductive type semiconductor layer and the second conductive type semiconductor layer, wherein the plurality of well layers are close to the first conductive type semiconductor layer. A first well layer, a third well layer close to the second conductive semiconductor layer, and a second well layer disposed between the first and second well layers, wherein the third well layer comprises the first It includes a plurality of layers that are greater than the number of layers in the well layer, and the indium composition ratio is smaller as the layer closer to the second conductive type semiconductor layer among the plurality of layers in the third well layer.

Description

Light emitting device, light emitting device manufacturing method, and light emitting device package {LIGHT EMITTING DEVICE, METHOD FOR FABRICATING THE SAME, AND LIGHT EMITTING DEVICE PACKAGE}

The embodiment relates to a light emitting device, a method of manufacturing a light emitting device, and a light emitting device package.

Light Emitting Diode (LED) is a light emitting device that converts current into light. Recently, light emitting diodes have been increasingly used as light sources for display, light sources for automobiles, and light sources for lighting as the luminance gradually increases.

Recently, a high-power light emitting chip capable of realizing full color by generating short wavelength light such as blue or green has been developed. Accordingly, by applying a phosphor that absorbs a part of the light output from the light-emitting chip and outputs a wavelength different from that of the light on the light-emitting chip, light-emitting diodes of various colors can be combined and light-emitting diodes emitting white light can also be implemented. Do.

The embodiment provides a light emitting device having an improved structure of an active layer.

The embodiment provides a light emitting device capable of preventing the interface between a well layer and a barrier layer of an active layer from collapsing.

The light emitting device according to the embodiment includes: a first conductive type semiconductor layer; A second conductive type semiconductor layer disposed on the first conductive type semiconductor layer; And an active layer including a plurality of well layers and a plurality of barrier layers between the first conductive type semiconductor layer and the second conductive type semiconductor layer, wherein the plurality of well layers are close to the first conductive type semiconductor layer. A first well layer, a third well layer close to the second conductive semiconductor layer, and a second well layer disposed between the first and third well layers, wherein the third well layer comprises the first It includes a plurality of layers that are greater than the number of layers in the well layer, and the indium composition ratio is smaller as the layer closer to the second conductive type semiconductor layer among the plurality of layers in the third well layer.

A light emitting device according to an embodiment includes: a first conductive type semiconductor layer; A second conductive type semiconductor layer disposed on the first conductive type semiconductor layer; And an active layer including a plurality of well layers and a plurality of barrier layers between the first conductive type semiconductor layer and the second conductive type semiconductor layer, wherein the plurality of well layers are close to the first conductive type semiconductor layer. A first well layer, a third well layer close to the second conductive semiconductor layer, and a second well layer disposed between the first and third well layers, wherein the plurality of barrier layers include the first Between the first barrier layer disposed between the well layer and the second well layer, the second barrier layer disposed between the second well layer and the third well layer, and the third well layer and the second conductive semiconductor layer And a third barrier layer disposed, wherein the second and third barrier layers include a plurality of layers greater than the number of layers in the first barrier layer, and the third well layer among a plurality of layers in the third barrier layer The closer to the layer is, the more indium composition ratio is and the thickness is thinner, and the closer to the second well layer among the plurality of layers in the second barrier layer, the indium composition ratio is higher and the thickness is thinner.

Embodiments can provide an active layer having a new quantum well structure.

The embodiment can improve the internal quantum efficiency of the active layer.

The embodiment provides a light emitting device with improved reliability at a high current.

The embodiment may stabilize the active layer of the light emitting device.

The embodiment may improve the reliability of a light emitting device and a light emitting device package including the same.

1 is a side cross-sectional view of a light emitting device according to a first embodiment.
FIG. 2 is a diagram illustrating a well layer and a barrier layer of the active layer of FIG. 1.
3 is a diagram illustrating a well layer and a barrier layer according to a growth direction of the active layer of FIG. 2.
4 is a diagram showing a well layer and a barrier layer of an active layer of a comparative example.
5 is a side cross-sectional view of a light emitting device according to a second embodiment.
6 is a diagram illustrating an active layer of a light emitting device according to a third embodiment.
7 is a diagram illustrating an active layer of a light emitting device according to a fourth embodiment.
8 is a diagram illustrating an active layer of a light emitting device according to a fifth embodiment.
9 is a view showing an active layer of a light emitting device according to a sixth embodiment.
10 is an example in which electrodes are disposed in the light emitting device of FIG. 1.
11 is a view showing another light emitting device having an active layer according to an embodiment.
12 is a diagram showing internal quantum efficiency of a light emitting device according to an embodiment.
13 is a diagram illustrating a light emitting device package having a light emitting device according to an embodiment.
14 is a diagram illustrating a display device having a light emitting device or a light emitting device package according to an exemplary embodiment.
15 is a diagram illustrating another example of a light emitting device or a display device having a light emitting device package according to the embodiment.
16 is a view showing a lighting device having a light emitting device or a light emitting device package according to an embodiment.

Hereinafter, a light emitting device according to an embodiment and a method of manufacturing the same will be described in detail with reference to the accompanying drawings. In the description of the embodiment, each layer (film), region, pattern, or structure is formed in "on" or "under" of the substrate, each layer (film), region, pad or patterns When described as being "on" and "under", both "directly" or "indirectly" are formed. In addition, standards for the top/top or bottom of each layer will be described based on the drawings. In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. Also, the size of each component does not fully reflect the actual size.

1 is a cross-sectional view of a light emitting device according to a first embodiment.

Referring to FIG. 1, the light emitting device 100 includes a substrate 111, a first semiconductor layer 113, a second semiconductor layer 115, a first conductive semiconductor layer 117, an active layer 119, and a third semiconductor layer. A semiconductor layer 121 and a second conductive type semiconductor layer 123 are included.

The substrate 111 may be a light transmitting, insulating or conductive substrate, for example, sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP, Ge, Ga ₂ O ₃ , At least one of LiGaO ₃ may be used. A plurality of protrusions 112 may be formed on the upper surface of the substrate 111, and the plurality of protrusions 112 may be formed through etching of the substrate 111, or a separate roughness, such as It can be formed in a light extraction structure. The protrusion 112 may have a stripe shape, a hemispherical shape, or a dome shape. The thickness of the substrate 111 may be formed in the range of 30 μm to 150 μm, but is not limited thereto.

A first semiconductor layer 113 may be formed on the substrate 111. The first semiconductor layer 113 may be formed to mitigate a difference in lattice constant between the substrate 111 and the nitride-based semiconductor layer, and may be defined as a defect control layer. The first semiconductor layer 113 may have a value between the lattice constant between the substrate 111 and the nitride-based semiconductor layer.

The first semiconductor layer 113 may be formed as at least one layer using a compound semiconductor of a group II to VI element. The first semiconductor layer 113 includes a semiconductor layer using a compound semiconductor of a group III-V element, for example, In _x Al _y Ga _1-xy N (0≦x≦1, 0≦y≦1, A semiconductor having a composition formula of 0≦x+y≦1), and includes at least one of compound semiconductors such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and GaP. .

The first semiconductor layer 113 may be formed of an oxide such as a ZnO layer, but is not limited thereto. The first semiconductor layer 113 may be formed in a range of 30 to 500 nm, but is not limited thereto. The first semiconductor layer 113 may be formed in a super-lattice structure by alternately disposing different semiconductor layers.

A second semiconductor layer 115 may be formed on the first semiconductor layer 113. The second semiconductor layer 115 is an undoped semiconductor layer and has a conductivity lower than that of the first conductive semiconductor layer 117. The second semiconductor layer 115 may be implemented as a GaN-based semiconductor using a compound semiconductor of a group III-V element, and such an undoped semiconductor layer exhibits first conductivity type characteristics even if it is not intentionally doped with a conductivity type dopant. Will have. The undoped semiconductor layer may not be formed, but the embodiment is not limited thereto.

A first conductive type semiconductor layer 117 may be formed on the second semiconductor layer 115. The first conductive type semiconductor layer 117 is implemented as a compound semiconductor of a group III-V element doped with a first conductive type dopant, for example, In _x Al _y Ga _1-xy N (0≦x≦1, 0 It may be formed of a semiconductor material having a composition formula of ≤y≤1, 0≤x+y≤1). When the first conductive semiconductor layer 117 is an N-type semiconductor layer, the first conductive type dopant is an N-type dopant and includes Si, Ge, Sn, Se, and Te.

At least one of the second semiconductor layer 115 and the first conductive semiconductor layer 117 may have a superlattice structure in which different first and second layers are alternately disposed, and the first The thickness of the layer and the second layer may be formed to be several A or more.

A first conductive type cladding layer (not shown) may be formed between the first conductive type semiconductor layer 117 and the active layer 119. The first conductive cladding layer may be formed of a GaN-based semiconductor, and a band gap thereof may be formed to be greater than or equal to the band gap of the barrier layer of the active layer 119. This first conductive cladding layer serves to confine the carrier.

An active layer 119 may be formed on the first conductive semiconductor layer 117. The active layer 119 may be formed of at least one of a single quantum well, a multiple quantum well (MQW), a quantum line, and a quantum dot structure. In the active layer 119, as shown in FIG. 2, a well layer 11 and a barrier layer 12 are alternately disposed, and a pair of the well layer 11 and the barrier layer 12 is formed in 2 to 20 cycles. It may be, for example, may be formed in 2 to 10 cycles. The well layer 11 is, for example, a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as an InGaN-based semiconductor Can be formed as The barrier layer 12 is a semiconductor layer having a wider band gap than the band gap of the well layer 11, for example, In _x Al _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≦x+y≦1) may be formed of a semiconductor material, for example, a GaN-based semiconductor. The pair of the well layer 11 and the barrier layer 12 is, for example, InGaN/GaN, AlGaN/GaN, InGaN/AlGaN, InGaN/InGaN, AlGaAs/GaA, InGaAs/GaAs, InGaP/GaP, AlInGaP/InGaP, InP Contains at least one of /GaAs.

The thickness of the well layer 11 may be formed within the range of 1.5 to 5 nm, for example, may be formed within the range of 2.5 to 6 nm. The thickness of the barrier layer 12 may be thicker than the thickness of the well layer 11 and may be formed within a range of 3 to 15 nm, for example, may be formed within a range of 5 to 10 nm. The barrier layer 12 may include an n-type dopant, but is not limited thereto.

The active layer 119 may selectively emit light within a wavelength range from an ultraviolet band to a visible light band. The active layer 119 may emit at least one of ultraviolet light, blue light, green light, or red light.

A third semiconductor layer 121 is formed on the active layer 119, and the third semiconductor layer 121 has a band gap higher than that of the barrier layer 12 of the active layer 119, III- It may be formed of a group V compound semiconductor, such as a GaN-based semiconductor.

A second conductive type semiconductor layer 123 is formed on the third semiconductor layer 121, and the second conductive type semiconductor layer 123 includes a second conductive type dopant. The second conductive type semiconductor layer 123 may be formed of any one of compound semiconductors such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and GaP. When the second conductive type semiconductor layer 123 is a P type semiconductor layer, the second conductive type dopant is a P type dopant and may include Mg, Zn, Ca, Sr, Ba, or the like.

The conductive type of the layers of the light emitting structure layer 150 may be reversed. For example, the second conductive type semiconductor layers 121 and 123 are an N-type semiconductor layer, and the first conductive type semiconductor layer 117 is a P type. It can be implemented as a semiconductor layer. Further, an N-type semiconductor layer, which is a third conductive type semiconductor layer having a polarity opposite to that of the second conductive type, may be further formed on the second conductive type semiconductor layer 123. The semiconductor light emitting device 100 may include the first conductive type semiconductor layer 117, the active layer 119, and the second conductive type semiconductor layer 123 as a light emitting structure layer 150, and the light emitting structure The layer 150 may be implemented in any one of an NP junction structure, a PN junction structure, an NPN junction structure, and a PNP junction structure. In the N-P and P-N junction, an active layer is disposed between two layers, and the N-P-N junction or P-N-P junction includes at least one active layer between the three layers.

Meanwhile, the compound semiconductor layers 113 to 123 on the substrate 111 may be grown by the following growth equipment. The growth equipment includes, for example, electron beam evaporator, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporator sputtering, metal organic vapor deposition (MOCVD). chemical vapor deposition), but is not limited to such equipment.

The method of growing the active layer 119 is, for example, NH ₃ , TMGa (or TEGa), TMIn, TMAl using H ₂ or/and N ₂ as a carrier gas under a predetermined growth temperature (eg 700 to 950°C). By selectively supplying as a source, a well layer 11 made of an InGaN-based semiconductor and a barrier layer 12 made of a GaN-based semiconductor can be formed.

In the active layer 119 according to the embodiment, as shown in FIGS. 2 and 3, a well layer 11 and a barrier layer 12 are alternately stacked. The well layer 11 includes a first well layer 13 adjacent to the first conductive type semiconductor layer 117, a second well layer 14 on the first well layer 13, and the second conductive type semiconductor. And a third well layer 15 adjacent to the layer 123. The barrier layer 12 is between the first well layer 13 and the second well layer 14 and between the first barrier layer 16 and the second well layer 14 and the third well layer 15 A second barrier layer 17 and a third barrier layer 18 between the third well layer 15 and the third semiconductor layer 121 are included.

The first well layer 13 may be formed of a semiconductor having a composition formula of In _x Ga _1-x N (0.10≦ _x ≦0.15) or a semiconductor having an indium composition ratio of 10 to 15%. The first well layer 13 may be formed to a thickness of 2.5 to 6 nm. The first well layer 13 may be formed of a number of layers smaller than the number of layers of the second and third well layers 14 and 15, for example, a single layer.

The first barrier layer 16 may be formed of a semiconductor different from the first well layer 13, for example, a GaN-based semiconductor. The first barrier layer 16 may contain indium, and the indium composition ratio may range from 0 to 4%. The first barrier layer 16 is formed to have a thickness greater than that of the first well layer 13, for example, 3-15 nm.

The second well layer 14 includes a plurality of InGaN-based semiconductor layers, and each layer has a different indium composition ratio. The second well layer 14 includes a first layer 1 and a second layer 2, and the first layer 1 is disposed on the first barrier layer 16, and the second layer (2) is disposed between the first layer 1 and the second barrier layer 17. The first layer 1 and the second layer 2 may be smaller as the indium composition ratio is closer to the second barrier layer 17. The indium composition ratio of the first layer 1 may be in the range of 10 to 15%, and the indium composition ratio of the second layer 2 may be in the range of 2 to 12%. The thickness of the first and second layers 1 and 2 may be thinner as the layer closer to the second barrier layer 17 or the second conductive semiconductor layer is, for example, the thickness of the first layer 1 It is in the range of 50% to 70% of the second well layer 14, for example, 2 to 4 nm, and the thickness of the second layer 2 is in the range of 0.5 to 1 nm. The number of layers of the second well layer 14 may be greater than the number of layers of the first well layer 13 and may be formed to be smaller than the number of layers of the third well layer 15.

The second barrier layer 16 may be formed of a semiconductor different from the first well layer 13, for example, a GaN-based semiconductor. The second barrier layer 16 may include indium, and the indium composition ratio may range from 0 to 4%. The second barrier layer 16 is formed to have a thickness greater than that of the first well layer 13, for example, 3-15 nm.

The third well layer 15 includes a plurality of InGaN-based semiconductor layers, and each layer has a different indium composition ratio. The third well layer 15 includes first to third layers 3,4,5, the first layer 3 is disposed on the second barrier layer 17, and the second layer (4) is disposed on the first layer (3), and the third layer (5) is disposed between the second layer (4) and the third barrier layer (17). The indium composition ratio of the first to third layers 3, 4, and 5 may be smaller as the layer is closer to the third barrier layer 18 or the second conductive semiconductor layer. For example, the indium composition ratio of the first layer 3 may be in the range of 10 to 15%, the indium composition ratio of the second layer 4 may be in the range of 5 to 10%, and the indium composition ratio of the third layer 5 Is in the range of 1-5%. The thickness of the first to third layers 3, 4, 5 may be thinner as the layer closer to the third barrier layer 18 or the second conductive semiconductor layer is, for example, the first layer 3 The thickness is in the range of 50% to 70% of the third well layer 15, for example, 2 to 4 nm, the thickness of the second layer 4 is in the range of 0.5 to 1 nm, and the thickness of the third layer 5 Is in the range of 0.0001 to 1 nm. The number of layers of the third well layer 15 may be greater than that of each of the first and second well layers 13 and 14.

The third barrier layer 18 may be formed of a semiconductor different from the first well layer 13, for example, a GaN-based semiconductor. The third barrier layer 18 may include indium, and the indium composition ratio may range from 0 to 4%. The third barrier layer 18 is formed to have a thickness greater than that of the first well layer 13, for example, 3-15 nm.

In an embodiment, the difference in lattice constant at the interface (S3) between the third well layer 15 and the third barrier layer 18 is the interface between the second well layer 14 and the second barrier layer 17 ( It may be smaller than the difference in lattice constant in S2), and the difference in lattice constant of the escher at the interface (S2) between the second well layer 14 and the second barrier layer 17 is It may be smaller than the difference in lattice constant at the interface S1 between the first barrier layers 16. That is, among the layers in the third well layer 15, the difference in lattice constant from the third barrier layer 18 becomes smaller as the layer closer to the second conductive semiconductor layer. Therefore, as the layer closer to the second conductive semiconductor layer 123 is, the lattice constants at the interfaces (S1, S2, S3) between the well layers 13, 14, 15 and the barrier layers 16, 17, 18 By gradually reducing the difference, it is possible to solve the problem that the interface between the well layers 13, 14, and 15 and the barrier layers 16, 17, and 18 collapse. That is, it is possible to prevent a problem in which the second or third barrier layers 17 and 18 are not grown after the second and third well layers 14 and 15 are grown.

If, as shown in FIG. 4, when the active layers 119 of the comparative example are alternately stacked with InGaN well layers W1, W2, W3 and GaN barrier layers B1, B2, B3, the first well layer W1 The interface (S11) between the and the second barrier layer (B1) did not collapse, but the interface (S12) between the second well layer (W2) and the second barrier layer (B2), the third well layer (W3) and the third barrier There is a problem that the interface S13 between the layers B3 is collapsed. This is due to the difference in lattice constant, when growing the second or third barrier layers B2 and B3 after the growth of the second or third well layers W2 and W3, the second or third barrier layers B2 and B3 Is not well grown, there is a problem that the interfaces (S12, S13) collapse. When the interfaces S12 and S13 are collapsed in this way, there is a problem that the internal quantum efficiency falls at a high current. Accordingly, the reliability of the active layer is lowered.

The embodiment is by adjusting the indium composition ratio so that the interfaces (S1, S2, S3) between the well layers (11: 13, 14, 15) and the barrier layers (12:16, 17, 18) of the active layer 119 do not collapse. , It is possible to prevent a decrease in the internal quantum efficiency, and in particular, it is possible to prevent the decrease in efficiency even at a high current.

5 is a diagram illustrating an active layer of a light emitting device according to a second embodiment.

Referring to FIG. 5, the active layer 119A of the light emitting device includes first to third well layers 13, 14A, and 15A, and first and third barrier layers 16, 17, and 18.

The first well layer 13 is formed as a single layer having a constant first indium composition ratio. The second well layer 14A includes a first layer 5 having the first indium composition ratio; And a second layer 6 on the first layer 5 that gradually decreases as a region closer to the second conductive type semiconductor layer within a second indium composition ratio smaller than the first indium composition ratio. The third well layer 15A includes a first layer 8 having the first indium composition ratio; A second layer 9 may be formed on the first layer 8 to gradually decrease as a region closer to the second conductive type semiconductor layer within a third indium composition ratio smaller than the second indium composition ratio.

For example, the first well layer 13 may be a semiconductor having a composition formula of In _x Ga _1-x N (0.10≦ _x ≦0.15), or may be formed of a semiconductor having an indium composition ratio of 10 to 15%. . The first well layer 13 may be formed to a thickness of 2.5 to 6 nm. The first well layer 13 may be formed of a number of layers smaller than the number of layers of the second and third well layers 14 and 15, for example, a single layer.

The second well layer 14A includes a plurality of InGaN-based semiconductor layers, and each layer has a different indium composition ratio. The second well layer 14A includes a first layer 6 and a second layer 7 on the first layer 6, and the indium of the first layer 6 and the second layer 7 The composition ratio may decrease as the layer is closer to the second barrier layer 17. The indium composition ratio of the first layer 6 is in the range of 10 to 15%, and the indium composition ratio of the second layer 7 is graded toward an area close to the second barrier layer 17 within the range of 10 to 5%. It can be reduced by (grading). That is, the first layer 6 has a constant indium composition ratio, the second layer 7 has an indium composition ratio smaller than the indium composition ratio of the first layer 6, and the closer the area to the second barrier layer 17 is, the more graded. Can be reduced. The thickness of the first and second layers 6 and 7 may be thinner as the layer closer to the second barrier layer 17 is. For example, the thickness of the first layer 6 may be the second well layer ( 14A) is in the range of 50% to 70%, for example, 2 to 4 nm, and the thickness of the second layer 7 is in the range of 0.5 to 1 nm.

The third well layer 15A includes a plurality of InGaN-based semiconductor layers, and each layer has a different indium composition ratio. The third well layer (15A) includes a first layer (8) and a second layer (9) on the first layer (8), and the first and second layers (8, 9) are the third The closer to the barrier layer 18, the less indium composition ratio may be. For example, the indium composition ratio of the first layer 8 is in the range of 10 to 15%, and the indium composition ratio of the second layer 9 is in the range of 1 to 5%. Here, the indium composition ratio of the second layer 9 decreases as the indium composition ratio is graded in an area closer to the third barrier layer 18. In this case, the indium composition ratio of the second layer 9 may be smaller than the indium composition ratio of the second layer 7 of the second well layer 14A. The thickness of the first layer 8 is in the range of 50% to 70% of the third well layer 15A, for example, 2 to 4 nm, and the thickness of the second layer 9 is in the range of 0.5 to 1 nm.

The first to third barrier layers 16, 17, and 18 may be formed of a semiconductor different from the first well layer 13, for example, a GaN-based semiconductor. Each of the barrier layers 16, 17, 18 may contain indium, and the indium composition ratio may range from 0 to 4%. Each of the barrier layers 16, 17, 18 may be formed to have a thickness greater than that of the first well layer 13, for example, 3-15 nm.

In an embodiment, the lattice constant difference at the interface between the third well layer 15A and the third barrier layer 18 is the lattice constant at the interface between the second well layer 14A and the second barrier layer 17 May be less than the difference. This can gradually reduce the difference in lattice constants between the interfaces close to the second conductive semiconductor layer 123, thereby solving the problem that the interface between the well layer and the barrier layer collapses. That is, it is possible to prevent a problem in which the second or third barrier layers 17 and 18 are not grown after the second and third well layers 14A and 15A are grown.

6 is a diagram illustrating an active layer of a light emitting device according to a third embodiment.

6, the active layer 119B includes a well layer 11A having first to sixth well layers 21-26, and a barrier layer 12A having the first to sixth barrier layers 31-36. ). The first well layer 21 is disposed under the first barrier layer 31, and each of the second to sixth well layers 22-26 is the first to sixth barrier layers 31-36 It is disposed between, and the sixth barrier layer 36 is disposed on the sixth well layer 26.

The active layer 119B has a structure in which pairs of the first well layer 13 to the third barrier layer 18 of FIG. 2 are repeatedly stacked twice. The first to third well layers 21 to 23 have a semiconductor having the same indium composition ratio and thickness as the first to third well layers 13-15 of FIG. 2. The first to third barrier layers 31-33 have the same semiconductor and thickness as the first to third barrier layers 16-18 of FIG. 2. For example, the first and fourth well layers 21 and 24 are the first well layers 13 of FIG. 2, and the second and fifth well layers 22 and 25 are the second well layers ( 15) For example, it includes a first layer (1) and a second layer (2), and the third and sixth well layers (23, 26) are the third well layer (15) of FIG. It may include three layers (3, 4, 5).

The first to sixth barrier layers 31 to 36 may be formed of a GaN-based semiconductor. Each of the barrier layers 31-36 may contain indium, and the composition ratio of indium may range from 0 to 4%. Each of the barrier layers 31-36 may be formed to a thickness of 3-15 nm, for example.

7 is a diagram illustrating an active layer of a light emitting device according to a fourth embodiment.

Referring to FIG. 7, the active layer 119C includes a well layer 11B having first to ninth well layers 41-49 and a barrier layer 12B having first to ninth barrier layers 51-59. ). The first well layer 41 is disposed under the first barrier layer 51, and each of the second to ninth well layers 42-49 is the first to ninth barrier layers 51-59 And the ninth barrier layer 59 is disposed on the ninth well layer 49.

The active layer 119C has a structure in which pairs of the first well layer 13 to the third barrier layer 18 of FIG. 2 are repeatedly stacked three times. For example, the first, fourth, and seventh well layers 41, 44 and 47 are the first well layers 13 of FIG. 2, and the second, fifth and eighth well layers 42, 45, and 48 ) Includes the second well layer 15 of FIG. 2, for example, the first and second layers 1 and 2, and the third, sixth, and ninth well layers 43, 46 and 49 of FIG. The third well layer 15 may include, for example, first to third layers 3, 4 and 5. The first to ninth barrier layers 51 to 59 may be formed of a GaN-based semiconductor. Each of the barrier layers 51 to 59 may include indium, and the indium composition ratio may range from 0 to 4%. Each of the barrier layers 51-59 may be formed to have a thickness of, for example, 3-15 nm.

8 is a diagram illustrating an active layer of a light emitting device according to a third embodiment.

Referring to FIG. 8, the active layer 119D of the light emitting device is a barrier having a well layer 11C having first to seventh well layers 61-67, and a barrier having the first to seventh barrier layers 71-77. Layer 12C. The first well layer 61 is disposed under the first barrier layer 71, and each of the second to seventh well layers 62-67 is between the first to seventh barrier layers 71-77. And the seventh barrier layer 77 is disposed on the seventh well layer 67.

The first, fourth, and sixth well layers 61, 64, and 66 may be formed of a semiconductor having the same indium composition ratio and thickness as the first well layer 13 of FIG. 2. Each of the second and fifth well layers 63 and 65 is formed of the second well layer 14 of FIG. 2 and includes, for example, a first layer 1 and a second layer 2. The third and seventh well layers 63 and 67 are formed of the third well layer 15 of FIG. 2, for example, the first to third layers 3, 4 and 5 of the third well layer 15 Includes.

The first to seventh barrier layers 71 to 77 may be formed of a GaN-based semiconductor. Each of the barrier layers 71 to 77 may contain indium, and the composition ratio of indium may range from 0 to 4%. Each of the barrier layers 71-77 may be formed to a thickness of 3-15 nm, for example.

The above embodiment was formed by adjusting the indium composition ratio of the well layer, for example, the second and third well layers, but hereinafter, the difference in lattice constant at the interface between the barrier layer and the well layer was adjusted by adjusting the indium composition ratio of the barrier layer. It can be reduced.

9 is a view showing a light emitting device according to the sixth embodiment. The description of FIG. 9 will be described as the description of FIG. 1.

1 and 9, in the active layer 119E, well layers 11D: 81, 82, and 83 and barrier layers 12D: 91, 92, and 93 are alternately stacked. The well layer 11D includes a first well layer 81 adjacent to the first conductive type semiconductor layer 117, a second well layer 82 on the first well layer 81, and the second conductive type semiconductor. And a third well layer 83 adjacent to the layer 123. The barrier layer 12D is between the first well layer 81 and the second well layer 82 and between the first barrier layer 91 and the second well layer 82 and the third well layer 83 A second barrier layer 92 and a third barrier layer 93 between the third well layer 83 and the third semiconductor layer 121 are included.

The first to third well layers 81, 82 and 83 may be formed as a single layer, and are semiconductors having a composition formula of In _x Ga _1-x N (0.10≦ _x ≦0.15), or an indium composition ratio of 10 to It can be formed of a semiconductor having a range of 15%. Each of the first to third well layers 81, 82, and 83 may be formed to a thickness of 2.5 to 6 nm.

The second and third barrier layers 92 and 93 include a plurality of layers greater than the number of layers in the first barrier layer 91, and among a plurality of layers in the third barrier layer 93, the third well The closer the layer to the layer 83 is, the more indium composition ratio is and the thickness may be thinner. Among the plurality of layers in the second barrier layer 92, the closer to the second well layer 82, the greater the indium composition ratio and the thinner the thickness may be.

The first barrier layer 91 may be formed of a semiconductor different from the first well layer 81, for example, a GaN-based semiconductor, and may include indium. The indium composition ratio of the first barrier layer 91 may range from 0 to 4%. The first barrier layer 91 is formed to have a thickness greater than that of the first well layer, for example, 3-15 nm.

The second barrier layer 92 includes a plurality of layers, for example, a first layer 1A and a second layer 2A, and the first layer 1A and the second layer 2A have different indium composition ratios. For example, a layer closer to the third well layer 83 may have a smaller indium composition ratio, or a layer closer to the second well layer 82 may increase the indium composition ratio. The first layer 1A may be formed of an InGaN-based semiconductor having an indium composition ratio of 2 to 12%, and the second layer 2A has an indium composition ratio of 0 to 4% less than that of the first layer 1A. It may be formed of a GaN-based semiconductor having a composition ratio. The thickness of the first (1A) and the second layer (2A) may be gradually increased as the thickness is closer to the third well layer (84), or the thickness is gradually thinner as the thickness is closer to the second well layer (82). I can lose. For example, the thickness of the second layer 2A is in the range of 80% to 95% of the second barrier layer 92, for example, in the range of 4 to 14 nm, and the thickness of the first layer 1A is in the range of 0.5 to 1 nm. The second barrier layer 92 is formed to have a thickness greater than that of the first well layer 81, for example, 3-15 nm. The number of layers of the second barrier layer 92 may be greater than the number of layers of the first barrier layer 91 and may be formed to be smaller than the number of layers of the third barrier layer 93.

The third barrier layer 93 includes a plurality of layers, for example, a first layer 3A, a second layer 4A, and a third layer 5A, and the first layer 3A to the third layer ( 5A) may be formed with different indium composition ratios, for example, the indium composition ratio gradually decreases as the layer closer to the second conductive semiconductor layer 123 is, or the indium composition ratio is gradually decreased as the layer closer to the third well layer 83 There can be many. The first layer 3A may be formed of an InGaN-based semiconductor having an indium composition ratio of 5 to 10%, and the second layer 4A is 1 to 5% less than the indium composition ratio of the first layer 3A. A range of InGaN-based semiconductors may be used, and the third layer 5A may be formed of a GaN-based semiconductor having an indium composition ratio of 0 to 1% smaller than that of the second layer 4A. The thickness of the first (3A) to third layers (5A) may be thinner as the layer closer to the third well layer 84 is, for example, the thickness of the third layer 5A is the third barrier layer. (93) is in the range of 80% to 95%, for example, 4 to 14 nm, the thickness of the first layer 3A is in the range of 0.5 to 1 nm, and the second layer 4A is formed to a thickness in the range of 0.0001 to 1 nm. I can. The third barrier layer 93 is formed to have a thickness greater than that of the first well layer 81, for example, 3-15 nm. The number of layers of the third barrier layer 93 may be greater than the number of layers of the second barrier layer 92.

As the plurality of barrier layers 91, 92, and 93 are closer to the second conductive semiconductor layer, the difference in lattice constants from the well layers 81, 82, and 83 may decrease.

The difference in lattice constant at the interface between the third well layer and the third barrier layer is smaller than the difference in lattice constant at the interface between the second well layer and the second barrier layer.

In the ninth embodiment, a difference in lattice constants may be reduced by adjusting the indium composition ratio of the barrier layer 12D. For example, when growing the second barrier layer 92 and the third barrier layer 93, by adjusting the indium composition ratio and thickness of each of the barrier layers 92 and 93, the second and third well layers 82, 83) and the difference in lattice constant can be reduced.

10 is an example of arranging electrodes in the light emitting device of FIG. 1.

Referring to FIG. 10, in the light emitting device 101, an electrode layer 141 and a second electrode 145 are formed on a light emitting structure layer 150, and a first electrode 143 is formed on the first conductive semiconductor layer 117. ) Is formed.

The electrode layer 141 is a current diffusion layer and may be formed of a material having transmittance and electrical conductivity. The electrode layer 141 may be formed with a refractive index lower than that of the compound semiconductor layer.

The electrode layer 141 is formed on the upper surface of the second conductive semiconductor layer 123, and the materials are indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), and indium aluminum oxide (IAZO). zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), ZnO, IrOx, RuOx, NiO, etc. It is selected and may be formed in at least one layer. The electrode layer 141 may be formed as a reflective electrode layer, and the material may be selectively formed from, for example, Al, Ag, Pd, Rh, Pt, Ir, and two or more alloys thereof.

The second electrode 145 may be formed on the second conductive semiconductor layer 123 and/or the electrode layer 141, and may include an electrode pad. The second electrode 145 may further include a current diffusion pattern having an arm structure or a finger structure. The second electrode 145 may be made of a metal having characteristics of ohmic contact, an adhesive layer, and a bonding layer, and may be non-transmitting, but is not limited thereto.

A first electrode 143 is formed on a part of the first conductive semiconductor layer 117. The first electrode 143 and the second electrode 145 are Ti, Ru, Rh, Ir, Mg, Zn, Al, In, Ta, Pd, Co, Ni, Si, Ge, Ag, and Au, and their It can be selected among optional alloys.

An insulating layer may be further formed on the surface of the light emitting device 101, and the insulating layer may prevent interlayer shorts of the light emitting structure layer 145 and prevent moisture penetration.

11 is an example showing another electrode arrangement example of the light emitting device of FIG. 1.

Referring to FIG. 11, a current blocking layer 161, a channel layer 163, and a second electrode 170 are disposed under the light emitting structure layer 150. The current blocking layer 161 may include at least one of SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , and TiO ₂ , and at least one between the channel layers 163 Can be formed.

The current blocking layer 161 is disposed on the lower surface of the light emitting structure layer 117 and disposed to correspond to the first electrode 181 and the light emitting structure layer 150 in a thickness direction. The current blocking layer 161 may block the current supplied from the second electrode 170 and diffuse it to another path.

The channel layer 163 is formed along the bottom edge of the second conductive semiconductor layer 123 and may be formed in a ring shape, a loop shape, or a frame shape. The channel layer 163 is at least one of ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO, SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ Can include. An inner portion of the channel layer 163 is disposed under the second conductive semiconductor layer 123, and an outer portion is disposed further outside a side surface of the light emitting structure layer 150.

A second electrode 170 may be formed under the second conductive semiconductor layer 123. The second electrode 170 may include a plurality of conductive layers 165, 167, and 169.

The second electrode 170 includes a contact layer 165, a reflective layer 167, and a bonding layer 169. The contact layer 165 may be a low-conductivity material such as ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO, or a metal of Ni or Ag. A reflective layer 167 is formed under the contact layer 165, and the reflective layer 167 is composed of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, and combinations thereof. It may be formed in a structure including at least one layer made of a material selected from the group. The reflective layer 167 may be in contact under the second conductive semiconductor layer 123, and may be in ohmic contact with a metal or with a low-conducting material such as ITO, but is not limited thereto.

A bonding layer 169 is formed under the reflective layer 167, and the bonding layer 169 may be used as a barrier metal or a bonding metal, and the material may be, for example, Ti, Au, Sn, Ni, Cr, It may contain at least one of Ga, In, Bi, Cu, Ag, and Ta and an optional alloy.

A support member 173 is formed under the bonding layer 169, and the support member 173 may be formed of a conductive member, and the material is copper (Cu-copper), gold (Au-gold), nickel It may be formed of a conductive material such as (Ni-nickel), molybdenum (Mo), copper-tungsten (Cu-W), or a carrier wafer (eg, Si, Ge, GaAs, ZnO, SiC, etc.). As another example, the support member 173 may be implemented as a conductive sheet.

Here, the substrate of FIG. 1 is removed. The removal method of the growth substrate may be removed by a physical method (eg, laser lift off) or/or a chemical method (such as wet etching), and exposes the first conductive type semiconductor layer 117. Isolation etching is performed through the direction in which the substrate is removed to form a first electrode 181 on the first conductive semiconductor layer 117.

A light extraction structure 117A such as roughness may be formed on an upper surface of the first conductive semiconductor layer 117. An outer portion of the channel layer 163 is exposed outside a sidewall of the light emitting structure layer 150, and an inner portion of the channel layer 163 may contact a lower surface of the second conductive semiconductor layer 123. .

Accordingly, the light-emitting device 102 having a vertical electrode structure having a first electrode 181 on the light-emitting structure layer 150 and a support member 173 under it may be manufactured.

12 is a diagram showing the internal quantum efficiency of the light emitting device according to the embodiment. As the current increases, the internal quantum efficiency increases. Here, it can be seen that the internal quantum efficiency is improved as compared to the comparative example as the current goes to a certain or more, for example, the high current 1E-6.

Meanwhile, FIG. 13 is a diagram illustrating a light emitting device package to which a light emitting device according to an embodiment is applied.

13, a light emitting device package according to an embodiment includes a body 210, a first lead electrode 211 and a second lead electrode 222 disposed on the body 210, and the body 210 The light emitting device 101 according to the embodiment provided in the first lead electrode 211 and electrically connected to the second lead electrode 222, and a molding member 220 surrounding the light emitting device 101 Can include.

The body 210 may be formed of a silicon or epoxy material, a synthetic resin material, or a metal material, and may include a reflective portion 215 having a cavity having an inclined surface around the light emitting device 101. .

The first lead electrode 211 and the second lead electrode 212 are electrically separated from each other, and supply power to the light emitting device 101. In addition, the first lead electrode 211 and the second lead electrode 212 reflect light generated from the light emitting device 101 to increase light efficiency, and the heat generated from the light emitting device 101 It can also play a role of discharging to outside.

The light emitting device 101 may be disposed on the body 210 or may be disposed on the first lead electrode 211 or the second lead electrode 212.

The light emitting device 101 may be connected to the first lead electrode 211 and the second lead electrode 212 by a wire 216 or may be electrically connected by either a flip chip method or a die bonding method.

The molding member 220 may surround the light emitting device 101 to protect the light emitting device 100. Further, the molding member 220 may include a phosphor to change the wavelength of light emitted from the light emitting device 101.

A plurality of light emitting devices or light emitting device packages according to the embodiment may be arrayed on a substrate, and an optical member such as a lens, a light guide plate, a prism sheet, and a diffusion sheet may be disposed on an optical path of the light emitting device package. Such a light emitting device package, substrate, and optical member may function as a light unit. The light unit may be implemented in a top view or a side view type, and may be provided to display devices such as portable terminals and notebook computers, or may be variously applied to lighting devices and indication devices.

Another embodiment may be implemented as a lighting device including the light emitting device or the light emitting device package described in the above-described embodiments. For example, the lighting device may include a lamp, a street light, an electric sign, and a headlamp. In addition, the lighting device according to the embodiment may be applied not only to a vehicle headlight but also to a rear light.

The light emitting device according to the embodiment may be applied to a light unit. The light unit includes a structure in which a plurality of light emitting elements are arrayed, and may include a display device illustrated in FIGS. 14 and 15 and a lighting device illustrated in FIG. 16.

Referring to FIG. 14, a display device 1000 according to an embodiment includes a light guide plate 1041, a light emitting module 1031 providing light to the light guide plate 1041, and a reflective member 1022 under the light guide plate 1041. ), an optical sheet 1051 on the light guide plate 1041, a display panel 1061 on the optical sheet 1051, the light guide plate 1041, a light emitting module 1031, and a reflective member 1022. The bottom cover 1011 may be included, but is not limited thereto.

The bottom cover 1011, the reflective sheet 1022, the light guide plate 1041, and the optical sheet 1051 may be defined as a light unit 1050.

The light guide plate 1041 serves to diffuse light into a surface light source. The light guide plate 1041 is made of a transparent material, for example, acrylic resin series such as PMMA (polymethyl metaacrylate), PET (polyethylene terephthlate), PC (polycarbonate), COC (cycloolefin copolymer), and PEN (polyethylene naphthalate). It may contain one of the resins.

The light emitting module 1031 provides light to at least one side of the light guide plate 1041, and ultimately acts as a light source of the display device.

At least one of the light emitting modules 1031 may be provided in the bottom cover 1011, and light may be provided directly or indirectly from one side of the light guide plate 1041. The light emitting module 1031 may include a substrate 1033 and a light emitting device or a light emitting device package 200 according to the embodiment described above. The light emitting device package 200 may be arranged on the substrate 1033 at predetermined intervals.

The substrate 1033 may be a printed circuit board (PCB) including a circuit pattern. However, the substrate 1033 may include not only a general PCB, but also a metal core PCB (MCPCB, Metal Core PCB), a flexible PCB (FPCB, Flexible PCB), etc., but is not limited thereto. When the light emitting device package 200 is provided on a side surface of the bottom cover 1011 or on a heat dissipation plate, the substrate 1033 may be removed. Here, a part of the heat dissipation plate may contact the upper surface of the bottom cover 1011.

In addition, the plurality of light emitting device packages 200 may be mounted such that an emission surface from which light is emitted is spaced apart from the light guide plate 1041 by a predetermined distance, but the embodiment is not limited thereto. The light emitting device package 200 may directly or indirectly provide light to a light-incident portion, which is one side of the light guide plate 1041, but is not limited thereto.

The reflective member 1022 may be disposed under the light guide plate 1041. The reflective member 1022 reflects the light incident on the lower surface of the light guide plate 1041 and directs it upward, thereby improving the brightness of the light unit 1050. The reflective member 1022 may be formed of, for example, PET, PC, PVC resin, or the like, but is not limited thereto. The reflective member 1022 may be an upper surface of the bottom cover 1011, but is not limited thereto.

The bottom cover 1011 may accommodate the light guide plate 1041, the light emitting module 1031 and the reflective member 1022. To this end, the bottom cover 1011 may include a receiving portion 1012 having a box shape with an open top surface, but is not limited thereto. The bottom cover 1011 may be coupled to the top cover, but the embodiment is not limited thereto.

The bottom cover 1011 may be formed of a metal material or a resin material, and may be manufactured using a process such as press molding or extrusion molding. In addition, the bottom cover 1011 may include a metal or non-metal material having good thermal conductivity, but is not limited thereto.

The display panel 1061 is, for example, an LCD panel, and includes first and second substrates made of transparent materials facing each other, and a liquid crystal layer interposed between the first and second substrates. A polarizing plate may be attached to at least one surface of the display panel 1061, and the structure of the polarizing plate is not limited thereto. The display panel 1061 displays information by light passing through the optical sheet 1051. The display device 1000 can be applied to various types of portable terminals, monitors of notebook computers, monitors of laptop computers, and televisions.

The optical sheet 1051 is disposed between the display panel 1061 and the light guide plate 1041, and includes at least one translucent sheet. The optical sheet 1051 may include at least one of, for example, a diffusion sheet, a horizontal and vertical prism sheet, and a brightness enhancement sheet. The diffusion sheet diffuses incident light, the horizontal or/and vertical prism sheet condenses incident light to a display area, and the brightness enhancement sheet reuses lost light to improve luminance. In addition, a protective sheet may be disposed on the display panel 1061, but the embodiment is not limited thereto.

Here, as an optical member on the light path of the light emitting module 1031, the light guide plate 1041 and the optical sheet 1051 may be included, but the embodiment is not limited thereto.

15 is a diagram illustrating another example of a display device according to an exemplary embodiment.

Referring to FIG. 15, the display device 1100 includes a bottom cover 1152, a substrate 1020 on which the light emitting devices 100 disclosed above are arrayed, an optical member 1154, and a display panel 1155. The substrate 1020 and the light emitting device package 200 may be defined as a light emitting module 1060. The bottom cover 1152 may include an accommodating part 1153, but the embodiment is not limited thereto.

Here, the optical member 1154 may include at least one of a lens, a light guide plate, a diffusion sheet, a horizontal and vertical prism sheet, and a brightness enhancement sheet. The light guide plate may be made of a PC material or a poly methy methacrylate (PMMA) material, and the light guide plate may be removed. The diffusion sheet diffuses incident light, the horizontal and vertical prism sheets condense incident light into a display area, and the brightness enhancement sheet reuses lost light to improve brightness.

The optical member 1154 is disposed on the light emitting module 1060 and performs a surface light source, diffusion, or condensation of light emitted from the light emitting module 1060.

16 is a view showing a lighting device according to an embodiment.

Referring to FIG. 16, a lighting device according to an embodiment includes a cover 2100, a light source module 2200, a radiator 2400, a power supply unit 2600, an inner case 2700, and a socket 2800. I can. In addition, the lighting device according to the embodiment may further include one or more of a member 2300 and a holder 2500. The light source module 2200 may include a light emitting device package according to the embodiment.

For example, the cover 2100 may have a shape of a bulb or a hemisphere, and may be provided in a shape with a hollow and an open portion. The cover 2100 may be optically coupled to the light source module 2200. For example, the cover 2100 may diffuse, scatter, or excite light provided from the light source module 2200. The cover 2100 may be a kind of optical member. The cover 2100 may be coupled to the radiator 2400. The cover 2100 may have a coupling portion coupled to the radiator 2400.

A milky white paint may be coated on the inner surface of the cover 2100. The milky white paint may include a diffuser that diffuses light. The surface roughness of the inner surface of the cover 2100 may be larger than the surface roughness of the outer surface of the cover 2100. This is to allow light from the light source module 2200 to be sufficiently scattered and diffused to be emitted to the outside.

The material of the cover 2100 may be glass, plastic, polypropylene (PP), polyethylene (PE), polycarbonate (PC), or the like. Here, polycarbonate is excellent in light resistance, heat resistance, and strength. The cover 2100 may be transparent or opaque so that the light source module 2200 is visible from the outside. The cover 2100 may be formed through blow molding.

The light source module 2200 may be disposed on one surface of the radiator 2400. Accordingly, heat from the light source module 2200 is conducted to the radiator 2400. The light source module 2200 may include a light source unit 2210, a connection plate 2230, and a connector 2250.

The member 2300 is disposed on an upper surface of the radiator 2400 and has guide grooves 2310 into which a plurality of light source units 2210 and a connector 2250 are inserted. The guide groove 2310 corresponds to the substrate and the connector 2250 of the light source unit 2210.

The surface of the member 2300 may be coated or coated with a light reflective material. For example, the surface of the member 2300 may be coated or coated with a white paint. The member 2300 reflects light reflected on the inner surface of the cover 2100 and returning toward the light source module 2200 toward the cover 2100. Therefore, it is possible to improve the light efficiency of the lighting device according to the embodiment.

The member 2300 may be made of an insulating material, for example. The connection plate 2230 of the light source module 2200 may include an electrically conductive material. Accordingly, electrical contact may be made between the radiator 2400 and the connection plate 2230. The member 2300 is made of an insulating material to block an electrical short between the connection plate 2230 and the radiator 2400. The radiator 2400 receives heat from the light source module 2200 and heat from the power supply unit 2600 to radiate heat.

The holder 2500 blocks the receiving groove 2719 of the insulating part 2710 of the inner case 2700. Accordingly, the power supply unit 2600 accommodated in the insulating unit 2710 of the inner case 2700 is sealed. The holder 2500 has a guide protrusion 2510. The guide protrusion 2510 has a hole through which the protrusion 2610 of the power supply unit 2600 passes.

The power supply unit 2600 processes or converts an electrical signal provided from the outside and provides it to the light source module 2200. The power supply unit 2600 is accommodated in the storage groove 2719 of the inner case 2700 and is sealed inside the inner case 2700 by the holder 2500. The power supply unit 2600 may include a protrusion 2610, a guide portion 2630, a base 2650, and an extension 2670.

The guide portion 2630 has a shape protruding outward from one side of the base 2650. The guide part 2630 may be inserted into the holder 2500. A number of components may be disposed on one surface of the base 2650. A number of components include, for example, a DC converter for converting AC power provided from an external power source to DC power, a driving chip for controlling the driving of the light source module 2200, and an ESD for protecting the light source module 2200. (ElectroStatic discharge) may include a protection element, but is not limited thereto.

The extension part 2670 has a shape protruding outward from the other side of the base 2650. The extension part 2670 is inserted into the connection part 2750 of the inner case 2700 and receives an electrical signal from the outside. For example, the extension part 2670 may be provided equal to or smaller than the width of the connection part 2750 of the inner case 2700. Each end of the "+ wire" and "- wire" may be electrically connected to the extension part 2670, and the other end of the "+ wire" and "- wire" may be electrically connected to the socket 2800. .

The inner case 2700 may include a molding unit together with the power supply unit 2600 therein. The molding part is a part in which the molding liquid is hardened, and allows the power supply part 2600 to be fixed inside the inner case 2700. Features, structures, effects, etc. described in the above embodiments are at least in the present invention. It is included in one embodiment, and is not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in each embodiment can be implemented by combining or modifying other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Accordingly, contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

In addition, although the embodiments have been described above, these are only examples and do not limit the present invention, and those of ordinary skill in the field to which the present invention belongs are illustrated above within the scope not departing from the essential characteristics of the present embodiment. It will be seen that various modifications and applications that are not available are possible. For example, each component specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims.

11,11A,11B,11C,11D,13,14,14A,15,15A,21-26, 41-49, 61-67, 81-83: well layer
12,16,17,18, 31-36, 51-59, 71-77, 91-93: barrier layer
100,101,102: light-emitting element
111: substrate
113: first semiconductor layer
115: second semiconductor layer
117: first conductive type semiconductor layer
119,119A,119B,119C,119D,119E: active layer
121: third semiconductor layer
123: second conductive type semiconductor layer

Claims (14)

delete delete delete delete delete delete delete delete delete delete delete delete A first conductive type semiconductor layer;
A second conductive type semiconductor layer disposed on the first conductive type semiconductor layer; And
And an active layer including a plurality of well layers and a plurality of barrier layers between the first conductive semiconductor layer and the second conductive semiconductor layer,
The plurality of well layers include a first well layer close to the first conductive type semiconductor layer, a third well layer close to the second conductive type semiconductor layer, and a second well layer disposed between the first and third well layers. Includes a well layer,
The plurality of barrier layers include a first barrier layer disposed between the first well layer and the second well layer, a second barrier layer disposed between the second well layer and the third well layer, and the third well layer. And a third barrier layer disposed between the well layer and the second conductive semiconductor layer,
The second and third barrier layers include a plurality of layers greater than the number of layers in the first barrier layer,
Among the plurality of layers in the third barrier layer, the closer to the third well layer, the greater the indium composition ratio and the thinner the thickness,
A light emitting device having a larger indium composition ratio and a thinner thickness as a layer closer to the second well layer among the plurality of layers in the second barrier layer. The method of claim 13,
A light emitting device in which a difference in lattice constant from the well layer decreases as a layer closer to the second conductive semiconductor layer among the plurality of barrier layers.

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