KR102172392B1 - Organic Light Emitting Display For Compensating Degradation Of Driving Element - Google Patents

Abstract

The organic light emitting display device according to the present invention is a display panel in which a plurality of pixels PIX including an OLED and a driving TFT DT that controls a driving current flowing through the OLED according to a gate-source bias voltage Vgs are formed. (10); And a negative bias voltage (Vn) is preset in order to restore the operating characteristics of the driving TFT due to the positive bias voltage (Vp), and the panel driving time is counted to determine a positive bias time (Tp) to which the positive bias voltage is applied. After derivation, a degradation compensation circuit that calculates a negative bias time Tn based on the positive bias time, and applies the negative bias voltage Vn between the gate and source of the driving TFT during the calculated negative bias time ( 16).

Description

Organic Light Emitting Display For Compensating Degradation Of Driving Element {Organic Light Emitting Display For Compensating Degradation Of Driving Element}

The present invention relates to an organic light-emitting display device, and more particularly, to an organic light-emitting display device capable of compensating for deterioration of a driving element.

An organic light emitting diode display of an active matrix type includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light by itself, and has a fast response speed and a high luminous efficiency, luminance, and viewing angle.

OLED, which is a self-luminous device, includes an anode electrode and a cathode electrode, and an organic compound layer (HIL, HTL, EML, ETL, EIL) formed therebetween. The organic compound layer is a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer, EIL). When a driving voltage is applied to the anode and cathode electrodes, holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) are moved to the emission layer (EML) to form excitons, and as a result, the emission layer (EML) is It generates visible light.

The organic light emitting display device arranges pixels including OLEDs in a matrix form and adjusts the luminance of the pixels according to the gradation of video data. Each of the pixels includes a driving TFT (Thin Film Transistor) to control a driving current flowing through the OLED. The driving TFT controls the driving current flowing through the OLED according to the voltage (Vgs) applied between its gate electrode and the source electrode. However, in the organic light-emitting display device, due to changes over time, the electrical characteristics of the driving TFTs between pixels may vary, thereby deteriorating image quality. When the gate-source voltage (Vgs) of the same polarity is applied to the driving TFT for a long time, the gate-bias stress increases, the threshold voltage of the driving TFT is shifted, resulting in deterioration of the operating characteristics of the driving TFT. will be.

To solve this problem, various deterioration compensation methods have been proposed in which a compensation signal of opposite polarity is applied to the driving TFT. However, in the prior art, since a signal line for applying a compensation signal is further required, the aperture ratio is lowered, and a compensation period is allocated within a real-time driving period, thereby increasing the driving frequency for image display and complicating the timing logic.

Accordingly, an object of the present invention is to provide an organic light emitting display device capable of compensating for a change over time of a driving TFT without lowering the aperture ratio and without increasing the driving frequency for image display and changing the timing logic.

In order to achieve the above object, the organic light emitting display device according to an embodiment of the present invention is a display panel in which a plurality of pixels are formed, each including an OLED and a driving TFT that controls a driving current flowing through the OLED according to a gate-source bias voltage. ; And setting a negative bias voltage in advance to restore the operating characteristics of the driving TFT due to the positive bias voltage, counting the panel driving time to derive a positive bias time to which the positive bias voltage is applied, and then calculating the positive bias time. A deterioration compensation circuit for calculating a negative bias time based on the calculated negative bias time and for applying the negative bias voltage between the gate-source of the driving TFT during the calculated negative bias time; The positive bias voltage is applied between the gate-source of the driving TFT during the on sequence period in which the panel driving power is maintained in an on state, whereas the negative bias voltage is applied in the off sequence period after the panel driving power is turned off. A signal wiring applied between the gate-source of the driving TFT and for applying the positive bias voltage between the gate-source of the driving TFT, and for applying the negative bias voltage between the gate-source of the driving TFT The signal wiring is characterized in that they are identical to each other.

In performing the deterioration compensation, this erasure solves the problem of lowering the aperture ratio as in the prior art because the array configuration of the display panel for image display is not changed (ie, signal wiring is not added) and is used as it is. In addition, since the present invention performs deterioration compensation during an off-sequence period rather than an on-sequence period, it is not necessary to change the driving frequency and timing logic for image display due to the deterioration compensation.

1 is a view showing an organic light emitting display device according to an embodiment of the present invention.
2 is a diagram illustrating a pixel array formed on the display panel of FIG. 1.
3A is a diagram illustrating an example of applying a positive bias voltage for image display during an on sequence period.
3B is a diagram illustrating an example of applying a negative bias voltage to compensate for degradation during an off sequence period.
4 is a diagram showing waveforms of driving signals applied during an on/off sequence period.
5 and 6 are diagrams showing an operating characteristic shift rate due to a positive bias stress and an operating characteristic shift rate due to a negative bias stress.
7 is a view showing an example of the degradation compensation circuit shown in FIG.
8 and 9 are diagrams showing an operation procedure of the degradation compensation circuit of FIG. 7 performed during an off sequence period.
10 is a view showing another example of the degradation compensation circuit shown in FIG.
8 and 11 are diagrams showing an operation procedure of the degradation compensation circuit of FIG. 10 performed during an off sequence period.
12 is a diagram showing repetitive arrangement timing of on and off sequence periods.
13 is a diagram showing an example of a local deterioration compensation scheme.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 1 to 13.

1 shows an organic light emitting display device according to an exemplary embodiment of the present invention, and FIG. 2 shows a part of a pixel array formed on the display panel of FIG. 2.

1 and 2, an organic light emitting display device according to an embodiment of the present invention includes a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a degradation compensation. A circuit 16 is provided.

A plurality of data lines 14 and a plurality of gate lines 15 intersect on the display panel 10, and pixels PIX are arranged in a matrix form in each of the cross regions.

The data lines 14 include a plurality of data voltage supply lines 14A and a plurality of reference voltage supply lines 14B. In addition, the gate lines 15 include a plurality of first gate lines 15C and a plurality of second gate lines 15D.

Each pixel PIX is connected to one of the data voltage supply lines 14A, one of the reference voltage supply lines 14B, one of the first gate lines 15C, and the second gate line. It is connected to any one of them 15D. Each pixel PIX receives a data voltage through the data voltage supply line 14A, receives a compensated reference voltage through the reference voltage supply line 14B, and receives a first gate through the first gate line 15C. A pulse SCAN is input, and a second gate pulse SEN is input through the second gate line 15D. In the on sequence period for image display, the pixels PIX are driven in a row sequential manner in response to the first and second gate pulses SCAN and SEN. On the other hand, in the off-sequence period for deterioration compensation, all the pixels PIX may be simultaneously driven in response to the first and second gate pulses SCAN and SEN.

Each of the pixels PIX receives a high potential driving voltage EVDD from a power generation unit, not shown. The pixel PIX of the present invention may include an OLED, a driving TFT, a first and a second switch TFT, and a storage capacitor. The TFTs constituting the pixel PIX may be implemented as a p-type or an n-type. Further, the semiconductor layers of the TFTs constituting the pixel PIX may include amorphous silicon, polysilicon, or oxide.

The pixel structure shown in FIG. 2 is only an example to aid understanding of the present invention. Since the pixel structure to which the present invention is applied can be modified in various ways, the technical idea of the present invention is not limited to this embodiment. The pixel PIX of the present invention may include an OLED, a driving TFT (Thin Film Transistor) (DT), a storage capacitor (Cst), a first switch TFT (ST), and a second switch TFT (ST2).

The OLED includes an anode electrode connected to the second node N2, a cathode electrode connected to an input terminal of a low potential driving voltage EVSS, and an organic compound layer positioned between the anode electrode and the cathode electrode. The driving TFT DT controls the driving current Ioled flowing through the OLED according to the gate-source voltage Vgs. The driving TFT DT includes a gate electrode connected to the first node N1, a drain electrode connected to the input terminal of the high potential driving voltage EVDD, and a source electrode connected to the second node N2. The storage capacitor Cst is connected between the first node N1 and the second node N2.

The first switch TFT ST applies the data voltage Vdata on the data voltage supply line 14A to the first node N1 in response to the first gate pulse SCAN. The first switch TFT (ST) includes a gate electrode connected to the first gate line 15C, a drain electrode connected to the data voltage supply line 14A, and a source electrode connected to the first node N1.

The second switch TFT ST2 switches the current flow between the second node N2 and the reference voltage supply line 14B in response to the second gate pulse SEN, so that the reference voltage Vref on the reference voltage supply line 14B. ) Is applied to the second node N2. The second switch TFT ST2 includes a gate electrode connected to the second gate line 15D, a drain electrode connected to the reference voltage supply line 14B, and a source electrode connected to the second node N2.

The data driving circuit 12 is connected to each pixel PIX through a data voltage supply line 14A and a reference voltage supply line 14B. The data driving circuit 12 converts the pixel data DATA into a data voltage for image display according to the data timing control signal DDC applied from the timing controller 11 during the on-sequence period, and the data voltage supply lines 14A. In addition to supplying to, the reference voltage Vref for image display of the first level is generated and supplied to the reference voltage supply lines 14B. The data driving circuit 12 converts off data input from the degradation compensation circuit 16 into a data voltage for compensation of degradation during the off sequence period and supplies it to the data voltage supply lines 14A, and compensates for degradation. The second level deterioration compensation reference voltage Vref input from the circuit 16 is supplied to the reference voltage supply lines 14B.

The gate driving circuit 13 generates first and second gate pulses SCAN and SEN based on the gate control signal GDC input from the timing controller 11. The gate driving circuit 13 generates a first gate pulse SCAN during the on-sequence period and sequentially supplies it to the first gate lines 15C according to a row sequential method, and generates a second gate pulse to generate a row sequential method. Accordingly, the second gate lines 15D are sequentially supplied. The gate driving circuit 13 generates the first and second gate pulses SCAN and SEN in the form of a single pulse at the same timing during the off-sequence period and simultaneously supplies them to the first and second gate lines 15C and 15D. .

The timing controller 11 is based on timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a dot clock signal (DCLK), and a data enable signal (DE) input from a system (not shown). A data control signal DDC for controlling the operation timing of the data driving circuit 12 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13 are generated.

The degradation compensation circuit 16 derives a positive bias time based on the count result for the panel driving time, and calculates a negative bias time by multiplying the derived positive bias time by the ratio of the negative coefficient to the positive coefficient. In addition, the degradation compensation circuit 16 outputs a reference voltage Vref for degradation compensation and OFF DATA corresponding to a data voltage for degradation compensation according to a predetermined negative bias voltage during the calculated negative bias time. Here, the negative bias voltage is a gate-source voltage (Vgs) of the driving TFT, between the data voltage for deterioration compensation applied to the gate electrode of the driving TFT and the reference voltage Vref for deterioration compensation applied to the source electrode of the driving TFT. It corresponds to the difference.

On the other hand, the degradation compensation circuit 16 controls the low potential driving voltage EVSS to prevent unnecessary light emission of the OLED in the off sequence period. To this end, the degradation compensation circuit 16 may output the low potential driving voltage EVSS higher than the reference voltage for degradation compensation in the off sequence period.

FIG. 3A shows an example of applying a positive bias voltage to display an image during an on sequence period, and FIG. 3B shows an example of applying a negative bias voltage to compensate for deterioration during an off sequence period. In addition, FIG. 4 shows waveforms of driving signals applied in the on/off sequence period.

The present invention provides a compensation signal of opposite polarity without increasing an additional signal line in the display panel and without changing the driving frequency and timing logic for image display in order to improve the problem of shifting the operation characteristics of the driving TFT due to long-time driving. We present a plan to approve

First, the pixel operation during the on-sequence period P1 will be described with reference to FIGS. 3A and 4. Here, during the on-sequence period P1, both the system power (operation power of the deterioration compensation circuit) and the panel driving power (power for driving the display panel) are maintained in an activated state. The on sequence period P1 may include a plurality of display frames including an initialization period, a programming period, and a light emission period.

In the initialization period, the second switch TFT ST2 is turned on to supply an image display reference voltage Vref (eg, 0V) to the second node N2. Subsequently, in the programming period, the first switch TFT ST1 is turned on to supply the image display data voltage Vdata-ON, for example, 10V to the first node N1. In the programming period, the gate-source voltage (Vgs) of the driving TFT (DT) is the difference (10V) between the image display data voltage (Vdata-ON, 10V) and the image display reference voltage (Vref, 0V), that is, positive bias. It is programmed to voltage (+10V). In the light emission period, the first and second switch TFTs ST1 and ST2 are turned off, and the driving TFT DT generates a driving current Ioled according to the programmed positive bias voltage and applies it to the OLED. The OLED emits light with a brightness corresponding to the driving current (Ioled) to display an image. When the on-sequence period P1 is repeated for a long time, the operating characteristic of the driving TFT DT is shifted in the positive (+) direction (that is, the threshold voltage Vth of the driving TFT DT increases).

Next, the pixel operation during the off-sequence period P2 will be described with reference to FIGS. 3B and 4. Here, the system power (operation power of the deterioration compensation circuit) is activated during the off sequence period P2, while the panel driving power (power to drive the display panel) is deactivated.

In the off-sequence period P2, the first and second switch TFTs ST1 and ST2 are turned on, so that the data voltage Vdata-OFF for deterioration compensation (for example, 0V) is supplied from the data voltage supply line to the first node N1. , A reference voltage Vref for deterioration compensation (eg, 7.16V) is supplied from the reference voltage supply line to the second node N2. Therefore, in the off-sequence period P2, the gate-source voltage Vgs of the driving TFT DT is the difference between the data voltage Vdata-OFF, 0V for deterioration compensation and the reference voltage Vref, 7.16V for deterioration compensation. It is set to (-7.16V), that is, the negative bias voltage (-7.16V). Due to this negative bias voltage (-7.16V), the operating characteristics of the driving TFT DT, which has been shifted in the positive (+) direction during the on sequence period P1, can be restored to its original state.

On the other hand, since the reference voltage (Vref, 7.16V) for deterioration compensation is applied high in the off-sequence period (P2), when the low-potential driving voltage (EVSS) is maintained at 0V as in the on-sequence period (P1), deterioration compensation is performed. Unnecessary light emission can be made and recognized by the user. Accordingly, in the present invention, during the off-sequence period P2, the low-potential driving voltage EVSS is adjusted to a predetermined level (eg, 10V) to be higher than the reference voltage Vref, 7.16V for degradation compensation.

5 and 6 show an operation characteristic shift rate due to a positive bias stress and an operation characteristic shift rate due to a negative bias stress.

Applicants set the positive bias voltage to 10V and the negative bias voltage to -7.16V, and conducted an experiment to derive an operating characteristic shift rate for positive/negative bias stress per 1V. 5 and 6, the applicant can find that the operating characteristic shift rate per 1V is 6.5 times higher when applying the negative bias stress compared to when applying the positive bias stress. This means that, assuming that the average TV viewing time per day is 4 hours, the operating characteristics of the driving TFT can be restored to the original state through compensation driving (negative bias driving) of about 36 minutes.

Referring to the above experimental results, the present invention presets the negative bias voltage to be applied to the driving TFT, calculates the negative bias time according to the positive bias time proportional to the driving time, and then calculates the negative bias voltage during the calculated negative bias time. Is applied. In performing such a series of deterioration compensation, the present invention solves the problem of lowering the aperture ratio as in the prior art since the array configuration of the display panel for image display is not changed (ie, signal wiring is not added) and is used as it is. In addition, since the present invention performs deterioration compensation during an off-sequence period rather than an on-sequence period, it is not necessary to change the driving frequency and timing logic for image display due to the deterioration compensation.

7 shows an example of the degradation compensation circuit 16 shown in FIG. 1. In addition, FIGS. 8 and 9 show an operation procedure of the deterioration compensation circuit 16 of FIG. 7 performed in the off sequence period.

Referring to FIG. 7, the degradation compensation circuit 16 includes a driving power detection unit 161, a counter 162, a memory 163, a Tn calculation unit 164, an OFF DATA output unit 165, and a Vref adjustment unit 166. ), EVSS adjustment unit 167 is provided.

The driving power detection unit 161 detects the off of the panel driving power and outputs an off detection signal.

The counter 162 counts the panel driving time starting from when the panel driving power is turned on and until the off detection signal is input. (S1, S2, S3) The counter 162 is a system for counting the panel driving time. It is based on the timing signals (Vsync, DE, etc.) input from The counter 162 derives the panel driving time obtained through the counting operation as a positive bias time Tp, and outputs the value Tp. (S4)

The Tn calculation unit 164 calculates the negative bias time Tn based on the positive bias time Tp input from the counter 162 (S5).

Specifically, the Tn calculation unit 164 reads out the preset negative coefficient α and the positive coefficient β from the memory 163, and then reads out the ratio of the negative coefficient α to the positive coefficient β (α /β) is multiplied by the positive bias time (Tp) to calculate the negative bias time (Tn) (Tn=Tp*α/β). (S5-1, S5-2) Here, the negative coefficient α is the driving It corresponds to a value obtained by dividing the negative shift rate Sn, which is known in advance as the operating characteristic value of the TFT, by a predetermined negative bias voltage Vn. In addition, the positive coefficient β corresponds to a value obtained by dividing the positive shift rate Sp known in advance as the operating characteristic value of the driving TFT by the predetermined positive bias voltage Vp.

The OFF DATA output unit 165 outputs OFF data corresponding to the data voltage for degradation compensation according to a predetermined negative bias voltage Vn during the negative bias time Tn input from the Tn calculation unit 164 do. In addition, the Vref adjustment unit 166 outputs a reference voltage Vref for deterioration compensation according to a predetermined negative bias voltage Vn during the negative bias time Tn input from the Tn calculation unit 164 (S6).

The EVSS adjusting unit 167 adjusts the low-potential driving voltage EVSS and outputs it higher than the reference voltage for deterioration compensation.

This circular drive continues for a negative bias time (Tn) derived through calculation (S7).

10 shows another example of the degradation compensation circuit 16 shown in FIG. 1. In addition, FIGS. 8 and 11 show an operation procedure of the deterioration compensation circuit 16 of FIG. 10 performed in the off sequence period. 12 shows repetitive arrangement timing of on and off sequence periods.

The driving power detection unit 161 detects the off of the panel driving power and outputs an off detection signal.

The counter 162 counts the panel driving time starting from when the panel driving power is turned on and until the off detection signal is input. (S1, S2, S3) The counter 162 is a system for counting the panel driving time. It is based on the timing signals (Vsync, DE, etc.) input from The counter 162 derives the panel driving time obtained through the counting operation as a positive bias time Tp, and outputs the value Tp. (S4)

The Tn calculation unit 164 calculates the negative bias time Tn based on the positive bias time Tp input from the counter 162 (S5).

Specifically, the Tn calculation unit 164 reads out a preset negative coefficient α from the memory 163, receives the positive coefficient β obtained through calculation from the logic unit 170, and then receives the positive coefficient. The negative bias time (Tn) is calculated by multiplying the ratio (α/β) of the negative coefficient (α) to (β) by the positive bias time (Tp) (Tn=Tp*α/β). (S5-3, S5-4)

Here, the negative coefficient α corresponds to a value obtained by dividing the negative shift rate Sn, which is known in advance as the operating characteristic value of the driving TFT, by a predetermined negative bias voltage Vn. The positive coefficient β corresponds to a value obtained by dividing the positive shift rate Sp, which is the operating characteristic value of the driving TFT, by the positive bias voltage Vp. The positive shift rate Sp and the positive bias voltage Vp may be selected as predetermined values, but it is more advantageous in terms of accuracy to calculate through the following calculation process.

The logic unit 170 may include a Vp calculation unit 171, a Vth calculation unit 172, and a β calculation unit 173 to calculate the positive coefficient β. During the positive bias time Tp input from the counter 162, the Vp calculation unit 171 analyzes image data to accumulate representative grayscale values in units of frames, and averages the accumulated representative grayscale values to generate a positive bias voltage (Vp). ). (S5-1) The representative grayscale value may include at least one of a frame average value, a frame maximum value, and a frame mode value.

ㅿVth calculation unit 172 is the threshold voltage (Vth) of the pixels through a predetermined sensing method proposed in the application number 10-2013-0141334, application number 10-2013-0149395 previously applied by the applicant of the present application. Is sensed, and the sensing values acquired in the current off-sequence period (P2(n) in FIG. 12) are compared with the sensing values acquired in the previous off-sequence period (P2(n-1) in FIG. 12) to be positive. The threshold voltage shift amount (ㅿVth) is calculated. The β calculation unit 173 receives the positive bias time Tp and the positive bias voltage Vp from the Vp calculation unit 171, and inputs the positive threshold voltage shift amount (ㅿVth) from the ㅿVth calculation unit 172. Receive. The β calculating unit 173 calculates a positive shift rate Sp by dividing the positive threshold voltage shift amount ㅿVth by the positive bias time Tp. Then, the β calculating unit 173 calculates a positive coefficient β by dividing the positive shift rate Sp by the positive bias voltage Vp. (S5-2)

The OFF DATA output unit 165 outputs OFF data corresponding to the data voltage for degradation compensation according to a predetermined negative bias voltage Vn during the negative bias time Tn input from the Tn calculation unit 164 do. In addition, the Vref adjustment unit 166 outputs a reference voltage Vref for deterioration compensation according to a predetermined negative bias voltage Vn during the negative bias time Tn input from the Tn calculation unit 164 (S6).

The EVSS adjusting unit 167 adjusts the low-potential driving voltage EVSS and outputs it higher than the reference voltage for deterioration compensation.

This circular drive continues for a negative bias time (Tn) derived through calculation (S7).

13 shows an example of a local deterioration compensation scheme.

The above-described deterioration compensation scheme of the present invention may be implemented for the entire area of the display panel 10, or may be implemented locally for the preset afterimage generation predicted areas AR1 and AR2 as shown in FIG. 13. May be. The areas where the afterimage generation is expected (AR1, AR2) may be selected as an area in which a bright image such as a broadcaster logo is continuously displayed.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: data lines 15: gate lines
16: degradation compensation circuit

Claims (6)

A display panel in which a plurality of pixels each including an OLED and a driving TFT are formed; And
In order to restore the operating characteristics of the driving TFT, which changes due to the positive bias voltage, a negative bias voltage is preset, a negative bias time corresponding to the positive bias time to which the positive bias voltage is applied is calculated, and during the calculated negative bias time. A deterioration compensation circuit for applying the negative bias voltage between the gate and source of the driving TFT;
Whereas the positive bias voltage is applied between the gate and source of the driving TFT in the on sequence period for image display, the negative bias voltage is applied between the gate and the source of the driving TFT during the off sequence period for deterioration compensation. Become,
An organic light-emitting display device, wherein a low-potential driving voltage applied to the cathode electrode of the OLED during the off-sequence period is higher than a reference voltage for deterioration compensation applied to the source electrode of the driving TFT for the negative bias voltage. The method of claim 1,
The positive bias voltage is applied to an image driving data voltage applied to the gate electrode of the driving TFT through a data voltage supply line in the on-sequence period and an image driving method applied to the source electrode of the driving TFT through a reference voltage supply line. Indicating the difference between the reference voltages,
The negative bias voltage is applied to the source electrode of the driving TFT through the data voltage for compensation of the deterioration applied to the gate electrode of the driving TFT through the data voltage supply line and the reference voltage supply line in the off-sequence period. An organic light emitting display device, characterized in that indicating a difference between reference voltages for compensation. delete The method of claim 2,
The degradation compensation circuit,
A counter for counting the panel driving time to derive the positive bias time;
A memory for storing preset negative coefficients and positive coefficients;
A Tn calculator configured to calculate the negative bias time by multiplying the ratio of the negative coefficient to the positive coefficient by the positive bias time;
An OFF DATA output unit for outputting off data corresponding to the deterioration compensation data voltage according to the negative bias voltage during the negative bias time; And
And a Vref adjusting unit for outputting the reference voltage for deterioration compensation according to the negative bias voltage during the negative bias time;
The negative coefficient is defined as a value obtained by dividing a negative shift rate, which is an operating characteristic value of the driving TFT, by the negative bias voltage, and the positive coefficient is a value obtained by dividing a positive shift rate, which is an operating characteristic value of the driving TFT, by the positive bias voltage. An organic light emitting display device, characterized in that defined as. The method of claim 2,
The degradation compensation circuit,
A counter for counting the panel driving time to derive the positive bias time;
A memory for storing a preset negative coefficient;
A logic unit that calculates a positive coefficient;
A Tn calculator configured to calculate the negative bias time by multiplying the ratio of the negative coefficient to the positive coefficient by the positive bias time;
An OFF DATA output unit for outputting off data corresponding to the deterioration compensation data voltage according to the negative bias voltage during the negative bias time; And
And a Vref adjusting unit for outputting the reference voltage for deterioration compensation according to the negative bias voltage during the negative bias time;
The negative coefficient is defined as a value obtained by dividing a negative shift rate, which is an operating characteristic value of the driving TFT, by the negative bias voltage, and the positive coefficient is a value obtained by dividing a positive shift rate, which is an operating characteristic value of the driving TFT, by the positive bias voltage. An organic light emitting display device, characterized in that defined as. The method of claim 5,
The logic unit,
A Vp calculator configured to calculate the positive bias voltage by analyzing image data during the positive bias time, accumulating representative grayscale values for each frame, and averaging the accumulated representative grayscale values;
A ㅿVth calculator for calculating a positive threshold voltage shift amount by comparing the threshold voltage sensing values of the driving TFTs acquired in the adjacent off-sequence periods; And
An organic light-emitting display comprising a β calculator configured to calculate the positive coefficient by dividing the positive threshold voltage shift amount by the positive bias time to calculate a positive shift rate, and then dividing the positive shift rate by the positive bias voltage to calculate the positive coefficient. Device.

Images