KR102168195B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display having a structure in which one data signal is divided into two data lines at a data signal output terminal and input in a liquid crystal display of a double rate driving (DRD) type. First to eighth subpixels arranged in four rows; First to fourth gate wires disposed in a horizontal direction for each of the subpixels in each row and having two subpixels formed between the subpixels in each row; First to fourth data lines intersecting the first to fourth gate lines and disposed between the subpixels in each column from the left of the subpixels in the first column; And first to eighth thin film transistors respectively disposed on the first to eighth subpixels, wherein a first data signal is applied from a first data signal output terminal to the first and third data lines, and the second And a second data signal is applied to the fourth data line from the second data signal output terminal.

Description

Liquid crystal display device

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display having a structure in which one data signal is divided into two data wirings at an output terminal of a data signal in a liquid crystal display of a double rate driving (DRD) type.

In recent years, due to the rapid progress of semiconductor technology, the demand for a flat panel display device as an electronic display device suitable for a new environment is rapidly increasing in accordance with the trend of low voltage and low power consumption of various electronic devices, as well as miniaturization, thinness and weight reduction of electronic devices. It is increasing.

Accordingly, flat panel display devices such as a liquid crystal display device (LCD), a plasma display device (PDP), and an organic EL display device (OELD) are being developed, and among these flat panel display devices, it is easy to reduce size, weight, and thickness. In particular, a liquid crystal display device having a low power consumption and a low driving voltage is drawing attention.

In a liquid crystal display, a liquid crystal material having anisotropic dielectric constant is injected between an upper transparent insulating substrate on which a common electrode, a color filter, a black matrix, etc. are formed, and a lower transparent insulating substrate on which a switching element and pixel electrode are formed. By applying different potentials to the electrode and the common electrode, the intensity of the electric field formed in the liquid crystal material is adjusted to change the molecular arrangement of the liquid crystal material, and through this, the amount of light transmitted through the transparent insulating substrate is adjusted to express a desired image. It is a display device.

As such a liquid crystal display, a thin film transistor liquid crystal display (TFT LCD) using a thin film transistor (TFT) element as a switching element is mainly used.

Such a liquid crystal display device includes a liquid crystal display panel on which an image is displayed. When driving the liquid crystal display panel, in order to prevent deterioration of the internal liquid crystal and improve the display quality of the image, the polarity is reversed in a certain unit. It is common that the version drive method is used.

The inversion driving method is classified into a frame inversion method, a line inversion method, and a dot inversion method according to a unit in which the polarity is inverted. In recent years, unlike the above method, a Z inversion method has been proposed to reduce the power consumption of the circuit unit by reducing voltage variation.

In the Z-inversion method, the TFTs formed on the liquid crystal panel are arranged in zigzag in the vertical line direction, and the polarity controlled data is supplied to the liquid crystal panel in a column inversion method using a column inversion type data driving circuit. It is a method of driving by dot inversion.

This Z-inversion method can improve display quality by minimizing flicker between vertical and horizontal lines as the liquid crystal panel is driven by dot inversion, and when the liquid crystal panel is driven using a dot inversion data driving circuit. Compared to this, power consumption can be reduced.

The liquid crystal display device includes a gate driver for driving the gate lines GL and a data driver for driving the data lines DL, and the number of ICs constituting the required driving unit increases as the LCD device becomes larger and higher in resolution. Are doing.

However, since the IC of the data driver is relatively expensive compared to other devices, several methods to reduce the number of ICs are being researched and developed in recent years to lower the production cost of liquid crystal display devices. Instead of doubling the number of devices, a double rate driving (DRD) method was proposed that reduced the number of data lines by 1/2, reducing the number of ICs required by half, and implementing the same resolution as before.

A DRD type liquid crystal display device drives a plurality of liquid crystal cells arranged on one horizontal line by using two gate wires and data wires of 1/2 of the plurality of liquid crystal cells.

1 is a diagram showing a conventional DRD type liquid crystal display. The liquid crystal display is formed above and below the first to eighth subpixels SP1 to SP8 arranged in two rows and four columns, and the first to eighth subpixels SP1 to SP8, and between the subpixels of each row. There are two first to fourth gate wires GL1 to GL4, and the first to fourth gate wires GL1 to GL4, and the first to fourth gate wires GL1 to GL4, each formed from the left of the first row to the second row of subpixels. First to third data lines DL1 to DL3, and first to eighth thin film transistors T1 to T8 respectively formed in the first to eighth subpixels SP1 to SP8.

The first gate wiring GL1 is connected to the second and fourth thin film transistors T2 and T4, and the second gate wiring GL2 is connected to the first and third thin film transistors T1 and T3, and the third The gate wiring GL3 is connected to the sixth and eighth thin film transistors T6 and T8.

The fourth gate wiring GL4 is connected to the fifth and seventh thin film transistors T5 and T7, and the first data line DL1 is connected to the first and fifth thin film transistors T1 and T5, and the second The data line DL2 is connected to the second, third, sixth, and seventh thin film transistors T2, T3, T6 and T7, and the third data line DL3 is the fourth and eighth thin film transistors T4 and T7. T8) is connected.

As shown in FIG. 1, such a DRD type liquid crystal display is driven in a horizontal 2-dot inversion method to minimize flicker and reduce power consumption.

Accordingly, two subpixels adjacent to each other with one data line interposed therebetween are connected to the two gate lines, respectively, and a data signal having the same polarity supplied through the data line is applied.

Accordingly, when a gate signal is applied to the first gate line GL1, the second and fourth thin film transistors T2 and T4 are turned on, and the second subpixel SP2 is connected to the second subpixel SP2 through the second data line DL2. A data signal of negative polarity (-) is applied, a data signal of positive polarity (+) is applied to the fourth subpixel SP4 through the fourth data line DL4, and sequentially, the second gate line GL2 When a gate signal is applied to, the first and third thin film transistors T1 and T3 are turned on, and a positive data signal is applied to the first sub-pixel SP1 through the first data line DL1. When a data signal of negative polarity (-) is applied to the third subpixel SP3 through the second data line DL2, and a gate signal is sequentially applied to the third gate line GL3, the 6th and 8 The thin film transistors T6 and T8 are turned on, a negative data signal is applied to the sixth subpixel SP6 through the second data line DL2, and the third data line DL3 is connected. When a data signal of positive polarity (+) is applied to the eighth sub-pixel SP8 and the gate signal is sequentially applied to the fourth gate line GL4, the fifth and seventh thin film transistors T5 and T7 are turned. -The data signal of positive polarity (+) is applied to the fifth sub-pixel SP5 through the first data line DL1 and sub-pixels SP7 through the second data line DL2. A data signal of polarity (-) is applied.

In the liquid crystal display device according to the prior art constructed as described above, one data signal is applied to each data line from one data signal output terminal of the data driver IC, and the polarity of the two columns of subpixels arranged on the left and right sides of each data line is Each of the two columns has the same polarity as positive (+) or negative (-), and there is a problem that afterimages or defects in vertical lines occur when driving Z inversion, and to solve the above problems. When 2 dot inversion is driven, there is a problem that more power consumption is consumed than when the Z inversion is driven.

In addition, as the PPI (pixel per inch) of the liquid crystal panel increases, the non-opening areas such as the gate wiring and the data wiring increase, and the aperture ratio decreases. In particular, in the case of the DRD structure, the gate wiring doubles and increases as much as the gate wiring area. There is a problem that the aperture ratio decreases.

The present invention is to solve the conventional problems as described above, by reducing the number of data driver ICs through the DRD method, to reduce the production cost of a liquid crystal display device, and to reduce the power consumption of the liquid crystal display device through Z-inversion driving. It is an object of the present invention to provide a liquid crystal display device capable of maximizing an aperture ratio by preventing liquid crystal deterioration of a liquid crystal panel, improving image defects, and reducing a non-opening area.

The present invention for achieving the above object is, the first to eighth subpixels arranged in two rows and four columns, and the subpixels of each row are arranged in a horizontal direction, but between the subpixels of each row 2 First to fourth data wires intersecting the first to fourth gate wires in which dogs are disposed and the first to fourth gate wires and disposed between the subpixels in each column from the left of the subpixel in the first column, and the first to fourth data wires, respectively. Including first to eighth thin film transistors respectively formed in the eighth subpixel, the first data signal is applied from the first data signal output terminal to the first and third data wires, and the second and fourth data wires There is provided a DRD type liquid crystal display device, characterized in that a second data signal is applied from a second data signal output terminal.

In addition, the second and fourth thin film transistors are connected to the first gate wire, the first and third thin film transistors are connected to the second gate wire, and the fifth and seventh thin film transistors are connected to the third Is connected to a gate line, the sixth and eighth thin film transistors are connected to the fourth gate line, the first thin film transistor is connected to the first data line, and the fifth and sixth thin film transistors are connected to the first data line. 2 is connected to the data line, the second and seventh thin film transistors are connected to the third data line, and the third and fourth thin film transistors are connected to the fourth data line.

In addition, the second and third thin film transistors are connected to the first gate wire, the first and fourth thin film transistors are connected to the second gate wire, and the fifth and eighth thin film transistors are connected to the third gate wire. Is connected to a gate line, the sixth and seventh thin film transistors are connected to the fourth gate line, the first and fifth thin film transistors are connected to the first data line, and the second and sixth thin film transistors Is connected to the second data line, the third and seventh thin film transistors are connected to the third data line, and the fourth and eighth thin film transistors are connected to the fourth data line.

In addition, the second and third thin film transistors are connected to the first gate wire, the first and fourth thin film transistors are connected to the second gate wire, and the fifth and eighth thin film transistors are connected to the third gate wire. Is connected to a gate line, the sixth and seventh thin film transistors are connected to the fourth gate line, the first thin film transistor is connected to the first data line, and the second and fifth thin film transistors are connected to the first data line. 2 is connected to the data line, the third and sixth thin film transistors are connected to the third data line, and the fourth and seventh thin film transistors are connected to the fourth data line.

Further, a polarity of the first data signal and a polarity of the second data signal are opposite to each other.

In addition, the first to eighth thin film transistors may be formed by being disposed to the left or right of the first to eighth subpixels, respectively.

In addition, a data signal may be applied to the first to eighth subpixels from one of left and right data lines of each subpixel.

In addition, a portion where the third data line and the second data link line connected to the second data line by a second bridge pattern intersect, or the second data line and the third data line by a third bridge pattern. A portion where the connected third data link wiring crosses is arranged in different layers.

1st to 32nd subpixels arranged in 4 rows and 8 columns, and 1st to 8th gate wirings which are horizontally arranged at the top and bottom of the subpixels in each row, and 2 are arranged between the subpixels in each row, and the First to eighth data wires intersecting with the first to eighth gate wires and disposed between the subpixels in each column from the left of the subpixels in the first column, and first to 32th thin film transistors respectively disposed in the plurality of subpixels A first data signal is applied from a first data signal output terminal to the first and fifth data wires, a second data signal is applied from a second data signal output terminal to the second and sixth data wires, DRD, characterized in that a third data signal is applied from a third data signal output terminal to the third and seventh data wires, and a fourth data signal is applied from a fourth data signal output terminal to the fourth and eighth data wires. It provides a liquid crystal display device.

The second, fourth, sixth, and eighth thin film transistors are connected to the first gate wire, the first, third, fifth and seventh thin film transistors are connected to the second gate wire, The 10th, 12th, 14th, and 16th thin film transistors are connected to the third gate line, the ninth, 11th, 13th, and 15th thin film transistors are connected to the fourth gate line, and the 18th , 20th, 22nd, and 24th thin film transistors are connected to the fifth gate line, the 17th, 19th, 21st, and 23rd thin film transistors are connected to the sixth gate line, and the 26th, 28th, 30th, and 32th thin film transistors are connected to the seventh gate line, and the 25th, 27th, 29th and 31st thin film transistors are connected to the eighth gate line,

The first and ninth thin film transistors are connected to the first data line, and the 17th, 18th, 25th and 26th thin film transistors are connected to the second data line, and the second, tenth, and The 19th and 27th thin film transistors are connected to the third data line, the third, fourth, eleventh, and 12th thin film transistors are connected to the fourth data line, and the 20th, 21st, 28th and The 29th thin film transistor is connected to the fifth data line, the fifth, sixth, 13th, and 14th thin film transistors are connected to the sixth data line, and the 7, 15th, 22nd and 30th thin film transistors are connected to the sixth data line. The DRD type liquid crystal display device, wherein the thin film transistor is connected to the seventh data line, and the 23rd, 24th, 31st, and 32nd thin film transistors are connected to the eighth data line.

In addition, polarities of the first and third data signals and polarities of the second and fourth data signals are opposite to each other.

In addition, the second to fourth data lines and the fifth to seventh data link lines are located on different layers.

In addition, the second to fourth data wires and the fifth data link wires are intersected to each other, and first to third regions overlap each other, and the third and fourth data wires and the sixth data link wires cross each other. And a sixth region overlapping the fourth and fifth regions and crossing and overlapping the fourth data line and the seventh data link line.

In addition, a common wire intersecting the first to eighth data wires and extending from the common wires and the common wires respectively positioned above the first gate wires overlaps the first to third and sixth to eighth data wires, respectively. It further includes first to sixth compensation patterns.

In addition, the first to third areas are the same as the area of the first compensation pattern.

In addition, the third, fifth and sixth regions are the same as the area of the sixth compensation pattern.

In addition, the fourth and fifth regions and the fourth compensation pattern are the same as the area of the second compensation pattern, and the second and fourth regions, and the third compensation pattern are of the fifth compensation pattern. It is characterized by the same area as the area.

Further, first to 22nd subpixels arranged in 2 rows and 11 columns; The first to fourth gate wires are formed in a horizontal direction for each of the subpixels in each row, and two subpixels are formed between the subpixels in each row and the first and second gate wires cross each other, and the subpixels in the first column From the left side, first to twelfth data lines respectively formed between subpixels in each column and first to 22th thin film transistors respectively formed in the plurality of subpixels, and the first and seventh data lines include first A first data signal is applied from a data signal output terminal, a second data signal is applied from a second data signal output terminal to the second and eighth data wires, and a third data signal output terminal is applied to the third and ninth data wires. A third data signal is applied, a fourth data signal is applied from a fourth data signal output terminal to the fourth and tenth data wires, and a fifth data signal is applied from a fifth data signal output terminal to the fifth and eleventh data wires. Is applied, and a sixth data signal is applied to the sixth and twelfth data lines from a sixth data signal output terminal.

The present invention reduces the number of ICs in the data driver through the DRD method, thereby reducing the production cost of the liquid crystal display device, reducing the power consumption of the liquid crystal display device through Z-inversion driving, preventing liquid crystal deterioration of the liquid crystal panel, and image defects. Can be improved. In addition, since each thin film transistor can be freely arranged to the left or right of the sub-pixel, two thin film transistors can be gathered in one place, thereby reducing the non-opening area to maximize the aperture ratio. In particular, while driving DRD and Z inversion, each thin film transistor formed in each subpixel can receive a data signal from any one of the left and right data lines of the subpixel, so the liquid crystal panel is inverted with 2 dots horizontally and 2 dots vertically. Both version and 1-dot inversion can be selectively driven.

1 is a diagram showing a conventional DRD type liquid crystal display.
2 is a view showing a first embodiment of the present invention.
3 is a diagram showing a second embodiment of the present invention.
4 is a diagram showing a third embodiment of the present invention.
5A is a first diagram illustrating an array substrate corresponding to A of FIG. 2.
5B is a second diagram illustrating an array substrate corresponding to A of FIG. 2.
6 is a diagram showing a fourth embodiment of the present invention.
7 is a plan view of an array substrate corresponding to B of FIG. 6.
8 is a diagram showing a fifth embodiment of the present invention.

In the following description, the drawings referenced for the embodiments of the present specification are not intended to limit the shape and position of the constituent elements to the illustrated form, and in particular, the drawings provide an understanding of the structure and shape, which are technical features of the present invention. To help, the scale of some components is exaggerated or reduced. In addition, in the following description, components overlapping with the conventional liquid crystal display device are omitted for convenience of description.

Hereinafter, the liquid crystal display device according to the present invention will be described in more detail with reference to the accompanying drawings.

<First Example>

2 is a diagram illustrating a liquid crystal panel driven by a horizontal 2-dot inversion method according to the first embodiment of the present invention. As shown in FIG. 2, the liquid crystal display device of the present invention includes first to eighth subpixels SP1 to SP8 arranged in two rows and four columns, and each of the subpixels in each row is formed in a horizontal direction. The first to fourth gate wires GL1 to GL4 are formed between the subpixels in the row, and the first to fourth gate wires GL1 to GL4 cross each other, and the subpixels in each column from the left of the subpixel in the first column First to fourth data lines DL1 to DL4 respectively formed therebetween, and first to eighth thin film transistors T1 to T8 respectively formed in the first to eighth subpixels SP1 to SP8. .

A first data signal is applied from a first data signal output terminal DS1 of a data driver IC to the first and third data lines DL1 and DL3, and data is applied to the second and fourth data lines DL2 and DL4. The second data signal is applied from the second data signal output terminal DS2 of the driver IC.

The polarities of the first data signal applied to the first and third data lines DL1 and DL3 and the polarity of the second data signal applied to the second and fourth data lines DL2 and DL4 are opposite to each other. .

For example, the first data signal may have a positive polarity (+) and the second data signal may have a negative polarity (-). Gate signals are sequentially applied to the first to fourth gate lines GL1 to GL4. When a gate signal is applied through the first gate line GL1, the second and fourth thin film transistors T2 and T4 are turned- When turned on and the first data signal is applied from the first data signal output terminal DS1 through the third data line DL1, the polarity of the second subpixel SP2 becomes positive (+), and the second data signal When the second data signal is applied from the output terminal DS2 through the fourth data line DL4, the polarity of the fourth subpixel SP4 becomes negative (-).

When a gate signal is applied through the second gate line GL2, the first and third thin film transistors T1 and T3 are turned on, and the first data signal is transferred from the first data signal output terminal DS1 to the first data line. When applied through (DL1), the polarity of the first subpixel SP1 becomes positive (+), and when a second data signal is applied from the second data signal output terminal DS2 through the fourth data line DL4 The polarity of the third sub-pixel SP3 becomes negative (-).

When a gate signal is applied through the third gate line GL3, the fifth and seventh thin film transistors T5 and T7 are turned on, and the second data signal is transferred from the second data signal output terminal DS2 to the second data line. When applied through (DL2), the polarity of the fifth subpixel SP5 becomes negative (-), and when the first data signal is applied from the first data signal output terminal DS1 through the third data line DL3 The polarity of the seventh subpixel SP7 is positive (+).

When a gate signal is applied through the fourth gate line GL4, the sixth and eighth thin film transistors T6 and T8 are turned on, and the second data signal is transferred from the second data signal output terminal DS2 to the second data line. When applied through (DL2), the polarity of the sixth sub-pixel SP6 becomes negative (-).

Accordingly, the first embodiment of the present invention reduces the number of data driver ICs through the DRD method to reduce the production cost of the liquid crystal display device, and reduces the power consumption of the liquid crystal display device through Z-inversion driving. It is possible to prevent liquid crystal deterioration and improve image defects.

<Second Example>

3 is a diagram illustrating a liquid crystal panel driven by a vertical two-dot inversion method according to a second embodiment of the present invention. As shown in FIG. 3, the liquid crystal display of the present invention includes first to eighth subpixels (SP1 to SP8) arranged in two rows and four columns, and each of the subpixels in each row is formed in a horizontal direction. The first to fourth gate wires GL1 to GL4 are formed between the subpixels in the row, and the first to fourth gate wires GL1 to GL4 cross each other, and the subpixels in each column from the left of the subpixel in the first column First to fourth data lines DL1 to DL4 respectively formed therebetween, and first to eighth thin film transistors T1 to T8 respectively formed in the first to eighth subpixels SP1 to SP8.

A first data signal is applied from a first data signal output terminal DS1 of a data driver IC to the first and third data lines DL1 and DL3, and data is applied to the second and fourth data lines DL2 and DL4. The second data signal is applied from the second data signal output terminal DS2 of the driver IC.

The polarities of the first data signal applied to the first and third data lines DL1 and DL3 and the polarity of the second data signal applied to the second and fourth data lines DL2 and DL4 are opposite to each other. .

For example, the first data signal may have a positive polarity (+) and the second data signal may have a negative polarity (-). Gate signals are sequentially applied to the first to fourth gate lines GL1 to GL4. When a gate signal is applied through the first gate line GL1, the second and third thin film transistors T2 and T3 are turned- When turned on and the first data signal is applied from the first data signal output terminal DS1 through the third data line DL3, the polarity of the third subpixel SP3 becomes positive (+), and the second data signal When the second data signal is applied from the output terminal DS2 through the second data line DL2, the polarity of the second subpixel SP2 becomes negative (-).

When a gate signal is applied through the second gate line GL2, the first and fourth thin film transistors T1 and T4 are turned on, and the first data signal is transferred from the first data signal output terminal DS1 to the first data line. When applied through (DL1), the polarity of the first subpixel SP1 becomes positive (+), and when a second data signal is applied from the second data signal output terminal DS2 through the fourth data line DL4 The polarity of the fourth sub-pixel SP4 becomes negative (-).

When a gate signal is applied through the third gate line GL3, the fifth and eighth thin film transistors T5 and T8 are turned on, and the first data signal is transferred from the first data signal output terminal DS1 to the first data line. When applied through (DL1), the polarity of the fifth sub-pixel SP5 becomes positive (+), and when the second data signal is applied from the second data signal output terminal DS2 through the fourth data line DL4 The polarity of the eighth subpixel SP8 becomes negative (-).

When a gate signal is applied through the fourth gate line GL4, the sixth and seventh thin film transistors T6 and T7 are turned on, and the first data signal is transferred from the first data signal output terminal DS1 to the third data line. When applied through (DL3), the polarity of the seventh sub-pixel SP7 becomes positive (+), and when the second data signal is applied from the second data signal output terminal DS2 through the second data line DL2 The polarity of the sixth sub-pixel SP6 becomes negative (-).

Accordingly, the second embodiment of the present invention reduces the number of data driver ICs through the DRD method to reduce the production cost of the liquid crystal display device, and reduces the power consumption of the liquid crystal display device through Z-inversion driving. It is possible to prevent liquid crystal deterioration and improve image defects.

<Third Example>

4 is a diagram illustrating a liquid crystal panel driven by a 1-dot inversion method according to a third embodiment of the present invention. As shown in FIG. 4, the liquid crystal display of the present invention includes first to eighth subpixels (SP1 to SP8) arranged in two rows and four columns, and each of the subpixels in each row is formed in a horizontal direction. The first to fourth gate wires GL1 to GL4 are formed between the subpixels in the row, and the first to fourth gate wires GL1 to GL4 cross each other, and the subpixels in each column from the left of the subpixel in the first column First to fourth data lines DL1 to DL4 respectively formed therebetween, and first to eighth thin film transistors T1 to T8 respectively formed in the first to eighth subpixels SP1 to SP8. .

A first data signal is applied from a first data signal output terminal DS1 of a data driver IC to the first and third data lines DL1 and DL3, and data is applied to the second and fourth data lines DL2 and DL4. The second data signal is applied from the second data signal output terminal DS2 of the driver IC.

The polarities of the first data signal applied to the first and third data lines DL1 and DL3 and the polarity of the second data signal applied to the second and fourth data lines DL2 and DL4 are opposite to each other. .

For example, the first data signal may have a positive polarity (+) and the second data signal may have a negative polarity (-). Gate signals are sequentially applied to the first to fourth gate lines GL1 to GL4. When a gate signal is applied through the first gate line GL1, the second and third thin film transistors T2 and T3 are turned- When turned on and the first data signal is applied from the first data signal output terminal DS1 through the third data line DL3, the polarity of the third subpixel SP3 becomes positive (+), and the second data signal When the second data signal is applied from the output terminal DS2 through the second data line DL2, the polarity of the second subpixel SP2 becomes negative (-).

When a gate signal is applied through the second gate line GL2, the first and fourth thin film transistors T1 and T4 are turned on, and the first data signal is transferred from the first data signal output terminal DS1 to the first data line. When applied through (DL1), the polarity of the first subpixel SP1 becomes positive (+), and when a second data signal is applied from the second data signal output terminal DS2 through the fourth data line DL4 The polarity of the fourth sub-pixel SP4 becomes negative (-).

When a gate signal is applied through the third gate line GL3, the fifth and eighth thin film transistors T5 and T8 are turned on, and the second data signal is transferred from the second data signal output terminal DS2 to the second data line. When applied through (DL2), the polarity of the fifth sub-pixel SP5 becomes negative (-).

When a gate signal is applied through the fourth gate line GL4, the sixth and seventh thin film transistors T6 and T7 are turned on, and the first data signal is transferred from the first data signal output terminal DS1 to the third data line. When applied through (DL3), the polarity of the sixth sub-pixel SP6 becomes positive (+), and when the second data signal is applied from the second data signal output terminal DS2 through the fourth data line DL4 The polarity of the seventh subpixel SP7 becomes negative (-).

In particular, as shown in FIGS. 2 to 4, each thin film transistor formed in each subpixel can be freely disposed to the left or right of the subpixel, so that the first to eighth subpixels SP1 to SP8 A data signal of positive polarity (+) or negative polarity (-) may be applied from any one of the left and right data lines of each subpixel.

Accordingly, the third embodiment of the present invention reduces the number of data driver ICs through the DRD method to reduce the production cost of the liquid crystal display device, and reduces the power consumption of the liquid crystal display device through Z-inversion driving. It is possible to prevent liquid crystal deterioration and improve image defects.

5A and 5B are first and second views illustrating an array substrate corresponding to A of FIG. 2.

First, as shown in FIG. 5A, the first to fourth data lines DL1 to DL4 and the first to fourth data lines DL1 to DL4 are connected on a substrate in a non-display area between the data driver IC and the subpixel. Exposing portions of the first to fourth data link wires (DLL1 to DLL4), the first to fourth data wires (DL1 to DL4), and the first to fourth data link wires (DLL1 to DLL4) respectively connected The first to eighth contact holes CH1 to CH8, the first to fourth data lines DL1 to DL4, and the first to fourth data link lines DLL1 to DLL4 are connected to the first to eighth contact holes. First to fourth bridge patterns BP1 to BP4 electrically connected through (CH1 to CH8), respectively.

The first data line DL1 and the first data link line DLL1 are connected by a first bridge pattern BP1 electrically connected through the second and first contact holes CH2 and CH1, respectively, and the third data The wiring DL3 and the third data link wiring DLL3 are connected by a third bridge pattern BP3 electrically connected through the fourth and third contact holes CH4 and CH3, respectively, and the first and third data The link wirings DLL1 and DLL3 are connected to the first data signal output terminal (not shown) of the data driver IC.

The second data line DL2 and the second data link line DLL2 are connected by a second bridge pattern BP2 electrically connected through the sixth and fifth contact holes CH6 and CH5, respectively, and the fourth data The wiring DL4 and the fourth data link wiring DLL4 are connected by a fourth bridge pattern BP4 electrically connected through the eighth and seventh contact holes CH8 and CH7, respectively, and the second and fourth data The link wirings DLL2 and DLL4 are connected to a second data signal output terminal (not shown) of the data driver IC.

In addition, the first to fourth data wires DL1 to DL4 are formed of the same layer and the same material as the source and drain electrodes of a thin film transistor (not shown), and the first to fourth data link wires DLL1 to DLL4 Silver is formed of the same layer and the same material as the gate electrode of the thin film transistor (not shown), and the first to fourth bridge patterns BP1 to BP4 are made of the same layer and the same material as the pixel electrode of the thin film transistor (not shown). Can be formed.

In particular, the third data line DL3 and the second data link line DLL2 are formed to cross each other and are formed of different layers.

And, as shown in FIG. 5B, on the substrate in the non-display area between the data driver IC and the subpixel, the first to fourth data lines DL1 to DL4 and the first to fourth data lines DL1 to DL4 are connected. Exposing portions of the first to fourth data link wires (DLL1 to DLL4), the first to fourth data wires (DL1 to DL4), and the first to fourth data link wires (DLL1 to DLL4) respectively connected The first to eighth contact holes CH1 to CH8, the first to fourth data lines DL1 to DL4, and the first to fourth data link lines DLL1 to DLL4 are connected to the first to eighth contact holes. First to fourth bridge patterns BP1 to BP4 electrically connected through (CH1 to CH8), respectively.

The first data line DL1 and the first data link line DLL1 are connected by a first bridge pattern BP1 electrically connected through the second and first contact holes CH2 and CH1, respectively, and the third data The wiring DL3 and the third data link wiring DLL3 are connected by a third bridge pattern BP3 electrically connected through the fourth and third contact holes CH4 and CH3, respectively, and the first and third data The link wirings DLL1 and DLL3 are connected to the first data signal output terminal (not shown) of the data driver IC.

The second data line DL2 and the second data link line DLL2 are connected by a second bridge pattern BP2 electrically connected through the sixth and fifth contact holes CH6 and CH5, respectively, and the fourth data The wiring DL4 and the fourth data link wiring DLL4 are connected by a fourth bridge pattern BP4 electrically connected through the eighth and seventh contact holes CH8 and CH7, respectively, and the second and fourth data The link wirings DLL2 and DLL4 are connected to a second data signal output terminal (not shown) of the data driver IC.

In addition, the first to fourth data wires DL1 to DL4 are formed of the same layer and the same material as the source and drain electrodes of a thin film transistor (not shown), and the first to fourth data link wires DLL1 to DLL4 Silver is formed of the same layer and the same material as the gate electrode of the thin film transistor (not shown), and the first to fourth bridge patterns BP1 to BP4 are made of the same layer and the same material as the pixel electrode of the thin film transistor (not shown). Can be formed.

In particular, the second data line DL2 and the third data link line DLL3 are formed to cross each other and are formed of different layers.

<Fourth Example>

6 is a diagram illustrating a liquid crystal panel driven by a 4-dot inversion method according to a fourth embodiment of the present invention.

As shown in FIG. 6, the liquid crystal display device of the present invention is formed in a horizontal direction for each of the first to 32nd subpixels SP1 to SP32 arranged in 4 rows and 8 columns, and the subpixels in each row. The first to eighth gate wires GL1 to GL8 and the first to eighth gate wires GL1 to GL8 are formed between the subpixels in each row, and from the left of the subpixels in the first column to the subpixels in each column First to eighth data lines DL1 to DL8 each formed between pixels, and first to 32th thin film transistors T1 to T32 respectively formed on the plurality of subpixels.

A first data signal is applied from a first data signal output terminal DS1 to the first and fifth data lines DL1 to DL5, and a second data signal output terminal is applied to the second and sixth data lines DL2 to DL6. A second data signal is applied from DS2, a third data signal is applied from the third data signal output terminal DS3 to the third and seventh data lines DL3 and DL7, and the fourth and eighth data The fourth data signal is applied from the fourth data signal output terminal DS4 to the wirings DL4 and DL8.

Polarities of the first and third data signals and polarities of the second and fourth data signals are opposite to each other.

For example, when the first and third data signals have positive polarity (+) and the second and fourth data signals have negative polarity (-), the gates are sequentially gated to the first to eighth gate lines GL1 to GL8. A signal is applied. When a gate signal is applied through the first gate line GL1, the second, fourth, sixth, and eighth thin film transistors T2, T4, T6, and T8 are turned on, and the second data When the second data signal is applied from the signal output terminal DS2 through the sixth data line DL6, the polarity of the sixth subpixel SP6 becomes negative (-), and the second data signal is applied from the third data signal output terminal DS3. 3 When the data signal is applied through the third data line DL3, the polarity of the second sub-pixel SP2 becomes positive (+), and the fourth data signal is transferred from the fourth data signal output terminal DS4 to the fourth data signal. When applied through the wiring DL4, the polarity of the fourth subpixel SP4 becomes negative (-).

Next, when a gate signal is applied through the second gate line GL2, the first, third, fifth, and seventh thin film transistors T1, T3, T5, and T7 are turned on, and the first data signal output terminal ( When the first data signal from DS1) is applied through the first data line DL1, the polarity of the first sub-pixel SP1 becomes positive (+), and the second data signal is output from the second data signal output terminal DS2. When is applied through the sixth data line DL6, the polarity of the fifth sub-pixel SP5 becomes negative (-), and the third data signal is transferred from the third data signal output terminal DS3 to the seventh data line DL7. ), the polarity of the seventh subpixel SP7 becomes positive (+), and if the fourth data signal from the fourth data signal output terminal DS4 is applied through the fourth data line DL4, the third The polarity of the sub-pixel SP3 becomes negative (-).

Next, when a gate signal is applied through the third gate line GL3, the 10th, 12th, 14th, and 16th thin film transistors T10, T12, T14, T16 are turned on, and the second data signal output terminal ( When the second data signal from DS2) is applied through the sixth data line DL6, the polarity of the 14th subpixel SP14 becomes negative (-), and the third data signal from the third data signal output terminal DS3 When is applied through the third data line DL3, the polarity of the tenth sub-pixel SP10 becomes positive (+), and the fourth data signal from the fourth data signal output terminal DS4 is transferred to the fourth data line DL4. When applied through ), the polarity of the twelfth sub-pixel SP12 becomes negative (-).

Next, when a gate signal is applied through the fourth gate line GL4, the ninth, eleventh, thirteenth, and fifteenth thin film transistors T9, T11, T13, and T15 are turned on, and the first data signal output terminal ( When the first data signal from DS1) is applied through the first data line DL1, the polarity of the ninth sub-pixel SP9 becomes positive (+), and the second data signal is output from the second data signal output terminal DS2. When is applied through the sixth data line DL6, the polarity of the thirteenth sub-pixel SP13 becomes negative (-), and the third data signal from the third data signal output terminal DS3 is transferred to the seventh data line DL7. ), the polarity of the fifteenth subpixel SP15 becomes positive (+), and if the fourth data signal from the fourth data signal output terminal DS4 is applied through the fourth data line DL4, the eleventh The polarity of the sub-pixel SP11 becomes negative (-).

Next, when a gate signal is applied through the fifth gate line GL5, the 18th, 20th, 22nd, and 24th thin film transistors T18, T20, T22, T24 are turned on, and the first data signal output terminal ( When the first data signal from DS1) is applied through the fifth data line DL5, the polarity of the 20th subpixel SP20 becomes positive (+), and the second data signal from the second data signal output terminal DS2 When is applied through the second data line DL2, the polarity of the 18th sub-pixel SP18 becomes negative (-), and the third data signal from the third data signal output terminal DS3 is transferred to the seventh data line DL7. ), the 22nd subpixel SP22 has a positive polarity (+), and when the 4th data signal is applied from the 4th data signal output terminal DS4 through the 8th data line DL8, the 24th The polarity of the sub-pixel SP24 becomes negative (-).

Next, when a gate signal is applied through the sixth gate line GL6, the 17th, 19th, 21st, and 23rd thin film transistors T17, T19, T21, T23 are turned on, and the first data signal output terminal ( When the first data signal from DS1) is applied through the fifth data line DL5, the polarity of the 21st subpixel SP21 becomes positive (+), and the second data signal from the second data signal output terminal DS2 When is applied through the second data line DL2, the polarity of the 17th sub-pixel SP17 becomes negative (-), and the third data signal from the third data signal output terminal DS3 is transferred to the third data line DL3. ), the polarity of the 19th subpixel SP19 becomes positive (+), and when the fourth data signal from the fourth data signal output terminal DS4 is applied through the eighth data line DL8, the 23rd The polarity of the sub-pixel SP23 becomes negative (-).

Next, when a gate signal is applied through the seventh gate line GL7, the 26th, 28th, 30th, and 32th thin film transistors T26, T28, T30, and T32 are turned on, and the first data signal output terminal ( When the first data signal from DS1) is applied through the fifth data line DL5, the polarity of the 28th subpixel SP28 becomes positive (+), and the second data signal from the second data signal output terminal DS2 When is applied through the second data line DL2, the polarity of the 26th sub-pixel SP26 becomes negative (-), and the third data signal is transferred from the third data signal output terminal DS3 to the seventh data line DL7. ), the polarity of the 30th subpixel SP30 becomes positive (+), and when the fourth data signal from the fourth data signal output terminal DS4 is applied through the eighth data line DL8, the 32nd The polarity of the sub-pixel SP32 becomes negative (-).

Next, when a gate signal is applied through the eighth gate line GL8, the 25th, 27th, 29th, and 31th thin film transistors T25, T27, T29, and T31 are turned on, and the first data signal output terminal ( When the first data signal from DS1) is applied through the fifth data line DL5, the polarity of the 29th subpixel SP29 becomes positive (+), and the second data signal from the second data signal output terminal DS2 When is applied through the second data line DL2, the polarity of the 25th subpixel SP25 becomes negative (-), and the third data signal from the third data signal output terminal DS3 is transferred to the third data line DL3. ), the 27th subpixel SP27 has a positive polarity (+), and when the fourth data signal is applied from the fourth data signal output terminal DS4 through the eighth data line DL8, the 31st The polarity of the sub-pixel SP31 becomes negative (-).

Therefore, the DRD method reduces the number of ICs in the data driver to reduce the production cost of the liquid crystal display device, and 4 dot inversion can be realized through column inversion driving, thereby reducing the power consumption of the liquid crystal display device. It is possible to improve the image quality defect by preventing the deterioration of the liquid crystal.

7 is a plan view of an array substrate corresponding to B of FIG. 6.

First, as shown in FIG. 7, the first to eighth data lines DL1 to DL8 and the first to eighth data lines DL1 to DL8 are connected on the substrate in the non-display area between the data driver IC and the subpixel. Exposing portions of the first to eighth data link wires (DLL1 to DLL8), the first to eighth data wires (DL1 to DL8), and the first to eighth data link wires (DLL1 to DLL8) respectively connected The first to sixteenth contact holes CH1 to CH16, the first to eighth data wires DL1 to DL8, and the first to eighth data link wires DLL1 to DLL8 are connected to the first to sixteenth contact holes. It includes first to eight bridge patterns BP1 to BP8 electrically connected to each other through (CH1 to CH16).

The first data line DL1 and the first and fifth data link lines DLL1 and DLL5 are connected by a first bridge pattern BP1 electrically connected through first and second contact holes CH1 and CH2, respectively. The fifth data line DL5 and the fifth data link line DLL5 are electrically connected by a second bridge pattern BP2 electrically connected through the third and fourth contact holes CH3 and CH4, The first data link line DLL1 is connected to a first data signal output terminal (not shown) of the data driver IC.

The second data line DL2 and the second and sixth data link lines DLL2 and DLL6 are connected by a third bridge pattern BP3 electrically connected through fifth and sixth contact holes CH5 and CH6, respectively. The sixth data line DL6 and the sixth data link line DLL6 are electrically connected by a fourth bridge pattern BP4 electrically connected through the seventh and eighth contact holes CH7 and CH8, The second data link line DLL2 is connected to a second data signal output terminal (not shown) of the data driver IC.

The third data line DL3 and the third and seventh data link lines DLL3 and DLL7 are connected by a fifth bridge pattern BP5 electrically connected through the ninth and tenth contact holes CH9 and CH10, respectively. The seventh data line DL7 and the seventh data link line DLL7 are electrically connected by a sixth bridge pattern BP6 electrically connected through the 11th and 12th contact holes CH11 and CH12, The third data link line DLL3 is connected to a third data signal output terminal (not shown) of the data driver IC.

The fourth data line DL4 and the fourth and eighth data link lines DLL4 and DLL8 are connected by a seventh bridge pattern BP7 electrically connected through the 13th and 14th contact holes CH13 and CH14, respectively. The eighth data line DL8 and the eighth data link line DLL8 are electrically connected by the eighth bridge pattern BP8 electrically connected through the fifteenth and sixteenth contact holes CH15 and CH16, The fourth data link line DLL4 is connected to a fourth data signal output terminal (not shown) of the data driver IC.

In addition, the first to eighth data wires DL1 to DL8 are formed of the same layer and the same material as the source and drain electrodes of the thin film transistor (not shown), and the first to eighth data link wires DLL1 to DLL8 Silver is formed of the same layer and the same material as the gate electrode of the thin film transistor (not shown), and the first to eighth bridge patterns BP1 to BP8 are made of the same layer and the same material as the pixel electrode of the thin film transistor (not shown). Can be formed.

In particular, the third data line DL3 and the second data link line DLL2 are formed to cross each other and are formed of different layers.

In addition, first to third regions a1 to a3 overlap each other by crossing the second to fourth data lines DL2 to DL4 and the fifth data link line DLL5, and the third and fourth regions. The fourth and fifth regions a4 and a5 cross and overlap the data line DL4 and the sixth data link line DLL6, respectively, and the fourth data line DL4 and the seventh data link line ( DLL7) and the sixth region (a6) overlapping.

Meanwhile, the data signal of one data signal output terminal is divided into two data wires and input, and the load due to the parasitic capacitance is caused by the areas of the first to sixth regions (a1 to a6) where the data wire and the data link wire overlap. Will increase.

Accordingly, by forming the same load from one data signal output terminal until the data signals are applied to two data lines, it is possible to prevent deterioration of image quality due to data signal delay.

To this end, the first to eighth data lines DL1 to DL8 intersect and extend from the first to eighth data lines DL1 to DL8 and extend from the common wiring Vcom and the common wiring Vcom positioned above the first gate wiring GL1, respectively. The third and sixth to eighth data lines (DL1 to DL3 and DL6 to DL8) and the first to sixth compensation patterns CP1 overlapped and positioned respectively.

In this case, the first compensation pattern CP1 is formed to have an area equal to the sum of the areas of the first to third areas a1 to a3.

Therefore, by forming the same load until the first data signal is applied from the first data signal output terminal (not shown) to the first and fifth data lines DL1 and DL5, it is possible to prevent image quality deterioration due to data signal delay. I can.

In addition, the sixth compensation pattern is formed to have an area equal to the sum of the areas of the third, fifth, and sixth areas.

Therefore, by forming the same load until the first data signal is applied from the fourth data signal output terminal (not shown) to the fourth and eighth data lines DL4 and DL8, it is possible to prevent image quality deterioration due to data signal delay. I can.

In addition, the sum of the areas of the second compensation pattern CP2 and the first area a1 is equal to the sum of the areas of the fourth and fifth areas a4 and a5 and the fourth compensation pattern CP4. And the sum of the areas of the fifth compensation pattern CP5 and the sixth area a6 is the sum of the areas of the second and fourth areas a2 and a4 and the third compensation pattern CP3 Are formed to be the same.

Therefore, the second data signal is formed to have the same load until the second data signal is applied to the second and sixth data lines DL2 and DL6 from the second data signal output terminal (not shown), and from the third data signal output terminal (not shown). The third and seventh data lines DL3 and DL7 are formed to have the same load until the third data signal is applied, so that image quality deterioration due to a delay in the data signal can be prevented.

<Fifth Example>

8 is a diagram in which two data lines are connected to one data signal output terminal for every six subpixels according to the fifth embodiment of the present invention.

As shown in FIG. 8, the first to 22nd subpixels are arranged in 2 rows and 11 columns, and the subpixels in each row are horizontally formed, and two subpixels are formed between the subpixels in each row. First to fourth gate wires, first to twelfth data wires intersecting with the first and second gate wires and formed between the subpixels in each column from the left of the subpixels in the first column, and each formed in the plurality of subpixels It includes first to 22 thin film transistors.

A first data signal is applied from a first data signal output terminal to the first and seventh data wires, a second data signal is applied from a second data signal output terminal to the second and eighth data wires, and the third and A third data signal is applied from a third data signal output terminal to a ninth data line, a fourth data signal is applied from a fourth data signal output terminal to the fourth and tenth data lines, and the fifth and eleventh data lines A fifth data signal is applied to the fifth data signal output terminal, and a sixth data signal is applied from the sixth data signal output terminal to the sixth and twelfth data lines.

The liquid crystal display of FIG. 8 is only an example, and two odd data wires among the plurality of data wires are one for each n (n is a multiple of 6) subpixels based on the first data wire DL1. It is connected to the odd data signal output terminal, and two even data wires are connected to one even data signal output terminal for each n (n is a multiple of 6) subpixels based on the second data line DL2, and each data signal If the data signals are not applied simultaneously from the input terminal to each subpixel through two data lines, but are sequentially applied each time a gate signal is applied, all of the effects of the present invention are exhibited.

In the liquid crystal display of FIG. 8, compared to the embodiment of FIG. 4, the arrangement of the thin film transistor is the same, but only the connection method of two data wires and one data signal output terminal is different, and the liquid crystal panel is driven in a horizontal 2-dot inversion method. It is the same in that it becomes. That is, each thin film transistor formed in each subpixel is freely disposed to the left or right of the subpixel, so that a data signal can be applied from any one of the left and right data lines of each subpixel.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains can be implemented in other specific forms without changing the technical spirit or essential features. You can understand. Therefore, the embodiments described above are provided to completely inform the scope of the invention to those of ordinary skill in the art to which the present invention belongs, and should be understood to be illustrative and non-limiting in all respects. The invention is only defined by the scope of the claims.

GL1 ~ GL4: Gate wiring DL1 ~ DL12: Data wiring
SP1 ~ SP22: Sub-pixel T1 ~ T22: Thin film transistor
DS1 ~ DS6: Data signal output terminal DLL1 ~ DLL4: Data link wiring
CH1 ~ CH8: Contact hole BP1 ~ BP4: Bridge pattern

Claims (18)

delete delete delete delete delete delete delete delete First to 32nd subpixels arranged in 4 rows and 8 columns;
First to eighth gate wirings which are horizontally arranged above and below each subpixel in each row, and two are arranged between the subpixels in each row;
First to eighth data lines intersecting the first to eighth gate lines and disposed between the subpixels in each column from the left of the subpixels in the first column; And
Including first to 32th thin film transistors respectively disposed on a plurality of subpixels,
A first data signal is applied from a first data signal output terminal to the first and fifth data wires, a second data signal is applied from a second data signal output terminal to the second and sixth data wires, and the third and A third data signal is applied from the third data signal output terminal to the seventh data line, and a fourth data signal is applied from the fourth data signal output terminal to the fourth and eighth data lines,
The second, fourth, sixth, and eighth thin film transistors are connected to the first gate wire, the first, third, fifth and seventh thin film transistors are connected to the second gate wire, The 10th, 12th, 14th, and 16th thin film transistors are connected to the third gate line, the ninth, 11th, 13th, and 15th thin film transistors are connected to the fourth gate line, and the 18th , 20th, 22nd, and 24th thin film transistors are connected to the fifth gate line, the 17th, 19th, 21st, and 23rd thin film transistors are connected to the sixth gate line, and the 26th, 28th, 30th, and 32th thin film transistors are connected to the seventh gate line, and the 25th, 27th, 29th and 31st thin film transistors are connected to the eighth gate line,
The first and ninth thin film transistors are connected to the first data line, and the 17th, 18th, 25th and 26th thin film transistors are connected to the second data line, and the second, tenth, and The 19th and 27th thin film transistors are connected to the third data line, the third, fourth, eleventh, and 12th thin film transistors are connected to the fourth data line, and the 20th, 21st, 28th and The 29th thin film transistor is connected to the fifth data line, the fifth, sixth, 13th, and 14th thin film transistors are connected to the sixth data line, and the 7, 15th, 22nd and 30th thin film transistors are connected to the sixth data line. A DRD type liquid crystal display device, wherein a thin film transistor is connected to the seventh data line, and the 23rd, 24th, 31st, and 32nd thin film transistors are connected to the eighth data line.
delete The method of claim 9,
The DRD type liquid crystal display device, wherein polarities of the first and third data signals and polarities of the second and fourth data signals are opposite to each other.
delete First to 32nd subpixels arranged in 4 rows and 8 columns;
First to eighth gate wirings which are horizontally arranged above and below each subpixel in each row, and two are arranged between the subpixels in each row;
First to eighth data lines intersecting the first to eighth gate lines and disposed between the subpixels in each column from the left of the subpixels in the first column; And
Including first to 32th thin film transistors respectively disposed on a plurality of subpixels,
A first data signal is applied from a first data signal output terminal to the first and fifth data wires, a second data signal is applied from a second data signal output terminal to the second and sixth data wires, and the third and A third data signal is applied from the third data signal output terminal to the seventh data line, and a fourth data signal is applied from the fourth data signal output terminal to the fourth and eighth data lines.
Further comprising first to eighth data link wires respectively connected to the first to eighth data wires,
The second to fourth data wires and the fifth to seventh data link wires are located on different layers,
A common line intersecting the first to eighth data lines and positioned on the first gate line; And
The DRD type liquid crystal display device further comprising first to sixth compensation patterns extending from the common wires and overlapping with the first to third and sixth to eighth data wires, respectively.
The method of claim 13,
The DRD type liquid crystal display, characterized in that the sum of the areas of the first to third areas where the second to fourth data lines and the fifth data link lines cross and overlap each other is the same as the area of the first compensation pattern Device.
The method of claim 13,
DRD method, characterized in that the sum of the areas of the third, fifth, and sixth areas where the fourth data line and the fifth to seventh data link lines cross each other and overlap each other is the same as the area of the sixth compensation pattern Liquid crystal display.
The method of claim 14 or 15,
The sum of the areas of the fourth and fifth areas and the fourth compensation pattern overlapped by crossing the third and fourth data lines and the sixth data link lines, respectively, is equal to the second data line and the fifth data link line It is equal to the sum of the areas of the first area and the second compensation pattern overlapping and overlapping,
The sum of the areas of the second area, the fourth area, and the third compensation pattern overlapping each other by crossing the third data line and the fifth and sixth data link lines is the fourth data line and the seventh data link line The liquid crystal display of the DRD method, characterized in that the same as the sum of the areas of the sixth area and the fifth compensation pattern overlapping by being crossed.
First to 22nd subpixels arranged in 2 rows and 11 columns;
First to fourth gate wirings disposed in a horizontal direction for each of the subpixels in each row, and having two between the subpixels in each row;
First to twelfth data lines intersecting the first to fourth gate lines and disposed between the subpixels in each column from the left of the subpixels in the first column; And
Including first to 22 thin film transistors respectively disposed on a plurality of subpixels,
A first data signal is applied from a first data signal output terminal to the first and seventh data wires, a second data signal is applied from a second data signal output terminal to the second and eighth data wires, and the third and A third data signal is applied from a third data signal output terminal to a ninth data line, a fourth data signal is applied from a fourth data signal output terminal to the fourth and tenth data lines, and the fifth and eleventh data lines A fifth data signal is applied from a fifth data signal output terminal to the sixth data signal output terminal, and a sixth data signal is applied from the sixth data signal output terminal to the sixth and twelfth data lines,
The second, fourth, sixth, eighth and tenth thin film transistors are connected to the first gate wiring, and the first, third, fifth, seventh, ninth and eleventh thin film transistors are 2 connected to the gate line, the 12th, 14th, 16th, 18th, 20th, and 22nd thin film transistors are connected to the third gate line, and the 13th, 15th, 17th, 19th and The 21st thin film transistor is connected to the fourth gate wiring,
The first thin film transistor is connected to the first data line, the 12th and 13th thin film transistors are connected to the second data line, the second and 14th thin film transistors are connected to the third data line, , The third and fourth thin film transistors are connected to the fourth data line, the fifth and fifteenth thin film transistors are connected to the fifth data line, and the 16th and 17th thin film transistors are connected to the sixth data line Is connected to a wire, the sixth and eighteenth thin film transistors are connected to the seventh data wire, the seventh and eighth thin film transistors are connected to the eighth data line, and the ninth and nineteenth thin film transistors are The ninth data line is connected, the 20th and 21st thin film transistors are connected to the 10th data line, the 10th and 22nd thin film transistors are connected to the 11th data line, and the 11th thin film transistor Is connected to the twelfth data line.
delete

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