KR102155253B1 - Methods for processing silicon on insulator wafers - Google Patents

Abstract

A method of etching and/or depositing an epitaxial layer over an SOI structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer is provided. The silicon layer comprises a cleaved surface defining the outer surface of the structure. The cleaved surface of the wafer is then etched while controlling the temperature of the reactor so that the etching reaction is kineticly limited. The epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor so that the deposition rate on the cleaved surface is kineticly limited.

Description

How to process SOI wafers{METHODS FOR PROCESSING SILICON ON INSULATOR WAFERS}

Semiconductor wafers are generally prepared from single crystal ingots (eg, silicon ingots) and then cut into individual wafers. In this specification, reference is made to a semiconductor wafer made of silicon, but other materials such as germanium or gallium arsenide may also be used.

As a type of wafer, there is a silicon-on-insulator (SOI) wafer. The SOI wafer includes a thin layer of silicon on top of an insulating layer (ie, an oxide layer), and the insulating layer is in turn disposed over the silicon substrate. SOI wafer is a type of SOI structure.

An exemplary process of manufacturing an SOI wafer involves depositing an oxide layer over the polished front surface of a donor wafer. Particles (eg, a hydrogen atom or a combination of hydrogen and helium atoms) are implanted at a certain depth below the front of the donor wafer. The implanted particles form a cleave plane within the donor wafer at the specific depth into which they are implanted. The surface of the donor wafer is cleaned to remove material deposited on the wafer during the implantation process.

Thereafter, the front surface of the donor wafer is bonded to the handle wafer to form a bonded wafer. The donor wafer and the handle wafer are bonded to each other by exposing the wafer surface to a plasma comprising, for example, oxygen or nitrogen. Exposure to plasma alters the structure of a surface in a process commonly referred to as surface activation. After that, the wafers are pressed together, and a bond is formed between them. This bond is relatively weak and must be strengthened before another process can take place.

In some processes, the bond between the donor wafer and the handle wafer (ie, the bond wafer) is strengthened by heating or annealing the bonded wafer pair at a temperature between about 300°C and 500°C. The elevated temperature causes the formation of covalent bonds between the donor wafer and the adjacent surface of the handle wafer, thereby strengthening the bond between the donor wafer and the handle wafer. Simultaneously with heating or annealing of the bonded wafer, particles first injected into the donor wafer weaken the cleavage surface. Thereafter, a portion of the donor wafer is separated from the bonded wafer along the cleavage surface (ie, cleaves) to form an SOI wafer.

First, a bonded wafer is placed in a fixture in which a mechanical force is applied perpendicularly to opposite sides of the bonded wafer in order to pull a portion of the donor wafer away from the bonded wafer. According to some methods, a suction cup is used to apply a mechanical force. Separation of a portion of the donor wafer is initiated by applying a mechanical wedge to the edge of the bonded wafer to the cleavage surface to initiate propagation of the crack along the cleavage surface. The mechanical force applied by the suction cup then pulls a portion of the donor wafer from the bonded wafer, forming an SOI wafer. According to another method, the bonded pair may instead be exposed to an elevated temperature for a period of time to separate a portion of the donor wafer from the bonded wafer. Exposure to elevated temperatures causes the initiation and propagation of cracks along the cleavage surface, separating a portion of the donor wafer.

The resulting SOI wafer comprises a handle wafer and a thin layer of silicon (a portion of the donor wafer remaining after cleavage) disposed on top of the oxide layer. The cleaved surface of the thin layer of silicon has a rough surface that is not suitable for end use applications. Surface damage can be a result of particle implantation and the resulting dislocation in the silicon crystal structure. Therefore, an additional process is required to make the cleaved surface smooth.

In order to make the surface layer of silicon (i.e., the cleaved surface) smooth and thin, the previous process is hot gas etching (i.e. epi-smoothing) or deposition of a thin layer of silicon on the surface layer (i.e. epitaxial deposition (epi-smoothing)). -deposition)) was used. In these previous methods, etching or deposition is carried out at a temperature where the reaction is transport limited (i.e., the rate of reaction is limited by the availability of new reactants). This transport limiting reaction results in a thickness change (eg, a sharp slope in the thickness profile) at the edge of the silicon surface layer. Another process is required to eliminate the thickness change caused by the previous process. Previous attempts to reduce the thickness variation at the edges of the surface layer have involved peeling the exposed oxide layer from the handle wafer. However, peeling the oxide layer from the handle wafer is time consuming and expensive, and often results in bowing or warping of the wafer due to residual stress caused by the unexposed portion of the oxide layer.

Therefore, it will be said that there is an unsatisfied need for a wafer surface treatment method suitable for use in a bonded wafer processing operation and to solve the shortcomings of current processing operations.

One aspect is a method of processing a silicon-on-insulator (SOI) structure including a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer includes a cleaved surface defining the outer surface of the structure. The method includes inserting the structure into the reactor. Thereafter, the cleaved surface of the wafer is etched while controlling the temperature of the reactor so that the etching reaction is kineticly limited. Thereafter, an epitaxial layer is deposited on the wafer while controlling the temperature of the reactor so that the deposition rate on the cleaved surface is kineticly limited.

Another aspect is a method of processing an SOI structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer includes a cleaved surface defining the outer surface of the structure. The method includes inserting the structure into the reactor. Thereafter, the temperature of the reactor is set so that the etch rate of the cleaved surface is kineticly limited. Thereafter, the flow of the gas etchant into the reactor is initiated, and the cleaved surface is etched.

Another aspect is a method of processing an SOI structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer includes a cleaved surface defining the outer surface of the structure. The method involves inserting the structure into the reactor. Thereafter, the temperature of the reactor is set so that the rate of silicon deposition on the cleaved surface is kineticly limited. Thereafter, the flow of the deposited gas into the reactor is initiated, and silicon is deposited on the cleaved surface of the structure.

There are various improvements to the features described in connection with the above aspect. Other features may be included in the above aspect. These improvements and additional features may exist individually or in any combination. For example, the various features described below with respect to any of the illustrated embodiments may be included in any of the above aspects alone or in any combination.

The drawings are not to scale, and certain features may be exaggerated for convenience of illustration.
1A is a plan view of a donor silicon wafer.
1B is a cross-sectional view of the donor silicon wafer of FIG. 1A.
Fig. 2 is a cross-sectional view of a donor silicon wafer after ion implantation.
3 is a cross-sectional view of a bonded wafer including a donor silicon wafer bonded to a handle silicon wafer.
4 is a cross-sectional view of the bonded wafer of FIG. 3 after a portion of the donor wafer is removed.
5 is a cross-sectional view of the bonded wafer of FIG. 4 after treatment of the cleaved surface of the bonded wafer.
6 is a partially enlarged view of FIG. 5 in which features are exaggeratedly expressed for convenience of illustration.
7 is a flow diagram illustrating a method of performing an epitaxial smoothing process on an SOI wafer.
8 is a flow chart showing a method of performing an epitaxial deposition process on an SOI wafer.
9 is a diagram showing a relationship between an etch rate and temperature of a cleaved surface of a bonded wafer.
10A-10C show the relationship between the etch rates of the cleaved surface of the bonded wafer at varying distances from the center of the surface for different temperatures.
11 is a diagram showing the relationship between the deposition rate and temperature of the cleaved surface of a bonded wafer.

First, referring to FIGS. 1A and 1B, a donor wafer 110 and an oxide layer 120 are shown. 1A is a plan view of the donor wafer 110, while FIG. 1B is a cross-sectional view of the donor wafer. The oxide layer 120 is bonded to the front surface 112 of the donor wafer 110. The oxide layer 120 may be grown on the front side 112 by exposing the donor wafer 110 to an atmosphere suitable for growth of the oxide layer. Alternatively, the oxide layer 120 may be deposited over the front surface 112 through any known chemical deposition process and functions as an insulator (ie, a dielectric).

2 is a cross-sectional view of a donor wafer 110 into which particles (eg, a hydrogen atom or a combination of a hydrogen atom and a helium atom) are implanted. The donor wafer 110 is implanted with particles to a specific depth below the front surface 112 of the donor wafer 110. In some embodiments, the particles are hydrogen or helium ions implanted through an ion implantation process. Thereafter, a cleavage surface 114 is formed under the front surface 112 of the donor wafer 120 at a distance from the front surface equal to a specific depth into which the particles are implanted. The cleavage surface 114 defines a plane through the donor wafer 110 on which the donor wafer is substantially weakened by ion implantation upon subsequent heating of the donor wafer.

3 is a cross-sectional view of a donor wafer 110 and a handle wafer 130. The donor wafer 110 and the handle wafer 130 are bonded together according to any suitable method, such as hydrophilic bonding. The donor wafer 110 and the handle wafer 130 are bonded to each other by exposing the wafer surface to a plasma including, for example, oxygen or nitrogen. The surfaces of the wafers 110 and 130 are altered by exposure to plasma in a process commonly referred to as surface activation. Thereafter, the wafers 110 and 130 are pressed together, and a bond is formed therebetween. This bond is weak and must be strengthened before another process can take place. In some embodiments, the handle wafer 130 is covered by a thin oxide layer 156, as best shown in FIG. 6. The oxide layer 156 may be grown on the handle wafer 130 by exposing the handle wafer to an atmosphere suitable for growth of the oxide layer.

The donor wafer 110 and the handle wafer 130 together form a bonded wafer 140. In some processes, the hydrophilic bond between the donor wafer and the handle wafer (ie, bonded wafer) is strengthened by heating or annealing the bonded wafer pair at a temperature between about 300°C and 500°C. The elevated temperature causes the formation of covalent bonds between the donor wafer and adjacent surfaces of the handle wafer, thereby strengthening the bond between the donor wafer and the handle wafer. Simultaneously with heating or annealing of the bonded wafer, particles previously implanted in the donor wafer begin to move and weaken the cleavage surface.

4 is a cross-sectional view of the bonded wafer 140 shown in FIG. 3. A portion of the bonded wafer 140 is removed during the cleavage process, resulting in the creation of an SOI wafer, commonly referred to as 150. According to another method, the bonded pair may instead be exposed to an elevated temperature for a period of time to separate a portion of the donor wafer from the bonded wafer. Exposure to elevated temperatures serves to initiate and propagate cracks along the cleavage surface, separating a portion of the donor wafer.

Since the cleavage surface 114 has been substantially weakened by ion implantation, it defines a boundary line along which the wafer is easily separated when a force is applied. According to some embodiments, the bonded wafer 140 is first placed in a fixture in which a mechanical force is applied perpendicular to opposite sides of the bonded wafer to pull a portion of the donor wafer away from the bonded wafer. In one embodiment, a suction cup is used to apply a mechanical force. Separation of a portion of the donor wafer 110 is initiated by applying a mechanical wedge to the edge of the bonded wafer to the cleavage surface to initiate propagation of the crack along the cleavage surface. Due to the weakened structure of the cleavage surface, cracks propagate along the cleavage surface 114 until the bonded wafer 140 is separated into two pieces along the cleavage surface. Then, the mechanical force applied by the suction cup pulls the bonded wafer 140 into two pieces. One piece consists of only a portion of the donor wafer 110. The other piece is composed of a handle wafer 130 and a portion of the donor wafer 110 bonded thereto to form an SOI wafer 150.

The cleaved surface 152 of the SOI wafer 150 defines a surface that arises after separation of the bonded wafer 140 along the cleaved surface 114. The cleaved surface 152 has a damaged surface as a result of separation along the cleaved surface 114. In the absence of another treatment, the damage makes the surface unsuitable for the end-use application. Thus, the cleaved surface 152 undergoes additional processing steps to repair damage and smooth the cleaved surface 152.

5 is a cross-sectional view of the SOI wafer 150 after treatment of the cleaved surface 152, resulting in a smoothed cleaved surface 152S. As shown in Fig. 5, the smoothed cleaved surface 152S has a smooth surface with a uniform profile. The process of the SOI wafer 150 will be described in detail below with reference to FIGS. 7 to 9.

6 shows an enlarged portion of FIG. 5 with a greatly exaggerated portion. The relative thicknesses of the oxide layer 156, the oxide layer 120, and the smoothed cleaved surface 152S on the handle wafer 130 have been greatly exaggerated for clarity. In addition, the width of the terrace area 160 is also exaggerated. As shown in FIG. 6, the smoothed cleaved surface 152S and oxide layer 120 do not extend throughout the oxide layer 156 of the handle wafer 130. Instead, the smoothed cleaved surface 152S and adjacent oxide layer 120 terminate radially inwardly from the peripheral edge 158 of the handle wafer 130, such that the terrace region 160, and the oxide layer 156 Leave it exposed. The oxide layer 156 surrounds the handle wafer 130 and extends radially outward from its peripheral edge 158. The terrace region 160 thus includes a portion of the oxide layer 156 adjacent and surrounding the peripheral edge 158 of the handle wafer 130. In some embodiments, the width of the terrace region 160 may be twice the thickness of the handle wafer 130.

As described above, prior systems use epitaxial smoothing and epitaxial deposition processes at elevated temperatures to form the smooth cleaved surface 152S shown in FIG. 5. These processes are carried out in conventional systems at temperatures where the chemical reaction rate of each of these processes is transfer limiting. In other words, the rate of a chemical reaction is limited by the availability of new reactants, as opposed to a kinetic limiting reaction in which the rate of reaction is limited only by the kinetics of the chemical reaction.

It is believed that the transfer limitation of the process results in a sharp gradient in the thickness of the smoothed surface 152S adjacent to the peripheral edge 158 of the handle wafer 130. In some processes, the steep gradient of the thickness of the smoothed surface 152S extends 5 mm to 10 mm inward from the edge of the handle wafer 130.

When the reactants of the epitaxial smoothing or epitaxial deposition process come into contact with the edge of the smoothed surface 152S adjacent to the oxide layer 156 near the peripheral edge 158 of the handle wafer 130, The absence increases the reaction rate. In addition, the reactants of the epitaxial smoothing or epitaxial deposition process do not react with the oxide layer 156 of the terrace region. Thus, the rate of reaction at the edge increases, because there is a greater amount of available reactant compared to the available reactant for other areas of the smoothed surface 152S disposed inside the peripheral edge 158. to be. In addition, the increased reaction rate on the smoothed surface 152S near the terrace area is also due to the boundary layer theory and/or the lateral diffusion of reactants from the terrace area.

Thus, this increased reaction rate at or near the peripheral edge 158 in the epitaxial deposition process results in an increase in silicon deposition and correspondingly an increase in the thickness of the smoothed surface 152S adjacent the peripheral edge. In the epitaxial smoothing process, this increased reaction rate results in an increase in the amount of silicon etched from the surface and correspondingly a decrease in the thickness of the smoothed surface 152S adjacent to the peripheral edge 158.

7 shows a method 700 of performing an epitaxial smoothing (ie, etching) process on the cleaved surface 152 of the SOI wafer 150. Method 700 begins with the insertion of an SOI wafer 150 into the reactor. SOI wafer 150 can be inserted into the reactor by any suitable device, such as a robotic manipulator. The reactor may be any suitable epitaxial deposition and/or smoothing reactor suitable for performing an epitaxial smoothing process on an SOI wafer. The reactor typically has one or more lamps or other devices for heating the interior of the reactor.

Thereafter, in block 720, the temperature in the reactor is set such that the etch reaction is kineticly limited as opposed to transport limiting. As described above, by setting and controlling the temperature so that the epitaxial smoothing reaction is kineticly limited, the thickness on the cleaved surface 152 of the SOI wafer 150 becomes more uniform. When the reaction rate is kineticly limited, the difference in speed from the center to the outer edge of the SOI wafer 150 decreases. Instead of increasing at the edge of the SOI wafer 150, the reaction rate is relatively uniform across the surface of the SOI wafer 150. According to some embodiments, the temperature at which the etch reaction is kineticly limited is between 900°C and 950°C. In addition, the reduced temperature corresponding to the kinetic limitation of the deposition rate also allows a cooler offset temperature to be used. In some embodiments, there are three offset zones with independent temperature controllers within the reactor. The three offset areas are anterior, lateral, and posterior. To achieve temperature uniformity, the offset zone temperature set point is adjusted relative to the center zone temperature set point. Thus, a lower set point for the center area results in a lower set point used in the offset areas.

At block 730, flow of gaseous etchant into the reactor is initiated. According to some embodiments, the flow of gaseous etchant is initiated immediately after the SOI wafer 150 is inserted into the reactor. In these embodiments, the temperature of the reactor is already set at an appropriate temperature so that the etch reaction is kineticly limited. The gaseous etchant may be HCl or a mixture of chlorine and H ₂ , according to some embodiments.

After that, the flow of gaseous etchant into the reactor is continued for a certain period of time. The length of time can be determined based on the amount of silicon to be removed from the cleaved surface 152 of the SOI wafer and the rate at which the silicon is being etched. For example, if the etch rate is 3.0 Å/sec and the amount of silicon to be removed is 900 Å, the SOI wafer is removed from the reactor 300 seconds after the flow of the gas etchant is started.

After that, after the desired amount of silicon is removed by the flow of the gas etchant, the flow of the gas etchant is stopped. Then, the SOI wafer 150 is removed from the reactor. In some embodiments, SOI wafer 150 may be removed from the reactor by a robotic transfer system. In other embodiments, as will be described later with reference to FIG. 8, the SOI wafer 150 may be maintained in the reactor and may undergo an epitaxial deposition process in the same reactor.

8 shows a method 800 of performing an epitaxial deposition process on a cleaved surface 152 of an SOI wafer 150. The method 800 begins with the insertion of an SOI wafer 150 into a reactor. SOI wafer 150 may be inserted into the reactor by any suitable device, such as by a robot. The reactor may be of the same type as described above with respect to FIG. 7. In some embodiments where the SOI wafer 150 has previously undergone an epitaxial smoothing process, the wafer may already be placed in the reactor.

Thereafter, at block 820 the temperature in the reactor is set such that the deposition rate is kineticly limited as opposed to the transfer limiting. As described above, by setting and controlling the temperature so that the deposition rate is kineticly limited, the degree of change in thickness is more uniform across the cleaved surface 152 of the SOI wafer 150. When the deposition rate is kineticly limited, the difference in the thickness of the deposited layer of silicon from the center to the outer edge of the SOI wafer 150 decreases. Instead of increasing at the edge of the SOI wafer 150, the thickness of the deposited layer is relatively uniform across the surface of the wafer. According to some embodiments using trichlorosilane, the temperature at which the deposition rate is kineticly limited is between about 950°C and about 1050°C, or in yet another embodiment about 1000°C. For different silicon source gas types, the kinetically limited temperature range may be different. For other gases, for example dichlorosilane or monosilane, the kinetically limited growth temperature range is somewhat lower than that for trichlorosilane. In addition, the reduced temperature corresponding to the kinetic limitation of the deposition rate also allows a cooler offset temperature within the reactor to be used. A cooler offset temperature can be used to effectively control the thickness profile of the cleaved surface 152 near the terrace 160.

At block 830, flow of the deposited gas to the reactor is initiated. The deposition gas may be any of monosilane, dichlorosilane, trichlorosilane, tetrachlorosilane, or any other suitable gas. In some embodiments, the deposited gas may include hydrogen. According to some embodiments, the flow of the deposited gas is started immediately after the SOI wafer 150 is inserted into the reactor. In these embodiments, the temperature of the reactor is already set at a suitable temperature such that the deposition rate (ie, growth rate) is kineticly limited. In addition to the reduction and/or elimination of the thickness gradient near the terrace area 160, the increased temperature associated with the kinetic limitation of the deposition rate also enables the use of a larger flow rate of deposited gas. In addition, the larger flow rate of the deposited gas also results in a reduction in the recycle flow of the deposited gas due to the reduced Rayleigh number of the deposited gas. The reduced recycle flow also reduces the amount of silicon deposited on the reactor wall by the deposited gas.

After that, the flow of the deposited gas to the reactor continues for a certain period of time. The length of this time can be determined based on the amount of silicon to be deposited onto the cleaved surface 152 of the SOI wafer and the rate at which the silicon is being deposited. For example, if the deposition rate is 220 Å/sec and the amount of silicon to be deposited is 13200 Å (1.32 micrometers), the SOI wafer will be removed from the reactor 60 seconds after the flow of the deposited gas starts (or deposition). Gas flow stops).

Thereafter, the flow of the deposition gas is stopped after a desired amount of silicon is deposited on the cleaved surface 152 of the SOI wafer. Then, the SOI wafer 150 is removed from the reactor. In some embodiments, SOI wafer 150 may be removed from the reactor by a robotic transfer system.

9 shows the relationship between the etch rate and temperature of the surface of the SOI wafer. As clearly shown in FIG. 9, the etch rate rapidly decreases as the temperature decreases below 950°C. At about 950[deg.] C. the etch reaction ceases to be transport limiting and is instead thought to be kinetic limiting.

10A-10C show the relationship between the etch rates of the surface of an SOI wafer (200 mm SOI wafer in this case) at a variable distance from the center of the wafer. FIG. 10A shows the relationship for the epitaxial smoothing process performed at 1100°C, while FIG. 10B shows the relationship when it is performed at 950°C, and FIG. 10C shows the relationship at 900°C.

As clearly shown in Figs. 10A and 10B (indicating the relationship in the temperature used previously), the etch rate during the epitaxial smoothing process increases toward the edge of the wafer. This increase in the etch rate results in a corresponding decrease in the thickness of the wafer at or near the edge of the wafer, thus forming a steep degree of thickness gradient at or near the edge of the wafer. However, FIG. 10C shows the relationship between the etch rate and the distance from the center of the wafer according to the method described above in FIG. 7 in which the reaction is not transport-limited and kinetic-limited. As can be seen from FIG. 10C, the non-uniformity of the etch rate near the edge of the wafer is reduced by almost four times as compared with FIGS. 10A and 10B. In an exemplary embodiment the reaction is not transport-limited, and the kinetic-limited temperature is approximately between 900°C and 950°C.

The figure shown in Fig. 11 shows the relationship between the deposition rate and temperature on the surface of the SOI wafer. As can be clearly seen in Fig. 11, the deposition rate rapidly decreases as the temperature decreases below 950°C. At about 950° C. the deposition reaction ceases to be transport limiting and is instead thought to be kineticly limited.

The execution or order of execution of the operations in the embodiments of the present invention shown and described herein is not essential unless otherwise specified. That is, operations may be performed in any order, unless otherwise specified, and embodiments of the present invention may include additional or fewer operations than those disclosed herein. For example, it is contemplated to be within the scope of aspects of the present invention to perform or perform a particular operation before, simultaneously, or after another operation.

In introducing elements of the present invention or its embodiment(s), the articles (a, an, the, and said) are intended to mean that one or more elements are present. The term "comprising, including, having" is in an inclusive sense and means that additional elements other than the listed elements may exist.

Since various changes can be made in the above configuration without departing from the scope of the present invention, everything included in the above description and shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense.

Claims (10)

A method for processing a silicon-on-insulator (SOI) structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer, wherein the silicon layer is a cleaved surface defining an outer surface of the structure ( cleaved surface) -,
Inserting the structure into the reactor, the reactor comprising at least one heater and further comprising a central temperature zone and at least one offset temperature zone, the central temperature zone and at least one offset temperature zone each having a corresponding temperature controller. Equipped-;
Setting the temperature of the reactor so that the etch rate of the cleaved surface is kineticly limited-A temperature controller for each of the offset temperature regions is proportional to the temperature of the central temperature region to maintain a uniform temperature in the reactor. It is set to control the temperature of each of the offset temperature regions, and the temperature of the reactor is set to 925°C;
Initiating a flow of gas etchant into the reactor; And
Etching the cleaved surface
SOI structure processing method comprising a. The method of claim 1,
The etching step includes removing at least a portion of the silicon layer of the structure. The method of claim 1,
The gas etchant is a mixture of hydrogen and hydrogen chloride SOI structure treatment method. delete delete delete The method of claim 1,
Once the first amount of the silicon layer on the cleaved surface is removed by the gas etchant, stopping the flow of the gas etchant. The method of claim 7, further comprising performing an epitaxial deposition process on the structure after the flow of the gas etchant is stopped. A method of processing an SOI structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer, the silicon layer comprising a cleaved surface defining an outer surface of the structure,
Inserting the structure into the reactor, the reactor comprising at least one heater and further comprising a central temperature zone and at least one offset temperature zone, the central temperature zone and at least one offset temperature zone each having a corresponding temperature controller. Equipped-;
Setting the temperature of the reactor so that the deposition rate of silicon on the cleaved surface is kineticly limited-A temperature controller for each of the offset temperature regions maintains a uniform temperature in the reactor. Is set to control the temperature of each of the offset temperature regions in proportion to, and the temperature of the reactor is set between 950°C and 1050°C;
Initiating a flow of deposited gas to the reactor; And
Depositing silicon on the cleaved surface of the structure
SOI structure processing method comprising a. The method of claim 9,
The deposition gas is a method for treating an SOI structure comprising at least one of monosilane, dichlorosilane, trichlorosilane, and tetrachlorosilane.

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