KR102139870B1 - Resistive memory device and manufacturing method thereof - Google Patents

Abstract

A resistive memory device and a method of manufacturing the same are disclosed. The resistive memory device includes a plurality of word lines, a plurality of bit lines, and a plurality of resistors disposed between the plurality of word lines and the plurality of bit lines and electrically connected to one of the plurality of word lines and one of the plurality of bit lines, respectively. Memory cells. Each of the plurality of resistive memory cells includes a resistive change layer and an upper electrode that electrically connects the resistive change layer to a word line, and the upper electrode has a columnar shape contacting a portion of the resistive change layer. The columnar upper electrode is formed by forming a hole in the insulating layer and filling the hole with a metal material.

Description

RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to the field of resistance memory, and more particularly, to a resistance memory device with reduced switching voltage distribution and a method of manufacturing the same.

A resistive memory device is a memory device using a resistive change material at a specific voltage. When a voltage greater than or equal to a set voltage is applied to the resistance-changing material, the resistance of the resistance-changing material is lowered. At this time, a conductive filament is generated in the resistance-changing material and turned ON. In addition, when a reset voltage abnormality is applied to the resistance change material, the resistance is increased, and in this case, the generated conductive filament is cut off and turned OFF. A resistive memory device is a nonvolatile memory device using characteristics of a resistance change material whose resistance varies according to a specific voltage.

The biggest problem of the resistive memory device operating by the generation and short circuit of the conductive filament is that the distribution of the operating voltage is large. All memory chips used in modern times are at least 1 Gbit or more, which means that there is at least 1 billion memory devices per chip. If the difference between the operating voltages of the individual memory elements is large, the entire chip cannot be operated stably. In the extreme case, the sensing margin in the read operation is not sufficiently secured, so that 0 and 1 cannot be properly distinguished.

Conductive filaments are formed by vacancy formation and movement in the crystal structure, or by ionization and movement of metals in the metal electrode. The generation of such voids and ions has a certain degree of randomness, so the location and shape in which the filament is generated are not always constant. Due to this, the operating voltage may also be different for each unit element, or in a more severe case, it may be formed differently whenever it operates within the same unit element.

The probability of the generation of vacancy and ions is dominated by the strength of the electric field, and attempts have been made to artificially create a place where the electric field is particularly strong, so that filaments are generated at the site. For example, Korean Patent Publication No. 10-2008-0048757 proposed a configuration in which a central portion of a planar upper electrode has a protruding shape, and a conductive filament is preferentially generated at the protruding portion.

However, the above published patent has a problem in that a groove corresponding to the protrusion of the upper electrode is required on the upper surface of the resistance change layer on which the upper electrode is formed, and the formation of such a groove is not easily reproduced. For example, in the corresponding patent, chemical etching is applied to the entire upper surface of the resistive change layer to differentially etch along a grain boundary existing in the resistive change layer to form a groove. When the upper electrode layer is formed on the upper surface of the resistance change layer in which the groove is formed, a flat upper electrode having a protruding portion while being filled in the groove is provided. Another method disclosed in the same patent is to form a protruding planar lower electrode by placing a metal ball on the lower electrode and then forming a resistive change layer thereon. However, in the former, groove formation patterns are different, and reproducibility is extremely poor, which is difficult to apply industrially. In the latter case, there is a disadvantage that it can be applied only to a limited configuration in which a resistance change layer is formed on the lower electrode, and it is also difficult to control the shape of the protrusion.

Korean Patent Publication 10-2008-0048757

The present invention provides a resistance memory device in which switching voltage distribution is reduced in view of the above-described problems of the prior art.

The present invention also provides a method of manufacturing the improved resistive memory device described above.

The present invention provides a resistive memory device having a memory cell structure with reduced switching voltage distribution. The resistance memory cell employed in the present invention is a metal electrode that is electrically connected to a portion of a lower resistance change layer as a top electrode or a pillar shape in which the top electrode is not planar. Since the upper electrode is formed in a columnar shape, substantially point contact is realized between the upper electrode and the resistance change layer. In this way, by contacting the pillar-shaped metal electrode to a specific portion of the resistance change layer, the electric field can be intentionally focused on the corresponding portion to form a filament at a predetermined position. Conventional resistive memory cells employing a planar upper electrode are determined by initial defects in which filament formation is randomly formed, whereas memory cells employing a columnar upper electrode according to the present invention are not affected by initial defects. Without forming a filament at a predetermined position, the dispersion of the electric field is greatly reduced.

A resistance memory device according to an embodiment of the present invention includes: a plurality of word lines; A plurality of bit lines; And a plurality of resistive memory cells disposed between the plurality of word lines and the plurality of bit lines and electrically connected to one of the plurality of word lines and one of the plurality of bit lines, respectively. Each of the memory cells includes a resistive change layer and an upper electrode electrically connecting the resistive change layer to a word line, and the upper electrode has a column shape contacting a portion of the resistive change layer.

The resistance change layer provides a groove into which the lower end of the upper electrode is inserted, and each of the upper electrodes can be inserted into each groove of the resistance change layer.

The upper electrode may have a truncated cone or pyramid shape with a smaller circumference in the downward direction.

Each of the plurality of resistance memory cells may further include a selector connected to a bottom surface of the resistance change layer.

Each of the resistance change layers may extend in the length direction of the plurality of bit lines and be connected between adjacent cells, or may have a separate shape for each cell.

The present invention also provides a method for manufacturing a resistive memory device, which comprises: (I) arranging and forming a plurality of bit lines; (II) forming a plurality of resistive memory cells on each of the plurality of bit lines; (III) forming a plurality of word lines arranged in a direction intersecting the plurality of bit lines and electrically connected to predetermined memory cells of the plurality of resistive memory cells. The step (II) includes a plurality of selectors spaced apart from each other on each of the plurality of bit lines, a plurality of resistance change layers disposed on the plurality of selectors, and a plurality of upper portions arranged on the plurality of resistance change layers. And forming an electrode. The formation of the upper electrode may be implemented by forming an insulating layer having a plurality of holes to provide at least one hole corresponding to the corresponding resistance change layer on the plurality of resistance change layers, and then filling each hole with metal. Can.

In step (II), the plurality of holes may be formed in a cone shape by dry or wet etching the insulating layer.

In the step (II), the plurality of holes may be formed by etching the insulating layer, and over-etching may be performed to remove a portion of the lower resistance change layer from the etching.

According to the present invention, a resistance memory device with reduced switching voltage distribution is provided. The resistive memory cell employed in the present invention is provided with a columnar upper electrode to intensively generate a filament at a specific location. In addition, according to the present invention, since a metal layer is filled in the holes after forming an insulating layer corresponding to the frame (hole) of the columnar upper electrode, the same shape desired can be easily and repeatedly reproduced. Furthermore, this method of the present invention also has the advantage of being able to form columnar electrodes of various shapes and sizes.

1 is a view showing a resistance memory device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a resistance memory cell employed in the resistance memory device of FIG. 1.
3 to 12 are cross-sectional views illustrating a method of manufacturing a resistance memory device according to an embodiment of the present invention.
13 shows a simulation result of electric field concentration according to the bottom width of the columnar upper electrode in the resistance memory cell of the embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the embodiments of the present invention, when it is determined that detailed descriptions of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

The present invention relates to a resistive memory device with reduced switching voltage distribution and a method for manufacturing the same. For reference, hereinafter, a cell interposed between a word line and a bit line is referred to as a'memory cell', and a configuration including a memory cell, a word line and a bit line is referred to as a resistive memory device.

The resistive memory device or resistive memory cell of the present invention has a columnar upper electrode. The columnar upper electrode is electrically connected to the resistance change layer in substantially point contact. Therefore, a conductive filament can be intensively formed from the contact site, and the distribution of the switch voltage is greatly reduced.

In one embodiment, the pillar-shaped upper electrode may be formed by forming a hole exposing the resistance change layer on the bottom surface of the insulating layer and then filling the hole with a metal material. In one embodiment, the columnar upper electrode may be in the form of a cone, truncated cone, pyramid, or truncated pyramid with decreasing circumference (or width) as it goes downward. The structure of the columnar upper electrode can be obtained by dry or wet etching the insulating layer.

In some embodiments, the lower end portion of the columnar upper electrode may be inserted into a groove provided by the resistance change layer or may be in a form in contact with an upper surface of the resistance change layer.

In another embodiment, the columnar upper electrode may be cylindrical (cylindrical) having various circumferences. In another embodiment, the columnar upper electrode may have a cone shape, a truncated cone, a pyramid shape, or a pyramid shape having a larger circumference.

In the method for manufacturing a resistance memory device of the present invention, an insulating layer serving as a frame for an upper electrode is formed for forming a columnar upper electrode having various shapes and sizes, and a desired columnar upper electrode is formed by filling a metal material. . The insulating layer that forms the upper electrode can obtain various pillar-shaped upper electrodes by selecting a mask pattern and an etching method. The manufacturing method of the present invention makes it possible to easily and repeatedly form an upper electrode having essentially the same shape and size.

1 is a cross-sectional view showing a resistance memory device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a memory cell employed in the resistance memory device of FIG. 1.

1 and 2, the resistance memory device 100 according to an embodiment of the present invention includes a plurality of word lines 110 and a plurality of bit lines 120 arranged in a direction intersecting the word lines 110. And a plurality of resistive memory cells interposed at intersections between the word lines 110 and the bit lines 120. Each resistive memory cell is electrically connected to one of the plurality of word lines and one of the plurality of bit lines, respectively.

2 is a cross-sectional view of a portion of FIG. 1 showing a resistive memory cell. Here, the resistance memory cell is composed of a lower electrode (bit line, 120), a selector (selector, 130), a resistance change layer 140, and an upper electrode 150. In the resistance memory cell employed in the device of the present invention, the upper electrode 150 has a columnar shape, which is connected in a substantially point contact at a part of the upper surface of the lower resistance change layer 140, preferably at a predetermined position.

Preferably, the upper electrode 150 of the memory cell employed in the device 100 according to an embodiment of the present invention may have a cone, cone, pyramid, or pyramid shape with a smaller circumference. Also, preferably, the lower end of the upper electrode 150 may be inserted at a predetermined depth from the upper surface of the resistance change layer 140. To this end, the resistance change layer 140 may provide a groove 141 into which the lower end of the upper electrode 150 can be inserted, and this groove 141 is used in an etching process to form the insulating layer 180. A portion of the upper portion of the resistance change layer 140 may be formed by over-etching. That is, as described in more detail in the description of the manufacturing method below, by performing an over-etch in the etching process for forming the hole 181 in the insulating layer 180, the groove of the upper surface portion of the resistance change layer 140 After forming the 141, the metal material for the upper electrode plate 17 may be implemented by filling the groove 141 to the inside.

In one embodiment, the shape of the upper electrode 150 may be a cone shape by manufacturing the shape of the hole 181 in a cone shape by applying a dry or wet angle to the above-described etching process. The upper electrode 150 having the shape of a cone, cone, pyramid, or pyramid has a contact area with the word line 110 greater than that with the resistance change layer 140.

The shape of the upper electrode 150 and the connection configuration of the resistance change layer 140 allow the electric field to be concentrated at a predetermined point, thereby forming a filament at that point, thereby greatly reducing the dispersion of the electric field.

In other embodiments of the present invention, the shape of the upper electrode may be variously changed. For example, the columnar upper electrode may be a cylindrical (cylinder) type having a different diameter, or may be a conical or pyramid having a wider circumference.

3 to 11 are cross-sectional views illustrating a method of manufacturing a resistance memory device according to an embodiment of the present invention. In the drawing, the upper position of the drawing (the drawings indicated by'a') is a cross-sectional view as viewed in the X direction from the orientation shown in FIG. It is a sectional view seen from the Y direction.

As shown in FIG. 3, for example, a plurality of bit lines 120 are formed on the silicon substrate S. The plurality of bit lines 120 may be patterned through a photolithography process after depositing a metal film on the substrate S, for example. Materials that can be applied to the bit line 120 include, for example, W, WSi, NiSi, and CoSi, but are not limited thereto.

4, an insulating layer 160 exposing the upper surfaces of the bit lines 120 is formed while the upper surfaces are flat. This may be implemented, for example, by depositing an insulating film such as SiO ₂ on the substrate S and the bit line 120 to sufficiently cover the bit line 120, and then performing a CMP (Chemical Mechanical Planarization) operation on the insulating film. Can. As described above, the insulating layer 160 is planarized to expose the top surfaces of the bit lines 120.

5, a selector 130 is formed on each bit line 120. The selector 130 may be, for example, a diode formed of polysilicon. The selector 130 may be formed by, for example, laminating a polysilicon film and then patterning it through a photolithography process, and is disposed at each point that is an intersection of the bit lines 120 and the word lines 110.

Subsequently, as shown in FIG. 6, an insulating layer 170 is formed to provide a flat surface. The insulating layer 170 may be implemented by depositing an insulating film such as a silicon oxide film on the entire surface to cover the selector 130 and then performing planarization through CMP. As shown in the figure, the top surfaces of the selectors 130 are exposed through planarization.

As shown in FIG. 7, a resistance change layer 140 is formed on each selector 130. Resistance variable layer 140, for example, _{Nb 2 O 5, NiO, MgO} , TiO 2, ZrO 2, CuO 2, Nb: SrTiO 3, Cr: SrTiO 3, Cr: SrZrO 3, AlN, ZrN, CrN, FeN , Si ₃ N _{4 It} may be formed by laminating the material on the front surface and patterned through a photolithography process, but the applied material is not limited thereto. In the illustrated embodiment, the resistance change layer 140 extends in the longitudinal direction of the bit line 120 to show a structure shared with adjacent cells. Although not shown, another embodiment of the present invention includes a configuration having a resistive change layer separated for each cell.

8, an insulating layer 180 having a flat top surface is formed while covering the resistance change layers 140. Since the insulating layer 180 is an insulating layer forming the upper electrode plate 17, unlike the other insulating layers, the upper surface of the resistance change layer 140 is not exposed in this step. Accordingly, the formation of the insulating layer 180 having a flat top surface may be implemented by forming an insulating film such as a silicon oxide film on the entire surface and then applying a CMP process to the insulating film.

9, a plurality of holes 181 are formed in the insulating layer 180. A plurality of holes 181 are formed such that at least one is disposed in each cell, and are patterned through a photolithography process. The holes 181 formed in the insulating layer 180 are formed to expose the resistance change layer 140 on the bottom surface. Preferably, in the etching process, over-etching may be performed so that a groove 141 having a predetermined depth is formed on the upper surface of the resistance change layer 140. In addition, preferably, a dry or wet angle may be applied as in the illustrated embodiment, so that the circumference (or width) becomes smaller as the holes 181 are directed downward, thereby forming a cone shape. This makes it possible to minutely form the area of the bottom portion of the hole 181 to which the resistance change layer 140 is exposed even if a margin is given to some extent in the mask forming process.

As shown in FIG. 10, a metal material for an upper electrode is deposited on the entire surface of the insulating layer 180 including the plurality of holes 181. Metal materials are filled in the plurality of holes 181 by the deposition. The metal for the upper electrode plate 17 may include Ti, Al, Ta, TaN, TiN, and the like, but is not limited thereto.

Next, as shown in FIG. 11, the upper electrode 150 is formed by removing the remaining metals except for the metal filled in the plurality of holes 181. The removal of the metal located on the top surface of the insulating layer 180 may use CMP, for example.

As shown in the enlarged view of FIG. 11, the shape of the lower portion of the groove 141 formed in the resistance change layer 140 and the columnar upper electrode formed by filling the groove 141 may be changed. For example, rounded or angled corners can be obtained.

12, a plurality of word lines 110 arranged in a direction intersecting the bit lines 120 is formed. The metal applicable to the word line 110 may include, for example, W, WSi, NiSi, CoSi, etc., but is not limited thereto. The word line 110 is electrically connected to the upper electrodes 150 exposed from the insulating layer 180. Reference numeral 190 is an insulating layer formed after patterning of the word lines 110.

1 is a view illustrating a state in which the insulating layers 160, 170, 180, and 190, also called interlayer insulating layers, are excluded from the device 100 of the present invention manufactured through the above-described process.

13 shows a simulation result of electric field concentration according to the bottom width of the columnar upper electrode in the resistance memory cell of the embodiment of the present invention. In the drawing (a) to (c) are the upper electrodes employed in the present invention, the bottom width is 1nm, 3nm, and 5nm, respectively. In the drawing, (d) is a result of electric field concentration simulation of a conventional resistive memory cell employing a planar upper electrode. As can be seen in FIG. 13, the upper electrodes (a, b, c) whose circumference becomes smaller toward the lower end employed in the resistive memory device of the present invention show that the electric field is concentrated, while (d) and In the case of a memory cell employing the same conventional planar upper electrode, it shows that electric field concentration does not occur.

As described above, specific embodiments have been described in the detailed description of the present invention, but it is apparent to those skilled in the art that various modifications are possible without departing from the scope of the present invention.

100: resistance memory device, 110: word line, 120: bit line, 130: selector, 140: resistance change layer, 150: upper electrode, 160, 170, 180, 190: insulating layer, 141: groove, 181: hole

Claims (8)

As a resistive memory device:
A plurality of word lines;
A plurality of bit lines; And
And a plurality of resistive memory cells disposed between the plurality of word lines and the plurality of bit lines and electrically connected to one of the plurality of word lines and one of the plurality of bit lines, respectively.
Each of the plurality of resistance memory cells includes a resistance change layer and an upper electrode electrically connecting the resistance change layer to a word line,
The upper electrode has a columnar shape in contact with a portion of the resistance change layer,
The resistive change layer provides a groove into which the lower end of the upper electrode is inserted, and the upper electrode is a resistive memory device into which the lower end is inserted into the groove of the resistive change layer.
The method according to claim 1,
A lower end portion of the upper electrode inserted into the groove of the resistive change layer has a round shape.
The method according to claim 1,
The upper electrode is a resistive memory device having a conical or pyramidal shape with a smaller circumference in the downward direction.
The method according to claim 1,
Each of the plurality of resistive memory cells further includes a selector connected to a lower surface of the resistive change layer.
The method according to claim 1,
Each of the resistance changing layers extends in a length direction of the plurality of bit lines and is connected to adjacent cells or has a separate shape for each cell.
As a method for manufacturing a resistive memory device:
(I) arranging and forming a plurality of bit lines;
(II) forming a plurality of resistive memory cells on each of the plurality of bit lines;
(III) forming a plurality of word lines arranged in a direction crossing the plurality of bit lines to be electrically connected to predetermined memory cells of the plurality of resistive memory cells.
The step (II) includes a plurality of selectors spaced apart from each other on each of the plurality of bit lines, a plurality of resistance change layers disposed on the plurality of selectors, and a plurality of upper portions arranged on the plurality of resistance change layers. Forming an electrode,
The formation of the upper electrode is to form an insulating layer having a plurality of holes to provide at least one hole corresponding to the corresponding resistance change layer on the plurality of resistance change layers, and then fill each hole with metal.
The plurality of holes are formed by etching the insulating layer, and over etching is performed to remove a portion of the lower resistance change layer from the etching.
The method according to claim 6, in step (II),
The plurality of holes are dry memory or wet etching the insulating layer to form a cone shape.
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