JP2014150234A - Nonvolatile storage and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile storage in which occurrence of dimensional abnormality due to side etching of upper layer wiring, or occurrence of short circuit due to inclination of the upper layer wiring can be suppressed, when processing an underlying memory cell by dry etching, following to the processing of the upper layer wiring, in a cross point memory.SOLUTION: A nonvolatile storage includes a memory cell array MCA, a word line hookup WHU formed by leading out a plurality of word lines WL extending in the X direction to the outside of the memory cell array MCA, a bit line hookup BHU provided on an upper layer of the word lines WL and formed by leading out a plurality of bit lines BL extending in the Y direction to the outside of the memory cell array MCA, and a dummy wiring DL connected with the bit lines BL. The dummy wiring DL is provided so that the sum of the areas of the bit line BL and the dummy wiring DL is equal in each bit line BL.

Description

  Embodiments described herein relate generally to a nonvolatile memory device and a method for manufacturing the same.

  In recent years, attention has been paid to ReRAM (Resistive Random Access Memory) that stores resistance value information of an electrically rewritable variable resistance element, for example, a high resistance state and a low resistance state in a nonvolatile manner as a nonvolatile memory device. In such a memory cell array region in ReRAM, for example, a resistance change type memory cell in which a resistance change element as a storage element and a rectifying element such as a diode are connected in series extends in parallel in the first direction. Are arranged in an array at intersections of a plurality of word lines and a plurality of bit lines extending in parallel in a second direction perpendicular to the first direction. Further, the word line and the bit line are drawn out to the word line hookup region and the bit line hookup region, respectively, and connected to another wiring layer through a contact.

  Here, in the word line hookup region and the bit line hookup region, contact connection portions for connecting contacts to the word lines and the bit lines are provided so that the formation positions of adjacent wirings do not overlap. As a result, the word line wiring length and bit line wiring length including the memory cell array region and the hookup region are different between adjacent wirings. Therefore, a phenomenon occurs in which the amount of charge-up of the wiring differs at the stage of processing the word line or the bit line by the dry etching process. In particular, in the cross-point type memory, it is necessary to process the memory cell at the intersection after processing the upper layer wiring. However, the amount of charge-up between the wirings differs at the stage when the upper layer wiring is processed. In such a state, when the memory cell and the interlayer insulating film embedded between the memory cells are processed by dry etching, dimensional abnormality due to side etching of the upper layer wiring due to the bending of the trajectory of incident particles (ions, electrons), or upper layer wiring There is a problem that the lower interlayer insulating film is side-etched and the upper-layer wiring falls and short-circuits.

JP 2009-130140 A

  According to one embodiment of the present invention, in a cross-point type memory, when an upper layer wiring is processed and then a memory cell processing below the upper layer wiring is performed by dry etching, the occurrence of dimensional abnormality or upper layer due to side etching of the upper layer wiring It is an object of the present invention to provide a nonvolatile memory device that suppresses occurrence of a short circuit due to wiring collapse and a manufacturing method thereof.

  According to the embodiment, a non-volatile memory device including a memory cell formation region, a first wiring hookup region, a second wiring hookup region, and a first dummy wiring is provided. The memory cell formation region is a region having a memory cell array layer in which a plurality of nonvolatile memory cells are formed in a matrix. The first wiring hookup region is connected to the nonvolatile memory cell in the memory cell formation region, and a plurality of first wirings extending in a first direction are formed to be drawn out of the memory cell formation region. Area. The second wiring hookup region is connected to the nonvolatile memory cell in an upper layer than the first wiring in the memory cell formation region, and extends in a second direction intersecting the first direction. The wiring is a region formed by being drawn out of the memory cell formation region. The first dummy wiring is connected to the second wiring. The first dummy wiring is provided so that the sum of the areas of the second wiring and the first dummy wiring in the memory cell formation region and the second wiring hookup region is equal in each of the second wirings. .

FIG. 1 is a diagram schematically illustrating an example of a configuration of a resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 2A is a diagram schematically illustrating an example of the procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 2-2 is a diagram schematically illustrating an example of a procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 3A is a diagram schematically illustrating an example of the procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 3B is a diagram schematically illustrating an example of the procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 4A is a diagram schematically illustrating an example of the procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 4B is a diagram schematically illustrating an example of the procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 5A is a diagram schematically illustrating an example of the procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 5-2 is a diagram schematically illustrating an example of a procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 6A is a diagram schematically illustrating an example of the procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 6B is a diagram schematically illustrating an example of the procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 7A is a diagram schematically illustrating an example of the procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 7B is a diagram schematically illustrating an example of the procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. FIG. 8 is a top view schematically showing another configuration example of the nonvolatile memory device according to the embodiment. FIG. 9 is a top view schematically showing another configuration example of the nonvolatile memory device according to the embodiment.

  Exemplary embodiments of a nonvolatile memory device and a method for manufacturing the same will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment. In addition, cross-sectional views of the nonvolatile memory device used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like may be different from the actual ones. Furthermore, in the top view of the non-volatile memory device used in the following embodiments, hatching is given to make the relationship between the constituent members easy to understand. Furthermore, in the following embodiments, a resistance change type memory will be described as an example of a nonvolatile memory device.

  FIG. 1 is a diagram schematically illustrating an example of a configuration of a resistance change memory as a nonvolatile memory device according to the embodiment. FIG. 1A is a top view of the resistance change memory according to the embodiment. FIG. 1B is a cross-sectional view showing an example of the structure of the memory cell of the resistance change type memory. In FIG. 1A, the lower layer wiring is shown for convenience, and FIG. 1B shows a cross-sectional structure along the word line on the word line.

  In the resistance change type memory, a plurality of word lines WL extending in the X direction and a plurality of bit lines BL extending in the Y direction having a height different from the word line WL are arranged so as to cross each other. Each intersection has a memory cell array portion MCA in which a resistance change type memory cell (hereinafter also simply referred to as a memory cell) MC in which a resistance change element VR and a selector layer SL are connected in series is disposed. Further, a word line hookup unit WHU from which a word line WL is drawn from the memory cell array unit MCA is provided on one side in the X direction of the memory cell array unit MCA, and one side in the Y direction of the memory cell array unit MCA is provided. Is provided with a bit line hookup part BHU from which a bit line BL is drawn from the memory cell array part MCA.

  In the memory cell array unit MCA, as shown in FIG. 1B, a selector layer SL and a resistance change element VR constituting the memory cell MC are stacked on a word line WL extending in the X direction, and the resistance change element A bit line BL extending in the Y direction is formed on VR.

  The selector layer SL is a layer that controls the direction of the current flowing through the memory cell MC, and is made of a material having a rectifying action such as a Schottky diode, a PN junction diode, or a PIN diode, and is formed on the word line WL. For example, it can be constituted by a polycrystalline silicon film having a PIN junction.

  The resistance change element VR includes a lower electrode layer LE, a resistance change layer RW as a nonvolatile memory layer, and an upper electrode layer UE. The lower electrode layer LE and the upper electrode layer UE are made of a metal material or a metal nitride material that does not impair the variable resistance of the resistance change layer RW by reacting with the resistance change layer RW. As the lower electrode layer LE and the upper electrode layer UE, for example, at least one metal material selected from Pt, Au, Ag, Ru, Ir, Co, Al, Ti, W, Mo, Ta, or the like, or Ti Nitride of at least one metal material selected from W, Mo, Ta, etc. can be used. The upper electrode layer UE or the lower electrode layer LE may be omitted depending on circumstances.

  The resistance change layer RW is a resistance change material made of a metal oxide or a carbon film that can be switched between a high resistance state and a low resistance state by controlling a voltage value and an application time, and a crystal / amorphized state of a chalcogenide compound. It is composed of a phase change memory material that changes its resistance value by a change. Examples of resistance change materials include metal oxide films containing at least one element such as Si, Ti, Ta, Nb, Hf, Zr, W, Al, Ni, Co, Mn, Fe, Cu, and Mo. Can do. Note that when the variable resistance layer RW itself is a material having a rectifying characteristic, the selector layer SL is omitted.

  In the word line hookup part WHU, a word line WL extending from the memory cell array part MCA is formed. Here, of the word lines WL having a line-and-space pattern, the two word lines WL formed near the center in the Y direction are made the longest and gradually become shorter toward both ends in the Y direction. I have to. Further, a contact connection portion CC is provided at an end portion of the word line WL, and the word line contact WC is provided in the contact connection portion CC. The word line contact WC is connected to the wiring connected to the peripheral circuit at the end thereof.

  In the bit line hookup part BHU, a bit line BL extending from the memory cell array part MCA is formed. Here, of the bit lines BL in a line-and-space pattern, the two bit lines BL formed in the vicinity of the central portion in the X direction are made the longest, and gradually become shorter toward both ends in the X direction. I have to. Further, a contact connection portion CC is provided at an end portion of the bit line BL, and a bit line contact BC is provided in the contact connection portion CC. The bit line contact BC is connected to the wiring connected to the peripheral circuit at the end thereof.

  The adjacent memory cells MC and the word line WL and the bit line BL are insulated by, for example, an interlayer insulating film.

  In the present embodiment, as shown in FIG. 1A, in the bit line BL that is the upper wiring layer, the areas of the bit lines BL formed in the memory cell array portion MCA and the bit line hookup portion BHU are equal. As described above, the dummy wiring DL is provided in the bit line hookup portion BHU. In the example of FIG. 1A, the width of each bit line BL is usually the same, and the shape of the contact connection portion CC provided at one end of the bit line BL is also the same. The dummy wiring DL is provided so that the total length of BL and the dummy wiring DL is the same for any bit line BL. In this example, dummy wirings DL are provided on the other bit lines BL so as to match the length of the bit line BL provided at the center in the X direction of the bit line BL. As described above, the length of the bit line BL is the longest in the vicinity of the central portion in the X direction and is gradually shortened toward both end portions in the X direction. , Which are arranged at both ends in the X direction, are the longest and gradually become shorter toward the vicinity of the central portion in the X direction.

  As will be described later, when the layer between the upper layer wiring and the lower layer wiring is processed into a line and space shape, the dummy wiring DL has an equal charge-up amount in each upper layer wiring processed into a line and space shape. It has the function to do.

  In the resistance change memory having such a configuration, the voltage applied to the word line WL and the bit line BL is controlled so that a predetermined voltage is applied to the target memory cell MC, thereby configuring the memory cell MC. The resistance state of the resistance change layer RW is changed. Specifically, a current is passed through the resistance change layer RW in the low resistance state, and reset (erasing) processing is performed to return to the high resistance state in which the resistance has increased by one to two digits by Joule heating, or the resistance change layer in the high resistance state A set (write) process for applying a voltage to RW to return to a low resistance state is performed. As described above, the resistance value information is stored by creating the high resistance state / low resistance state by the reset process and the set process, and the memory function is made to function by detecting the difference in current flowing through the memory cell MC.

  Next, a manufacturing method of the resistance change type memory having such a configuration will be described. FIG. 2A to FIG. 7B are diagrams schematically illustrating an example of the procedure of the method of manufacturing the resistance change type memory as the nonvolatile memory device according to the embodiment. In these drawings, FIGS. 2-1 (a), 3-1 (a), 4-1 (a), 5-1 (a), 6-1 (a) and 7-1 (a) are shown. a) is a top view, FIG. 2-1 (b), FIG. 3-1 (b), FIG. 4-1 (b), FIG. 5-1 (b), FIG. 6-1 (b), and FIG. -1 (b) is a view corresponding to the AA cross section of FIG. 1 (a), and is a cross sectional view on the word line WL along the word line WL. FIGS. 2-2 (a) and 3-2 (A), FIG. 4-2 (a), FIG. 5-2 (a), FIG. 6-2 (a), and FIG. 7-2 (a) correspond to the BB cross section of FIG. In the figure, it is a cross-sectional view of a portion where there is no word line WL along the word line WL, and FIG. 2-2 (b), FIG. 3-2 (b), FIG. b), FIG. 6-2 (b) and FIG. 7-2 (b) are diagrams corresponding to the CC cross section of FIG. FIG. 2-2 (c), FIG. 3-2 (c), FIG. 4-2 (c), FIG. 5-2 (c), and FIG. 6-2. FIGS. 7C and 7C are diagrams corresponding to the DD cross section of FIG. 1A, and are cross-sectional views of portions where there is no bit line BL along the bit line BL. In FIG. 6A, the lower layer wiring is displayed for convenience.

  First, on a semiconductor substrate (not shown), a peripheral circuit (Complementary Metal) (not shown) including an element such as a cell control transistor connected to the word line WL and the bit line BL of the memory cell MC and a wiring layer connected to the element. -Oxide-Semiconductor (CMOS) Logic circuit or the like) is formed, and an interlayer insulating film ILD1 is formed on the peripheral circuit. Next, as shown in FIGS. 2-1 to 2-2, a film for forming a memory cell array layer is stacked on the entire surface of the interlayer insulating film ILD1. That is, the wiring material layer EL1, the selector layer SL, the lower electrode layer LE, the resistance change layer RW, and the upper electrode layer UE that form the resistance change element VR are sequentially stacked.

  Thereafter, as shown in FIGS. 3A to 3B, the upper electrode layer UE, the resistance change layer RW, the lower electrode layer LE, the selector layer SL, and the upper electrode layer UE using the word line pattern mask. The wiring material layer EL1 is patterned into a line-and-space shape extending in the X direction by dry etching such as reactive ion etching (Reactive Ion Etching). Here, etching is performed until the bottom of the wiring material layer EL1 is cut from the wiring material layer EL1 adjacent in the Y direction. Accordingly, the wiring material layer EL1 becomes the word line WL, and the selector layer SL, the lower electrode layer LE, the resistance change layer RW, and the upper electrode layer UE are formed as a pattern extending in the same X direction as the word line WL.

As shown in FIG. 3A, the word line WL is formed across the memory cell array formation region _RMCA and the word line hookup formation region _RWHU . In the word line hookup formation region _RWHU , the word line WL is the longest arranged at the center in the Y direction, and is patterned so as to become shorter toward both ends in the Y direction of the word line hookup formation region _RWHU. Is done. Further, in the word line hookup formation region _RWHU , an end portion in the X direction of the word line WL is connected to the word line contact WC and a contact connection portion CC having a width larger than the width of the word line WL is connected. Patterning. As a result, the stacked film from the upper electrode layer UE to the wiring material layer EL1 is removed except at the position where the word line WL is formed.

  Here, even if the wiring material layer EL1 is charged up during the etching, the wiring material layer EL1 has a flat shape before being cut as the word line WL, and the charge is evenly distributed. It is in. Therefore, the phenomenon that the trajectory of charged particles (ions and electrons) during etching is bent by the charge charged in the wiring material layer EL1 hardly occurs. Therefore, in this example, the lower layer wiring (word line WL) disposed in the lower layer of the memory cell array layer is etched by a conventional method.

Next, as shown in FIGS. 4A to 4B, an interlayer insulating film ILD2 such as a TEOS (Tetraethoxysilane) film is embedded in the etched region, and is formed above the upper electrode layer UE by a CMP (Chemical Mechanical Polishing) method. The upper surface is flattened while removing the interlayer insulating film ILD2 formed in the step. Thus, between the memory cell array forming region R _MCA and the word line hookup forming region R extends in the X direction _WHU line-and-space-like pattern, and the bit line hookup forming region R _BHU interlayer insulating film ILD2 embedded .

  Thereafter, as shown in FIGS. 5-1 to 5-2, a wiring material layer EL2 is formed on the upper electrode layer UE and the interlayer insulating film ILD2.

Next, as shown in FIGS. 6-1 to 6-2, using the bit line pattern mask, the wiring material layer EL2, the upper electrode layer UE, the resistance change layer RW, the lower electrode layer LE, and the selector layer SL are used. The laminated film and the interlayer insulating film ILD2 buried between the laminated films are patterned into a line and space shape extending in the Y direction by dry etching. Here, etching is performed until the bottom of the selector layer SL is separated from the selector layer SL adjacent in the X direction. As a result, the second wiring material layer EL2 becomes the bit line BL, and the width of the word line WL and the width of the bit line BL are set at each intersection position of the word line WL and the bit line BL in the memory cell array formation region _RMCA . A memory cell array is formed in which memory cells MC each including a stacked film of the selector layer SL defined in (1) and the resistance change element VR including the lower electrode layer LE, the resistance change layer RW, and the upper electrode layer UE are disposed.

  As shown in FIG. 6A, the bit line BL is formed across the memory cell array portion MCA and the bit line hookup portion BHU. In the bit line hookup part BHU, the bit line BL is the longest disposed at the center in the X direction, and is patterned so as to become shorter toward both ends in the X direction of the bit line hookup part BHU. Further, in the bit line hookup portion BHU, patterning is performed so that the end portion of the bit line BL in the Y direction is connected to the bit line contact BC and the contact connection portion CC having a width larger than the width of the bit line BL is connected. Is done. Thereby, the interlayer insulating film ILD2 is removed from the wiring material layer EL2 to the selector layer SL except at the position where the bit line BL is formed.

  Furthermore, in the present embodiment, in the bit line hookup portion BHU, the contact connection portion CC is extended so that the area of each bit line BL (the length when the width of each bit line BL is the same) is equal. Further, patterning is performed so that the dummy wiring DL is formed. Here, on the basis of the area (length) of the two bit lines BL arranged in the center portion in the X direction, dummy wires DL having different lengths are provided on the other bit lines BL.

  When patterning into the shape of the bit line BL which is the upper layer wiring in this way, the wiring material layer EL2 is processed into the bit-and-space bit line BL extending in the Y direction at the initial stage of etching, and etching is performed. It will be charged up. In particular, if the lengths of the bit lines BL are different, the charge-up amount varies. However, since the dummy wiring DL is provided so that the area (length) of the bit-and-space bit line BL is the same for all the bit lines BL, the charge-up amount of each bit line BL is substantially the same. The bit lines BL have substantially the same potential. That is, a difference in charge-up amount between the bit lines BL that are patterned so that the area (length) obtained by adding the dummy lines DL and the bit lines BL and the dummy lines DL becomes equal is less likely to occur.

  In addition, after processing the wiring material layer EL2, the laminated film including the upper electrode layer UE, the resistance change layer RW, the lower electrode layer LE, and the selector layer SL, and the interlayer insulating film ILD2 are also processed into a line and space shape. I must continue. At this time, if the wiring material layer EL2 processed as described above, that is, the charge-up amount of the bit line BL is different between the wirings, the trajectory of the incident particles is bent, and the film below the bit line BL is processed. Sometimes dimension anomalies occur. However, in this embodiment, since the dummy wirings DL are provided so that the areas (lengths) of the bit lines BL are equal, the potentials of the bit lines BL after processing can be made substantially equal during etching. As a result, incident particles during dry etching are incident on the substrate surface in a direction perpendicular to the substrate surface, dimensional anomalies due to side etching of the bit lines BL due to bending of the orbits of the incident particles, and interlayer insulating films below the bit lines BL. Can be prevented from being side-etched, causing the bit line BL to fall and short-circuit.

  Thereafter, as shown in FIGS. 7A and 7B, an interlayer insulating film ILD3 such as a TEOS film is embedded in the etched region, and an interlayer insulating film ILD3 formed above the bit line BL by a CMP method. Is removed and the upper surface is flattened. As a result, the interlayer insulating film ILD2 is buried between the line-and-space pattern extending in the Y direction between the memory cell array portion MCA and the bit line hookup portion BHU, and in the word line hookup portion WHU.

  Thereafter, through holes are formed in the interlayer insulating films ILD2 and ILD3 so as to be connected to the contact connection portion CC of the word line hookup portion WHU and the bit line hookup portion BHU. Subsequently, a word line contact WC and a bit line contact BC are formed in each region by embedding a conductive material in the through hole. Further, by forming a wiring layer connected to the word line contact WC and the bit line contact BC on the interlayer insulating film ILD3, a nonvolatile memory device as shown in FIGS. 1A and 1B is manufactured. Is done.

  An appropriate mask material can be used as the word line pattern mask used when patterning the word lines WL and the bit line pattern mask used when patterning the bit lines BL. For example, a line and space resist pattern may be used as a word line pattern mask or a bit line pattern mask. In addition, a hard mask and resist made of silicon oxide film, etc. are formed on the object to be processed, a line and space pattern is formed on the resist, and then the line and space pattern is transferred to the hard mask. It may be used as a mask or a bit line pattern mask.

  Further, a cap film made of a conductive material that functions as a stopper film may be provided between the upper electrode layer UE and the upper wiring (bit line BL) when the interlayer insulating film ILD2 is embedded. In this case, the cap film is formed on the upper electrode layer UE in the steps shown in FIGS. 2-1 to 2-2.

  As described above, the case where the dummy wiring DL is formed in the bit line hookup portion BHU is shown, but the present invention is not limited to this. FIG. 8 is a top view schematically showing another configuration example of the nonvolatile memory device according to the embodiment. In the case of FIG. 1A, the case where the dummy wiring DL is provided in the bit line hookup part BHU is shown. However, as shown in FIG. 8, the side opposite to the bit line hookup part BHU of the memory cell array part MCA. In addition, a dummy wiring DL may be provided. Also in this case, dummy wirings DL having different lengths are provided so that all bit lines BL have the same area (length).

  In the above example, the dummy wiring DL is made the same as the width of the bit line BL, and the length of the bit line BL is made the same, but the width of the dummy wiring DL is made different from the bit line BL. Also good. In this case, the length of the dummy wiring DL is adjusted so that the areas of all the bit lines BL are equal.

  Further, in the above example, the dummy wiring DL is arranged according to the area (length) of the longest bit line BL. However, according to the area (long length) larger than the longest bit line BL. Thus, the dummy wiring DL can be arranged.

  Furthermore, in the above description, the case where the resistance change type memory is constituted by one memory cell array layer is taken as an example. However, a plurality of memory cell array layers are stacked and between memory cell array layers adjacent in the stacking direction. The present embodiment can also be applied to a three-dimensional cross-point type memory having a structure sharing the bit line BL or the word line WL. In this case, the dummy wiring DL is provided in the wiring that becomes the bit line BL or the word line WL other than the lowermost layer.

  The manufacturing method in this case is, for example, after FIGS. 4-1 and 4-2, on the upper electrode layer UE and the interlayer insulating film ILD2, the second wiring material layer, the selector layer, the lower electrode layer, and the resistance change Layer and upper electrode layer are laminated in order, and the first layer from the second upper electrode layer in a line and space shape extending in a direction rotated 90 degrees in the substrate plane with respect to the extending direction of the wiring immediately below The selector layer SL is patterned, and an interlayer insulating film is embedded in the patterned region. Then, by repeating this process a predetermined number of times from the processes shown in FIGS. 2-1 to 2-2, an arbitrary number of stacked nonvolatile memory devices can be manufactured.

  FIG. 9 is a top view schematically showing another configuration example of the nonvolatile memory device according to the embodiment. In this figure, in a nonvolatile memory device in which a plurality of memory cell array layers are stacked, patterning of lower layer wirings (for example, word lines WL) and upper layer wirings (for example, bit lines BL) of memory cell array layers other than the lowermost memory cell array layer is performed. It shows a state. As shown in this figure, the dummy wiring DL is provided so as to be connected not only to the bit line BL which is the upper layer wiring but also to the word line WL which is the lower layer wiring. Also, the memory cell array layer, which is the lowermost layer of the nonvolatile memory device, may have such a structure.

  In the present embodiment, when the layer between the upper layer wiring and the lower layer wiring is dry-etched together with the upper layer line in a line-and-space manner, a dummy wiring DL connected to the line-and-space upper layer wiring is provided, and each line pattern The bit lines BL and dummy wirings DL were patterned so that the total area was substantially the same. As a result, the charge-up amount of each upper layer wiring during etching becomes substantially the same, and when processing the upper layer wiring and further processing the layer between the upper layer wiring and the lower layer wiring, the charge-up amount between the upper layer wirings is different. Is less likely to occur. As a result, there is an effect that it is possible to suppress the occurrence of a processing abnormality such as a wiring shape abnormality due to the bending of the trajectory of incident particles during dry etching.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

BC: Bit line contact, BHU: Bit line hookup part, BL: Bit line, CC: Contact connection part, DL: Dummy wiring, EL1, EL2 ... Wiring material layer, ILD1 to ILD3 ... Interlayer insulating film, LE ... Lower electrode Layer, MC ... memory cell, MCA ... memory cell array part, R _BHU ... bit line hookup formation region, R _MCA ... memory cell array formation region, RW ... resistance change layer, _RWHU ... word line hookup formation region, SL ... selector Layer, UE ... upper electrode layer, VR ... variable resistance element, WC ... word line contact, WHU ... word line hookup part, WL ... word line.

Claims (7)

A memory cell formation region having a memory cell array layer in which a plurality of nonvolatile memory cells in which a selector layer and a resistance change layer are sequentially stacked are formed in a matrix;
A first wiring hookup region formed by a plurality of first wirings connected to the nonvolatile memory cell in the memory cell formation region and extending in a first direction being drawn out of the memory cell formation region;
In the memory cell formation region, a plurality of second wirings connected to the nonvolatile memory cell in an upper layer than the first wiring and extending in a second direction intersecting the first direction are outside the memory cell formation region. A second wiring hookup region formed by being pulled out by
A first dummy wiring connected to the second wiring;
A second dummy wiring connected to the first wiring;
With
A plurality of the memory cell array layers are stacked in the height direction, and the first wiring or the second wiring is shared between the memory cell array layers adjacent in the height direction,
The variable resistance layer is a metal oxide containing at least one element selected from the group consisting of Si, Ti, Ta, Nb, Hf, Zr, W, Al, Ni, Co, Mn, Fe, Cu, and Mo. A membrane, a carbon membrane or a chalcogenide compound,
The length of the plurality of second wirings in the second wiring hookup region is the longest provided at the central portion in the first direction of the memory cell formation region, and is directed to both end portions in the first direction. Formed to be shorter as
The length of the plurality of first wirings in the first wiring hookup region is the longest that is provided in the central portion in the second direction of the memory cell formation region, and is directed to both end portions in the second direction. Formed to be shorter as
The first area of the memory cell formation region is set such that the sum of the areas of the second wiring and the first dummy wiring in the memory cell formation region and the second wiring hookup region is equal in each of the second wirings. The length of the first dummy wiring connected to the other second wiring is determined based on the length of the second wiring provided in the central portion of the direction,
The second area of the memory cell formation region is such that the sum of the areas of the first wiring and the second dummy wiring in the memory cell formation region and the first wiring hookup region is equal in each of the first wirings. A length of the second dummy wiring connected to the other first wiring is determined based on the length of the first wiring provided in the central portion in the direction. A memory cell formation region having a memory cell array layer in which a plurality of nonvolatile memory cells are formed in a matrix;
A first wiring hookup region formed by a plurality of first wirings connected to the nonvolatile memory cell in the memory cell formation region and extending in a first direction being drawn out of the memory cell formation region;
In the memory cell formation region, a plurality of second wirings connected to the nonvolatile memory cell in an upper layer than the first wiring and extending in a second direction intersecting the first direction are outside the memory cell formation region. A second wiring hookup region formed by being pulled out by
A first dummy wiring connected to the second wiring;
With
Providing the first dummy wiring so that the sum of the areas of the second wiring and the first dummy wiring in the memory cell formation region and the second wiring hookup region is equal in each of the second wirings; A non-volatile memory device. A second dummy wiring connected to the first wiring;
Providing the second dummy wiring so that the sum of the areas of the first wiring and the second dummy wiring in the memory cell formation region and the first wiring hookup region is equal in each of the first wirings; The nonvolatile memory device according to claim 2, wherein the nonvolatile memory device is a non-volatile memory device. The plurality of second wirings have the same width,
The first dummy wiring has the same width as the second wiring,
The length of the first dummy wiring is set so that the sum of the lengths of the second wiring and the first dummy wiring is equal in each second wiring,
The plurality of first wirings have the same width,
The second dummy wiring has the same width as the first wiring,
4. The nonvolatile memory according to claim 3, wherein a length of the second dummy wiring is set so that a sum of lengths of the first wiring and the second dummy wiring is equal in each of the first wirings. 5. Sex memory device. The length of the plurality of second wirings in the second wiring hookup region is the longest provided at the central portion in the first direction of the memory cell formation region, and is directed to both end portions in the first direction. Formed to be shorter as
The length of the first dummy wiring connected to the other second wiring is determined on the basis of the length of the second wiring provided in the central portion in the first direction of the memory cell formation region,
The length of the plurality of first wirings in the first wiring hookup region is the longest that is provided in the central portion in the second direction of the memory cell formation region, and is directed to both end portions in the second direction. Formed to be shorter as
The length of the second dummy wiring connected to the other first wiring is determined based on the length of the first wiring provided in the central portion in the second direction of the memory cell formation region. The nonvolatile memory device according to claim 4. A plurality of first wirings extending in the first direction, a plurality of second wirings extending in the second direction intersecting the first direction, and each intersection between the first wiring and the second wiring In a method for manufacturing a nonvolatile memory device, comprising: a nonvolatile memory cell array layer in which a plurality of nonvolatile memory cells are arranged so as to be sandwiched between positions;
On the substrate, a first wiring material layer serving as the first wiring and a memory layer constituting layer constituting the nonvolatile memory cell are sequentially laminated,
In the first wiring hookup region adjacent to the memory cell forming region and the first direction of the memory cell forming region by dry etching, the memory layer constituting layer and the first wiring material layer are etched, and the first wiring material layer is etched. A first pattern having a first line and space pattern extending in one direction is formed, and in a second wiring hookup region adjacent to the second direction of the memory cell formation region, the memory layer constituting layer and the first pattern 1 Wiring material layer is removed,
In the second wiring hookup region, the region removed by dry etching so that the memory cell formation region and the first wiring hookup region are embedded between the line patterns constituting the first line and space pattern. Next, an interlayer insulating film is formed,
Forming a second wiring material layer to be the second wiring on the interlayer insulating film and the memory layer constituting layer;
In the memory cell formation region and the second wiring hookup region, the second wiring material layer, the memory layer constituting layer, and the interlayer insulating film are processed by dry etching and extend in the second direction. Forming a second pattern having a second line and space pattern and a first dummy pattern connected to each line pattern such that the areas of the line patterns constituting the second line and space pattern are equal to each other. The method of manufacturing a nonvolatile memory device, wherein the second wiring material layer and the memory layer constituting layer are removed in the first wiring hookup region. A plurality of first wirings extending in the first direction, a plurality of second wirings extending in the second direction intersecting the first direction, and each intersection between the first wiring and the second wiring In a method for manufacturing a nonvolatile memory device, comprising: a nonvolatile memory cell array layer in which a plurality of nonvolatile memory cells are arranged so as to be sandwiched between positions;
On the substrate, a first wiring material layer serving as the first wiring and a first memory layer constituting layer constituting the nonvolatile memory cell are sequentially laminated,
In the first wiring hookup region adjacent to the memory cell forming region and the first direction of the memory cell forming region by dry etching, the first memory layer constituting layer and the first wiring material layer are etched, A first pattern having a first line and space pattern extending in the first direction is formed, and in the second wiring hookup region adjacent to the second direction of the memory cell formation region, the first memory layer configuration Removing the layer and the first wiring material layer;
In the second wiring hookup region, the region removed by dry etching so that the memory cell formation region and the first wiring hookup region are embedded between the line patterns constituting the first line and space pattern. Forming a first interlayer insulating film;
On the first interlayer insulating film and the first memory layer constituting layer, a second wiring material layer serving as the second wiring and a second memory layer constituting layer constituting a nonvolatile memory cell are sequentially laminated,
By dry etching, the second memory layer constituting layer, the second wiring material layer, the first memory layer constituting layer, and the first interlayer insulating film are formed in the memory cell forming region and the second wiring hookup region. The first line connected to each line pattern so that the areas of the second line and space pattern extending in the second direction and the line patterns constituting the second line and space pattern are equal to each other. A second pattern having a dummy pattern is formed, and in the first wiring hookup region, the second memory layer constituting layer, the second wiring material layer, the first memory layer constituting layer, and the first interlayer insulation are formed. A method for manufacturing a nonvolatile memory device, wherein the film is removed.

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