KR102085870B1 - Chip package - Google Patents

Abstract

The present invention relates to a chip package, the substrate; A semiconductor chip mounted on one surface of the substrate; And an organic coating layer formed on at least one of one surface of the substrate and the other surface of the substrate.

Description

Chip package {CHIP PACKAGE}

This embodiment relates to a chip package.

In today's semiconductor industry, the degree of integration of semiconductor chips is increasing, and the size of packages that house semiconductor chips and mount them in external systems is decreasing.

In response to the demand for reducing the package size, various packaging technologies have been developed.

A silicon chip, a light emitting diode (LED) or an IC chip is bonded onto the substrate through a wire bonding method or a flip chip bonding type.

In general, in the case of an IC chip package, a semiconductor chip is mounted on a cavity of an insulating layer of a substrate, and is electrically connected to a circuit pattern by a wire, wherein the semiconductor chip and the wire are a molding material such as a resin. Molded by.

However, in the conventional IC chip package, when the organic coating layer on the contact surface is formed, an organic coating layer is formed together on the bonding surface, and a semiconductor chip is mounted on the organic coating layer on the bonding surface, thereby improving adhesion. There is a problem that the IC chip is easily peeled off because of the lack.

The present embodiment has been made to solve the above-described problem, and when the organic coating layer on the contact surface of the chip package is formed, the organic coating layer formed together on the bonding surface by plasma treatment By removing, the peel strength of the semiconductor chip mounted on the chip package is further improved.

In addition, the present embodiment is to provide a chip package with high reliability, and to reduce manufacturing costs by minimizing defects in the manufacture of the chip package.

Chip package according to the present embodiment for solving the above problems, the substrate; A semiconductor chip mounted on one surface of the substrate; And an organic coating layer formed on at least one of one surface of the substrate and the other surface of the substrate.

According to another embodiment, the semiconductor chip may be mounted on one surface of the substrate from which the organic coating layer is removed by plasma treatment.

According to another embodiment, the peel strength between the semiconductor chip and the substrate may be formed to be 3 to 15 kg / cm by the plasma treatment.

According to another embodiment, the semiconductor chip may be an IC chip.

According to another embodiment, the semiconductor chip may further include a conductive adhesive layer attached to one surface of the substrate.

According to another embodiment, the conductive adhesive layer may include an epoxy resin and a metal material.

According to another embodiment, the substrate comprises a metal layer; And a plating layer formed on one surface of the metal layer and the other surface opposite to the one surface.

According to another embodiment, the metal layer may be made of copper (Cu), and the plating layer may be made of gold (Au).

According to another embodiment, the semiconductor device may further include an insulating layer formed on one surface of the substrate, and the semiconductor chip may be mounted in a cavity formed in the insulating layer.

According to another embodiment, the insulating layer may be composed of a prepreg containing a glass fiber and a resin.

According to the present embodiment, when the organic coating layer is formed on the contact surface of the chip package, the semiconductor coating layer formed on the bonding surface is removed by plasma treatment to remove the organic coating layer formed on the bonding surface. It is possible to further improve the peel strength of the chip.

In addition, according to the present embodiment, it is possible to provide a more reliable chip package, and to minimize manufacturing defects in manufacturing the chip package, thereby reducing manufacturing cost.

1 is a cross-sectional view of a chip package according to an embodiment of the present invention.
2 and 3 are diagrams illustrating a chip package according to an embodiment of the present invention.
4 is a view for explaining a plasma treatment according to an embodiment of the present invention.
5 and 6 are views for explaining the difference in flowability of the conductive adhesive layer with or without plasma treatment according to an embodiment of the present invention.
7 is a view for explaining a method of manufacturing a chip package according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention. However, in describing the embodiments, when it is determined that detailed descriptions of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. In addition, the size of each component in the drawings may be exaggerated for description, it does not mean the size that is actually applied.

1 is a cross-sectional view of a chip package according to an embodiment of the present invention.

As shown in FIG. 1, a chip package according to an exemplary embodiment of the present invention includes a substrate 110, a semiconductor chip 120, and an organic coating layer 130.

In addition, the substrate 110 includes a metal layer 111 and plating layers 112 and 113.

The semiconductor chip 120 is mounted on one surface of the substrate 110. In this case, the semiconductor chip 120 may be an IC (Intergrated Circuit) chip.

In more detail, plating layers 112 and 113 are formed on one surface of the metal layer 111 and the other surface facing the one surface, and the adhesive layer 140 is formed on the first plating layer 112 formed on one surface of the metal layer 111. The insulating layer 150 attached by the () is formed. In addition, a cavity 125 is formed in the insulating layer 150 so that the semiconductor chip 120 is mounted in the cavity 125.

In this case, the metal layer may be made of copper (Cu), the plating layer may be made of gold (Au), and the insulating layer 150 may be made of prepreg including glass fiber and resin. .

The organic coating layer 130 may be formed on at least one of one surface of the substrate 110 and the other surface opposite to the one surface. That is, the organic coating layer 130 may be formed on the first plating layer 112 and the second plating layer 113 of the substrate 110.

The organic coating layer 130 formed on the first plating layer 112 is removed by a plasma treatment.

As described above, the semiconductor chip 120 is mounted on the first plating layer 112 from which the organic coating layer 130 is removed by plasma treatment.

When the plasma treatment is performed on the first plating layer 112, the adhesion between the top surface of the first plating layer 112 and the semiconductor chip 120 is increased, so that the peeling between the top surface of the first plating layer 112 and the semiconductor chip 120 is increased. Peel strength rises.

At this time, a peeling strength of 3 to 15 kg / cm may be formed between the upper surface of the first plating layer 112 and the semiconductor chip 120, and the maximum between the first plating layer 112 and the semiconductor chip 120 by the plasma treatment. It can be configured to have a peel strength of 15 kg / cm, the separation strength of the first plating layer 112 and the semiconductor chip 120 does not occur when the peel strength of at least 3 kg / cm as described above to attract.

Meanwhile, the conductive adhesive layer 121 may be used to mount the semiconductor chip 120 on the first plating layer 112.

In more detail, the semiconductor chip 120 may be attached onto the first plating layer 112 by a conductive adhesive layer 121, and the conductive adhesive layer 120 may be an epoxy resin and a metal material. It may be configured to include. In this case, silver (Ag) may be used as the metal material.

That is, the conductive adhesive layer 121 is formed on the first plating layer 112 from which the organic coating layer 130 is removed by the plasma treatment, and the semiconductor chip 120 is formed by the conductive adhesive layer 121. It may be attached on the plating layer 112.

2 and 3 are diagrams illustrating a chip package according to an embodiment of the present invention.

2 illustrates a bottom surface of the chip package illustrated in FIG. 1, and FIG. 3 illustrates a top surface of the chip package illustrated in FIG. 1.

More specifically, FIG. 2 illustrates a contact surface of a chip package, and FIG. 3 illustrates a bonding surface of the chip package.

As illustrated in FIG. 3, a chip package includes a cavity 125 and a bonding hole 126, and a semiconductor chip may be mounted on the cavity 125.

According to an embodiment of the present invention, in order to improve peel strength when the semiconductor chip is mounted, a plasma process is performed on a substrate on which the semiconductor chip is mounted.

4 is a view for explaining a plasma treatment according to an embodiment of the present invention.

Referring to FIG. 4, a plasma process is performed by ionizing a plasma gas to form a plasma composed of electrons, neutrons, and both, and exposing the ionized plasma to the substrate 110.

The plasma includes hydrogen, oxygen, and argon plasma, and according to an embodiment of the present invention, the substrate may be plasma treated using argon gas.

Referring to FIG. 4, when the substrate 110 is exposed to the hydrogen plasma 210 or the oxygen plasma 220, the hydrogen plasma 210 or the oxygen plasma 220 is present on the substrate 110. carbon bonded to hydrogen or to out off as H20 or CO _2. As a result, the roughness of the substrate 110 is not increased.

However, when the argon plasma 230 is exposed to the substrate 110, the argon plasma 230 adheres to the surface on the substrate while being bonded to the carbon present on the substrate 110, thereby providing the Increase the roughness.

Accordingly, the peel strength between the semiconductor chip and the substrate 110 is increased.

Table 1 below shows the peel strength according to the plasma treatment strength.

plasma  Processing strength PLASMA POWER ) Peel strength ( Peel Strength ) ( kgf Of cm ) No plasma 0.02 2500 W 1.23 3000 W 1.07 3500 W 1.51 4000 W 1.98

As shown in Table 1, the larger the plasma treatment strength, the higher the peeling strength.

5 and 6 are views for explaining the flowability difference of the conductive adhesive layer with or without plasma treatment according to an embodiment of the present invention.

In more detail, FIGS. 5 and 6 illustrate embodiments in which the conductive adhesive layer 121 is formed on a substrate in the cavity 125.

That is, FIG. 5 illustrates an embodiment in which the conductive adhesive layer 121 is formed on the substrate in the cavity 125 without a separate plasma treatment in order to mount the semiconductor chip in the cavity 125. FIG. 6 illustrates the inside of the cavity 125. In order to mount the semiconductor chip, the conductive adhesive layer 121 is formed after the plasma treatment is performed on the substrate in the cavity 125.

In the embodiment of FIG. 5, the substrate having no plasma treatment has a low flowability of the conductive adhesive layer 121 formed because the conductive material is coated on the organic coating layer, but the plasma treatment is performed as in the embodiment of FIG. 6. Since the ground organic coating layer is removed, the flowability of the conductive adhesive layer 121 formed on the substrate is excellent.

As described above, when the semiconductor chip is bonded onto the substrate using the conductive adhesive layer 121 having excellent flowability by plasma treatment, the peeling strength between the semiconductor chip and the substrate can be greatly improved.

7 is a view for explaining a method of manufacturing a chip package according to an embodiment of the present invention.

As shown in FIG. 7, water masking is performed on the cavity of the chip package (S510), and an organic coating is performed on the contact surface of the chip package (S520).

Thereafter, the chip package is water cleaned (S530), and a bonding surface, which is an upper surface of the chip package, is plasma treated (S540).

As such, when the bonding surface of the chip package is plasma treated, an organic coating partially formed on the bonding surface may be removed during the organic coating on the contact surface.

Thereafter, the plasma-treated chip package may be dried (S550), and the chip package may be configured by mounting a semiconductor chip on the chip package.

As described above, according to the present embodiment, when the organic coating layer on the contact surface of the chip package is formed, the organic coating layer formed together on the bonding surface is removed by plasma treatment, thereby providing the chip. The peel strength of the semiconductor chip mounted on the package may be further improved.

In addition, according to the present embodiment, it is possible to provide a chip package with high reliability, and to minimize manufacturing defects in manufacturing the chip package, thereby reducing manufacturing cost.

In the detailed description of the invention as described above, specific embodiments have been described. However, many modifications are possible without departing from the scope of the invention. The technical spirit of the present invention should not be limited to the above-described embodiments of the present invention, but should be determined not only by the claims, but also by those equivalent to the claims.

110: substrate
111: metal layer
112 and 113: plating layers
120: semiconductor chip
121: conductive adhesive layer
125: cavity
126: bonding hole
130: organic coating layer
140: adhesive layer
150: insulation layer

Claims (10)

A substrate including a metal layer, a first plating layer disposed on an upper surface of the metal layer, and a second plating layer disposed on a lower surface of the metal layer;
A first organic coating layer disposed on a bottom surface of the second plating layer of the substrate;
An insulating layer disposed on an upper surface of the first plating layer of the substrate and including a cavity;
A conductive adhesive layer disposed on an upper surface of the first plating layer exposed through the cavity of the insulating layer; And
A semiconductor chip disposed on an upper surface of the conductive adhesive layer,
The semiconductor chip,
The second organic coating layer disposed on the upper surface of the first plating layer by argon plasma treatment is disposed on the upper surface of the first plating layer is removed,
The upper surface of the first plating layer corresponding to the upper surface of the substrate,
Through the argon plasma treatment has a roughness due to the combination of carbon and argon,
The conductive adhesive layer,
And a chip package disposed on an upper surface of the argon plasma treated first plating layer in the cavity. delete The method according to claim 1,
The chip package is formed by the argon plasma treatment, the peel strength between the semiconductor chip and the substrate is 3 to 15 kg / cm. The method according to claim 1,
The semiconductor chip,
Chip package, which is an IC chip. delete The method according to claim 1,
The conductive adhesive layer,
Chip package containing epoxy resin and metal material. delete The method according to claim 1,
The metal layer is made of copper (Cu), the first and second plating layer is a chip package consisting of gold (Au). The method according to claim 1,
A chip package disposed on an upper surface of the metal layer, the chip package including an adhesive layer in contact with the insulating layer. The method according to claim 1,
The insulating layer,
Chip package consisting of prepreg containing glass fiber and resin.

Images