KR102059148B1 - Three dimensional flash memory including buried type middle line and manufacturing method thereof - Google Patents

Abstract

Disclosed are a three-dimensional flash memory including a buried type middle wiring layer and a manufacturing method thereof. According to one embodiment, a three-dimensional flash memory including a buried type middle wiring layer includes a string including a channel layer extended in one direction; a channel connection part connecting an upper channel layer and a lower channel layer to each other in the middle region of the string; a middle wiring layer selectively usable as any one of a source electrode and a drain electrode for the string; and a wiring connection part connecting the channel connection part and the middle wiring layer to each other while at least a portion of the wiring connection part is embedded in the string. It is possible to improve integration and simplify a wiring process.

Description

Three-dimensional flash memory including a buried intermediate wiring layer and a manufacturing method thereof {THREE DIMENSIONAL FLASH MEMORY INCLUDING BURIED TYPE MIDDLE LINE AND MANUFACTURING METHOD THEREOF}

The following embodiments relate to a three-dimensional flash memory and a method of manufacturing the same, and more particularly, to a three-dimensional flash memory including a buried intermediate wiring layer and a method of manufacturing the same.

Flash memory devices are electrically erasable programmable read only memory (EEPROM), for example, a computer, a digital camera, an MP3 player, a game system, a memory stick. ) May be commonly used. Such a flash memory device electrically controls input / output of data by F-N tunneling (Fowler-Nordheimtunneling) or hot electron injection.

Specifically, referring to FIG. 1, which illustrates an existing array of three-dimensional flash memory, the array of three-dimensional flash memory includes a common source line CSL, a bit line BL, and a common source line CSL and a bit line BL. ) May include a plurality of cell strings CSTR.

The bit lines are arranged two-dimensionally, and a plurality of cell strings CSTR are connected in parallel to each other. The cell strings CSTR may be commonly connected to the common source line CSL. That is, the plurality of cell strings CSTR may be disposed between the plurality of bit lines and one common source line CSL. In this case, the common source lines CSL may be plural, and the plurality of common source lines CSL may be two-dimensionally arranged. Here, the same voltage may be applied to the plurality of common source lines CSL, or each of the plurality of common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground select transistor GST connected to a common source line CSL, a string select transistor SST connected to a bit line BL, and ground and string select transistors GST and SST. ) May be composed of a plurality of memory cell transistors MCT. In addition, the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be connected in common to the sources of the ground select transistors GST. In addition, the ground select line GSL, the plurality of word lines WL0-WL3 and the plurality of string select lines SSL, which are disposed between the common source line CSL and the bit line BL, select the ground. It may be used as electrode layers of the transistor GST, the memory cell transistors MCT, and the string select transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a memory element.

On the other hand, the conventional three-dimensional flash memory is increasing the density by stacking the cells vertically, in order to meet the high performance and low price required by the consumer.

For example, referring to FIG. 2, which illustrates the structure of a conventional three-dimensional flash memory, in the conventional three-dimensional flash memory, interlayer insulating layers 211 and horizontal structures 250 alternately on a substrate 200. A repeatedly formed electrode structure 215 is disposed and manufactured. The interlayer insulating layers 211 and the horizontal structures 250 may extend in the first direction. For example, the interlayer insulating layers 211 may be silicon oxide layers, and the lowermost interlayer insulating layers 211a of the interlayer insulating layers 211 may have a thickness thinner than the remaining interlayer insulating layers 211. Each of the horizontal structures 250 may include first and second blocking insulating layers 242 and 243 and an electrode layer 245. The electrode structures 215 may be provided in plural, and the plurality of electrode structures 215 may be disposed to face each other in a second direction crossing the first direction. The first and second directions may correspond to the x and y axes of FIG. 2, respectively. Trenchs 240 spaced apart from the plurality of electrode structures 215 may extend in the first direction. Highly doped impurity regions may be formed in the substrate 200 exposed by the trenches 240 so that the common source line CSL may be disposed. Although not shown, isolation insulating layers may be further disposed to fill the trenches 240.

Vertical structures 230 penetrating the electrode structure 215 may be disposed. In one example, the vertical structures 230 may be arranged in a matrix form, aligned in the first and second directions, in a plan view. As another example, the vertical structures 230 may be aligned in a second direction, but may be disposed in a zigzag shape in the first direction. Each of the vertical structures 230 may include a passivation layer 224, a charge storage layer 225, a tunnel insulation layer 226, and a channel layer 227. For example, the channel layer 227 may be disposed in a hollow tubular shape therein, and in this case, a buried film 228 may be further disposed to fill the inside of the channel layer 227. A drain region D is disposed on the channel layer 227, and a conductive pattern 229 is formed on the drain region D to be connected to the bit line BL. The bit line BL may extend in a direction crossing the horizontal electrodes 250, for example, in a second direction. For example, the vertical structures 230 aligned in the second direction may be connected to one bit line BL.

The first and second blocking insulating layers 242 and 243 included in the horizontal structures 250 and the charge storage layer 225 and the tunnel insulating layer 226 included in the vertical structures 230 are formed of a 3D flash memory. The information storage element may be defined as an oxide-nitride-oxide (ONO) layer. That is, some of the information storage elements may be included in the vertical structures 230, and some of the information storage elements may be included in the horizontal structures 250. In one example, the charge storage layer 225 and the tunnel insulating layer 226 of the information storage element are included in the vertical structures 230, and the first and second blocking insulating layers 242 and 243 are the horizontal structures 250. Can be included.

The epitaxial patterns 222 may be disposed between the substrate 200 and the vertical structures 230. The epitaxial patterns 222 connect the substrate 200 and the vertical structures 230. The epitaxial patterns 222 may be in contact with at least one layer of horizontal structures 250. That is, the epitaxial patterns 222 may be disposed to contact the lowermost horizontal structure 250a. According to another embodiment, the epitaxial patterns 222 may be disposed to contact the horizontal structures 250 of a plurality of layers, for example, two layers. Meanwhile, when the epitaxial patterns 222 are disposed to contact the lowermost horizontal structure 250a, the lowermost horizontal structure 250a may be thicker than the remaining horizontal structures 250. The lowermost horizontal structure 250a in contact with the epitaxial patterns 222 may correspond to the ground selection line GSL of the array of the three-dimensional flash memory described with reference to FIG. 1, and the vertical structures 230 The remaining horizontal structures 250 may correspond to the plurality of word lines WL0-WL3.

Each of the epitaxial patterns 222 has a recessed sidewall 222a. Accordingly, the bottommost horizontal structure 250a abutting the epitaxial patterns 222 is disposed along the profile of the recessed sidewall 222a. That is, the lowermost horizontal structure 250a may be disposed in a convex shape along the recessed sidewall 222a of the epitaxial patterns 222.

In the conventional three-dimensional flash memory having such a structure, as the number of vertically stacked stages increases, the length of the channel layer 227 increases, which causes a decrease in cell current and deterioration of cell characteristics.

Accordingly, in order to increase the cell current which decreases as the length of the channel layer increases in the 3D flash memory and to improve the cell characteristic deterioration due to the decrease in the cell current, at least one intermediate wiring layer is disposed in the middle region of the string. Was proposed.

However, the three-dimensional flash memory having a structure in which at least one intermediate wiring layer is disposed is based on the bulk of the substrate 200 because the channel layer in the string is divided into an upper channel layer and a lower channel layer by the at least one intermediate wiring layer. The erase operation is difficult to apply.

Therefore, a structure including an intermediate wiring layer disposed in the middle region of the string needs to be proposed to increase the cell current that decreases as the length of the channel layer increases, and to improve the cell characteristic deterioration according to the decrease in the cell current.

In addition, when the intermediate wiring layer is simply formed in the same shape as the existing bit line, the complexity of the wiring process may be increased and the density may be degraded. Therefore, the intermediate wiring layer may be manufactured at the same time as a simple wiring process. The structure needs to be proposed.

One embodiment includes an intermediate wiring layer that can be selectively used as either a source electrode or a drain electrode between adjacent strings, and at the same time includes a channel connection connecting the upper channel layer and the lower channel layer to each other in the string layer. 3D flash increases cell length that decreases with longer length, improves cell characteristics deterioration with reduced cell current, supports bulk-based bulk erase operations, improves integration, and simplifies wiring processes A memory device and a method of manufacturing the same are proposed.

According to one embodiment, a three-dimensional flash memory, the string including a channel layer extending in one direction; A channel connector connecting the upper channel layer and the lower channel layer to each other in the middle region of the string; An intermediate wiring layer selectively usable as any one of a source electrode and a drain electrode for the string; And a wire connection part connecting the channel connection part and the intermediate wiring layer to each other while at least a portion of the string is embedded in the string.

According to one side, the wire connection portion, is formed of an N + type material, the channel connection portion, may be formed of any one of a metal material or N- type material.

According to the other side, the three-dimensional flash memory is fabricated on a substrate comprising a P-type bulk and N + contacts, the channel connecting portion is connected to the upper channel layer and lower channel layer of the string by the bulk Therefore, the bulk erase operation can be supported.

According to another aspect, the intermediate wiring layer may be located in a space between the string and a neighboring string adjacent to the string.

According to another aspect, the intermediate wiring layer may be shared by the string and a neighboring string adjacent to the string.

According to an embodiment, a method of manufacturing a 3D flash memory may include: generating a lower channel layer; Forming a wire connection in a portion of an upper region of the lower channel layer; Generating an insulating layer to cover the wiring connection portion; Etching a portion of the insulating layer corresponding to a portion of the upper region of the lower channel layer except for an area in which the wiring connection portion is formed and a portion of the insulating layer corresponding to a portion of the upper region of the wiring connection portion; Forming an intermediate wiring layer in a space in which a portion of the insulating layer corresponding to a portion of an upper region of the wiring connection part is etched; Forming a channel connection part in a space in which an area corresponding to the remaining area except the area where the wiring connection part is formed in the upper area of the lower channel layer is etched in the insulating layer; And generating an upper channel layer on the channel connection part, wherein the intermediate wiring layer is selectively used as one of a source electrode and a drain electrode for a string including the upper channel layer and the lower channel layer. Do.

According to one side, the forming of the wiring connection portion, may include forming the wiring connection portion in the space between the adjacent string adjacent to the string and the string.

According to another side, the intermediate wiring layer may be shared by the string and a neighboring string adjacent to the string.

According to yet another aspect, the forming of the wire connection part may include forming the wire connection part with an N + type material, and the forming of the channel connection part may include at least one of a metal material and an N-type material. Forming a channel connection.

According to one embodiment, a three-dimensional flash memory, a plurality of strings each including a channel layer extending in one direction; A channel connector connecting the upper channel layer and the lower channel layer of each of the plurality of strings to each other in an intermediate region of each of the plurality of strings; An intermediate wiring layer shared by strings adjacent in a diagonal direction or a horizontal direction among the plurality of strings, and selectively usable by any one of a source electrode and a drain electrode for each of the strings adjacent in the diagonal direction or the horizontal direction; And a wire connection part connecting the channel connection part and the intermediate wiring layer of each of the strings adjacent to each other in the diagonal or horizontal direction while at least partially embedded in each of the strings adjacent to the diagonal or horizontal direction.

According to one side, the wiring connection of each of the adjacent strings in the diagonal or horizontal direction, is formed of an N + type material, the channel connection of each of the plurality of strings, is formed of any one of a metal material or N- type material Can be.

According to the other side, the three-dimensional flash memory is fabricated on a substrate comprising a P-type bulk and N + contacts, the upper channel layer of each of the plurality of strings by a channel connection of each of the plurality of strings As the lower channel layer is connected to the bulk, a bulk erase operation may be supported.

According to another side, the intermediate wiring layer may be located in the space between the adjacent strings in the diagonal or horizontal direction.

One embodiment includes an intermediate wiring layer that can be selectively used as either a source electrode or a drain electrode between adjacent strings, and at the same time includes a channel connection connecting the upper channel layer and the lower channel layer to each other in the string layer. 3D flash increases cell length that decreases with longer length, improves cell characteristics deterioration with reduced cell current, supports bulk-based bulk erase operations, improves integration, and simplifies wiring processes A memory device and a method of manufacturing the same can be proposed.

1 is a simplified circuit diagram showing an array of conventional three-dimensional flash memory.
2 is a perspective view showing the structure of a conventional three-dimensional flash memory.
3 is a top view illustrating a 3D flash memory according to an exemplary embodiment.
FIG. 4 is a cross-sectional view based on the X axis of the 3D flash memory shown in FIG. 3.
FIG. 5 is a cross-sectional view of the three-dimensional flash memory shown in FIG. 3 based on the Y axis.
FIG. 6 is a cross-sectional view of another example of the three-dimensional flash memory illustrated in FIG. 3.
FIG. 7 is a cross-sectional view of another embodiment of the three-dimensional flash memory illustrated in FIG. 3.
8 is a flowchart illustrating a method of manufacturing a 3D flash memory, according to an exemplary embodiment.
9 to 11 are cross-sectional views illustrating a method of manufacturing a 3D flash memory according to an embodiment.
15 to 20 are diagrams for describing a method of manufacturing a 3D flash memory, according to another exemplary embodiment.
21 to 28 are diagrams for describing a method of manufacturing a 3D flash memory, according to another exemplary embodiment.
29 is a top view illustrating a 3D flash memory according to another exemplary embodiment.
FIG. 30 is a cross-sectional view based on the X axis of the 3D flash memory shown in FIG. 29.
FIG. 31 is a cross-sectional view illustrating another example of the 3D flash memory of FIG. 29.
32 is a cross-sectional view of still another embodiment of the 3D flash memory of FIG. 29.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. Also, like reference numerals in the drawings denote like elements.

Also, the terminology used herein is a term used to properly express a preferred embodiment of the present invention, which may vary depending on a user, an operator's intention, or customs in the field to which the present invention belongs. Therefore, the definitions of the terms should be made based on the contents throughout the specification.

3 is a top view illustrating a 3D flash memory according to an exemplary embodiment, FIG. 4 is a cross-sectional view based on an X axis in the 3D flash memory illustrated in FIG. 3, and FIG. 5 is a 3D flash illustrated in FIG. 3. This is a cross section based on the Y axis in memory. More specifically, FIG. 3 is a top view illustrating a cross section in a horizontal direction with respect to an intermediate region in a vertical direction of a string in a 3D flash memory.

3 to 5, the 3D flash memory 300 according to an exemplary embodiment may include a string 310, a channel connector 320, an intermediate wiring layer 330, and a wiring connector 340 extending in one direction. Include.

The string 310 is described and illustrated as including the channel layers 311 and 312 extending in one direction, but the present invention is not limited thereto, and the string 310 may be provided with respect to the channel layers 311 and 312 in addition to the channel layers 311 and 312. It may include a plurality of electrode layers (not shown) stacked vertically and a plurality of insulating layers (not shown) disposed between the plurality of electrode layers.

The channel connector 320 connects the upper channel layer 311 and the lower channel layer 312 of the string 310 to each other in the middle region of the string 310. For example, the channel connector 320 may be formed of an N-type material (eg, N-type polysilicon) through an N-type ion implantation process similarly to the channel layers 311 and 312. However, the present invention is not limited thereto and may be formed of a metal material. Detailed description thereof will be described with reference to FIG. 6. As such, as the channel connector 320 connects the upper channel layer 311 and the lower channel layer 312 of the string 310 to each other in the middle region of the string 310, the upper channel layer 311 and the lower channel. All of the layers 312 are connected with a substrate including P-type bulk and N + contacts, thereby allowing bulk based erase operations to be performed.

The intermediate wiring layer 330 may be a metal material (eg, W (tungsten), Ti (titanium), Ta (tantalum), Au (copper) to be selectively used as either a source electrode or a drain electrode for the string 310. Or Au (gold). In more detail, when the upper wiring layer (not shown) included in the 3D flash memory 300 is used as the source electrode, the intermediate wiring layer 330 which is closest to each other with the upper wiring layer interposed therebetween with the memory cell to be controlled. ) May be used as the drain electrode, and when the upper wiring layer is used as the drain electrode, the closest adjacent intermediate wiring layer 330 may be used as the source electrode while sandwiching the memory cell to be controlled together with the upper wiring layer. Hereinafter, the memory cell refers to a charge storage layer, which is an information storage element, and an electrode layer in direct contact with the charge storage layer in the 3D flash memory 300.

Here, the intermediate wiring layer 330 may be implemented in plurality. For example, when the intermediate wiring layer 330 is implemented in plural numbers, such as the first intermediate wiring layer, the second intermediate wiring layer, and the third intermediate wiring layer (vertical in the order of the first intermediate wiring layer, the second intermediate wiring layer, and the third intermediate wiring layer). Direction), as the first intermediate wiring layer is used as the drain electrode, the second intermediate wiring layer closest adjacent to the memory cell to be controlled together with the first intermediate wiring layer can be used as the source electrode. In addition, as the third intermediate interconnection layer is used as the source electrode, the second intermediate interconnection layer closest to the memory cell to be controlled together with the third intermediate interconnection layer may be used as the drain electrode. That is, the intermediate wiring layer 330 is adaptive to one other electrode except for one of the electrodes used in response to the use of one of the source electrode and the drain electrode, which is another adjacent wiring layer between the memory cells to be controlled. Can be used as Hereinafter, when one wiring layer is used as a drain electrode and a source electrode in some cases, it means that the wiring layer is formed to be reconfigurable to be adaptively used as either the source electrode or the drain electrode. Thus, the intermediate wiring layer 330 may be formed to be reconfigurable.

In particular, since the intermediate wiring layer 330 is located in the space between the strings, the 3D flash memory 300 can be integrated and downsized. For example, the intermediate wiring layer 330 is located in the space between the first string 310 and the second string 350, which is a neighboring string adjacent to the first string 310, and thus, between the strings 310 and 350. Can be shared. In this case, the strings 310 and 350 sharing the intermediate wiring layer 330 may be adjacent strings 310 and 350 in diagonal directions among the plurality of strings included in the 3D flash memory 300.

Hereinafter, the intermediate wiring layer 330 is shared between the strings 310 and 350, wherein the intermediate wiring layer 330 is selectively used as either the source electrode or the drain electrode for the first string 310. This means that the two strings 350 are selectively used as either the source electrode or the drain electrode. For this purpose, the intermediate wiring layer 330 may be connected to the channel connection part 320 of the first string 310 and also to the channel connection part (not shown) of the second string 350.

The wire connection part 340 connects the channel connection part 320 and the intermediate wiring layer 330 to each other while at least a portion of the wire connection part 340 is buried in the string 310. For example, the wire connection part 340 may be formed to be at least partially embedded in the string 310 with an N + type material (eg, N + type polysilicon) through an N + type ion implantation process.

Although the structure of the 3D flash memory 300 has been described with reference to one string 310, the structure of the 3D flash memory 300 is not limited thereto, and the 3D flash memory 300 according to an embodiment may include the intermediate wiring layer 330. It may have a structure based on the plurality of strings (310, 350) to share. In this case, the 3D flash memory 300 may include the strings 310 and 350 diagonally adjacent to each other, and the upper channel layer 311 and the lower channel, respectively, in the diagonally adjacent strings 310 and 350. The channel connection 320 connecting the layers 312 to each other, shared by the diagonally adjacent strings 310 and 350, of the source electrode or the drain electrode for each of the diagonally adjacent strings 310 and 350. The channel connection part 320 of each of the intermediate wiring layers 330 and the diagonally adjacent strings 310 and 350 that are selectively used as one, and the strings 310 and 350 of the diagonally adjacent strings 310 and 350, respectively. It may be described as a structure including a wiring connection part 340 connecting the intermediate wiring layer 330 to each other. If the strings sharing the intermediate wiring layer 330 are horizontally adjacent strings instead of diagonally adjacent strings 310 and 350, the 3D flash memory 300 may be configured based on adjacent strings in the horizontal direction. It may have a structure to. Detailed description thereof will be described with reference to FIGS. 29 to 32.

As such, the 3D flash memory 300 according to an exemplary embodiment may include an intermediate wiring layer 330 that may be selectively used as one of a source electrode and a drain electrode between adjacent strings 310 and 350. By including the channel connection part 320 connecting the upper channel layer 311 and the lower channel layer 312 to each other in the 310 and 350, the cell current decreased as the length of the channel layer 311 and 312 is increased. It is possible to achieve the effect of reducing the cell current due to the decrease of the cell current, to support the bulk erase operation based on the bulk of the substrate, to improve the degree of integration, and to simplify the wiring process.

FIG. 6 is a cross-sectional view of another example of the three-dimensional flash memory illustrated in FIG. 3.

Referring to FIG. 6, the 3D flash memory 600 according to another embodiment has the same structure as the 3D flash memory 300 described above with reference to FIGS. 3 to 5, but the channel connector 610 is formed of a metallic material. There is a difference in that it is formed as. In more detail, the channel connector 610 included in the 3D flash memory 600 according to another embodiment may be formed of the same metal material as the intermediate wiring layer 620 (eg, W (tungsten), Ti (titanium), and Ta). (Tantalum), Au (copper), or Au (gold).

As described above, the 3D flash memory 600 according to another embodiment, which has been manufactured, may have only a difference between materials constituting the 3D flash memory 300 and the channel connection unit 610 according to an embodiment. In this case, the number of mask-based etching processes may be different. For example, in the 3D flash memory 300 according to the exemplary embodiment described above with reference to FIG. 3, since the intermediate wiring layer 330 and the channel connecting portion 320 are made of different materials, the wiring connecting portion 340 is formed. While the first mask process for forming a second mask process, the second mask process for forming the intermediate wiring layer 330, the third mask process for forming the channel connecting portion 320 are manufactured through a total of three mask-based etching process, In the 3D flash memory 600 according to another exemplary embodiment, since the intermediate interconnection layer 330 and the channel interconnection 320 are made of the same material, the 3D flash memory 600 may include a first mask process for forming the interconnection interconnection 630 and an intermediate interconnection layer ( 620 and the channel connection 610 may be manufactured through a total of two mask-based etching processes of the second mask process. However, the present disclosure is not limited thereto, and the three-dimensional flash memory 300 according to an embodiment and the three-dimensional flash memory 600 according to another embodiment may be manufactured through various processes that may implement the above-described structures. . Detailed description of the manufacturing method will be described with reference to FIGS. 8 to 11.

In addition, the three-dimensional flash memory 300 according to an embodiment and the three-dimensional flash memory 600 according to another embodiment, in addition to the above-described structures, the intermediate wiring layers 330 and 620 and the wiring connecting portions 340 and 630. It may be implemented in a structure including an additional connection (not shown) connecting the. Detailed description thereof will be described with reference to FIG. 7.

FIG. 7 is a cross-sectional view of another embodiment of the three-dimensional flash memory illustrated in FIG. 3.

Referring to FIG. 7, the 3D flash memory 700 according to another embodiment has the same structure as the 3D flash memory 300 described above with reference to FIGS. 3 to 5, but further includes an additional connector 710. There is a difference in that it includes. Specifically, the additional connection part 710 is an additional component connecting the intermediate wiring layer 720 and the wiring connection part 730, and unlike the intermediate wiring layer 720 extending in the Y-axis direction illustrated in FIG. 3, the wiring connection part 730. It may be a component that does not extend in the Y-axis direction as shown. Thus, the structure including the additional connector 710 may be used when the structure in which the intermediate wiring layer 720 and the wiring connector 730 directly contact each other is difficult to be applied.

In the drawing, although the 3D flash memory 700 according to another embodiment includes a channel connector 740 formed of an N-type material, the channel connector 740 is not limited thereto. Even in the case of a material, a structure including the additional connection part 710 may be applied.

As described, the three-dimensional flash memory 700 according to another embodiment, which is manufactured as described above, may be added differently from the three-dimensional flash memory 300 according to an embodiment and the three-dimensional flash memory 600 according to another embodiment. Only the difference of further including the connector 710, but in terms of manufacturing process may have a difference in the number of mask-based etching process. For example, as described above with reference to FIG. 6, a three-dimensional flash memory 300 according to one embodiment is manufactured through a total of three mask-based etching processes, and a three-dimensional flash memory 700 according to another embodiment. Is manufactured through a total of two mask-based etching processes, the three-dimensional flash memory 700 according to another embodiment forms a first mask process for forming the wiring connection portion 730, the additional connection portion 710 The second mask process, the third mask process for forming the intermediate wiring layer 720, and the fourth mask process for forming the channel connector 740 may be manufactured through a total of four mask-based etching processes.

8 is a flowchart illustrating a method of manufacturing a 3D flash memory, according to an embodiment. FIGS. 9 through 14 are cross-sectional views illustrating a method of manufacturing a 3D flash memory, according to an exemplary embodiment. 21 is a diagram for describing a method of manufacturing a 3D flash memory, and FIGS. 21 through 28 are diagrams for describing a method of manufacturing a 3D flash memory, according to another exemplary embodiment.

Hereinafter, the manufacturing method of the three-dimensional flash memory described with reference to FIGS. 8 to 28 is assumed to be performed by an automated and mechanized manufacturing system, and the three-dimensional flash memory 300 described above with reference to FIGS. A method of manufacturing the 3D flash memory 600 described above with reference to FIG. 6 and the 3D flash memory 700 described above with reference to FIG. 7.

9 to 28 are cross-sectional views cut along the X-axis direction of the strings 310 and 360 shown in FIG. 3 to explain a method of manufacturing a 3D flash memory. Thus, the manufacturing method to be described later, the manufacturing method of the three-dimensional flash memory based on the string 310 shown in FIG. 3 will be described, the manufacturing method described below also referred to as a three-dimensional flash memory string 350 The same can be prepared by.

First, the manufacturing system generates the lower channel layers 910, 1510, and 2110 in step S810. For example, the fabrication system can form the lower channel layers 910, 1510, 2110 with N-type materials as shown in FIGS. 9, 15, and 21. In this case, the lower channel layers 910, 1510, and 2110 may be implemented in the form of hollow tubes, and in this case, the buried films 911, 1511, and 2111 that fill the inside of the lower channel layers 910, 1510, and 2110. ) And side walls 912, 1512, and 2112 surrounding the outside of the lower channel layers 910, 1510, and 2110 may be further disposed.

Subsequently, in operation S820, the manufacturing system forms the wire connection portions 920, 1520, and 2120 in some of the upper regions of the lower channel layers 910, 1510, and 2110. For example, the manufacturing system may include some regions of the upper region of the lower channel layers 910, 1510, and 2110 with an N + type material (eg, N + type polysilicon) through an N + type ion implantation process as shown in FIGS. 10, 16, and 22. And wiring connections 920, 1520, and 2120 may be formed over a space between the strings. As a more specific example, the fabrication system may form the wiring connectors 920, 1520, and 2120 to partially cover a portion of the upper regions of the lower channel layers 910, 1510, and 2110 using a mask process.

Next, the manufacturing system generates the insulating layers 930, 1530, and 2130 to cover the wiring connectors 920, 1520, and 2120 in step S830. For example, the fabrication system may generate the insulating layers 930, 1530, and 2130 from an insulating material as shown in FIGS. 11, 17, and 23. In this case, the insulating layers 930, 1530, and 2130 may be formed of the same material as the interlayer insulating layer (not shown) disposed between the plurality of electrode layers (not shown) included in the string.

Next, in operation S840, the manufacturing system may include the remaining portions of the upper layers of the lower channel layers 910, 1510, and 2110 in the insulating layers 930, 1530, and 2130 except for the areas where the wiring connectors 920, 1520, and 2120 are formed. The portion corresponding to the region and the portion corresponding to the portion of the upper region of the wiring connection portions 920, 1520, and 2120 in the insulating layers 930, 1530, and 2130 are etched.

Next, in step S850, the manufacturing system includes spaces 931, 1531, and 2131 in which portions corresponding to some of the upper regions of the wiring connections 920, 1520, and 2120 in the insulating layers 930, 1530, and 2130 are etched. ), Intermediate wiring layers 940, 1540, and 2140 are formed.

Next, in operation S860, the manufacturing system may include the remaining portions of the upper layers of the lower channel layers 910, 1510, and 2110 in the insulating layers 930, 1530, and 2130 except for the areas where the wiring connectors 920, 1520, and 2120 are formed. Channel connections 950, 1550, and 2150 are formed in the spaces 932, 1532, and 2132 where portions corresponding to the regions are etched.

Here, in steps S840 to S860, the 3D flash memory 300 to be manufactured may be the 3D flash memory 300 described above with reference to FIG. 3, the 3D flash memory 600 described above with reference to FIG. 6, or FIG. 7. It may be performed differently in detail depending on which of the three-dimensional flash memory 700 described above with reference to.

For example, when manufacturing the 3D flash memory 300 described above with reference to FIG. 3, the manufacturing system may correspond to a portion of the upper region of the wiring connector 920 in the insulating layer 930 as shown in FIG. 12. After the etching is performed by using a mask process, the intermediate wiring layer 940 may be formed in the space 931 in which the portion of the insulating layer 930 corresponding to a portion of the upper region of the wiring connection portion 920 is etched. have. Subsequently, the manufacturing system etches a portion of the insulating layer 930 corresponding to the remaining region of the upper channel of the lower channel layer 910 except for the region where the wiring connection portion 920 is formed, as shown in FIG. 13, using a mask process. The channel connecting portion 950 may be formed in the space 932 in which the portion corresponding to the remaining portion of the insulating layer 930 except for the region where the wiring connecting portion 920 is formed among the upper regions of the lower channel layer 910 is etched. have. In this case, the manufacturing system may form the intermediate wiring layer 940 and the channel connecting portion 950 such that the wiring connecting portion 920 at least partially embedded in the string contacts the intermediate wiring layer 940 and the channel connecting portion 950. .

For another example, when manufacturing the 3D flash memory 600 described above with reference to FIG. 6, the manufacturing system may be formed in a portion of the upper region of the wiring connection 1520 in the insulating layer 1530 as shown in FIG. 18. After etching the portions corresponding to the remaining portions of the upper portion of the lower channel layer 1510 except for the region where the wiring connection portion 1520 is formed by using the mask process, as shown in FIG. 19. An intermediate wiring layer 940 is formed in the space 1531 in which a portion of the insulating layer 1530 corresponding to a portion of the upper region of the wiring connection unit 1520 is etched, and the lower channel layer 1510 in the insulating layer 1530. The channel connector 1550 may be formed in the space 1532 in which the portion corresponding to the remaining region except for the region where the wiring connector 1520 is formed is etched. In this case, the manufacturing system may form the intermediate interconnection layer 1540 and the channel interconnection 1550 such that the interconnection connection 1520 partially embedded in the string contacts the intermediate interconnection layer 1540 and the channel interconnection 1550. .

For another example, when manufacturing the 3D flash memory 700 described above with reference to FIG. 7, the manufacturing system may include some regions of the upper region of the wiring connection portion 2120 in the insulating layer 2130 as shown in FIG. 24. After etching a portion corresponding to, by using a mask process, an additional connection portion 2160 is formed in the space 2131 in which the portion corresponding to a portion of the upper region of the wiring connection portion 2120 in the insulating layer 2130 is etched. can do. Subsequently, the manufacturing system forms an intermediate wiring layer 2140 on the upper portion of the additional connection portion 2160 by using a mask process as shown in FIG. 25, and then covers the intermediate wiring layer 2140 as shown in FIG. 26. Create Accordingly, the manufacturing system masks portions of the insulating layer 2130 and the additional insulating layer 2133 corresponding to the remaining regions of the upper region of the lower channel layer 2110 except for the region where the wiring connection portion 2120 is formed, as shown in FIG. 27. After etching using a process, portions of the insulating layer 2130 and the additional insulating layer 2133 corresponding to the remaining regions of the upper region of the lower channel layer 2110 except for the region where the wiring connection portion 2120 is formed are etched. Channel connectors 2150 may be formed in the spaces 2132 and 2134. At this time, the manufacturing system may connect the additional connection portion 2160 and the channel connection portion so that the wiring connection portion 2120 at least partially embedded in the string contacts both the additional connection portion 2160 and the channel connection portion 2150 contacting the intermediate wiring layer 2140. 2150 may be formed.

The manufacturing system then creates an upper channel layer 960, 1560, 2170 on top of the channel connections 950, 1550, 2150 in step S870. For example, the fabrication system may form the upper channel layers 960, 1560, 2170 with N-type materials as shown in FIGS. 14, 20, and 28. In this case, the upper channel layers 960, 1560, and 2170 may be implemented in the form of hollow tubes inside the same as the lower channel layers 910, 1510, and 2110, and in this case, the upper channel layers 960, 1560, and 2170. The buried films 961, 1561, and 2171 filling the inside of the c) and sidewalls 962, 1562, and 2172 surrounding the outside of the upper channel layers 960, 1560, and 2170 may be further disposed.

FIG. 29 is a top view illustrating a 3D flash memory according to another exemplary embodiment. FIG. 30 is a cross-sectional view based on an X axis of the 3D flash memory illustrated in FIG. 29.

29 to 30, the 3D flash memory 2900 according to another embodiment has a structure similar to the 3D flash memory 300 described above with reference to FIGS. 3 to 5, but adjacent strings in diagonal directions are formed. The difference is that the intermediate wiring layer 2930 disposed between the strings 2910 and 2920 is shared by the strings 2910 and 2920 adjacent in the horizontal direction.

More specifically, in order for the intermediate wiring layer 2930 to be shared by the strings 2910 and 2920 adjacent in the horizontal direction, the wiring connection 2940 is formed with at least a portion of each of the strings 2910 and 2920 buried therein. The channel connectors 2911 and 2921 of the strings 2910 and 2920 and the intermediate wiring layer 2930 may be connected to each other.

The material in which each of the wire connection unit 2940, the channel connection units 2911 and 2921, and the intermediate wiring layer 2930 are formed may be formed of the wire connection unit 340 included in the 3D flash memory 300 described above with reference to FIGS. 3 to 5, Since the channel connection part 320 and the intermediate wiring layer 330 are the same as each, detailed description thereof will be omitted.

FIG. 31 is a cross-sectional view illustrating another example of the 3D flash memory of FIG. 29.

Referring to FIG. 31, the 3D flash memory 3100 may be formed of the same metal material as that of the channel connector 610 in which the channel connectors 3111 and 3121 are included in the 3D flash memory 600 described above with reference to FIG. 6. (For example, at least one of W (tungsten), Ti (titanium), Ta (tantalum), Au (copper) or Au (gold), the intermediate wiring layer as described above with reference to FIGS. 29 to 30. The difference is that 3130 is shared by strings 3110 and 3120 that are adjacent in the horizontal direction rather than strings that are diagonally adjacent. Similarly, in order for the intermediate wiring layer 3130 to be shared by the strings 3110 and 3120 adjacent in the horizontal direction, the wiring connection part 3140 is formed with at least a portion of each of the strings 3110 and 3120 embedded therein. The channel connection parts 3111 and 3121 and the intermediate wiring layer 3130 of each of the fields 3110 and 3120 may be connected to each other.

A material in which each of the wire connection unit 3140, the channel connection units 3111 and 3121, and the intermediate wiring layer 3130 is formed may be formed of the wire connection unit 630 and the channel connection unit included in the 3D flash memory 600 described above with reference to FIG. 6. Since 610 and the intermediate wiring layer 620 are the same as each, detailed description thereof will be omitted.

32 is a cross-sectional view of still another embodiment of the 3D flash memory of FIG. 29.

Referring to FIG. 32, the 3D flash memory 3200 has a structure further including an additional connection part 3230 like the 3D flash memory 700 described above with reference to FIG. 7. As described above with reference, the intermediate wiring layer 3240 is shared by the strings 3210 and 3220 adjacent in the horizontal direction, not the strings adjacent in the diagonal direction. Similarly, in order for the intermediate wiring layer 3240 to be shared by the strings 3210 and 3220 adjacent to each other in the horizontal direction, the wiring connection part 3250 is formed with at least a portion of each of the strings 3210 and 3220 embedded therein. Each of the channel connectors 3211 and 3221 and the additional connector 3210 may be connected to each other.

A material in which each of the wire connection unit 3250, the channel connection units 3211 and 3221, the intermediate wiring layer 3240, and the additional connection unit 3230 is formed may be a wire connection unit included in the 3D flash memory 700 described above with reference to FIG. 7. Since 730, the channel connector 740, the intermediate wiring layer 720, and the additional connector 710 are the same as each, detailed description thereof will be omitted.

The method of manufacturing the 3D flash memory 2900, 3100, and 3200 described above with reference to FIGS. 29 through 32 is the same as the method of manufacturing the 3D flash memory described above with reference to FIGS. 8 through 28, but a string adjacent in a diagonal direction is provided. The difference is that it produces an intermediate wiring layer that is shared by adjacent strings in the horizontal direction, rather than by them. Therefore, detailed description of the manufacturing method will be omitted.

Although the embodiments have been described by the limited embodiments and the drawings as described above, various modifications and variations are possible to those skilled in the art from the above description. For example, the described techniques may be performed in a different order than the described method, and / or components of the described systems, structures, devices, circuits, etc. may be combined or combined in a different manner than the described method, or other components. Or even if replaced or substituted by equivalents, an appropriate result can be achieved.

Therefore, other implementations, other embodiments, and equivalents to the claims are within the scope of the claims that follow.

Claims (13)

A string including a channel layer extending in one direction;
A channel connector connecting the upper channel layer and the lower channel layer to each other in the middle region of the string;
An intermediate wiring layer selectively usable as any one of a source electrode and a drain electrode for the string; And
A wire connection part connecting the channel connection part and the intermediate wiring layer to each other with at least a portion embedded in the string.
Including,
The wiring connection portion,
Formed of an N + type material,
The channel connection unit,
A three-dimensional flash memory formed of either a metallic material or an N-type material. delete The method of claim 1,
The three-dimensional flash memory,
A three-dimensional flash memory fabricated on a substrate comprising a P-type bulk and an N + contact, the channel connector supporting a bulk erase operation as the upper and lower channel layers of the string are connected with the bulk. . The method of claim 1,
The intermediate wiring layer,
And a space located between the string and a neighboring string adjacent to the string. The method of claim 4, wherein
The intermediate wiring layer,
And shared by the string and a neighboring string adjacent to the string. Creating a lower channel layer;
Forming a wire connection in a portion of an upper region of the lower channel layer;
Generating an insulating layer to cover the wiring connection portion;
Etching a portion of the insulating layer corresponding to a portion of the upper region of the lower channel layer except for the region where the wiring connection portion is formed and a portion of the insulating layer corresponding to a portion of the upper region of the wiring connection portion;
Forming an intermediate wiring layer in a space in which a portion of the insulating layer corresponding to a portion of the upper region of the wiring connection part is etched;
Forming a channel connection part in a space in which a portion of the upper layer of the lower channel layer corresponding to the remaining area except the area where the wiring connection part is formed is etched; And
Creating an upper channel layer on top of the channel connection portion
Including,
The intermediate wiring layer,
May be selectively used as any one of a source electrode and a drain electrode for the string including the upper channel layer and the lower channel layer,
Forming the wiring connection portion,
Forming the interconnection connection with an N + type material
Including,
Forming the channel connection portion,
Forming the channel connection with either a metal material or an N-type material
Method of manufacturing a three-dimensional flash memory comprising a. The method of claim 6,
Forming the wire connection portion,
Forming the wiring connection in a space between the string adjacent to the string and the string;
Method of manufacturing a three-dimensional flash memory comprising a. The method of claim 7, wherein
The intermediate wiring layer,
And shared by the string and a neighboring string adjacent to the string. delete A plurality of strings each including a channel layer extending in one direction;
A channel connector connecting the upper channel layer and the lower channel layer of each of the plurality of strings to each other in an intermediate region of each of the plurality of strings;
An intermediate wiring layer shared by strings adjacent in a diagonal direction or a horizontal direction among the plurality of strings, and selectively usable by any one of a source electrode and a drain electrode for each of the strings adjacent in the diagonal direction or the horizontal direction; And
Wiring connection portions connecting the channel connection portion and the intermediate wiring layer of each of the adjacent strings in the diagonal or horizontal direction to each other while at least partially embedded in each of the adjacent strings in the diagonal or horizontal direction.
Including,
Wiring connection portions of the strings adjacent to each other in the diagonal or horizontal direction,
Formed of an N + type material,
The channel connection of each of the plurality of strings,
A three-dimensional flash memory formed of either a metallic material or an N-type material. delete The method of claim 10,
The three-dimensional flash memory,
It is fabricated on a substrate comprising a P-type bulk and an N + contact, the bulk being connected as the upper and lower channel layers of each of the plurality of strings are connected to the bulk by a channel connection of each of the plurality of strings. Three-dimensional flash memory that supports erase operations. The method of claim 10,
The intermediate wiring layer,
And a space located between adjacent strings in the diagonal or horizontal direction.

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