KR102057481B1 - Liquid crystal display device - Google Patents

Abstract

The liquid crystal display according to the exemplary embodiment of the present invention is characterized in that when the oxide thin film transistor is applied as a switching element, a trench is formed around the display area to block moisture permeation into the oxide semiconductor. In addition, the liquid crystal display according to the exemplary embodiment of the present invention reduces the number of masks by applying an OC (overcoat) layer instead of a PAC (photo acryl) layer, and at the same time forms a sawtooth pattern in the OC trench to smooth the taper. As a result, it is characterized in that the residual film is prevented due to the OC step.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having an oxide thin film transistor as a switching element.

In general, the liquid crystal display device is driven by using the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Among them, an active matrix LCD (AMLCD), in which a thin film transistor (TFT) and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, is attracting attention due to its excellent resolution and video performance.

The LCD includes an upper substrate on which a color filter, a common electrode, and the like are formed, a lower substrate on which a switching element, a pixel electrode, and the like are formed, and a liquid crystal interposed between two substrates. Such a liquid crystal display device has excellent characteristics such as transmittance and aperture ratio by driving a liquid crystal by an electric field applied up and down between the common electrode and the pixel electrode.

On the other hand, general thin film transistors have used amorphous silicon as a semiconductor layer, but amorphous silicon has a low electron transfer speed, making it difficult to realize high resolution and high-speed driving capability on a very large screen. Therefore, an oxide thin film transistor having an electron transfer speed 10 times faster than that of amorphous silicon has emerged, and has recently been spotlighted as a device suitable for high resolution of UD (Ultra Definition) and high speed driving of 240 Hz or more.

[Related Technical Documents]

1. Oxide thin film transistor array substrate and its manufacturing method (Korean Patent Application No. 10-2011-0100901).

Recently used oxide thin film transistor has high electron transfer speed and is suitable for high resolution and high speed driving.

However, an oxide semiconductor is sensitive to an external environment such as oxygen or moisture, and thus moisture, hydrogen, and oxygen react with the oxide semiconductor to change the carrier concentration, thereby affecting the characteristics and reliability of the device.

The inventors of the present invention have invented a new structure that can block moisture permeation into an oxide semiconductor, taking into consideration that water must penetrate outside the display area to prevent moisture permeation, and that water permeates along the organic layer. .

That is, when the oxide thin film transistor is applied as a switching element, a trench may be formed in the organic layer around the display area to prevent moisture permeation into the oxide semiconductor.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of blocking moisture permeation to an oxide semiconductor in a display area.

In addition, the inventors of the present invention, in consideration of the fact that OC (overcoat) does not require a mask process, invented a new structure that can reduce the number of masks by applying OC in place of PAC (photo acryl).

Accordingly, another object of the present invention is to provide a liquid crystal display device capable of reducing the number of masks used in the manufacture of a liquid crystal display device.

On the other hand, when OC is applied to the organic layer instead of PAC, there is a concern that a residual film of the transparent conductive film is caused by a sharp taper increase in the OC trench. In this case, a short circuit may occur between the pad lines.

The inventors of the present invention, in the process of removing the OC to form the OC trench, the taper is sharply increased, the residual film generation of the transparent conductive film increases with the increase of the taper, and the corners of the pattern are sharply formed. In view of the fact that the taper can be smoothed in the case, the invention has been invented a new structure that can prevent the generation of residual film due to the OC step.

That is, by forming a sawtooth pattern in the OC trench to smooth the taper, residual film generation due to the OC step can be prevented.

Accordingly, another problem to be solved by the present invention is to provide a liquid crystal display device capable of preventing the generation of residual film due to the OC step.

The objects of the present invention are not limited to the above-mentioned objects, and other objects that are not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, a liquid crystal display device according to an exemplary embodiment of the present invention includes a liquid crystal panel and pixels that are divided into a display area in which pixels are arranged in a matrix, and a non-display area outside the display area. A thin film transistor which is mounted in a non-display area, a driver for driving pixels, at least one link wiring disposed in the non-display area to transmit a signal to the pixel from the driver, and a first protection including an overcoat (OC) under the link wiring The trench may include a trench disposed in the layer and the non-display area so as to pass through the link wiring, and the first protective layer is removed.

In order to solve the above problems, a liquid crystal display device according to another embodiment of the present invention, the liquid crystal panel, the pixels are divided into a display area in which the pixels are arranged in a matrix form, and a non-display area outside the display area A thin film transistor, a driver mounted in the non-display area to drive the pixels, at least one link wiring disposed in the non-display area to transmit a signal to the pixel from the driver, a first protective layer made of OC under the link wiring, The first protective layer may be disposed in the non-display area to pass through the link wiring, and the trench may include a trench formed in the trench to remove moisture from the inside of the display area and a sawtooth pattern to smooth the taper of the first protective layer. have.

Specific details of other embodiments are included in the detailed description and drawings.

According to the present invention, an oxide thin film transistor is applied as a switching element to realize high resolution and high speed driving capability in a very large screen. In addition, the reliability of the oxide thin film transistor can be improved by blocking moisture permeation into the oxide semiconductor. In addition, the manufacturing cost can be reduced by reducing the number of masks used for manufacturing the array substrate. In addition, short circuits between padlines can be prevented by preventing residual film generation due to the OC level, so that the yield can be improved.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram illustrating a structure of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 3 is a view schematically illustrating a cross section of a display area in the liquid crystal display according to the exemplary embodiment of the present invention shown in FIG. 2.
FIG. 4 is a view schematically illustrating a plane portion of a non-display area in the liquid crystal display according to the exemplary embodiment of the present invention shown in FIG. 2.
5A and 5B are schematic views illustrating a cross section taken along the line II ′ of the LCD of FIG. 4.
FIG. 6 is a view schematically illustrating a plane portion of a non-display area in a liquid crystal display according to another exemplary embodiment of the present invention.
7A and 7B are plan views and cross-sectional views showing an enlarged sawtooth pattern in an OC trench in a liquid crystal display according to another exemplary embodiment of the present invention.
8A to 8D are plan views illustrating the sawtooth pattern of the present invention as an example.
9A and 9B schematically illustrate a cross-sectional structure of a tooth pattern in an OC trench in a liquid crystal display according to another exemplary embodiment of the present invention.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims.

Shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated items. In addition, in describing the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'comprises', 'haves', 'consists of' and the like mentioned in the present specification, other parts may be added unless 'only' is used. In case of singular reference, the plural number includes the plural unless specifically stated otherwise.

In interpreting a component, it is interpreted to include an error range even if there is no separate description.

In the case of the description of the positional relationship, for example, if the positional relationship of the two parts is described as 'on', 'upon', 'lower', 'next to', etc. Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

When an element or layer is referred to as another element or layer includes both instances of intervening another layer or element directly on or in between.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be a second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout.

The size and thickness of each component shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated configuration.

Each of the features of the various embodiments of the present invention may be combined or combined with each other in part or in whole, various technically interlocking and driving as can be understood by those skilled in the art, each of the embodiments may be implemented independently of each other It may be possible to carry out together in an association.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a structure of a liquid crystal display according to an exemplary embodiment of the present invention. 2 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 3 is a view schematically showing a portion of a cross section of a FFS (Fringe Field Switching) mode display area in the liquid crystal display according to the exemplary embodiment shown in FIG. 2. However, the present invention is not limited to the FFS mode.

1 to 3, the liquid crystal display according to the exemplary embodiment of the present invention is largely divided into the display area AA and the non-display area NA, so that the pixels SP are disposed in the display area AA. The pixels SP are mounted in the liquid crystal panel 100 arranged in a matrix form, the backlight 170 disposed under the liquid crystal panel 100 to provide a light source, and the non-display area NA of the liquid crystal panel 100. ) May be configured as a driving unit and a power supply unit 160.

The driving unit may include a gate driver 140, a data driver 130, and a timing driver 150. The data signal and the gate may be provided to each of the data lines DL and the gate lines GL of the liquid crystal panel 100. A driver integrated circuit (IC) for applying a signal is included, and a chip on glass (COG) tape carrier package according to a method of mounting the driver IC on the liquid crystal panel 100. (Tape Carrier Package; TCP), Chip On Film (COF) and the like. In addition, the driving unit may be formed on the liquid crystal panel 100 in the form of a gate in panel (GIP).

The timing driver 150 may receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK, and a data signal DATA.

The timing driver 150 uses a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK, and the gate of the data driver 130 and the gate. The operation timing of the driver 140 may be controlled. Meanwhile, since the timing driver 150 may determine the frame period by counting the data enable signal DE of one horizontal period, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync supplied from the outside may be omitted. It may be. The control signals generated by the timing driver 150 include a gate timing control signal GDC for controlling the operation timing of the gate driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130. ) May be included.

The gate timing control signal GDC may include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP may be supplied to a gate drive integrated circuit (IC) where the first gate signal is generated. The gate shift clock GSC is a clock signal commonly input to gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE may control the output of the gate drive ICs.

The data timing control signal DDC may include a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, and the like. The source start pulse SSP may control a data sampling start time of the data driver 130. The source sampling clock SSC is a clock signal that controls the sampling operation of the data in the data driver 130 based on a rising or falling edge. The source output enable signal SOE may control the output of the data driver 130. Meanwhile, the source start pulse SSP supplied to the data driver 130 may be omitted depending on the data transmission method.

The liquid crystal panel 100 includes a thin film transistor substrate (hereinafter referred to as an array substrate) 110, a color filter substrate (not shown), and a liquid crystal layer disposed therebetween, and arranged in a matrix form. It may include.

In this case, data lines DL, gate lines GL, TFTs, storage capacitors, etc. may be formed on the array substrate 110, and black matrices, color filters, etc. may be formed on the color filter substrate. Can be. In this case, one pixel SP may be defined by the data line DL and the gate line GL that cross each other.

One pixel SP includes a TFT driven by a gate signal supplied through the gate line GL, a storage capacitor storing a data signal supplied through the data line DL as a data voltage, and a data voltage stored in the storage capacitor. A liquid crystal cell driven by may be included.

The liquid crystal cell may be driven by the data voltage supplied to the pixel electrode 118 and the common voltage supplied to the common electrode 108. The common electrode 108 is formed on the color filter substrate in the vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and is formed in the in-plane switching (IPS) mode and the fringe field switching (FFS) mode. In the horizontal electric field driving method, the pixel electrode 118 may be formed on the array substrate 110. The common electrode 108 may receive a common voltage from the common voltage wiring 165.

The polarizing plate may be attached to the array substrate 110 and the color filter substrate of the liquid crystal panel 100 configured as described above, and an alignment layer for setting a pre-tilt angle of the liquid crystal may be formed. The liquid crystal mode of the liquid crystal panel 100 may be implemented in any liquid crystal mode as well as the above-described TN mode, VA mode, IPS mode, FFS mode.

The gate driver 140 signals the swing width of the gate driving voltage at which the TFTs of the pixels SP included in the liquid crystal panel 100 can operate in response to the gate timing control signal GDC supplied from the timing driver 150. The gate signal is sequentially generated while shifting the level of. The gate driver 140 may supply the gate signals generated through the gate lines GL to the pixels SP included in the liquid crystal panel 100. As described above, the gate driver 140 may be mounted on the liquid crystal panel 100 in an IC form or formed on the liquid crystal panel 100 in a GIP form.

The data driver 130 samples and latches the data signal DATA supplied from the timing driver 150 in response to the data timing control signal DDC supplied from the timing driver 150 to latch the data of the parallel data system. Can be converted to In this case, when converting the data of the parallel data system, the data signal DATA may be converted into a gamma reference voltage. The data driver 130 may supply the data signal DATA converted through the data lines DL to the pixels SP included in the liquid crystal panel 100. The data driver 130 may be mounted on the liquid crystal panel 100 in an IC form or formed on the liquid crystal panel 100 in a GIP form.

In the non-display area NA, data link lines 131 and gate link lines 132 connected to the data lines DL and the gate lines GL may be formed. Data pads and gate pads may be connected to ends of the data link line 131 and the gate link line 132, respectively.

The data pad and the gate pad may be connected to a data driver IC and a gate driver IC mounted on the array substrate 110, respectively.

The data driver IC and the gate driver IC may be connected to an external printed circuit board through an FPC. The printed circuit board may include a timing driver 150 and a power supply 160. However, the present invention is not limited thereto.

The backlight unit 170 provides light to the liquid crystal panel 100. The backlight unit 170 may include a light source for emitting light, a light guide panel for guiding the light to the liquid crystal panel 100, an optical sheet for collecting and diffusing the light, and the like.

The power supply unit 160 may output the common voltage Vcom, the first high voltage Vdd, the second high voltage Vcc, and the like by converting the input power Vin supplied from the outside into the DC power. In this case, the common voltage Vcom is supplied to the common voltage wiring 165, while the first high voltage Vdd is supplied to the gate driver 140 and the data driver 130, and the second high voltage Vcc. May be supplied to the timing driver 150. The power supply unit 160 may be mounted on the printed circuit board connected to the liquid crystal panel 100.

Referring to FIG. 2, the liquid crystal panel 100 may include an array substrate 110 divided into a display area AA and a non-display area NA around the display area AA.

The display area AA may be defined as an area for displaying an image, and the non-display area NA may be defined as a bezel area as an area for non-displaying an image.

Pixels SP formed in a matrix form may be formed in the display area AA. On the other hand, in the non-display area NA, various wirings such as the data link line 131, the gate link line 132, and the common voltage wiring 165, the gate driver 140, the data driver 130, and the connection part 135. ) May be formed.

In FIG. 2, the gate driver 140 is formed on both sides of the liquid crystal panel 100, but the present invention is not limited thereto and may be formed on one side of the liquid crystal panel 100.

The data link line 131 is wired so that the data signals output from the data driver 130 are supplied to the data lines of the pixels SP, and the gate link line 132 is gate signals output from the gate driver 140. The wires are wired to be supplied to the gate lines of the pixels SP. The common voltage wiring 165 is wired such that the common voltage output from the power supply unit is supplied to the common electrodes of the pixels SP. The data link line 131, the gate link line 132, and the common voltage line 165 formed in the non-display area NA may be connected to the data line, gate line, and common electrode formed in the display area AA. Therefore, illustration and description thereof will be omitted. The connection unit 135 may be electrically connected to an external printed circuit board to supply various power and signals supplied from the outside to the driving unit and the common voltage wiring 165.

Hereinafter, the structure of the pixel SP will be described in more detail.

2 and 3, as described above, the liquid crystal display according to the exemplary embodiment of the present invention includes a display area AA, which is an area for displaying an image, and a non-display area NA outside the display area AA. ) Can be separated.

In the display area AA, a plurality of gate lines and a plurality of data lines cross each other to define a pixel area. In the pixel region, a thin film transistor may be formed as a switching element, and a pixel electrode 118 and a common electrode 108 for forming an electric field may be formed.

The gate electrode 121 may be disposed on the array substrate 110, and the gate insulating layer 115a may be disposed on the gate electrode 121.

The gate line may be disposed on the same layer as the gate electrode 121 in the first direction.

The gate electrode 121 and the gate line are aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy) , Gold (Au), Au alloy, Chromium (Cr), Titanium (Ti), Titanium alloy (Ti alloy), Moly tungsten (MoW), Molaritanium (MoTi), Copper / Mortinium (Cu / MoTi At least one selected from the group of conductive metals, or a combination of two or more thereof, or other suitable material.

As the gate insulating layer 115a, a silicon (Si) -based oxide film, a nitride film, or a compound containing the same, a metal oxide including an Al ₂ O ₃ , an organic insulating film, and a low dielectric constant (low-k) ) Material having a value of. For example, the gate insulating layer 115a may include silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide (Ta). ₂ O ₅ ), any one selected from the group consisting of barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O), Or combinations of two or more thereof, or other suitable materials.

An active layer 124 is disposed on the gate insulating layer 115a, and a source electrode 122 extending from the data line and a drain electrode 123 spaced apart from the source electrode 122 are disposed on the active layer 124. Can be.

The data line may be disposed in a second direction crossing the first direction to partition the pixel area together with the gate line.

In this case, an ohmic contact layer 125 forming an ohmic contact between the source region and the drain region of the active layer 124 and the source electrode 122 and the drain electrode 123 may be disposed on the active layer 124. The ohmic contact layer 125 is not formed in an area spaced between the source electrode 122 and the drain electrode 123.

For example, the active layer 124 may be patterned at the same time as the data line and the source / drain electrodes 122 and 123, and in this case, may be patterned to have the same shape as the source / drain electrodes 122 and 123.

The active layer 124 according to an embodiment of the present invention may be formed of an oxide semiconductor.

As the oxide semiconductor, one or more materials selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga) and aluminum (Al) and zinc ( It may be made of a material in which silicon (Si) is added to an oxide semiconductor including Zn). For example, the active layer 124 may be formed of silicon indium zinc oxide (Si-InZnO: SIZO) in which silicon ions are added to indium zinc complex oxide (InZnO).

When the active layer 124 is made of SIZO, the composition ratio of the silicon (Si) atom content to the total content of zinc (Zn), indium (In), and silicon (Si) atoms in the active layer 124 is about 0.001% by weight ( wt%) to about 30 wt%. The higher the silicon (Si) atomic content, the stronger the role of controlling electron generation, so that the mobility may be lowered, but the stability of the device may be better.

As the oxide semiconductor, in addition to the above materials, Group I elements such as lithium (Li) or potassium (K), Group II elements such as magnesium (Mg), calcium (Ca) or strontium (Sr), gallium (Ga) and aluminum Group III elements such as (Al), indium (In) or yttrium (Y), group IV elements such as titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge), tantalum Group V elements such as (Ta), vanadium (V), niobium (Nb) or antimony (Sb), or lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm) , Samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) or ruthedium Lanthanum (Ln) -based elements such as (Lu) may be further included.

Source / drain electrodes 122 and 123 and data lines are aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy (Ag alloy), gold (Au), gold alloy (Au alloy), chromium (Cr), titanium (Ti), titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenum (MoTi), copper / molybdenum It may also comprise at least one selected from the group of conductive metals containing (Cu / MoTi), or a combination of two or more thereof, or other suitable material.

An interlayer insulating layer 115b may be disposed on the array substrate 110 including the source / drain electrodes 122 and 123 and the data line.

The common electrode 108 may be disposed on the interlayer insulating layer 115b.

The interlayer insulating layer 115b may be formed of a silicon-based oxide film, a nitride film, or a compound including the same, and a metal oxide, an organic insulating film, and a low dielectric constant (low-k) value including Al ₂ O ₃ . It may include a material having a. For example, the interlayer insulating layer 115b may include silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide (Ta). ₂ O ₅ ), any one selected from the group consisting of barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O), Or combinations of two or more thereof, or other suitable materials.

A low dielectric constant first protective layer 115c may be further disposed between the interlayer insulating layer 115b and the common electrode 108. The first passivation layer 115c may be formed of a low dielectric constant organic insulating material such as photo acryl (PAC) or overcoat (OC) to prevent coupling between the data line and the common electrode 108. have.

The common electrode 108 may be made of a transparent metal material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The common electrode 108 may have a plate shape in the pixel area, but may have a first opening in a predetermined area. The first opening may be formed in the contact hole region where the drain electrode 123 is exposed. This is to prevent a short from occurring during electrical connection between the drain electrode 123 and the pixel electrode 118 through the contact hole. That is, when the common electrode 108 does not include the first opening, a short occurs between the common electrode 108 and the pixel electrode 118 during the electrical connection between the pixel electrode 118 and the drain electrode 123. In order to prevent this, the common electrode 108 may be provided with a first opening in the contact hole region.

In addition, the common electrode 108 may include a second opening in the thin film transistor region. This is because when the common electrode 108 is formed in the thin film transistor region, it may interfere with the movement of electrons in the channel region of the active layer 124. Therefore, the second opening may be formed on the spaced apart region between the source electrode 122 and the drain electrode 123 in the thin film transistor region.

In addition, the common electrode 108 may include a third opening in the non-display area. The third opening may be provided in the trench 180 region to be described later.

The second passivation layer 115d may be disposed on the common electrode 108.

The second passivation layer 115d may be formed of a silicon (Si) based oxide film, a nitride film, or a compound including the same, and a metal oxide, an organic insulating film, and a low dielectric constant (low-k) including Al ₂ O ₃ . It may include a material having a value. For example, as the second protective layer 115d, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) Or combinations of two or more thereof, or other suitable materials.

The pixel electrode 118 may be disposed on the second passivation layer 115d.

The pixel electrode 118 may be formed of a transparent metal material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In this case, the pixel electrode 118 may be connected to the drain electrode 123 through a contact hole. The contact hole may be formed in a predetermined region of the interlayer insulating layer 115b, the first passivation layer 115c, and the second passivation layer 115d to expose the drain electrode 123.

A plurality of slits 118s may be provided in the pixel electrode 118 to form a fringe field together with the common electrode 108.

On the other hand, as described above, the liquid crystal display according to the exemplary embodiment of the present invention includes a trench 180 in the non-display area NA outside the display area AA to provide moisture permeation into the display area AA. It is characterized by blocking.

That is, the oxide semiconductor is sensitive to an external environment such as oxygen or moisture, and thus moisture, hydrogen, and oxygen react with the oxide semiconductor to change the carrier concentration, thereby affecting the characteristics and reliability of the device.

An embodiment of the present invention focuses on the fact that the penetration of moisture outside the display area AA is effective to prevent moisture permeation, and that moisture penetrates along the first protective layer 115c, which is an organic layer. A new structure that can block moisture permeation into a semiconductor is disclosed.

That is, when the oxide thin film transistor is applied as a switching device, the trench 180 may be enclosed so as to surround the display area AA in the non-display area NA outside the display area AA. It is characterized by blocking the moisture semiconductor to the active layer 124 of the oxide semiconductor, that is, the oxide thin film transistor.

In addition, one embodiment of the present invention, in view of the fact that OC does not require a mask process for patterning, by reducing the number of masks by applying the OC instead of PAC to form the first protective layer 115c It is done.

FIG. 4 is a view schematically illustrating a plane portion of a non-display area in the liquid crystal display according to the exemplary embodiment of the present invention shown in FIG. 2. 5A and 5B are schematic views illustrating a cross section taken along the line II ′ of the LCD of FIG. 4.

4 illustrates an A portion of the non-display area NA through which the gate link line 132 passes, in the liquid crystal display according to the exemplary embodiment of the present invention illustrated in FIG. 2. Therefore, hereinafter, the gate link line 132 will be described only, but the present invention is not limited thereto. The data link line 131 may be similarly applied.

5A and 5B illustrate an example in which the first protective layers 115c 'and 115c are formed of PAC and OC in the liquid crystal display of FIG. 4 as an example.

4 and 5A and 5B, the gate insulating layer 115a and the interlayer insulating layer 115b may be disposed on the array substrate 110 of the non-display area NA. .

The gate insulating layer 115a and the interlayer insulating layer 115b may be formed of a silicon-based oxide film, a nitride film, or a compound including the same, and a metal oxide, an organic insulating film, and a low dielectric material including Al ₂ O ₃ . Material with a low (k) value. For example, the gate insulating layer 115a and the interlayer insulating layer 115b may include silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), and titanium oxide (TiO _2). ), A group consisting of tantalum oxide (Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) It may also comprise any one selected from, or a combination of two or more thereof, or other suitable material.

First protective layers 115c ′ and 115c including trenches 180 may be disposed on the interlayer insulating layer 115b.

In this case, the first protective layer 115c ′ of FIG. 5A may be composed of a PAC, and the first protective layer 115c of FIG. 5B may be composed of OC.

As described above, the first passivation layers 115c ′ and 115c according to the exemplary embodiment of the present invention may be formed of a low dielectric constant PAC or OC between the interlayer insulating layer 115b and the common electrode 108. It may serve to prevent coupling between the common electrodes 108.

The trench 180 may be disposed in a plurality of non-display areas NA outside the display area AA.

The trench 180 may be disposed to surround the display area AA.

The trench 180 may have a bar shape having a predetermined width with respect to one surface of the display area AA. Thus, the trench 180 may have a rectangular frame shape that surrounds four surfaces around the display area AA.

The first passivation layers 115c ′ and 115c in the trench 180 may be removed to expose the surface of the interlayer insulating layer 115b.

The common electrode 108 having the third opening O may be disposed on the first passivation layers 115c 'and 115c.

The common electrode 108 may be made of a transparent metal material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

As described above, the common electrode 108 may have a plate shape in the pixel area, but may have a first opening and a second opening in a predetermined area. The first opening may be formed in the contact hole region where the drain electrode is exposed. This is to prevent a short from occurring during electrical connection between the drain electrode and the pixel electrode 118 through the contact hole.

In addition, the common electrode 108 may include a second opening in the thin film transistor region. This is because when the common electrode 108 is formed in the thin film transistor region, it may interfere with the movement of electrons in the channel region of the active layer. Therefore, it is preferable that the second opening is formed on the spaced apart region between the source electrode and the drain electrode in the thin film transistor region.

For example, the third opening O may be provided in the trench 180 region where the data link line 131 and the gate link line 132 do not pass. The third opening O is formed in the region of the trench 180 through which the data link line 131 and the gate link line 132 do not pass, thereby removing the common electrode 108. This is to partially block the penetration of moisture from the water. In addition, in the trench 180 region where the data link line 131 and the gate link line 132 pass, the moisture infiltration as the penetration path of moisture through the common electrode 108 is actually lengthened by the plurality of trenches 180. Can be suppressed.

The second passivation layer 115d may be disposed on the common electrode 108.

The second passivation layer 115d may be formed of a silicon (Si) -based oxide film, a nitride film, or a compound including the same, and a metal oxide, an organic insulating film, and a low dielectric constant (low-k) including Al ₂ O ₃ . It may include a material having a value. For example, as the second protective layer 115d, silicon oxide (SiO ₂ ), silicon nitride (SiNx), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), and tantalum oxide ( Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) Or combinations of two or more thereof, or other suitable materials.

Link wirings of the pixel electrode, the data link line 131, and the gate link line 132 may be disposed on the second passivation layer 115d.

The pixel electrode, the data link line 131, and the gate link line 132 may be formed of a transparent metal material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Meanwhile, when applying the PAC to the organic layer, referring to FIG. 5A, the first passivation layer 115 ′ in the trench 180 may be patterned to have a gentle slope. However, there is a disadvantage in that a mask process is added to the patterning of the first passivation layer 115 ′ for forming the trench 180.

On the other hand, when OC is applied to the organic layer instead of PAC, a mask process is not added. Referring to FIG. 5B, the first protective layer 115 in the trench 180 is patterned to have a steep slope. That is, in this case, as the OC trench 180 is formed, it can be seen that the taper increases rapidly.

As described above, when OC is applied to the organic layer instead of PAC, the number of masks is reduced, but there is a concern that the residual film R ″ of the transparent conductive film may be generated due to a sharp taper increase in the OC trench 180. In this case, a short circuit may occur between the link wirings of the data link line 131 and the gate link line 132. That is, when the taper is abrupt, due to the step of the first protective layer 115 'in the trench 180, The transparent conductive films for the data link line 131 and the gate link line 132 formed later are not removed and remain as the remaining film R ″. When the residual layer R ″ is connected to each other, a short circuit between adjacent link wires may occur.

On the other hand, referring to Figure 5a, the residual film (R ') of the transparent conductive film may also be generated in the PAC trench 180, but the residual film (R') is not generated enough to cause a short circuit between the link wiring due to the tapered tape It can be seen that.

Accordingly, in another embodiment of the present invention, in the process of forming the OC trench by removing OC, the taper rapidly increases, the residual film generation of the transparent conductive film increases according to the increase of the taper, and the corner portion of the pattern. In view of the fact that the taper may be smoothed when sharply formed, a new structure capable of preventing the formation of residual film due to OC step is disclosed.

FIG. 6 is a view schematically illustrating a plane portion of a non-display area in a liquid crystal display according to another exemplary embodiment of the present invention. 7A and 7B are a plan view and a cross-sectional view showing an enlarged sawtooth pattern in an OC trench in a liquid crystal display according to another exemplary embodiment of the present invention. 8A to 8D are plan views illustrating the sawtooth pattern of the present invention as an example.

6 illustrates a portion of the non-display area through which the gate link line 232 passes in the liquid crystal display according to another exemplary embodiment of the present invention. Therefore, hereinafter, the gate link line 232 will be described only, but the present invention is not limited thereto, and the same may be applied to the data link line.

7A and 7B show an enlarged view of a sawtooth pattern 285 in the OC trench 280 in the liquid crystal display according to the exemplary embodiment of FIG. 6. FIG. 7B schematically illustrates a cross section taken along line II-II ′ of the sawtooth pattern 285 shown in FIG. 7A.

6, 7A, and 7B, a gate insulating layer 215a and an interlayer insulating layer 215b may be disposed on the array substrate 210 of the non-display area.

In addition, the first passivation layer 215c including the trench 280 may be disposed on the interlayer insulating layer 215b.

In this case, the first protective layer 215c may be composed of OC.

As described above, the first passivation layer 215c according to another embodiment of the present invention is composed of a low dielectric constant OC between the interlayer insulating layer 215b and the common electrode, thereby providing a coupling between the data line and the common electrode. may serve to prevent coupling.

The trench 280 may be disposed in a plurality of non-display areas outside the display area.

The trench 280 may be disposed to surround the display area.

The trench 280 may have a bar shape having a predetermined width with respect to one surface of the display area. Accordingly, the trench 280 may have a rectangular frame shape that surrounds four surfaces around the display area.

The first passivation layer 215c in the trench 280 may be removed to expose a portion of the surface of the interlayer insulating layer 215b.

Although not shown, a common electrode having a third opening may be disposed on the first passivation layer 215c.

As in the exemplary embodiment of the present invention described above, as an example, the third opening may be provided in an area of the trench 280 where the link wiring of the data link line and the gate link line 232 does not pass. This is to partially block penetration of moisture from the outside through the common electrode by removing the common electrode by forming a third opening in the trench 280 region where the link wiring does not pass. In addition, in the trench 280 region through which the data link line and the gate link line 232 pass, the penetration of moisture through the plurality of trenches 280 actually increases the penetration path of the moisture through the common electrode.

The second passivation layer 215d may be disposed on the common electrode.

The link wirings of the pixel electrode, the data link line, and the gate link line 232 may be disposed on the second passivation layer 215d.

Another embodiment of the present invention has the advantage that the mask process is not added by applying OC instead of PAC as the organic layer. In addition, another embodiment of the present invention is characterized by forming a sawtooth pattern 285 in the trench 280 to smooth the taper of the first protective layer 215c to prevent the formation of residual film due to the OC step. do.

The sawtooth pattern 285 may be provided at the boundary of the trench 280 through which the link wiring of the data link line and the gate link line 232 passes.

The sawtooth pattern 285 may be provided at both sides of the boundary of the trench 280.

The sawtooth pattern 285 may be composed of a single body 285b connecting the bottom side of the plurality of teeth 285a and the plurality of teeth 285a.

The toothed portion 285a may have a vertex or a vertex.

The toothed portion 285a may have one or more vertices.

A vertex or a vertex of the tooth portion 285a is characterized in that its width is narrower than that of the other portions.

The corner portion of the tooth portion 285a is a region where OC dry etching overlaps on both sides, and the taper becomes smooth (see arrows in FIG. 7B). The tapered taper can prevent a short circuit between the link wirings due to the remaining film of the transparent conductive film.

Although some residual film remains at the edge portion of the tooth portion 285a, it can be seen that the residual film does not exist at the vertex or the vertex.

7A illustrates an example in which the toothed portion 285a has a triangular shape, but the present invention is not limited thereto. 8A to 8D, the tooth parts 285a, 385a, 485a, and 585a may have various shapes, such as a trapezoid narrowing in width in addition to a triangle shape, an ellipse, and a pointed tip like a needle. These teeth 285a, 385a, 485a, 585a may vary in size, shape, or inclination of the inclined surface.

That is, irrespective of the size and shape of the toothed portions 285a, 385a, 485a, and 585a, it is applicable when the vertex or vertex is narrower than the other portions. In addition, the present invention is applicable when the vertex or the vertex is narrower than the other portions, regardless of the inclination of the inclined surfaces of the teeth 285a, 385a, 485a, and 585a. In this case, it can be seen that the residual film is improved regardless of the size or shape of the teeth 285a, 385a, 485a, 585a. In addition, as shown in FIG. 8D, when the tooth 285a has a triangular shape, it can be seen that the smaller the angle of the vertex, the better the residual film improvement. This is because the smaller the angle of vertex, the smoother the taper and the flatter the PR.

In addition, in one embodiment and another embodiment of the present invention, but the case of having a spacing of about 20㎛ between the teeth 285a, 385a, 485a, 585a as an example, the present invention is not limited thereto, The invention is applicable regardless of the spacing between the teeth 285a, 385a, 485a, 585a.

Thus, the residual film improvement by the tooth pattern 285 is judged to be the effect by PR planarization of the tooth part 285a other than the taper by the tooth part 285a mentioned above.

9A and 9B schematically illustrate a cross-sectional structure of a tooth pattern in an OC trench in a liquid crystal display according to another exemplary embodiment of the present invention.

9A illustrates a cross-sectional view taken along line II-II 'of the tooth portion 285a of the sawtooth pattern 285 shown in FIG. 7A, and FIG. 9B is illustrated in FIG. 7A. A cross section taken along line III-III 'of the body 285b of the sawtooth pattern 285 is shown as an example.

9A and 9B, a gate insulating layer 215a and an interlayer insulating layer 215b may be disposed on the array substrate 210 of the non-display area.

In addition, a first protective layer 215c including a trench may be disposed on the interlayer insulating layer 215b.

In this case, the first protective layer 215c may be composed of OC.

As described above, the first passivation layer 215c according to another embodiment of the present invention is composed of a low dielectric constant OC between the interlayer insulating layer 215b and the common electrode, thereby providing a coupling between the data line and the common electrode. may serve to prevent coupling.

As described above, a plurality of trenches may be disposed in the non-display area outside the display area.

The trench may be arranged to surround the display area.

The trench may have a bar shape having a predetermined width with respect to one surface of the display area. Accordingly, the trench may have a rectangular frame shape that surrounds four surfaces around the display area.

A portion of the surface of the interlayer insulating layer 215b may be exposed by removing the first protective layer 215c in the trench.

Although not shown, a common electrode 208 having a third opening may be disposed on the first passivation layer 215c.

As in the embodiment of the present invention described above, as an example, the third opening may be provided in a trench region in which the link wiring of the data link line and the gate link line does not pass. This is to partially block penetration of moisture from the outside through the common electrode 208 by removing the common electrode 208 by forming a third opening in the trench region where the link wiring does not pass. In addition, in the trench region through which the data link line and the gate link line pass, moisture penetration may be suppressed as the penetration path of moisture through the common electrode 208 is actually lengthened by the plurality of trenches.

The second passivation layer 215d may be disposed on the common electrode 208.

In this case, the pixel electrode and the link wiring of the data link line and the gate link line may be disposed on the second passivation layer 215d. To this end, the transparent conductive film 206 and the PR may be stacked on the second protective layer 215d.

In this case, according to another embodiment of the present invention, the mask process is not added as OC is applied to the organic layer instead of PAC. In addition, another embodiment of the present invention is characterized by forming a sawtooth pattern in the trench to smooth the taper of the first protective layer 215c to prevent the formation of residual film due to the OC step.

The sawtooth pattern may be provided at the boundary of the trench through which the link wiring of the data link line and the gate link line passes.

The sawtooth pattern may be provided at both sides of the boundary of the trench.

The sawtooth pattern may be composed of a plurality of teeth 285a (see FIG. 9A) and one body 285b (see FIG. 9B) connecting bottom sides of the plurality of teeth 285a.

The toothed portion 285a may have a vertex or a vertex.

The toothed portion 285a may have one or more vertices.

A vertex or a vertex of the tooth portion 285a is characterized in that its width is narrower than that of the other portions.

The corner portion of the tooth portion 285a is a region where OC dry etching overlaps on both sides, and the taper becomes smooth. The tapered taper can prevent a short circuit between the link wirings due to the remaining film of the transparent conductive film.

Referring to FIG. 9A, it can be seen that the tooth portion 285a is thinner than the body 285b by the thickness d1 of the PR itself due to planarization with the surroundings. That is, it can be seen that the remaining film of the transparent conductive film 206 is improved due to the reduction of the edge PR thickness d1 of the tooth portion 285a.

On the other hand, referring to Figure 9b, it can be seen that the body 285b thickens the PR thickness d2 due to the OC step, and as a result, the remaining film of the transparent conductive film 206 is generated during the development.

Exemplary embodiments of the invention may be described as follows.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a display area in which pixels are arranged in a matrix, a liquid crystal panel divided into a non-display area outside the display area, a thin film transistor provided in pixels, and a non-display area. At least one link wiring disposed in the non-display area to transmit a signal from the driver to the pixel, a first protective layer formed of an overcoat (OC) below the link wiring, and a link wiring in the non-display area. It may be disposed to pass through, and may include a trench in which the first protective layer is removed.

According to another feature of the invention, the liquid crystal display may further include a sawtooth pattern provided in the trench.

According to another feature of the invention, the sawtooth pattern may be provided at the boundary of the trench through which the link wiring passes.

According to another feature of the invention, the sawtooth pattern may be provided on both sides of the boundary of the trench.

According to another feature of the invention, the sawtooth pattern may be composed of a single body connecting the plurality of teeth and the bottom side of the teeth.

According to another feature of the invention, the toothed portion may have one or more vertices or vertices.

According to another feature of the invention, the tooth portion, the vertex or vertex may be narrower than the other portion.

According to another feature of the invention, the tooth portion may have a triangular shape, narrowing trapezoid, ellipse, or the tip is pointed like a needle.

According to another feature of the present invention, the liquid crystal display device may further include a data line and a gate line disposed in the display area and intersecting pixels.

According to another feature of the present invention, the link wiring may include a data link line connected to the data line and a gate link line connected to the gate line.

According to another feature of the invention, the thin film transistor may include an active layer made of an oxide semiconductor.

According to another feature of the invention, the liquid crystal display may further include a common electrode provided on the first protective layer of the display area.

According to another feature of the invention, the common electrode may have an opening around the trench.

According to another feature of the present invention, the opening may be provided in the trench region through which the link wiring does not pass.

According to another feature of the present invention, a plurality of trenches may be disposed in the non-display area.

According to another feature of the present invention, the trench may surround the display area.

According to another feature of the present invention, the trench may have a bar shape having a predetermined width with respect to one surface of the display area, and may have a rectangular frame shape surrounding four surfaces around the display area.

According to another feature of the invention, the first protective layer in the trench may be removed to expose the surface of the interlayer insulating layer below it.

According to another feature of the present invention, the liquid crystal display may further include a second protective layer disposed on the common electrode and a pixel electrode provided on the second protective layer of the display area.

A liquid crystal display according to another exemplary embodiment of the present invention includes a liquid crystal panel divided into a display area in which pixels are arranged in a matrix, a non-display area outside the display area, a thin film transistor provided in pixels, and a non-display area. A driver mounted in the area to drive the pixels, at least one link wiring disposed in the non-display area to transmit a signal to the pixel from the driver, a first protective layer made of OC under the link wiring, and a link wiring in the non-display area. The first protective layer may be disposed to pass through, and may include a trench for removing moisture in the display area and a sawtooth pattern formed in the trench to smooth the taper of the first protective layer.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: liquid crystal panel
108: common electrode
110: array substrate
115a: gate insulating layer
115b, 215b: interlayer insulating layer
115c, 115c ', 215c: first protective layer
115d: second protective layer
118: pixel electrode
131,132,232: link wiring
180,280: trench
285: tooth pattern
285a, 385a, 485a, 585a: tooth part
285b: body

Claims (20)

A liquid crystal panel divided into a display area in which pixels are arranged in a matrix and a non-display area outside the display area;
A thin film transistor provided in the pixels;
A driving unit mounted in the non-display area to drive the pixels;
At least one link wiring disposed in the non-display area to transfer a signal from the driver to the pixel;
A first protective layer formed of an overcoat (OC) under the link wiring;
A trench disposed in the non-display area so as to pass through the link wiring and having the first protective layer removed; And
It includes a sawtooth pattern provided in the trench,
The tooth pattern is composed of a body connecting the plurality of teeth and the bottom side of the tooth,
And the plurality of teeth have a taper that is gentler than that of the body. delete The method of claim 1,
And the sawtooth pattern is provided at a boundary portion of the trench through which the link wiring passes. The method of claim 1,
The sawtooth pattern is provided on both sides of the boundary of the trench. delete The method of claim 1,
And the tooth portion has one or more vertices or vertices. The method of claim 6,
And the tooth portion is narrower in width than the vertex or the vertex. The method of claim 1,
Wherein the tooth portion has a triangular shape, a narrow trapezoidal shape, an ellipse, or a pointed tip like a needle. The method according to any one of claims 1, 3, 4, 6 to 8,
And a data line and a gate line disposed in the display area and crossing the pixel to intersect the pixel. The method of claim 9,
The link line may include a data link line connected to the data line and a gate link line connected to the gate line. The method of claim 9,
The thin film transistor includes an active layer made of an oxide semiconductor. The method of claim 9,
And a common electrode on the first passivation layer of the display area. The method of claim 12,
And the common electrode has an opening around the trench. The method of claim 13,
And the opening is provided in the trench region where the link wiring does not pass. The method of claim 9,
And a plurality of trenches in the non-display area. The method of claim 9,
And the trench surrounds the periphery of the display area. The method of claim 9,
The trench has a bar shape having a predetermined width with respect to one surface of the display area, and has a rectangular frame shape surrounding four surfaces around the display area. The method of claim 9,
And the first protective layer in the trench is removed to expose a surface of an interlayer insulating layer underneath. The method of claim 12,
A second protective layer disposed on the common electrode; And
And a pixel electrode on the second passivation layer of the display area. A liquid crystal panel divided into a display area in which pixels are arranged in a matrix and a non-display area outside the display area;
A thin film transistor provided in the pixels;
A driving unit mounted in the non-display area to drive the pixels;
At least one link wiring disposed in the non-display area to transfer a signal from the driver to the pixel;
A first protective layer made of OC under the link wiring;
A trench disposed in the non-display area so as to pass the link wiring, and having the first protective layer removed to block moisture permeation into the display area; And
A tooth pattern provided in the trench to smooth the taper of the first protective layer;
The tooth pattern is composed of a body connecting the plurality of teeth and the bottom side of the tooth,
And the plurality of teeth have a taper that is gentler than that of the body.

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