KR20190078907A - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device according to an exemplary embodiment of the present invention is characterized in that when an oxide thin film transistor is applied as a switching element, a trench is formed around a display region to prevent the penetration of moisture into oxide semiconductor. In addition, the liquid crystal display device according to the embodiment of the present invention is characterized in that the number of masks is reduced by applying an OC (overcoat) layer instead of a PAC (photo acryl) layer, and at the same time the generation of a residual film caused by an OC step is prevented by forming a sawtooth pattern in an OC trench and smoothing a taper. The liquid crystal display device includes a liquid crystal panel, a thin film transistor, a driving part, a linking line, a first protection layer, and a trench.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device including an oxide thin film transistor as a switching device.

Generally, a liquid crystal display device is driven by using optical anisotropy and polarization properties of a liquid crystal. Liquid crystals are narrow and long in structure, so they have a directionality in the arrangement of molecules and can control the direction of the molecular arrangement by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Active matrix LCDs (AMLCDs), in which a thin film transistor (TFT) and a pixel electrode connected to a thin film transistor are arranged in a matrix manner, have been attracting attention because of their excellent resolution and video realization capability.

The liquid crystal display device includes an upper substrate on which a color filter, a common electrode, and the like are formed, a lower substrate on which switching elements and pixel electrodes are formed, and liquid crystal interposed between the two substrates. In such a liquid crystal display device, the liquid crystal is driven by an electric field that is vertically applied between the common electrode and the pixel electrode, and thus the characteristics such as the transmittance and the aperture ratio are excellent.

On the other hand, a general thin film transistor has used amorphous silicon as a semiconductor layer, but amorphous silicon has a slow electron transfer speed, so it has been difficult to realize a high resolution and a high driving ability in a very large screen. Therefore, an oxide thin film transistor having an electron transfer rate 10 times faster than that of amorphous silicon has appeared, and recently, it has attracted attention as a device suitable for high resolution of over UD (Ultra Definition) and high-speed driving of 240 Hz or more.

[Related Technical Literature]

1. An oxide thin film transistor array substrate and a manufacturing method thereof (Korean Patent Application No. 10-2011-0100901).

Recent oxide thin film transistors are suitable for high-resolution and high-speed driving because of their high electron mobility.

However, oxide semiconductors are sensitive to the external environment such as oxygen and moisture, and moisture, hydrogen, and oxygen react with the oxide semiconductor to change the carrier concentration, thereby affecting the characteristics and reliability of the device.

The inventors of the present invention have invented a new structure capable of blocking moisture permeation into the oxide semiconductor, taking into consideration that it is effective in preventing permeation of moisture by blocking the penetration of moisture outside the display region, and that moisture permeates along the organic layer .

That is, when an oxide thin film transistor is used as a switching element, a trench is formed in an organic layer around the display region, thereby preventing moisture permeation into the oxide semiconductor.

Accordingly, a problem to be solved by the present invention is to provide a liquid crystal display device capable of blocking moisture permeation into an oxide semiconductor in a display area.

The inventors of the present invention have also invented a new structure capable of reducing the number of masks by applying OC instead of PAC (photo acryl) in view of the fact that a mask process is not required for OC (overcoat).

Accordingly, another object of the present invention is to provide a liquid crystal display device capable of reducing the number of masks used in the manufacture of a liquid crystal display device.

On the other hand, when OC is used instead of PAC as an organic layer, there is a concern that the occurrence of a residual film of the transparent conductive film due to an abrupt taper increase in OC trenches. In this case, a pad short circuit may occur.

The inventors of the present invention have found that the taper is increased sharply in the process of forming the OC trench by removing the OC and that the occurrence of the residual film of the transparent conductive film is increased as the taper is increased and that the corner portion of the pattern is sharpened The inventors invented a new structure capable of preventing the occurrence of a residual film due to the OC step difference.

That is, by forming a sawtooth pattern in the OC trench and making the taper gentle, it is possible to prevent the occurrence of the residual film due to the OC step.

Accordingly, another object of the present invention is to provide a liquid crystal display device capable of preventing the occurrence of a residual film due to the OC step difference.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a liquid crystal display device including a liquid crystal panel divided into a display region in which pixels are arranged in a matrix form and a non-display region in a periphery of the display region, A driver for driving the pixels mounted on the non-display region, at least one link line disposed in the non-display region for transmitting a signal from the driver to the pixel, and a first protection formed of OC (overcoat) And a trench in which the first protective layer is removed, the trench being disposed across the link wiring in the non-display region and the non-display region.

According to another aspect of the present invention, there is provided a liquid crystal display device including a liquid crystal panel divided into a display region in which pixels are arranged in a matrix form and a non-display region in a periphery of the display region, A driving circuit for driving the pixels mounted in the non-display area, at least one link line arranged in the non-display area for transmitting a signal from the driver to the pixel, a first protective layer made of OC under the link line, A trench pattern that is disposed in the non-display area so as to pass through the link wiring and that is provided in the trench and the trench that cuts off the first protective layer and blocks the moisture permeation into the display area to smooth the taper of the first protective layer have.

The details of other embodiments are included in the detailed description and drawings.

The present invention can realize a high resolution and a high-speed driving capability in a very large screen by applying an oxide thin film transistor as a switching device. In addition, reliability of the oxide thin film transistor can be improved by blocking moisture permeation into the oxide semiconductor. In addition, the manufacturing cost can be reduced by reducing the number of masks used in manufacturing the array substrate. In addition, by preventing the occurrence of a residual film due to the OC step difference, human short circuiting can be prevented, and the yield can be improved.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a block diagram illustrating a structure of a liquid crystal display device according to an exemplary embodiment of the present invention.
2 is a plan view illustrating an exemplary liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 3 is a schematic view showing a part of a cross section of a display region in the liquid crystal display according to an embodiment of the present invention shown in FIG. 2. Referring to FIG.
FIG. 4 is a schematic plan view of a non-display region of a liquid crystal display according to an embodiment of the present invention shown in FIG. 2. Referring to FIG.
5A and 5B are views schematically showing a cross section cut along a line I-I 'in the liquid crystal display shown in FIG.
6 is a diagram schematically showing a planar part of a non-display region in a liquid crystal display according to another embodiment of the present invention.
FIGS. 7A and 7B are a plan view and a cross-sectional view illustrating, in an enlarged manner, a sawtooth pattern in an OC trench in a liquid crystal display device according to another embodiment of the present invention.
8A to 8D are plan views showing an example of the sawtooth pattern of the present invention.
FIGS. 9A and 9B are views schematically showing a cross-sectional structure of a sawtooth pattern in an OC trench in a liquid crystal display according to another embodiment of the present invention. FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

It will be understood that when an element or layer is referred to as being on another element or layer, it encompasses the case where it is directly on or intervening another element or intervening another element or element.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or entirely and technically various interlocking and driving is possible as will be appreciated by those skilled in the art, It may be possible to cooperate with each other in association.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a structure of a liquid crystal display device according to an exemplary embodiment of the present invention. 2 is a plan view illustrating an exemplary liquid crystal display device according to an exemplary embodiment of the present invention. FIG. 3 is a schematic view showing a part of a cross section of a FFS (Fringe Field Switching) mode display region in the liquid crystal display according to an embodiment of the present invention shown in FIG. However, the present invention is not limited to the FFS mode.

1 to 3, a liquid crystal display according to an exemplary embodiment of the present invention is roughly divided into a display area AA and a non-display area NA. In the display area AA, A liquid crystal panel 100 arranged in a matrix form and a backlight 170 disposed at a lower portion of the liquid crystal panel 100 to provide a light source and a non-display area NA of the liquid crystal panel 100, And a power supply unit 160. The power supply unit 160 may include a power supply unit and a power supply unit.

The driving unit may include a gate driving unit 140, a data driving unit 130 and a timing driving unit 150. The driving unit 140 may include a data signal and a data signal, respectively, to the data lines DL and the gate lines GL of the liquid crystal panel 100, A chip on glass (COG), and a tape carrier package (IC) are mounted on the liquid crystal panel 100 according to a method of mounting a driving IC on the liquid crystal panel 100. [ (Tape Carrier Package; TCP), and Chip On Film (COF). In addition, the driving unit may be formed on the liquid crystal panel 100 in the form of a GIP (Gate In Panel).

The timing driver 150 may receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK, and a data signal DATA.

The timing driver 150 generates a timing signal for driving the data driver 130 and the gate driver 140 using timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. The operation timing of the driving unit 140 can be controlled. On the other hand, the timing driver 150 can determine the frame period by counting the data enable signal DE in one horizontal period, so that the externally supplied vertical synchronizing signal Vsync and the horizontal synchronizing signal Hsync are omitted It is possible. The control signals generated by the timing driver 150 include a gate timing control signal GDC for controlling the operation timing of the gate driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130. [ ) May be included.

The gate timing control signal GDC may include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. The gate start pulse GSP may be supplied to a gate drive IC (Integrated Circuit) generating the first gate signal. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE can control the output of the gate drive ICs.

The data timing control signal DDC may include a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE) signal, and the like. The source start pulse SSP may control the data sampling start timing of the data driver 130. The source sampling clock SSC is a clock signal for controlling a sampling operation of data in the data driver 130 based on a rising or falling edge. The source output enable signal SOE can control the output of the data driver 130. Meanwhile, the source start pulse SSP supplied to the data driver 130 may be omitted depending on the data transfer mode.

The liquid crystal panel 100 includes a thin film transistor substrate 110 (hereinafter, referred to as an array substrate), a color filter substrate (not shown), and a liquid crystal layer interposed therebetween, . ≪ / RTI >

At this time, data lines DL, gate lines GL, TFTs, storage capacitors, and the like may be formed on the array substrate 110, and black matrices, color filters, and the like may be formed on the color filter substrate . At this time, one pixel SP may be defined by a data line DL and a gate line GL which cross each other.

One pixel SP includes a TFT driven by a gate signal supplied through a gate line GL, a storage capacitor for storing a data signal supplied through a data line DL as a data voltage, A liquid crystal cell driven by a liquid crystal cell may be included.

The liquid crystal cell can be driven by the data voltage supplied to the pixel electrode 118 and the common voltage supplied to the common electrode 108. [ The common electrode 108 is formed on a color filter substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. And may be formed on the array substrate 110 together with the pixel electrode 118 in the horizontal field driving method. And the common electrode 108 can receive a common voltage from the common voltage wiring 165. [

An alignment film may be formed on the array substrate 110 and the color filter substrate of the liquid crystal panel 100 constructed as described above to attach a polarizing plate and to set a pre-tilt angle of the liquid crystal. The liquid crystal mode of the liquid crystal panel 100 may be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, and FFS mode described above.

The gate driver 140 responds to the gate timing control signal GDC supplied from the timing driver 150 and supplies the signal SW to the gate driver 140 based on the swing width of the gate driving voltage at which the TFTs of the pixels SP included in the liquid crystal panel 100 are operable. The gate signal is sequentially generated while shifting the level of the gate signal. The gate driver 140 may supply a gate signal generated through the gate lines GL to the pixels SP included in the liquid crystal panel 100. [ As described above, the gate driver 140 may be mounted on the liquid crystal panel 100 in the form of an IC or may be formed on the liquid crystal panel 100 in the form of a GIP.

The data driver 130 samples and latches the data signal DATA supplied from the timing driver 150 in response to the data timing control signal DDC supplied from the timing driver 150, . ≪ / RTI > At this time, when converting into the data of the parallel data system, the data signal DATA can be converted into the gamma reference voltage. The data driver 130 may supply the data signal DATA converted through the data lines DL to the pixels SP included in the liquid crystal panel 100. [ The data driver 130 may be mounted on the liquid crystal panel 100 in the form of an IC or may be formed on the liquid crystal panel 100 in the form of a GIP.

The data link line 131 and the gate link line 132 connected to the data line DL and the gate line GL may be formed in the non-display area NA. A data pad and a gate pad may be connected to the ends of the data link line 131 and the gate link line 132, respectively.

The data pad and the gate pad may be respectively connected to the data driving IC and the gate driving IC mounted on the array substrate 110.

The data driving IC and the gate driving IC can be connected to an external printed circuit board through the FPC. The printed circuit board may include a timing driver 150 and a power supply 160. However, the present invention is not limited thereto.

The backlight unit 170 provides light to the liquid crystal panel 100. The backlight unit 170 may include a light source for emitting light, a light guide panel for guiding light to the liquid crystal panel 100, and an optical sheet for condensing and diffusing light.

The power supply unit 160 may convert the input power supply Vin supplied from the outside to a direct current power and output the common voltage Vcom, the first high voltage Vdd and the second high voltage Vcc. At this time, the common voltage Vcom is supplied to the common voltage wiring 165 while the first high voltage Vdd may be supplied to the gate driver 140 and the data driver 130 and the second high voltage Vcc may be supplied to the gate driver 140 and the data driver 130, May be supplied to the timing driver 150. The power supply unit 160 may be mounted on a printed circuit board connected to the liquid crystal panel 100.

2, the liquid crystal panel 100 may include an array substrate 110 divided into a display area AA and a non-display area NA around the display area AA.

The display area AA is defined as an area for displaying an image, and the non-display area NA is defined as a bezel area as a non-display area.

Pixels SP formed in a matrix shape may be formed in the display area AA. On the other hand, in the non-display area NA, various wirings such as the data link line 131, the gate link line 132, and the common voltage line 165, the gate driver 140, the data driver 130, May be formed.

Although the gate driver 140 is illustrated as being formed on both sides of the liquid crystal panel 100 in FIG. 2, the present invention is not limited thereto and may be formed on one side of the liquid crystal panel 100.

The data link line 131 is wired such that the data signals output from the data driver 130 are supplied to the data lines of the pixels SP and the gate link line 132 is connected to the gate lines And is supplied to the gate lines of the pixels SP. The common voltage wiring 165 is wired so that the common voltage output from the power supply portion is supplied to the common electrode of the pixels SP. The manner in which the data link line 131 and the gate link line 132 and the common voltage line 165 formed in the non-display area NA are connected to the data line, the gate line, and the common electrode formed in the display area AA are various So that the illustration and description thereof will be omitted. The connection unit 135 may be electrically connected to an external printed circuit board or the like such that various power and signals supplied from the outside are supplied to the driver, the common voltage wiring 165, and the like.

Hereinafter, the structure of the pixel SP will be described in more detail.

2 and 3, a liquid crystal display according to an embodiment of the present invention includes a display area AA as an area for displaying an image and a non-display area NA ).

In the display area AA, a plurality of gate lines and a plurality of data lines may be formed to intersect with each other to define a pixel area. In the pixel region, a thin film transistor is formed as a switching element, and a pixel electrode 118 and a common electrode 108 for forming an electric field can be formed.

A gate electrode 121 may be disposed on the array substrate 110 and a gate insulating layer 115a may be disposed on the gate electrode 121. [

The gate line may be arranged in the first direction on the same layer as the gate electrode 121. [

The gate electrode 121 and the gate line may be formed of a metal such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag) Au alloy, Au alloy, Cr alloy, Ti alloy, Ti alloy, MoW, MoTi, Cu / MoTi alloy, ), Or a combination of two or more thereof, or other suitable materials.

A gate insulating layer (115a), the silicon (Si) oxide film, a nitride film, or a metal oxide (metal oxide) containing compound, Al ₂ O ₃ comprising the same in the series, the organic insulating film, a low dielectric constant (low-k ) ≪ / RTI > value. For example, a gate insulating layer (115a), the silicon oxide (SiO _2), silicon nitride (SiNx), zirconium oxide (ZrO _2), hafnium oxide (HfO _2), titanium oxide (TiO _2), tantalum oxide (Ta ₂ O _5), barium-one selected from the group consisting of oxygen compounds (Bi-Zn-Nb-O ), - a strontium-titanium-oxygen compound (Ba-Sr-Ti-O ) and bismuth-zinc-niobium Or a combination of two or more thereof, or other suitable materials.

An active layer 124 is disposed on the gate insulating layer 115a and a drain electrode 123 spaced apart from the source electrode 122 and the source electrode 122 extending from the data line is disposed on the active layer 124 .

The data lines are arranged in a second direction intersecting with the first direction, so that the pixel regions can be defined along with the gate lines.

An ohmic contact layer 125 may be disposed on the active layer 124 to form ohmic contacts between the source and drain regions of the active layer 124 and the source and drain electrodes 122 and 123. The ohmic contact layer 125 is not formed in a region spaced apart from the source electrode 122 and the drain electrode 123. [

The active layer 124 may be patterned at the same time as the data line and the source / drain electrodes 122 and 123, for example, and may be patterned to have the same shape as the source / drain electrodes 122 and 123 in this case.

The active layer 124 according to an embodiment of the present invention may be formed of an oxide semiconductor.

As the oxide semiconductor, at least one material selected from the group consisting of germanium (Ge), tin (Sn), lead (Pb), indium (In), titanium (Ti), gallium (Ga) Zn) may be made of a material added with silicon (Si). For example, the active layer 124 may be made of silicon-indium zinc (Si-InZnO: SIZO) to which silicon ions are added to the indium zinc composite oxide (InZnO).

In the case where the active layer 124 is made of SIZO, the composition ratio of the silicon (Si) atom content to the total content of zinc (Zn), indium (In) and silicon (Si) atoms in the active layer 124 is about 0.001 wt% wt%) to about 30 wt%. The higher the silicon (Si) atom content is, the stronger the role of controlling electron generation is, and the lower the mobility, the better the stability of the device.

Examples of the oxide semiconductor include a group I element such as lithium (Li) or potassium (K), a group II element such as magnesium (Mg), calcium (Ca), or strontium (Sr), a group II element such as gallium Group III elements such as aluminum (Al), indium (In) or yttrium (Y), Group IV elements such as titanium (Ti), zirconium (Zr), silicon (Si), tin (Sn) or germanium (Ge) Such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), or a Group V element such as tantalum (Ta), vanadium (V), niobium (Nb) (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium And lanthanum (Ln) -based elements such as Lu and the like.

The source / drain electrodes 122 and 123 and the data line may be formed of a metal such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Mo) A metal alloy such as Ag alloy, Au, Au alloy, Cr, Ti, Ti alloy, MoW, MoTi, (Cu / MoTi), or a combination of two or more thereof, or other suitable material.

The interlayer insulating layer 115b may be disposed on the array substrate 110 including the source / drain electrodes 122 and 123 and the data lines.

The common electrode 108 may be disposed on the interlayer insulating layer 115b.

The interlayer insulating layer 115b may be formed of a silicon oxide-based oxide film, a nitride film or a compound containing the same, a metal oxide including Al ₂ O ₃ , an organic insulating film, a low dielectric constant (low-k) As shown in FIG. For example, the inter-layer insulation layer (115b) is a silicon oxide (SiO _2), silicon nitride (SiNx), zirconium oxide (ZrO _2), hafnium oxide (HfO _2), titanium oxide (TiO _2), tantalum oxide (Ta ₂ O _5), barium-one selected from the group consisting of oxygen compounds (Bi-Zn-Nb-O ), - a strontium-titanium-oxygen compound (Ba-Sr-Ti-O ) and bismuth-zinc-niobium Or a combination of two or more thereof, or other suitable materials.

A first protective layer 115c having a low dielectric constant may be additionally disposed between the interlayer insulating layer 115b and the common electrode 108. [ The first protective layer 115c may be formed of an organic insulating material having a low dielectric constant such as PAC (photo acryl) or OC (overcoat) to prevent coupling between the data line and the common electrode 108 have.

The common electrode 108 may be formed of a transparent metal material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

The common electrode 108 may have a plate shape in the pixel region, but may have a first opening in a predetermined region. The first opening may be formed in the contact hole region where the drain electrode 123 is exposed. This is to prevent a short from occurring in the electrical connection between the drain electrode 123 and the pixel electrode 118 through the contact hole. That is, if the common electrode 108 does not have the first opening, a short circuit occurs between the common electrode 108 and the pixel electrode 118 during the electrical connection between the pixel electrode 118 and the drain electrode 123 To prevent this, the common electrode 108 may be provided with a first opening in the contact hole region.

In addition, the common electrode 108 may have a second opening in the thin film transistor region. This is because when the common electrode 108 is formed in the thin film transistor region, it may interfere with the movement of electrons in the channel region of the active layer 124. Therefore, it is preferable that the second opening is formed in a region above the spaced-apart region between the source electrode 122 and the drain electrode 123 in the thin film transistor region.

Further, the common electrode 108 may have a third opening in the non-display area. The third opening may be provided in the trench 180 region described later.

And the second protective layer 115d may be disposed on the common electrode 108. [

A second protection layer (115d) is a metal oxide (metal oxide), an organic insulating film, a low dielectric constant (low-k) that contains the compound and, Al ₂ O ₃ containing oxide film, a nitride film, or it of the silicon (Si) series Value. ≪ / RTI > In one embodiment, the second protection layer (115d) is a silicon oxide (SiO _2), silicon nitride (SiNx), zirconium oxide (ZrO _2), hafnium oxide (HfO _2), titanium oxide (TiO _2), tantalum oxide ( Ta ₂ O _5), barium-strontium-titanium-one selected from the group consisting of oxygen compounds (Bi-Zn-Nb-O ) - oxygen compound (Ba-Sr-Ti-O ) and bismuth-zinc-niobium , Or a combination of two or more thereof, or other suitable materials.

And the pixel electrode 118 may be disposed on the second passivation layer 115d.

The pixel electrode 118 may be formed of a transparent metal material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

At this time, the pixel electrode 118 may be connected to the drain electrode 123 through the contact hole. The contact hole may be formed in a predetermined region of the interlayer insulating layer 115b and the first passivation layer 115c and the second passivation layer 115d so that the drain electrode 123 is exposed.

A plurality of slits 118s may be provided in the pixel electrode 118 to form a fringe field together with the common electrode 108. [

As described above, in the liquid crystal display device according to the embodiment of the present invention, the trench 180 is provided in the non-display area NA outside the display area AA to prevent the penetration of moisture into the display area AA .

That is, oxide semiconductors are sensitive to the external environment such as oxygen and moisture, and moisture, hydrogen, and oxygen react with the oxide semiconductor to change the carrier concentration, thereby affecting the characteristics and reliability of the device.

In view of the fact that moisture permeation along the first protective layer 115c, which is an organic layer, is effective in preventing moisture permeation by blocking moisture penetration outside the display area AA, Discloses a new structure capable of blocking the moisture permeation to the semiconductor.

That is, in one embodiment of the present invention, when an oxide thin film transistor is used as a switching element, a trench 180 is formed in the non-display area NA outside the display area AA so as to surround the display area AA Thereby blocking the moisture permeation of the oxide semiconductor, that is, the active layer 124 of the oxide thin film transistor.

In the embodiment of the present invention, it is noted that OC is not required to perform a mask process for patterning, and OC is applied instead of PAC to form the first protective layer 115c, thereby reducing the number of masks .

FIG. 4 is a schematic plan view of a non-display region of a liquid crystal display according to an embodiment of the present invention shown in FIG. 2. Referring to FIG. 5A and 5B are views schematically showing a cross section cut along a line I-I 'in the liquid crystal display shown in FIG.

4 illustrates an A portion of the non-display area NA through which the gate link line 132 passes in the liquid crystal display according to the embodiment of the present invention shown in FIG. Therefore, only the gate link line 132 will be described below, but the present invention is not limited thereto, and the same can be applied to the data link line 131 as well.

5A and 5B show an example in which the first protective layers 115c 'and 115c are formed of PAC and OC, respectively, in the liquid crystal display device shown in FIG.

Referring to FIG. 4 and FIGS. 5A and 5B, the gate insulating layer 115a and the interlayer insulating layer 115b may be disposed on the array substrate 110 of the non-display area NA .

A gate insulating layer (115a) and the inter-layer insulation layer (115b) is silicon (Si) oxide film, a nitride film, or a metal oxide (metal oxide) containing compound, Al ₂ O ₃ comprising the same in the series, the organic insulating film, a low dielectric And may include a material having a low-k value. For example, a gate insulating layer (115a) and the inter-layer insulation layer (115b), silicon oxide (SiO _2), silicon nitride (SiNx), zirconium oxide (ZrO _2), hafnium oxide (HfO _2), titanium oxide (TiO ₂ A group consisting of tantalum oxide (Ta ₂ O ₅ ), barium-strontium-titanium-oxygen compound (Ba-Sr-Ti-O) and bismuth-zinc-niobium-oxygen compound (Bi-Zn-Nb-O) , Or a combination of two or more thereof, or other suitable materials.

The first passivation layers 115c 'and 115c including the trenches 180 may be disposed on the interlayer insulating layer 115b.

In this case, the first protective layer 115c 'of FIG. 5A may be formed of PAC, and the first protective layer 115c of FIG. 5B may be formed of OC.

As described above, the first protective layers 115c 'and 115c according to an embodiment of the present invention are formed of PAC or OC having a low dielectric constant between the interlayer insulating layer 115b and the common electrode 108, And can prevent coupling between the common electrodes 108. FIG.

The trenches 180 may be arranged in a plurality of non-display areas NA outside the display area AA.

The trenches 180 may be arranged to surround the periphery of the display area AA.

The trench 180 may have a bar shape having a predetermined width with respect to one surface of the display area AA. Accordingly, the trench 180 may have a rectangular frame shape surrounding four sides around the display area AA.

The first passivation layers 115c 'and 115c in the trench 180 may be removed to expose the surface of the interlayer insulating layer 115b.

A common electrode 108 having a third opening O on the first passivation layer 115c ', 115c may be disposed.

The common electrode 108 may be formed of a transparent metal material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

As described above, the common electrode 108 may have a plate shape in the pixel region, but it may have a first opening and a second opening in a predetermined region. The first opening may be formed in the contact hole region where the drain electrode is exposed. This is to prevent a short in the electrical connection between the drain electrode and the pixel electrode 118 through the contact hole.

In addition, the common electrode 108 may have a second opening in the thin film transistor region. This is because, when the common electrode 108 is formed in the thin film transistor region, it may interfere with movement of electrons in the channel region of the active layer. Therefore, it is preferable that the second opening is formed in a region above the spaced-apart region between the source electrode and the drain electrode in the thin film transistor region.

For example, the third opening O may be provided in the trench 180 region where the data link line 131 and the gate link line 132 do not pass. This is because the third opening O is formed in the trench 180 region where the data link line 131 and the gate link line 132 do not pass and the common electrode 108 is removed, In order to block the penetration of moisture from the water. The area of the trench 180 through which the data link line 131 and the gate link line 132 pass is longer due to the longer penetration path of moisture through the common electrode 108 by the plurality of trenches 180, Can be suppressed.

And the second protective layer 115d may be disposed on the common electrode 108. [

A second protection layer (115d) is a metal oxide (metal oxide), an organic insulating film, a low dielectric constant (low-k) that contains the compound and, Al ₂ O ₃ containing oxide film, a nitride film, or it of the silicon (Si) series Value. ≪ / RTI > In one embodiment, the second protection layer (115d) is a silicon oxide (SiO _2), silicon nitride (SiNx), zirconium oxide (ZrO _2), hafnium oxide (HfO _2), titanium oxide (TiO _2), tantalum oxide ( Ta ₂ O _5), barium-strontium-titanium-one selected from the group consisting of oxygen compounds (Bi-Zn-Nb-O ) - oxygen compound (Ba-Sr-Ti-O ) and bismuth-zinc-niobium , Or a combination of two or more thereof, or other suitable materials.

The pixel electrode and the link wiring of the data link line 131 and the gate link line 132 may be disposed on the second protective layer 115d.

The pixel electrode, the data link line 131 and the gate link line 132 may be formed of a transparent metal material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or the like.

Referring to FIG. 5A, when the PAC is applied to the organic layer, the first passivation layer 115 'in the trench 180 may be patterned to have a gentle slope. However, there is a disadvantage in that a mask process is added to the patterning of the first passivation layer 115 'for forming the trench 180.

On the other hand, when OC is used instead of PAC as an organic layer, a mask process is not added. However, referring to FIG. 5B, the first passivation layer 115 in the trench 180 is patterned to have a sharp inclination. That is, in this case, it can be seen that the OC trench 180 is formed and the taper increases abruptly.

When OC is used instead of PAC as the organic layer, there is an advantage that the number of masks is reduced. However, there is a fear that the residual film R "of the transparent conductive film due to an abrupt taper increase in the OC trench 180 is generated. In this case, a short circuit may occur between the link lines of the data link line 131 and the gate link line 132. That is, when the taper is abrupt, due to the step of the first protective layer 115 'in the trench 180, The transparent conductive film for the data link line 131 and the gate link line 132 to be formed later is not removed but remains as a residual film R ". If these residual films R "are connected to each other, a short circuit between neighboring link wirings may occur.

5A, a residual film R 'of the transparent conductive film may be generated in the PAC trench 180, but the residual film R' is not generated to such an extent that a short circuit between the link wirings is generated due to a gentle taper .

Another object of the present invention is to provide a method of manufacturing a semiconductor device, which is characterized in that a taper is rapidly increased in the process of forming an OC trench by removing an OC, that the occurrence of a remainder of a transparent conductive film increases with an increase in taper, The taper may become gentle when it is formed into a pointed shape, and a new structure capable of preventing the occurrence of a residual film due to the OC step difference is disclosed.

6 is a diagram schematically showing a planar part of a non-display region in a liquid crystal display according to another embodiment of the present invention. 7A and 7B are a plan view and a cross-sectional view showing, in an enlarged scale, a tooth pattern in an OC trench in a liquid crystal display device according to another embodiment of the present invention. 8A to 8D are plan views showing an example of the sawtooth pattern of the present invention.

6 illustrates a portion of the non-display region through which the gate link line 232 passes in the liquid crystal display device according to another embodiment of the present invention. Therefore, only the gate link line 232 will be described below, but the present invention is not limited thereto, and the same can be applied to the data link line.

7A and 7B are enlarged views of one tooth pattern 285 in the OC trench 280 in the liquid crystal display according to another embodiment of the present invention shown in FIG. FIG. 7B schematically shows a cross section cut along a line II-II 'of the sawtooth pattern 285 shown in FIG. 7A.

Referring to FIG. 6 and FIGS. 7A and 7B, a gate insulating layer 215a and an interlayer insulating layer 215b may be disposed on an array substrate 210 in a non-display region.

Further, a first protective layer 215c including a trench 280 may be disposed on the interlayer insulating layer 215b.

At this time, the first protective layer 215c may be composed of OC.

As described above, the first passivation layer 215c according to another embodiment of the present invention is composed of OC having a low dielectric constant between the interlayer insulating layer 215b and the common electrode, and the coupling between the data line and the common electrode coupling can be prevented.

The plurality of trenches 280 may be disposed in the non-display area outside the display area.

The trenches 280 may be arranged to surround the periphery of the display area.

The trench 280 may have a bar shape with a predetermined width for one side of the display area. Thus, the trenches 280 may have the shape of a square frame surrounding four sides around the display area.

The first protective layer 215c in the trench 280 may be removed to expose a part of the surface of the interlayer insulating layer 215b.

Although not shown, a common electrode having a third opening may be disposed on the first passivation layer 215c.

As in the embodiment of the present invention described above, the third opening may be provided in the trench 280 region where the link wiring of the data link line and the gate link line 232 does not pass. This is because the third opening is formed in the region of the trench 280 where the link wiring does not pass and the common electrode is removed to partially block moisture penetration from the outside through the common electrode. In addition, as the penetration path of water through the common electrode is actually extended by the plurality of trenches 280 in the region of the trench 280 where the data link line and the gate link line 232 pass, moisture penetration can be suppressed.

And the second protective layer 215d may be disposed on the common electrode.

The pixel electrode and the data link line and the link wiring of the gate link line 232 may be disposed on the second protective layer 215d.

According to another embodiment of the present invention, there is an advantage that a mask process is not added by applying OC to an organic layer instead of a PAC. Another embodiment of the present invention is characterized in that a sawtooth pattern 285 is formed in the trench 280 to gently taper the first protective layer 215c to prevent the occurrence of a residual film due to the OC step do.

The sawtooth pattern 285 may be provided at the boundary of the trench 280 where the data link line and the gate link line 232 do not pass the link wiring.

The sawtooth pattern 285 may be provided on both sides of the boundary of the trench 280.

The sawtooth pattern 285 may be composed of a plurality of teeth 285a and a single body 285b connecting the base of the plurality of teeth 285a.

The teeth 285a may have a vertex or apex.

Teeth 285a may have one or more vertices.

The apex or apex of the tooth 285a is characterized by a narrower width than other portions.

The corner portion of the tooth 285a is an area in which the OC dry etching is overlapped on both sides, and an effect of gentler taper (see arrow in Fig. 7B) occurs. It is possible to prevent a short circuit between the link wirings due to the residual film of the transparent conductive film due to the gentle taper.

It can be seen that a part of the residual film remains at the edge of the tooth 285a, but no residual film exists at the apex or apex.

FIG. 7A illustrates an example in which the tooth portion 285a has a triangular shape, but the present invention is not limited thereto. 8A to 8D, the teeth 285a, 385a, 485a and 585a may have various shapes such as a triangular shape, a trapezoid having a narrow width, a ellipse, and a pointed end like a needle. The tooth portions 285a, 385a, 485a, and 585a may vary in size, shape, or inclination of the inclined surface.

That is, regardless of the size or shape of the teeth 285a, 385a, 485a, and 585a, the present invention is applicable to a case in which the vertex or apex is narrower than other portions. Further, the present invention is applicable to a case where the width of the vertex or vertex is narrower than the other portions regardless of the inclination of the inclined surfaces of the teeth 285a, 385a, 485a, and 585a. In this case, it can be seen that the residual film is improved regardless of the size and shape of the teeth 285a, 385a, 485a, and 585a. In addition, when the tooth 285a has a triangular shape as shown in FIG. 8D, it can be seen that the smaller the angle of the apex angle, the better the improvement of the residual film. This is because as the angle of the apex angle is smaller, the taper becomes gentler and the PR becomes flat.

In the embodiment of the present invention and another embodiment, the interval between the teeth portions 285a, 385a, 485a, and 585a is about 20 占 퐉. However, the present invention is not limited thereto. The invention is applicable regardless of the spacing between the serrations 285a, 385a, 485a, 585a.

The improvement of the residual film by the sawtooth pattern 285 is judged to be an effect of the PR flattening of the teeth 285a in addition to the effect of softening the taper by the teeth 285a.

FIGS. 9A and 9B are views schematically showing a cross-sectional structure of a sawtooth pattern in an OC trench in a liquid crystal display according to another embodiment of the present invention. FIG.

9A is a cross-sectional view taken along a line II-II 'of the tooth portion 285a of the illustrated sawtooth pattern 285 shown in FIG. 7A, and FIG. 9B is a cross- Sectional view taken along the line III-III 'of the body 285b of the sawtooth pattern 285 is shown as an example.

9A and 9B, a gate insulating layer 215a and an interlayer insulating layer 215b may be disposed on an array substrate 210 in a non-display area.

Further, a first protective layer 215c including a trench may be disposed on the interlayer insulating layer 215b.

At this time, the first protective layer 215c may be composed of OC.

As described above, the first passivation layer 215c according to another embodiment of the present invention is composed of OC having a low dielectric constant between the interlayer insulating layer 215b and the common electrode, and the coupling between the data line and the common electrode coupling can be prevented.

As described above, the trenches can be arranged in plural in the non-display area outside the display area.

The trench may be arranged to surround the periphery of the display area.

The trench may have a bar shape with a predetermined width for one side of the display area. Thus, the trench may have a rectangular frame shape surrounding four sides around the display area.

The first protective layer 215c in the trench can be removed and a part of the surface of the interlayer insulating layer 215b can be exposed.

Although not shown, a common electrode 208 having a third opening may be disposed on the first passivation layer 215c.

As in the above-described embodiment of the present invention, for example, the third opening may be provided in the trench region where the link wiring of the data link line and the gate link line does not pass. This is because a third opening is formed in the trench region where the link wiring does not pass and the common electrode 208 is removed to partially block moisture penetration from the outside through the common electrode 208. [ In addition, the trench region through which the data link line and the gate link line pass can be prevented from penetrating moisture as a penetration path of moisture through the common electrode 208 becomes longer by a plurality of trenches.

And the second protective layer 215d may be disposed on the common electrode 208. [

At this time, the pixel electrode, the data link line, and the gate link line may be disposed on the second passivation layer 215d. To this end, the transparent conductive layer 206 and the PR may be stacked on the second passivation layer 215d.

In this case, according to another embodiment of the present invention, since OC is used instead of PAC as an organic layer, there is an advantage that a mask process is not added. Another embodiment of the present invention is characterized in that a sawtooth pattern is formed in the trench so that the taper of the first protective layer 215c is made gentle, thereby preventing the occurrence of a residual film due to the OC step.

The sawtooth pattern may be provided at the boundary of the trench where the link wiring of the data link line and the gate link line does not pass.

The sawtooth pattern may be provided on both sides of the boundary portion of the trench.

The sawtooth pattern may be composed of a single body 285b (see FIG. 9B) connecting a plurality of teeth 285a (see FIG. 9A) and a base of a plurality of teeth 285a.

The teeth 285a may have a vertex or apex.

Teeth 285a may have one or more vertices.

The apex or apex of the tooth 285a is characterized by a narrower width than other portions.

The edge portion of the tooth 285a is an area where the OC dry etching is overlapped on both sides, and the effect of tapering the taper is generated. It is possible to prevent a short circuit between the link wirings due to the residual film of the transparent conductive film due to the gentle taper.

Referring to FIG. 9A, it can be seen that the thickness d1 of the teeth 285a becomes thinner due to planarization of the PR per se compared with the body 285b. That is, it can be seen that the residual film of the transparent conductive film 206 is improved due to the reduction of the edge PR thickness d1 of the tooth 285a.

On the other hand, referring to FIG. 9B, it can be seen that the PR thickness d2 is increased by the OC step in the body 285b, and as a result, a residual film of the transparent conductive film 206 is generated due to PR remaining during development.

An exemplary embodiment of the present invention can be described as follows.

A liquid crystal display device according to an embodiment of the present invention includes a liquid crystal panel divided into a display region in which pixels are arranged in a matrix form and a non-display region in a periphery of the display region, a thin film transistor provided in the pixels, A first protective layer disposed in the non-display area and formed of OC (overcoat) under the link wiring, at least one link wiring disposed in the non-display area for transmitting a signal from the driver to the pixel, And may include a trench in which the first passivation layer is removed.

According to another aspect of the present invention, the liquid crystal display may further include a sawtooth pattern provided in the trench.

According to another aspect of the present invention, the sawtooth pattern may be provided at the boundary portion of the trench through which the link wiring does not pass.

According to another aspect of the present invention, the sawtooth pattern may be provided on both sides of the boundary of the trench.

According to still another aspect of the present invention, the sawtooth pattern may be constituted by one body connecting the plurality of teeth and the base of the teeth.

According to another aspect of the invention, the serrations can have one or more vertices or vertices.

According to another aspect of the present invention, the serrations may be narrower in width than the vertex or apex portion.

According to another aspect of the present invention, the serrations may have a triangular shape, a narrow trapezoid, an ellipse, or a pointed shape like a needle.

According to still another aspect of the present invention, a liquid crystal display device may further include a data line and a gate line disposed in a display area and intersecting with each other to define pixels.

According to another aspect of the present invention, the link wiring may include a data link line connected to the data line and a gate link line connected to the gate line.

According to another aspect of the present invention, the thin film transistor may include an active layer made of an oxide semiconductor.

According to another aspect of the present invention, the liquid crystal display may further include a common electrode provided on the first protective layer of the display area.

According to another aspect of the present invention, the common electrode may have an opening around the trench.

According to still another aspect of the present invention, the opening may be provided in a trench region where the link wiring does not pass.

According to another aspect of the present invention, the plurality of trenches may be disposed in the non-display region.

According to another aspect of the present invention, the trench may surround the periphery of the display region.

According to another aspect of the present invention, the trench may have a bar shape having a predetermined width with respect to one side of the display area, and may have a rectangular frame shape surrounding four sides around the display area.

According to another aspect of the present invention, the first protective layer in the trench can be removed to expose the surface of the interlayer insulating layer under the trench.

According to another aspect of the present invention, the liquid crystal display may further include a second passivation layer disposed on the common electrode and a pixel electrode provided on the second passivation layer of the display area.

According to another aspect of the present invention, there is provided a liquid crystal display device including a liquid crystal panel divided into a display region in which pixels are arranged in a matrix form and a non-display region in a periphery of the display region, a thin film transistor provided in the pixels, At least one link wiring disposed in a non-display area for transferring a signal from the driver to the pixel, a first protection layer made of OC below the link wiring, and a link wiring in the non-display area And a sawtooth pattern that is provided in the trench and the trench that blocks the moisture permeation into the display area by removing the first protective layer and smoothes the taper of the first protective layer.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: liquid crystal panel
108: common electrode
110: array substrate
115a: Gate insulating layer
115b and 215b: an interlayer insulating layer
115c, 115c ', and 215c:
115d: second protective layer
118:
131, 132, 232:
180,280: Trench
285: sawtooth pattern
285a, 385a, 485a, 585a:
285b: Body

Claims (20)

A liquid crystal panel divided into a display area in which pixels are arranged in a matrix form and a non-display area in the outside of the display area;
A thin film transistor provided in the pixels;
A driving unit mounted on the non-display area to drive the pixels;
At least one link wiring disposed in the non-display area and transmitting a signal from the driver to the pixel;
A first protective layer made of OC (overcoat) under the link wiring; And
And a trench in which the first protective layer is removed so as to pass through the link wiring in the non-display area. The method according to claim 1,
And a sawtooth pattern provided in the trench. 3. The method of claim 2,
Wherein the sawtooth pattern is provided at a boundary portion of the trench not passing through the link wiring. 3. The method of claim 2,
Wherein the sawtooth pattern is provided on both sides of the boundary of the trench. 3. The method of claim 2,
Wherein the sawtooth pattern is constituted by one body connecting a plurality of serrations and a base of the serrations. 6. The method of claim 5,
Wherein the toothed portion has at least one vertex or vertex. The method according to claim 6,
Wherein the serrations have narrower widths than the vertexes or the vertexes. 6. The method of claim 5,
Wherein the toothed portion has a triangular shape, a narrow trapezoid, an ellipse, or a sharp end like a needle. 9. The method according to any one of claims 1 to 8,
And a data line and a gate line which are arranged in the display region and which intersect and divide the pixel. 10. The method of claim 9,
Wherein the link wiring includes a data link line connected to the data line and a gate link line connected to the gate line. 10. The method of claim 9,
Wherein the thin film transistor includes an active layer made of an oxide semiconductor. 10. The method of claim 9,
And a common electrode provided on the first protective layer of the display region. 13. The method of claim 12,
And the common electrode has an opening around the trench. 14. The method of claim 13,
Wherein the opening is provided in the trench region where the link wiring does not pass. 10. The method of claim 9,
And the plurality of trenches are arranged in the non-display region. 10. The method of claim 9,
And the trench surrounds the periphery of the display region. 10. The method of claim 9,
Wherein the trench has a bar shape having a predetermined width with respect to one surface of the display region and has a rectangular frame shape surrounding four sides around the display region. 10. The method of claim 9,
Wherein the first protective layer in the trench is removed to expose the surface of the lower interlayer insulating layer. 13. The method of claim 12,
A second protective layer disposed on the common electrode; And
And a pixel electrode provided on the second protective layer of the display region. A liquid crystal panel divided into a display area in which pixels are arranged in a matrix form and a non-display area in the outside of the display area;
A thin film transistor provided in the pixels;
A driving unit mounted on the non-display area to drive the pixels;
At least one link wiring disposed in the non-display area and transmitting a signal from the driver to the pixel;
A first protective layer made of OC under the link wiring;
A trench that is disposed in the non-display area so as to pass through the link wiring, and the first protection layer is removed to block moisture permeation into the display area; And
And a sawtooth pattern provided in the trench to smooth the taper of the first protective layer.

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