KR102056670B1 - Mother substrate for thin film transistor array substrate - Google Patents

Abstract

In an exemplary embodiment of the present invention, a mother substrate for a thin film transistor array substrate includes: a gate line formed in a direction crossing each other to define a display area and a non-display area, and define a plurality of pixel areas corresponding to the display area; A data line, a plurality of thin film transistors formed in an intersection region between the gate line and the data line, corresponding to the plurality of pixel regions, and a plurality of thin film transistors formed corresponding to the plurality of pixel regions, and connected to the plurality of thin film transistors. A plurality of effective portions each including a plurality of pixel electrodes; And first and second peripheral wires formed on the first surface of the substrate, the first and second peripheral wires being formed around the respective effective portions, wherein the gate line is the first metal film on the one surface of the substrate. The gate line and the first peripheral line are formed to be disconnected from the first peripheral line, and the gate line and the first peripheral line are respectively covered with at least one insulating layer covering the first metal layer, and the first jump line is formed on the at least one insulating layer. Provided is a mother substrate for a thin film transistor array substrate to be connected.

Description

MOTHER SUBSTRATE FOR THIN FILM TRANSISTOR ARRAY SUBSTRATE}

The present invention relates to a mother substrate for a thin film transistor array substrate, and more particularly, to a mother substrate capable of improving the yield of a flat panel display device.

As the information age enters full swing, the display field for visually displaying electrical information signals is rapidly developing. Accordingly, researches for developing performances such as thinning, weight reduction, and low power consumption for various flat panel display devices have been continued.

Representative examples of such flat panel displays include liquid crystal displays (LCDs), plasma display panels (PDPs), field emission display devices (FEDs), and electroluminescent displays. Electroluminescent display device (ELD), electro-wetting display device (EWD), and organic light emitting display device (OLED). Such flat panel display devices commonly include a flat panel display panel for realizing an image. A flat panel display panel is a structure in which a pair of substrates facing each other with a unique light emitting material or a polarizing material interposed therebetween.

In general, a flat panel display of an active matrix driving mode includes a thin film transistor array substrate for driving each of a plurality of pixel regions independently.

The thin film transistor array substrate may include: a gate line and a data line formed in an intersecting direction to define a plurality of pixel areas corresponding to the display area, a plurality of thin film transistors formed corresponding to the plurality of pixel areas in the intersection area thereof; And a plurality of pixel electrodes corresponding to the plurality of pixel regions and connected to the plurality of thin film transistors. Accordingly, the thin film transistor array substrate may include a gate line, a data line, a gate electrode of the thin film transistor, a source electrode and a drain electrode, at least two metal patterns corresponding to the pixel electrodes, and at least one insulating layer insulating the metal patterns. It is formed into a thin film structure containing.

In manufacturing such a flat panel display device, in order to improve the yield, it is common to form a plurality of thin film transistor array substrates simultaneously using a large area substrate.

That is, a general method of manufacturing a thin film transistor array substrate may include forming a mother substrate including a plurality of thin film transistor array substrates (hereinafter, referred to as “substrate parts”) and peripheral wiring parts connected to the plurality of substrate parts. After forming a cover substrate to be opposed to each of the substrate portion, and separating the plurality of substrate portion of the mother substrate individually.

Here, the peripheral wiring unit includes a first peripheral wiring connected to gate lines of each substrate part and a second peripheral wiring connected to data lines of each substrate. The peripheral wiring portion is provided for shielding or releasing static electricity flowing into each substrate portion during the formation of the mother substrate, or for performing defect inspection on the plurality of substrate portions after forming the mother substrate.

The separating of the plurality of substrate portions individually includes forming a scribing line corresponding to an edge of each substrate portion, and separating the plurality of substrate portions individually using the scribing line.

1A to 1C are process diagrams illustrating a process of separating a plurality of substrate parts individually in a general mother substrate.

As shown in FIG. 1A, a thin film structure 12 corresponding to the substrate portion 10A and the peripheral wiring portion 10B is formed on one surface of the substrate 11. In this case, the thin film structure 12 includes a metal layer 12a corresponding to the substrate portion 10A and the peripheral wiring portion 10B on one surface of the substrate 11.

For example, one portion of the metal layer 12a corresponding to the substrate portion 10A may be a gate line, and the other portion corresponding to the peripheral wiring portion 10B may be a first peripheral wiring connected to the gate line.

After the mother substrate 10 is formed in this way, the scribing device 20 is used to form the scribing line SL corresponding to the edge of each substrate portion 10A on the other surface of the substrate 11. Form. Here, the scribing line SL is a groove for generating a vertical crack corresponding to the edge of each substrate portion 10A.

As illustrated in FIG. 1B, an external force is applied to the substrate 11 on which the scribing line SL is formed to generate a crack 13 corresponding to the scribing line SL. In this case, the crack 13 is formed in the vertical direction X toward the light emitting structure 12 in the scribing line SL to separate the substrate 10A and the peripheral wiring 10B.

However, since the mother substrate 10 includes peripheral wiring parts 10B connected to each of the substrate parts 10A, the scribing line SL and the metal layer 12a intersect with each other.

Accordingly, the crack 13 by the scribing line SL extends in the vertical direction X in the substrate 11, but when the crack 13 is adjacent to the metal layer 12a formed on one surface of the substrate 11, the substrate 13. It also extends in the horizontal direction Y to avoid the metal layer 12a having a higher tensile strength than (11).

Therefore, as shown in FIG. 1C, in the substrate portion 10A separated from the mother substrate 10, the thin film structure 12 is formed by the crack 13 including the vertical direction X and the horizontal direction Y. FIG. Chipping defects may occur.

As described above, the general mother substrate includes a scribing line SL that intersects the metal layer 12a formed on one surface of the substrate 11 so that cracks in the vertical direction X and the horizontal direction Y are prevented. Thereby, there arises a problem that chipping defects occur in the substrate portion 10A.

Thereby, the uniformity and reliability of each board | substrate part 10A fall, and there exists a problem that there exists a limit in yield improvement. In addition, since the bezel of the flat panel display device including the thin film transistor array substrate must be provided to a width that is not affected by the chipping defect, there is a problem in that the bezel width is reduced by the chipping defect.

The present invention is to provide a mother substrate for a thin film transistor array substrate and a method for manufacturing the thin film transistor array substrate can reduce the chipping defects, improve the yield of the thin film transistor array substrate.

In order to solve this problem, the present application is a mother substrate for a thin film transistor array substrate, the display area and the non-display area are each defined, and formed in a direction crossing each other to define a plurality of pixel areas corresponding to the display area. A plurality of thin film transistors formed at intersections between the gate lines and the data lines, corresponding to the gate lines and the data lines, and the plurality of pixel regions, and the plurality of thin film transistors. A plurality of effective portions each including a plurality of pixel electrodes connected to the transistors; And first and second peripheral wires formed on the first surface of the substrate, the first and second peripheral wires being formed around the respective effective portions, wherein the gate line is the first metal film on the one surface of the substrate. The gate line and the first peripheral line are formed to be disconnected from the first peripheral line, and the gate line and the first peripheral line are respectively covered with at least one insulating layer covering the first metal layer, and the first jump line is formed on the at least one insulating layer. Provided is a mother substrate for a thin film transistor array substrate to be connected.

The mother substrate for a thin film transistor array substrate according to an exemplary embodiment of the present disclosure may include a first peripheral line formed to be disconnected from the gate line on the same layer as the gate line of each effective portion, and at least one covering the gate line and the first peripheral line, respectively. And a first jump wire formed on the insulating film.

As such, as the metal pattern is removed from the crack generation region due to the scribing line, cracking in the horizontal direction due to the metal pattern can be prevented, thereby reducing chipping defects and improving yield.

1A to 1C are process diagrams illustrating a process of separating a plurality of substrate parts individually in a general mother substrate.
2 is a schematic diagram of a mother substrate for a thin film transistor array substrate according to an embodiment of the present application.
3 is a schematic diagram illustrating a first valid part of FIG. 2.
4 is a cross-sectional view illustrating the thin film transistor of FIG. 3.
FIG. 5 is a cross-sectional view illustrating part I of FIG. 3.
FIG. 6 is a cross-sectional view illustrating part II of FIG. 3.

Hereinafter, a mother substrate for a thin film transistor array substrate according to each embodiment of the present application will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic diagram of a mother substrate for a thin film transistor array substrate according to an exemplary embodiment of the present disclosure, and FIG. 3 is a schematic diagram illustrating a first effective part of FIG. 2. 4 is a cross-sectional view illustrating the thin film transistor of FIG. 3, FIG. 5 is a cross-sectional view illustrating part I of FIG. 3, and FIG. 6 is a cross-sectional view illustrating part II of FIG. 3.

As shown in FIG. 2, the mother substrate 100 for a thin film transistor array substrate according to an exemplary embodiment of the present disclosure includes a plurality of effective portions AA1, AA2, AA3, and AA4 arranged in a matrix, and a plurality of effective portions, respectively. It includes an outer periphery OA.

Each of the effective parts AA1, AA2, AA3, AA4 defines a display area that emits light to display an image by emitting light, and a non-display area that is outside the display area.

The peripheral portion OA is formed at the periphery of each of the plurality of effective portions AA1, AA2, AA3, AA4 and connected to each of the plurality of effective portions AA1, AA2, AA3, AA4, and the peripheral portion OL. The peripheral pad part OP connected to the wiring part OL is included.

As shown in FIG. 3, the first effective portion AA1 of the plurality of valid portions AA1, AA2, AA3, and AA4 is formed in a direction crossing each other to define a plurality of pixel regions corresponding to the display region. A plurality of thin film transistors TFT formed at an intersection area between the gate line GL and the data line DL to correspond to the line GL and the data line DL, and the plurality of pixel areas, and the plurality of pixel areas. And a plurality of pixel electrodes PE formed correspondingly and connected to the plurality of thin film transistors TFT.

The first valid portion AA1 further includes a gate pad GP formed corresponding to one end of each gate line GL, and a data pad DP formed corresponding to one end of each data line DL. Include.

The first valid part AA1 further includes a test gate line TGL connected to each gate line GL, and a test data line TDL connected to each data line DL.

Each of the first and second peripheral wires OL1 and OL2 is formed in the peripheral portion OA as a first metal film on one surface of the substrate.

In this case, the first peripheral line OL1 is disposed to face the gate pad DP with the scribing line SL1 of the first effective portion AA1 interposed therebetween.

Like the first peripheral line OL1, the gate line GL is formed of a first metal film on one surface of the substrate, and is disconnected from the first peripheral line OL1. In addition, the gate extension line GL ′, which is an extension line of the gate line GL extending from the gate pad GP to the first peripheral line OL1, may be formed of the first metal layer and the first peripheral line OL1. It is formed to be disconnected.

In this case, each of the gate extension line GL ′ and the first peripheral line OL1 is formed to be spaced apart from the scribing line SL1 of the first valid portion AA1 at predetermined intervals. As a result, the gate extension line GL ′ and the gate line GL subsequent thereto are formed to be disconnected from the first peripheral line OL1.

The first peripheral line OL1 is connected to the gate extension line GL 'and the subsequent gate line GL through the first jump line JL1 formed on at least one insulating layer covering the first metal layer. do.

Similarly, the second peripheral line OL2 is disposed to face the data pad DP with the scribing line SL1 of the first effective portion AA1 interposed therebetween.

The data line DL is formed of a second metal film on the gate insulating film covering the first metal film. In addition, the data extension line DL ′ of FIG. 6, which is an extension line of the data line DL extending from the data pad DP to the second peripheral line OL2, is a first metal layer, and the second peripheral line OL2. It is formed to be disconnected.

In this case, each of the data extension line DL 'and the second peripheral line OL2 is formed to be spaced apart from the scribing line SL1 of the first valid portion AA1 at predetermined intervals. As a result, the data extension line DL ′ and the data line DL subsequent thereto are formed to be disconnected from the second peripheral line OL2.

The second peripheral line OL2 is connected to the data extension line DL ′ and the data line DL subsequent thereto through the second jump line JL2 formed on at least one insulating layer covering the first metal layer. .

In addition, the test gate line TGL is connected to the gate extension line GL ′ between the gate pad GP and the scribing line SL1.

The test data line TDL is connected to a data extension line DL ′ between the data pad DP and the scribing line SL1.

The test gate wiring TGL and the test data wiring TDL are provided for the defective test of the effective unit AA.

As shown in FIG. 4, the thin film transistor TFT corresponding to each pixel region is a first metal film formed on the substrate 101 and branched from the gate line GL in FIG. 3. On the gate insulating film 110 covering the gate electrode GL on the entire surface of the substrate 101, the active layer ACT formed to overlap at least a portion of the gate electrode GL and the gate insulating film 110. As a second metal film, a source electrode SE which is branched from the data line (DL in FIG. 3) and overlaps on one side of the active layer ACT, and as a second metal film on the gate insulating film 110, The drain electrode DE is spaced apart from the electrode SE and is formed to overlap on the other side of the active layer ACT.

The thin film transistor TFT is covered with the first and second interlayer insulating films 121 and 122.

That is, the first interlayer insulating layer 121 is formed on the gate insulating layer 110 to cover each of the data line DL, the active layer ACT, the source electrode SE, and the drain electrode DE. In this case, the first interlayer insulating layer 121 may be formed of silicon oxide (SiOx) or silicon nitride (SiNx).

The second interlayer insulating film 122 is formed on the first interlayer insulating film 121 to cover the first interlayer insulating film 121. In this case, the second interlayer insulating film 122 may be photo acryl.

In addition, the pixel electrode PX corresponding to each pixel region may pass through the thin film transistor through the pixel contact hole CT_PE passing through the first and second interlayer insulating layers 121 and 122 to expose a portion of the drain electrode DE. It is connected to the drain electrode DE of the TFT.

The common electrode CE corresponding to the plurality of pixel regions may be further formed on the second interlayer insulating layer 122 together with the pixel electrode PE. In this case, in each pixel area, the pixel electrode PE and the common electrode CE may be alternately disposed.

Next, referring to FIGS. 5 and 6, the first and second jump wires JL1 and JL2 according to the exemplary embodiment of the present application will be described in more detail.

As illustrated in FIG. 5, the gate line GL, the first gate pad layer GP1, and the gate extension line GL ′ corresponding to the first effective portion AA1 may be formed of a first metal on one surface of the substrate 101. Film 131. Here, the gate line GL, the first gate pad layer GP1, and the gate extension line GL 'are subsequent metal patterns.

The first peripheral wire OL1 corresponding to the peripheral portion OA is also formed of the first metal film 131 on one surface of the substrate 101. Here, the first peripheral line OL1 is a metal pattern disconnected from the gate extension line GL '.

The gate extension line GL ′ and the first peripheral line OL1 are regions where cracks are generated by the scribing line SL1. That is, each of the gate extension line GL 'and the first peripheral line OL1 is spaced apart from the scribing line SL1 at a predetermined interval based on the horizontal direction. In this case, the separation distance between each of the gate extension line GL ′ and the first peripheral line OL1 formed of the first metal layer 131 and the scribing line SL1 may include a horizontal crack generation region. Μm to 500 μm.

The gate insulating layer 110 is formed on the entire surface of the substrate 101 to cover each of the gate line GL, the first gate pad layer GP1, the gate extension line GL ′, and the first peripheral line OL1. .

The first and second interlayer insulating films 121 and 122 are sequentially stacked on the gate insulating film 110.

The first jump wiring JL1 is formed on the second interlayer insulating film 122. At this time, before forming the first jump line JL1, the first and second interlayer insulating films 121 and 122 and the gate insulating film are exposed to expose portions of the gate extension line GL ′ and the first peripheral line OL1, respectively. The first contact hole CT1 and the second contact hole CT2 penetrating the 110 are formed.

The first jump wiring JL1 is formed to include the first and second contact holes CT1 and CT2 on the second interlayer insulating film 122, thereby forming the first and second contact holes CT1 and CT2. The gate extension line GL 'and the first peripheral line OL1 are connected to each other to connect the gate extension line GL' and the first peripheral line OL1.

In addition, the gate pad GP may not only be formed on the first gate pad GP1 but also on the second gate pad layer GP2 formed of the second metal film on the gate insulating film 110, and the second interlayer insulating film 122. It may further include at least one of the third gate pad layer GP3 formed.

As illustrated in FIG. 6, the data line DL corresponding to the first effective portion AA1 is formed of the second metal film 132 on the gate insulating layer 110.

The data pad DP is formed of the first data pad layer DP1 formed of the first metal film 131 on one surface of the substrate 101 and the second metal film 132 formed on the gate insulating film 110. 2 includes a data pad layer DP2. The data pad DP may further include a third data pad layer DP3 formed on the second interlayer insulating film 122.

The data extension line DL 'extends the first data pad layer DP1 toward the second peripheral line OL2 and is formed of the first metal film 131 on the substrate 101. In this case, the data extension line DL 'and the second peripheral line OL2 are metal patterns that are disconnected from each other.

The data extension line DL 'and the second peripheral line OL2 are areas where cracks are generated by the scribing line SL1. That is, each of the data extension line DL ′ and the second peripheral line OL2 is spaced apart from the scribing line SL1 at a predetermined interval based on the horizontal direction. In this case, the distance between each of the data extension line DL ′ and the second peripheral line OL2 formed of the first metal layer 131 and the scribing line SL1 is 200 μm to include a horizontal crack generation region. ˜500 μm.

The second jump wiring JL2 is formed on the second interlayer insulating film. In this case, before forming the second jump line JL2, the first and second interlayer insulating films 121 and 122 and the gate may be exposed to expose portions of each of the data extension line DL ′ and the second peripheral line OL2. Third and fourth contact holes CT3 and CT4 are formed through the insulating layer 110.

The second jump wiring JL2 is formed to include the third and fourth contact holes CT3 and CT4 on the second interlayer insulating film 122, thereby forming the third and fourth contact holes CT3 and CT4. The data extension line DL 'and the second peripheral line OL2 are connected to each other, thereby connecting the data extension line DL' and the second peripheral line OL2.

As described above, according to the exemplary embodiment of the present disclosure, the metal pattern in which the gate extension line GL 'and the first peripheral line OL1 connected to the gate line GL are disconnected from each other with the scribing line SL1 interposed therebetween. The data extension line DL ′ and the second peripheral line OL2 subsequent to the data line DL are formed of a metal pattern that is disconnected from each other with the scribing line SL1 interposed therebetween. That is, the first metal film 131 is not formed in the crack generation region by the scribing line SL1. Therefore, when cracks are formed to individually separate the plurality of thin film transistor array substrates AA1, AA2, AA3, and AA4 formed on the mother substrate 100, cracks in the vertical direction are generated along the scribing line SL1. The crack in the horizontal direction due to the first metal film 131 may be prevented.

As a result, in the process of separately separating the plurality of effective portions AA1, AA2, AA3, and AA4 formed on the mother substrate 100, chipping defects of the effective portions due to cracks in the horizontal direction may be reduced. The yield of can be improved.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is conventional in the art that various substitutions, modifications and changes are possible within the scope without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

100: mother substrate for a thin film transistor array substrate
AA1, AA2, AA3, AA4: first, second, third, fourth effective portion
OA: Peripheral OL: Peripheral Wiring
OP: Peripheral pad part
GL: Gateline DL: Dataline
TFT: thin film transistor PE: pixel electrode
GP: Gatepad DP: Datapad
OL1: 1st peripheral wiring OL2: 2nd peripheral wiring
JL1: first jump wiring JL2: second jump wiring
TGL: Test Gate Wiring TDL: Test Data Wiring

Claims (8)

In the mother substrate for a thin film transistor array substrate,
A display area and a non-display area, each of which is defined to have a gate line and a data line intersecting to define a plurality of pixel areas corresponding to the display area, and corresponding to the plurality of pixel areas; A plurality of effective portions formed in a plurality of thin film transistors formed at intersections between data lines, and a plurality of pixel electrodes formed corresponding to the plurality of pixel regions, respectively, and connected to the plurality of thin film transistors;
First and second peripheral wirings formed on the outer surface of each of the plurality of effective portions by a first metal film on one surface of the substrate;
A gate extension line formed in each of the plurality of effective parts, the gate extension line being formed of the first metal layer, connected to the gate line, and disconnected from the first peripheral line;
A data extension line formed in each of the plurality of effective parts, the data line being formed of the first metal film, electrically connected to the data line, and disconnected from the second peripheral line;
A first contact hole covering the first metal layer, exposing a portion of the gate extension line, a second contact hole exposing a portion of the first peripheral line, and a third contact hole exposing a portion of the data extension line And at least one insulating layer including a fourth contact hole exposing a portion of the second peripheral line.
A first jump wire disposed on the at least one insulating layer and connected between the gate extension line and the first peripheral wire through the first contact hole and the second contact hole; And
A mother substrate for a thin film transistor array substrate, the second substrate being disposed on the at least one insulating layer and including a second jump line connecting the data extension line and the second peripheral line through the third contact hole and the fourth contact hole. . The method of claim 1,
Each of the plurality of effective portions
The mother substrate for a thin film transistor array substrate further comprising a gate pad formed between one end of the gate line and the gate extension line. The method of claim 2,
The data line is a second metal film on the gate insulating film covering the first metal film, the mother substrate for a thin film transistor array substrate. The method of claim 3, wherein
Each of the plurality of effective portions
The mother substrate for a thin film transistor array substrate further comprising a data pad formed between one end of the data line and the data extension line. The method of claim 4, wherein
Each of the plurality of effective portions
A test gate line formed between the gate pad and the first peripheral line and connected to the gate line, and
And a test data line formed between the data pad and the second peripheral line and connected to the data line. The method of claim 1,
Further comprising a scribing line corresponding to the edge of each of the plurality of effective portions,
The scribing line is spaced apart from each of the gate extension line, the data extension line, and the first and second peripheral lines formed of the first metal layer, and crosses the first jump line and the second jump line. A mother substrate for a thin film transistor array substrate. The method of claim 6,
And a separation distance between the scribing line and the first metal layer is 200 to 500 μm. The method of claim 1,
Each of the plurality of thin film transistors
A gate electrode formed of the first metal layer so as to be connected to the gate line corresponding to each pixel area;
An active layer formed on the gate insulating layer covering the first metal layer to overlap at least a portion of the gate electrode;
A source electrode formed to overlap one side of the active layer and connected to the data line; And
A drain electrode spaced apart from the source electrode and overlapping the other side of the active layer;
Each of the plurality of pixel electrodes,
On at least one interlayer insulating film covering the data line, the active layer, the source electrode, and the drain electrode, corresponding to each pixel area;
The mother substrate for a thin film transistor array substrate of which the first jump wiring and the second jump wiring are on the same layer as the pixel electrode.

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