TWI706393B - Array substrate - Google Patents

Abstract

An array substrate includes a substrate and data lines, scan lines, pixel units, at least one first data signal transmission line and at least one second data signal transmission line on the substrate. The scan lines cross the data lines. Each pixel unit is electrically connected to the data line and the scan line. The first data signal transmission line crosses the scan lines. The second data signal transmission line crosses the data line. The first data signal transmission line is electrically connected to the second data signal transmission line through a first data through hole. The second data signal transmission line is electrically connected to the data line through a second data through hole.

Description

Array substrate

The disclosure relates to an array substrate.

With the advancement of science and technology, the technology of displays has also been continuously developed. For example, the types of displays include liquid crystal displays (LCD), organic light emitting displays (OLED), and electrophoretic displays (EPD), and are widely used in various electronic products, such as smart phones, notebook computers, and tablet computers, etc. .

In order to reduce the cost of the manufacturing process, the cost of masks of different sizes can be avoided by cutting large-size displays to obtain various small-size displays. The element configuration of the large-size rectangular display can be that several source driving circuits are arranged on the upper and lower sides of the display, and several gate driving circuits are arranged on the left and right sides of the display to achieve the effect of arbitrarily cutting. In recent years, the application of displays has been extended to wearable displays, public signs and other fields, making the demand for non-rectangular displays grow rapidly. Generally speaking, the gate drive circuit and the source drive circuit of the circular display are arranged along the circumference. If you want to cut the large circular display to obtain various small circular displays, the circular cutting line will cut The connection between the gate drive circuit and the source drive circuit and the circuit of the display is broken, so that part of the display cannot be displayed normally.

The present disclosure provides an array substrate, which can achieve the advantage of flexible non-rectangular cutting size of the non-rectangular array substrate.

The array substrate disclosed in the present disclosure includes a substrate and a plurality of data lines, a plurality of scan lines, a plurality of pixel units, at least one first data signal transmission line and at least one second data signal transmission line arranged on the substrate. The scan line intersects the data line. Each pixel unit is electrically connected to the data line and the scan line. The first data signal transmission line intersects the scan line. The second data signal transmission line is arranged on the substrate and intersects the data line. The first data signal transmission line is electrically connected to the second data signal transmission line through the first data through hole. The second data signal transmission line is electrically connected to the data line through the second data via.

The array substrate disclosed in the present disclosure includes a substrate and a plurality of data lines, a plurality of scan lines, a plurality of pixel units and at least one scan signal transmission line arranged on the substrate. The substrate has an active area and a peripheral area surrounding the active area. The scan line intersects the data line. Each pixel unit is electrically connected to the data line and the scan line. The scanning signal transmission line intersects the scanning line. The scanning signal transmission line and the scanning line are electrically connected through the scanning through hole, and the scanning through hole is located in the peripheral area.

The array substrate of the present disclosure includes a substrate and a plurality of data lines, a plurality of scan lines, a plurality of pixel units and at least one first data signal transmission line arranged on the substrate. The substrate has an active area and a peripheral area surrounding the active area. The active area has a first pixel area and a second pixel area located on two opposite sides of the first pixel area, and the substrate defines a center line passing through the center of the substrate. The center line passes through the first pixel area, and there is an interval between the center line and the second pixel area along the first direction. The data line extends along a second direction, and the second direction intersects the first direction. Scan line Extend in the first direction. Each pixel unit is electrically connected to the data line and the scan line. The first data signal transmission line is located in the first pixel area and extends along the second direction. The first data signal transmission line is not located in the second pixel area. The first data signal transmission line and the second data signal transmission line are electrically connected through the first data via.

The array substrate of the present disclosure includes a substrate and a plurality of data lines, a plurality of scan lines, a plurality of pixel units, at least one first scan signal transmission line and at least one second scan signal transmission line arranged on the substrate. The substrate defines a first reference line extending along the first direction and a second reference line extending along the second direction. The first direction is substantially perpendicular to the second direction. The first reference line and the second reference line partition the substrate into a first sub-region, a second sub-region, a third sub-region, and a fourth sub-region. The data line is substantially parallel to the second direction. The scan line is substantially parallel to the first direction. Each pixel unit is electrically connected to the data line and the scan line. The first scanning signal transmission line is substantially parallel to the second direction. The first scan signal transmission line and the scan line are electrically connected through the first scan through hole. The second scanning signal transmission line is substantially parallel to the first direction. The second scan signal transmission line and the scan line are electrically connected through the second scan through hole.

Based on the above, in the array substrate of the present disclosure, by arranging the first data signal transmission line and the second data signal transmission line, the data signal transmission effect and the advantages of flexibility of the non-rectangular cutting size of the array substrate are achieved. Moreover, by providing the scanning signal transmission line, the effect of transmitting the scanning signal and the flexibility of the non-rectangular cutting size of the array substrate are achieved.

100, 100’, 100”, 100a, 100b, 100c, 100d‧‧‧Array substrate

102‧‧‧Substrate

104‧‧‧Source drive circuit

104a‧‧‧First group

104b‧‧‧The second group

106‧‧‧Gate drive circuit

106a‧‧‧The first group

106b‧‧‧The second group

108’、108”‧‧‧Pre-cutting line

110‧‧‧First data signal transmission line

112‧‧‧Second data signal transmission line

114‧‧‧First scan signal transmission line

116‧‧‧Auxiliary Line

118‧‧‧Second scan signal transmission line

120‧‧‧Bridge connection

200, 202, 204‧‧‧ direction

300, 302‧‧‧ direction

400, 402, 404‧‧‧ direction

600, 602‧‧‧ direction

AA, AA’, AA"‧‧‧active area

Section A-A‧‧‧

BL1‧‧‧First Baseline

BL2‧‧‧Second Baseline

BTH‧‧‧Bridge through hole

C‧‧‧Center

CL‧‧‧Centerline

D1‧‧‧First direction

D2‧‧‧Second direction

DL‧‧‧Data line

DTH1‧‧‧First data through hole

DTH2‧‧‧Second data through hole

FR‧‧‧Wiring area

IN‧‧‧Insulation layer

NA, NA’, NA"‧‧‧ Surrounding area

P1‧‧‧The first pixel area

P2‧‧‧Second pixel area

P3‧‧‧The third pixel area

P4‧‧‧Fourth pixel area

PE‧‧‧Pixel electrode

PE1‧‧‧The first pixel electrode

PE2‧‧‧Second pixel electrode

PU‧‧‧Pixel unit

PU1‧‧‧First sub-pixel

PU2‧‧‧Second sub-pixel

S1‧‧‧Interval

SL‧‧‧Scan line

SL1‧‧‧First scan line

SL2‧‧‧Second scan line

SR1‧‧‧First subregion

SR2‧‧‧Second subregion

SR3‧‧‧The third subregion

SR4‧‧‧The fourth subregion

STH1‧‧‧First scan through hole

STH2‧‧‧Second scan through hole

T‧‧‧Thin Film Transistor

T1‧‧‧The first thin film transistor

T2‧‧‧Second thin film transistor

Read the following detailed description and match the corresponding diagrams to understand this Multiple aspects of disclosure. It should be noted that many of the features in the drawing are not drawn in actual proportions according to the standard practice in the industry. In fact, the size of the feature can be increased or decreased arbitrarily to facilitate the clarity of the discussion.

1A and 1B are schematic top views of an array substrate according to an embodiment of the disclosure.

Fig. 1C is an enlarged schematic diagram of area R in Fig. 1B.

Figure 1D is a schematic cross-sectional view of Figure 1C along the section line A-A.

FIG. 1E shows a schematic top view of the scan line and the first scan signal transmission line of FIG. 1C on the array substrate.

2A and 2B are schematic top views of an array substrate according to another embodiment of the disclosure.

FIG. 3 is a schematic top view of an array substrate according to another embodiment of the disclosure.

4A and 4B are schematic top views of an array substrate according to another embodiment of the disclosure.

FIG. 5 is a schematic top view of an array substrate according to another embodiment of the disclosure.

The following will clearly illustrate the spirit of the present disclosure with drawings and detailed descriptions. Anyone with ordinary knowledge in the relevant technical field can change and modify the techniques taught in the present disclosure after understanding the embodiments of the present disclosure. Depart from the spirit and scope of this disclosure. For example, the statement "the first feature is formed on or on the second feature" will include the first feature and the second feature in the embodiment Have direct contact; and also include the first feature and the second feature as indirect contact, with additional features formed between the first feature and the second feature. In addition, the present disclosure will reuse component numbers and/or text in multiple examples. The purpose of repetition is to simplify and clarify, and it does not determine the relationship between multiple embodiments and/or the discussed configurations.

In addition, relative terms such as "below", "below", "below", "above" or "up" or similar terms are used in this article to facilitate the description of the words shown in the diagram The relationship of one element or feature to another element or feature. In addition to describing the position of the device in the diagram, the relative position vocabulary includes the different positions of the device under use or operation. When the device is additionally set (rotated by 90 degrees or other facing orientation), the relative terms of the orientation used in this article can also be explained accordingly.

1A and 1B are schematic top views of an array substrate 100 according to an embodiment of the disclosure. The difference between Fig. 1B and Fig. 1A is that Fig. 1B also shows a pre-cut line 108' and a pre-cut line 108". Please refer to Fig. 1A and Fig. 1B at the same time, the array substrate 100 of the disclosed embodiment includes a substrate 102. The source drive circuit 104 and the gate drive circuit 106. The source drive circuit 104 and the gate drive circuit 106 are arranged on one side of the array substrate 100. It should be noted that the source drive circuit depicted in the figure in this specification The numbers of 104 and gate drive circuits 106 are only used to illustrate the present disclosure, but not to limit the present disclosure. In other embodiments, the numbers of source drive circuits 104 and gate drive circuits 106 may also be other appropriate numbers .

The shape of the substrate 102 is non-rectangular, and in this embodiment, the shape of the substrate 102 is circular. The substrate 102 has an active area AA and surrounds the active area AA The surrounding area NA. The array substrate 100 can be cut along the pre-cut line 108', thereby obtaining a non-rectangular array substrate 100' with a reduced size. The array substrate 100' has a corresponding active area AA' and a peripheral area NA surrounding the active area AA' '. Or the array substrate 100 can be cut along the pre-cut line 108" to obtain a non-rectangular array substrate 100" with another reduced size. The array substrate 100" has a corresponding active area AA" and a surrounding active area AA" The surrounding area NA". In this embodiment, the pre-cut lines 108', 108" are non-rectangular. For example, the pre-cut lines 108', 108" are circular. In one embodiment, the substrate 102 is a transparent substrate. For example, the material of the substrate 102 may include glass.

For the convenience of description, the figure shows the first direction D1 and the second direction D2, and the first direction D1 and the second direction D2 are different, for example, the first direction D1 and the second direction D2 are respectively the 1A and 1B The horizontal and vertical directions of the figure are orthogonal to each other. The active area AA has a first pixel area P1 and a second pixel area P2 located on two opposite sides of the first pixel area P1. The first pixel area P1 is closer to the center of the array substrate 100 than the second pixel area P2 C. In other words, the substrate 102 defines a center line CL, the center line CL passes through the center C of the array substrate 100, the gate driving circuit 106, and the source driving circuit 104, the center line CL passes through the first pixel region P1, and the center line CL and the There is a minimum interval S1 between the two-pixel area P2 along the first direction D1. The peripheral area NA also includes a wiring area FR. The wiring area FR is located between the source driving circuit 104 and the first pixel area P1. Fan-out lines (not shown) are provided in the wiring area FR. The first pixel area P1 and the second pixel area P2 are electrically connected to the gate driving circuit 106 and the source driving circuit 104 through a fan-out line.

Figure 1C is an enlarged schematic view of area R in Figure 1B, Figure 1D is a schematic cross-sectional view of Figure 1C along the section line A-A, please refer to Figure 1B, Figure 1C and Figure 1D. The area R covers the first pixel area P1 and the second pixel area P2. The first pixel area P1 includes a plurality of data lines DL, a plurality of scan lines SL, a plurality of pixel units PU, at least one first data signal transmission line 110, at least one second data signal transmission line 112, At least one first scan signal transmission line 114 and auxiliary line 116. The second pixel area P2 includes a plurality of data lines DL, a plurality of scan lines SL, a plurality of pixel units PU, at least one second data signal transmission line 112, and at least one first scan signal transmission line 114 disposed on the substrate 102. In other words, the first data signal transmission line 110 and the auxiliary line 116 are not located in the second pixel area P2. Each pixel unit PU is electrically connected to the data line DL and the scan line SL. The pixel units PU are arranged in an array along the first direction D1 and the second direction D2, and each pixel unit PU includes a plurality of thin film transistors T and a plurality of pixel electrodes PE electrically connected to each other. In addition, the pixel unit PU may include one or more capacitors (not shown), and the capacitors may be electrically connected to the thin film transistor T and/or the pixel electrode PE.

The data line DL intersects the scan line SL. In this embodiment, the scan line SL and the second data signal transmission line 112 extend along the first direction D1, the data line DL, the first data signal transmission line 110, the auxiliary line 116, and the first The scan signal transmission line 114 extends along the second direction D2. The scan line SL and the second data signal transmission line 112 are formed by the first patterned conductive layer on the substrate 102. The data line DL, the first data signal transmission line 110, the auxiliary line 116, and the first scan signal transmission line 114 are formed on the substrate 102. The second patterned conductive layer above is formed, wherein the first patterned conductive layer and the second patterned conductive layer are located in different layers. There is an insulating layer IN between the first patterned conductive layer and the second patterned conductive layer.

The first data signal transmission line 110 intersects the scan line SL and the second The data signal transmission line 112. The first data signal transmission line 110 is electrically connected to the second data signal transmission line 112 through the first data via DTH1. The second data signal transmission line 112 is electrically connected to the data line DL through the second data through hole DTH2. In this way, even if the data line DL located in the second pixel area P2 is cut off by the pre-cut lines 108', 108", the data signal from the source driving circuit 104 can still pass through the first data signal transmission line 110, the second The data signal transmission line 112 and the data line DL transfer the data signal to the pixel unit PU of the second pixel area P2, thereby achieving the advantage that the non-rectangular array substrate 100 can be arbitrarily cut to obtain the array substrate 100 of different non-rectangular sizes. That is, the array substrate 100 of circular size can be arbitrarily cut to obtain the advantages of the array substrate 100 having a reduced circular size. In this embodiment, each data line DL located in the second pixel area P2 is matched with one The first data signal transmission line 110 and the second data signal transmission line 112, that is, the number of the first data signal transmission line 110 is the same as the number of the second data signal transmission line 112, so as to achieve the effect of transmitting the data signal.

The data signals transmitted by two adjacent data lines DL have different potential polarities, which means that the data signals transmitted by the local 2M+1 data lines DL (odd-numbered data lines DL) have positive potentials, and the 2M-th data line DL (even-numbered data lines) The data signal transmitted by the data line DL) is negative, and vice versa, where M is a positive integer. Between the auxiliary line 116 and one of the adjacent data lines DL (for example, the data line DL on the right side of the auxiliary line 116), there is a first data signal transmission line 110, the auxiliary line 116 and another adjacent data line DL (for example, the auxiliary line 116). There is a pixel unit PU between the data lines DL on the left. In this embodiment, the auxiliary line 116 is electrically connected to the adjacent data line DL (that is, the data line DL on the left side of the auxiliary line 116), in other words, the auxiliary line 116 The potential of and the potential of the adjacent data line DL have the same polarity. So one In this way, the capacitive coupling effect (Couple Effect) between the first data signal transmission lines 110 can be avoided to interfere with the data line DL, and the potential difference of the data line DL is fixed, so that the pixel unit PU presents the required gray scale.

For illustration, FIG. 1E shows a schematic top view of the scan line SL and the first scan signal transmission line 114 of FIG. 1C on the array substrate 100. For clarity, FIG. 1E omits the depiction of other circuit elements (such as data lines DL, The first data signal transmission line 110, the second data signal transmission line 112 and the source drive circuit 104). Please refer to Figure 1E and Figure 1C at the same time. In this embodiment, the array substrate 100 adopts the gate driving circuit 106 to perform a single-side single-drive scanning method. The first scan signal transmission line 114 and the scan line SL are electrically connected to each other through the first scan through hole STH1. Pre-cut lines 108' and 108" are defined on the substrate 102, as described above, and will not be repeated here. When the array substrate 100 is cut along the pre-cut line 108' to obtain the array substrate 100', a part of the first scanning through holes STH1 is located in the peripheral area NA', and another part of the first scanning through hole STH1 is located in the active area AA'. When the array substrate 100 is cut along the pre-cut line 108" to obtain the array substrate 100", a part of the first scanning through hole STH1 is located The peripheral area NA", and the other part of the first scan through hole STH1 is located in the active area AA". By arranging the first scan signal transmission line 114, even if the pre-cut lines 108', 108" cut the scan line SL, the gate driving circuit 106 The gate signal of φ can still be sequentially transmitted to the corresponding pixel unit PU via the first scan signal transmission line 114 and the scan line SL.

2A and 2B are schematic top views of an array substrate 100a according to another embodiment of the disclosure. The difference between Figures 2A and 2B and Figure 1E is that the gate drive circuit 106 in Figures 2A and 2B is a double gate drive circuit. The array substrate 100a adopts a double-sided double drive scanning method, and the wiring area FR is located on the array substrate. The peripheral area NA on the upper side and the peripheral area NA on the lower side of 100a. In this way, the position of the pre-cut lines 108', 108" can be close to the gate driving circuit 106 on the upper side or the gate driving circuit 106 on the lower side. In this way, the non-rectangular shape of the non-rectangular array substrate 100a can be achieved. The advantage of cutting size flexibility, that is, the circular array substrate 100a can be arbitrarily cut to obtain the advantages of the array substrate 100a having different circular sizes.

FIG. 3 is a schematic top view of an array substrate 100b according to another embodiment of the disclosure. Please refer to FIG. 3, the array substrate 100b is an array substrate 100b driven by a tri gate structure. The pixel unit PU is arranged in an active element (such as a thin film transistor T) electrically connected to the same data line DL. ) Is arranged alternately on both sides of the data line DL along the row direction (ie, the second direction D2). The source driving circuit 104 (not shown) drives the array substrate 100b in a row inversion manner. Under this structure, The number of scan lines SL increases, the number of data lines DL decreases, and the number of source driver circuits 104 also decreases, which can reduce power consumption and save costs. The number of first data signal transmission lines 110 is the number of second data signal transmission lines 112 Tripled. The array substrate 100b further includes a bridge line 120 extending along the first direction D1, and the bridge line 120 intersects the first scan signal transmission line 114. In this embodiment, the bridge line 120 and the scan line SL are the same film layer. The bridge line 120 is electrically connected to the data line DL through the bridge via hole BTH, so that the data signal of the source driving circuit 104 (not shown) is transmitted to some pixel units PU through the data line DL and the bridge line 120 to achieve the transmission The effect of the data signal.

4A and 4B are schematic top views of an array substrate 100c according to another embodiment of the disclosure. The difference between FIGS. 4A and 4B and FIGS. 1A to 1E is that the array substrate 100c further includes a second scan signal transmission line 118. The substrate 102 defines a first reference line BL1 and a second reference line BL2. In this embodiment, the first reference line BL1 is substantially parallel to the second direction D2, the second reference line BL2 is substantially parallel to the first direction D1, and the second reference line BL2 is substantially perpendicular to the first reference line BL1. The included angle α between the first reference line BL1 and the center line CL is in the range of about 42 degrees to about 48 degrees, and the included angle β between the second reference line BL2 and the center line CL is in the range of about 42 degrees to about 48 degrees.

The position of the first pixel area P1 of the array substrate 100c is on the right side of the first reference line BL1, and the position of the second pixel area P2 is on the left side of the first reference line BL1. For clarity, FIG. 4A shows the data line DL, the first data signal transmission line 110, the second data signal transmission line 112, and the source driving circuit 104 of the array substrate 100c. FIG. 4B shows the scan line SL, the first scan signal transmission line 114, the second scan signal transmission line 118, and the gate driving circuit 106 of the array substrate 100c. Please refer to FIG. 4A first, the first reference line BL1 and the second reference line BL2 partition the array substrate 100c into a first sub-region SR1, a second sub-region SR2, a third sub-region SR3, and a fourth sub-region SR4. The pole driving circuit 104 is disposed on one side of the first sub-region SR1 of the array substrate 100c. The source driving circuit 104 includes a first group 104a and a second group 104b. The first group 104a is closer to the first reference line BL1 than the second group 104b. The data signals of the first group 104a of the source driving circuit 104 sequentially pass through the first data signal transmission line 110 (for example, toward the direction 200), the second data signal transmission line 112 (for example, toward the direction 202), and the data line DL (for example, toward the direction 204). ) The pixel unit PU transferred to the first pixel area P1 is as described in FIG. 1C, and will not be repeated here. The data signals of the second group 104b of the source driving circuit 104 are sequentially transmitted to the pixel units of the second pixel region P2 via the second data signal transmission line 112 (for example, toward the direction 300) and the data line DL (for example, toward the direction 302) PU. In other words source drive The first group 104a of the circuit 104 controls the pixel unit PU of the first pixel area P1, and the second group 104b of the source driving circuit 104 controls the pixel unit PU of the second pixel area P2. This achieves the advantage that the non-rectangular array substrate 100c can be arbitrarily cut to obtain array substrates 100c with different non-rectangular sizes, that is, the circular array substrate 100c can be arbitrarily cut to obtain array substrates with different circular sizes. The advantages of 100c.

Then please refer to Figure 4B. The gate driving circuit 106 is disposed on one side of the first sub-region SR1 of the array substrate 100c. The array substrate 100c can also be divided into a third pixel area P3 and a fourth pixel area P4. The position of the third pixel area P3 is above the second reference line BL2, and the position of the fourth pixel area P4 is below the second reference line BL2. The gate driving circuit 106 includes a first group 106a and a second group 106b. The first group 106a is closer to the second reference line BL2 than the second group 106b. In this embodiment, the second scan signal transmission line 118 extends along the first direction D1. In other words, the second scan signal transmission line 118 is substantially parallel to the scan line SL, and the second scan signal transmission line 118 and the first scan signal transmission line 114 Intersect, where the second scan signal transmission line 118 and the first scan signal transmission line 114 are electrically connected through the second scan through hole STH2. The scan signals of the first group 106a of the gate driving circuit 106 sequentially pass through the second scan signal transmission line 118 (for example, toward the direction 400), the first scan signal transmission line 114 (for example, toward the direction 402), and the scan line SL (for example, toward the direction 404). ) Is transferred to the pixel unit PU of the third pixel area P3. The scan signals of the second group 106b of the gate driving circuit 106 are sequentially transmitted to the pixel units of the fourth pixel region P4 via the first scan signal transmission line 114 (for example, toward the direction 600) and the scan line SL (for example, toward the direction 602) PU, as described in Figure 1E, will not be repeated here. In other words, the first group 106a of the gate driving circuit 106 controls the pixel unit of the third pixel region P3. The second group 106b of the gate driving circuit 106 controls the pixel unit PU of the fourth pixel area P4, thereby achieving the effect of transmitting the scanning signal and the advantage of flexible non-rectangular cutting size of the array substrate 100c. That is, to achieve the advantage that the non-rectangular array substrate 100c can be arbitrarily cut to obtain array substrates 100c with different non-rectangular sizes. In this embodiment, the circular array substrate 100c can be arbitrarily cut to obtain different The advantages of the circular-sized array substrate 100c.

FIG. 5 is a schematic top view of an array substrate 100d according to another embodiment of the disclosure. Referring to FIG. 5, the array substrate 100d includes a pixel unit PU, a first scan line SL1, a second scan line SL2, a data line DL, a first data signal transmission line 110, a second data signal transmission line 112, and a first scan signal transmission line 114 and bridge line 120. The first scan signal transmission line 114 is located on two opposite sides of the first data signal transmission line 110. The pixel unit PU includes a first sub-pixel PU1 and a second sub-pixel PU2. The first sub-pixel PU1 includes a first scan line SL1, a data line DL, a first thin film transistor T1, and a first pixel electrode PE1. The second sub-pixel PU2 includes a second scan line SL2, a data line DL, a second thin film transistor T2, and a second pixel electrode PE2. According to this embodiment, the first sub-pixel PU1 and the second sub-pixel PU2 share the same data line DL (not shown) to form a half source driving (HSD) pixel structure. The bridge line 120 extends along the first direction D1, and the bridge line 120 intersects the first data signal transmission line 110 and the first scan signal transmission line 114. In this embodiment, the bridge line 120 and the scan line SL are the same film layer. The bridge line 120 is electrically connected to the first data signal transmission line 110 through the bridge through hole BTH, so that the data signal of the source driving circuit 104 (not shown) is sequentially transmitted to the pixel via the first data signal transmission line 110 and the bridge line 120 The first sub-pixel PU1 and the second sub-pixel PU2 of the unit PU to transmit data The effect of the signal. In this way, the advantage that the non-rectangular array substrate 100d can be arbitrarily cut to obtain array substrates 100d of different non-rectangular sizes is achieved, that is, the circular array substrate 100d can be arbitrarily cut to obtain arrays of different circular sizes. Advantages of the substrate 100d.

In summary, the array substrate of the embodiment of the present disclosure has the first data signal transmission line and the second data signal transmission line to achieve the effect of transmitting data signals and the advantage of flexibility in the non-rectangular cutting size of the non-rectangular array substrate. In addition, by providing the scanning signal transmission line, the effect of transmitting the scanning signal and the flexibility of the non-rectangular cutting size of the non-rectangular array substrate are achieved.

The above summarizes the characteristics of several implementations or embodiments, so that those with ordinary knowledge in the field can better understand the present disclosure from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on this disclosure, so as to achieve the same purpose and/or to achieve the implementation modes or embodiments introduced herein The same advantages. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the disclosure. Without departing from the spirit and scope of this disclosure, various changes, substitutions or modifications can be made to this disclosure.

110‧‧‧First data signal transmission line

112‧‧‧Second data signal transmission line

114‧‧‧First scan signal transmission line

116‧‧‧Auxiliary Line

Section A-A‧‧‧

D1‧‧‧First direction

D2‧‧‧Second direction

DL‧‧‧Data line

DTH1‧‧‧First data through hole

DTH2‧‧‧Second data through hole

P1‧‧‧The first pixel area

P2‧‧‧Second pixel area

PE‧‧‧Pixel electrode

PU‧‧‧Pixel unit

R‧‧‧Region

SL‧‧‧Scan line

STH1‧‧‧First scan through hole

T‧‧‧Thin Film Transistor

Claims (10)

An array substrate includes: a substrate; a plurality of data lines arranged on the substrate; a plurality of scanning lines arranged on the substrate and intersecting the data lines; a plurality of pixel units arranged on the substrate, And each pixel unit is electrically connected to the data lines and the scan lines; at least one first data signal transmission line is disposed on the substrate and intersects the scan lines; and at least one second data signal transmission line, Is disposed on the substrate and intersects the data lines, wherein the first data signal transmission line is electrically connected to the second data signal transmission line through a first data through hole, and the second data signal transmission line is through a second data through hole Electrically connect the data line. The array substrate according to claim 1, wherein the number of the first data signal transmission lines is the same as the number of the second data signal transmission lines. The array substrate according to claim 1, wherein the number of the first data signal transmission lines is three times the number of the second data signal transmission lines. The array substrate according to claim 1, further comprising: an auxiliary line disposed on the substrate and substantially parallel to the data lines, wherein the auxiliary line is electrically connected to the adjacent data line. An array substrate, comprising: a substrate having an active area and a peripheral area surrounding the active area; a plurality of data lines arranged on the substrate; a plurality of scanning lines arranged on the substrate and intersecting the data lines A plurality of pixel units are arranged on the substrate, and each of the pixel units is electrically connected to the data lines and the scan lines; and at least one scan signal transmission line is arranged on the substrate and is connected to the scan lines The lines intersect, wherein the scan signal transmission line is electrically connected to the scan line through a scan through hole, and the scan through hole is located in the peripheral area. The array substrate according to claim 5, further comprising: a gate driving circuit arranged on one side of the peripheral area and electrically connected to the scan lines; and a source driving circuit arranged on the peripheral area The side is electrically connected to the data lines. An array substrate comprising: a substrate having an active area and a peripheral area surrounding the active area, wherein the active area has a first pixel area and a second picture located on two opposite sides of the first pixel area A pixel area, the substrate is defined with a center line passing through the center of the substrate, the center line passes through the first pixel area, and there is a gap between the center line and the second pixel area along a first direction ; A plurality of data lines are arranged on the substrate and extend along a second direction, wherein the second direction intersects the first direction; A plurality of scan lines are arranged on the substrate and extend along the first direction; a plurality of pixel units are arranged on the substrate, and each pixel unit is electrically connected to the data lines and the scan lines Connection; at least one first data signal transmission line arranged in the first pixel area and extending along the second direction, wherein the first data signal transmission line is not located in the second pixel area; and at least one second data The signal transmission line is arranged on the substrate and intersects the data lines, wherein the first data signal transmission line is electrically connected to the second data signal transmission line through a first data through hole, and the second data signal transmission line passes through a second data signal transmission line. The data via is electrically connected to the data line. An array substrate comprising: a substrate defining a first reference line extending along a first direction and a second reference line extending along a second direction, wherein the first direction is substantially perpendicular to The second direction, the first reference line and the second reference line partition the substrate into a first sub-area, a second sub-area, a third sub-area, and a fourth sub-area; multiple data lines , Arranged on the substrate and substantially parallel to the second direction; a plurality of scan lines arranged on the substrate and substantially parallel to the first direction; a plurality of pixel units arranged on the substrate, and each The pixel unit is electrically connected to the data lines and the scan lines; at least one first scan signal transmission line is disposed on the substrate and is substantially parallel to the second direction, wherein the first scan signal transmission line is scanning The line is electrically connected through a first scanning through hole; and at least one second scanning signal transmission line is disposed on the substrate and substantially parallel to the first direction, wherein the second scanning signal transmission line and the first scanning signal transmission line It is electrically connected through a second scanning through hole. The array substrate according to claim 8, further comprising: a source drive circuit arranged on one side of the first sub-region of the substrate; at least one first data signal transmission line arranged on at least the first sub-area of the substrate Sub-region and substantially parallel to the second direction; and at least one second data signal transmission line is provided at least in the first sub-region of the substrate and substantially parallel to the second direction, and the first data signal line passes through a The first data through hole is electrically connected with the second data signal transmission line, and the second data signal transmission line is electrically connected with the data line through a second data through hole. The array substrate according to claim 9, further comprising: a gate driving circuit disposed on the side of the first sub-region of the substrate and electrically connected to the scan lines.

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