KR102045321B1 - Manufacturing method for semiconductor device - Google Patents

Abstract

Disclosed is a method of manufacturing a semiconductor device. The present semiconductor device manufacturing method includes providing a semiconductor layer, etching the semiconductor layer to form a plurality of channel structures connecting the source structure and the drain structure to the source structure, the drain structure, and covering the plurality of channel structures. Forming a resist, performing an electron beam exposure process for gate foot patterning and gate head patterning on the resist, removing a portion exposed by the electron beam exposure process to form a gate foot pattern and a gate head pattern, a gate Depositing a gate material on the foot pattern and the gate head pattern and removing the resist.

Description

Semiconductor Device Manufacturing Method {MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE}

The present disclosure relates to a method for fabricating a semiconductor device, and to providing a method for fabricating a semiconductor device in which a T-gate can be applied to a fin device to improve high frequency characteristics.

As the degree of integration of semiconductor devices has increased, design rules for components of semiconductor devices have become strict. In particular, in semiconductor devices requiring a large number of transistors, the gate length, which is a standard for design rules, has been reduced and thus the channel length has been reduced. Induced.

The short channel effect means that the effective channel length of the transistor decreases due to the effect of the drain potential, thereby reducing the threshold voltage. Due to this short channel effect, control of the device becomes difficult and the off current of the device tends to increase. As a result, the reliability of the transistor is deteriorated, and for example, the refresh characteristic of the memory device is deteriorated.

Recently, a fin-type device, such as a fin-FET, which uses various surfaces of a thin fin as a channel to suppress a short channel effect that is a problem in a conventional planar transistor and simultaneously increase an operating current, is used. Semiconductor devices have been studied.

However, the fin-FET structure of semiconductor devices up to now has a planar gate shape, which makes it difficult to improve high frequency characteristics.

An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can be applied to the T-type gate (T-gate) to the fin (F) device to improve the high frequency characteristics.

According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include preparing a semiconductor layer and etching the semiconductor layer to form a source structure, a drain structure, and a plurality of channel structures connecting the source structure and the drain structure. And forming a resist to cover the plurality of channel structures, performing an electron beam exposure process for gate foot patterning and gate head patterning on the resist, and removing a portion exposed by the electron beam exposure process. Forming a gate foot pattern and a gate head pattern, depositing a gate material on the gate foot pattern and the gate head pattern, and removing the resist.

In this case, in the forming of the resist, the first resist, the second resist, and the third resist having different optical characteristics may be sequentially stacked from the bottom.

In this case, the height of the first resist may be higher than the height of the plurality of channel structures.

Meanwhile, the height of the first resist may be 1.25 to 1.5 times higher than the height of the plurality of channel structures.

On the other hand, the first resist is poly methyl methacrylate (poly methyl methacrylate), the second resist is a copolymer of methyl methacrylate (methyl methacrylate) and methacrylic acid (methacrylic acid), the third resist is It may be a copolymer of α-chloromethacrylate (α-chloromethacrylate) and α-methylstyrene.

The plurality of channel structures may be formed such that a ratio of the widths of the plurality of channel structures to the intervals between the plurality of channel structures is 1: 2.

The preparing of the semiconductor layer may include preparing a first semiconductor layer and forming a second semiconductor layer inducing a two-dimensional electron gas (2DEG) in the first semiconductor layer. It may comprise the step of forming on the semiconductor layer.

In this case, the first semiconductor layer may be made of GaN, and the second semiconductor layer may be made of AlGaN or AlN.

1 to 11 are diagrams for describing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;
12 is a diagram for describing a semiconductor device manufactured according to a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;
FIG. 13 is a scanning electron microscope (SEM) image of a semiconductor device manufactured according to a method of manufacturing a semiconductor device according to an embodiment of the present disclosure; FIG.
14 is a view for explaining a method of manufacturing a semiconductor device according to another embodiment of the present disclosure;
15 is a scanning electron microscope (SEM) image of a semiconductor device manufactured according to a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Before describing this disclosure in detail, the description method of this specification and drawings is demonstrated.

Terms used in the present specification and claims have been selected in general terms in consideration of their function in the various embodiments of the present disclosure, but these terms are intended to be used by those skilled in the art or legal or technical interpretation and new technologies. It may vary depending on the appearance of. In addition, some terms are terms arbitrarily selected by the applicant. Such terms may be interpreted in the meanings defined herein, and may be interpreted based on the general contents of the present specification and common technical knowledge in the art without specific term definitions.

In addition, the same reference numerals or symbols described in each drawing attached to the present specification represent parts or components that perform substantially the same function. For convenience of explanation and understanding, different embodiments will be described using the same reference numerals or symbols. That is, although all the components having the same reference numerals are shown in the plurality of drawings, the plurality of drawings does not mean an embodiment.

Also, in the present specification and claims, terms including ordinal numbers such as “first”, “second”, and the like may be used to distinguish between components. These ordinal numbers are used to distinguish the same or similar components from each other, and the meaning of the terms should not be construed as limited by the use of these ordinal numbers. For example, the components combined with these ordinal numbers should not be limited in order of use or arrangement by the number. If necessary, the ordinal numbers may be used interchangeably.

As used herein, the singular forms "a", "an" and "the" include plural forms unless the context clearly indicates otherwise. In this application, the terms "comprise" or "consist" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and one or more other It is to be understood that the present invention does not exclude the possibility of adding or presenting features or numbers, steps, operations, components, components, or combinations thereof.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the scope of other embodiments. Singular expressions may include plural expressions unless the context clearly indicates otherwise. The terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art described in this document. Among the terms used in this document, terms defined in the general dictionary may be interpreted as having the same or similar meaning as the meaning in the context of the related art, and ideally or excessively formal meanings are not clearly defined in this document. Not interpreted as In some cases, even if terms are defined in the specification, they may not be interpreted to exclude embodiments of the present disclosure.

Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to various embodiments of the present disclosure will be described. The semiconductor device of the present disclosure may be implemented in various ways, such as a transistor and a diode.

In addition, terms such as “deposition” and “growth” used in the present disclosure are used in the same sense as forming a semiconductor material layer, and the layer or thin film formed in various embodiments of the present disclosure may be formed by organometallic vapor deposition ( It can be grown in a growth chamber using metal-organic chamical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), etc. In addition, PECVD, APCVD, LPCVD, UHCVD, PVD, It may be formed by depositing by various methods such as electron beam method, resistance heating method. For example, in the case of using an organometallic chemical vapor deposition (MOCVD) method, it is possible to determine the flow rate of the gas injected therein according to the volume of the MOCVD reaction chamber, depending on the type of gas, the pressure inside the reaction chamber, temperature conditions, etc. Properties such as the thickness of the thin film grown, the surface roughness, the doped concentration of the dopant may vary. In particular, the higher the temperature, the better the crystallinity of the thin film can be obtained, which should be limited in consideration of the physical properties of the reaction gas, the temperature at which the reaction occurs. In particular, ALD (Atomic layer deposition) can be used for precise growth. According to the ALD method, the thin film growth can be controlled on an atomic basis.

In addition, the term "semiconductor layer" used below refers to a layer made of a semiconductor material, and may be replaced with another term such as an epitaxial layer, a material layer, or the like.

Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

1 to 11 are diagrams for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present disclosure.

Referring to FIG. 1, first, a semiconductor layer 100 is prepared. The semiconductor layer 100 may be formed on the lower layer 10 suitable for growing the semiconductor layer 100. According to various embodiments of the present disclosure, although not shown in FIG. 1, other layers may be disposed below the lower layer 10.

The bottom layer 10 may be, for example, a substrate. When the semiconductor layer 100 is, for example, a nitride layer, the lower layer 10 may be a sapphire (Al ₂ O ₃ ) substrate having a hexagonal crystal system such as a nitride layer, or silicon carbide (SiC) or silicon. (Si), zinc oxide (ZnO), gallium arsenide (Ga), gallium nitride (GaN), spinel (MgAlO ₄ ), or a substrate made of a material.

Alternatively, the lower layer 10 may be a buffer layer. The buffer layer serves as a buffer layer to reduce crystal defects caused by a mismatch between the crystal lattice of the substrate and the material grown thereon, and may serve as a resistance layer for preventing current leakage when a high voltage is applied. For example, the buffer layer may be an AlN layer, a GaN layer, an AlGaN layer, an AlN / GaN multi-layer layer, or a layer composed of several kinds of nucleation layers to gradually reduce crystal defects resulting from lattice mismatch with the substrate. .

When the semiconductor layer 100 is, for example, a nitride layer, the lower layer 10 may be a high resistance nitride layer. By using a high resistivity nitride layer, adequate drain-source current saturation can be achieved, perfect pinch-off can be achieved, and low losses can be expected at high frequencies, and crosstalk between adjacent devices Cross-talk can be minimized, especially current collapse. For example, such a high resistance nitride layer may be a layer doped with GaN at a high concentration with a p-type dopant. As the p-type dopant, for example, zinc (Zn), magnesium (Mg), cobalt (Co), nickel (Ni), copper (Cu) or iron (Fe) or carbon (C) may be used.

The semiconductor layer 100 may be a layer formed by depositing silicon, germanium, or III-V semiconductor material.

The III-V semiconductor material comprises one or more elements from group IIIA (B, Al, Ga, In, and Ti) of the periodic table and one or more elements from group VA (N, P, As, Sb, and Bi) of the periodic table. It can include any semiconductor material consisting of. For example, III-V semiconductor materials include, but are not limited to, GaN, GaP, GaAs, InN, InP, InAs, AlN, AlP, AlAs, InGaN, InGaP, InGaNP, and the like.

As an example of a III-V semiconductor material, III-nitride semiconductor material includes any III-V semiconductor material composed of nitrogen and one or more elements from Group IIIA (B, Al, Ga, In, and Ti) of the periodic table. can do. For example, III-nitride semiconductor materials include, but are not limited to, GaN, InN, AlN, InGaN, GaAlN, GaAlN, InAlN, and the like.

According to an embodiment, the semiconductor layer 100 may have a structure in which layers made of two different materials are stacked. That is, as shown in FIG. 2, the first semiconductor layer 110 and the second semiconductor layer 120 may be stacked.

The first semiconductor layer 110 may be made of GaN. The first semiconductor layer 110 may be an undoped GaN layer, and in some cases, may be a GaN layer doped with a predetermined impurity. Doping with a high concentration of n-type dopants reduces the series resistance of the device, allowing better current flow.

The second semiconductor layer 120 includes a semiconductor material different from the first semiconductor layer 110. For example, a second semiconductor layer 120 that induces two-dimensional electron gas (hereinafter referred to as '2DEG') in the first semiconductor layer 110 may be formed on the first semiconductor layer 110. have. In detail, the material constituting the second semiconductor layer 120 may have at least one of a polarization characteristic, an energy band gap, and a lattice constant different from the material constituting the first semiconductor layer 110. For example, at least one of a polarization rate and an energy band gap of the second semiconductor layer 120 may be larger than that of the first semiconductor layer 110. For example, the second semiconductor layer 120 may be an AlGaN layer or an AlN layer. The second semiconductor layer 120 may be an undoped layer, but in some cases, may be a layer doped with a predetermined impurity.

As the second semiconductor layer 120 is formed, 2DEG may be formed on a portion of the first semiconductor layer 110. The 2DEG may be formed in the region of the first semiconductor layer 110 under the heterojunction interface between the first semiconductor layer 110 and the second semiconductor layer 120. The 2DEG formed on the first semiconductor layer 110 is made of a gas composed of electrons that can move freely in two dimensions. In this case, a high concentration of electrons may be induced to increase electron mobility, and thus may be used as a high power device.

On the other hand, it has been described as using a GaN / AlGaN or GaN / AlN heterojunction, but is not limited to this, any combination of materials capable of forming a 2DEG layer at the heterojunction interface may fall within the scope of the present invention.

A semiconductor device manufactured according to an embodiment of the present disclosure may be a high electron mobility transistor (HEMT) using the 2DEG as a channel. Alternatively, as shown in FIG. 1, one semiconductor layer 100 which is not divided into the first and second semiconductor layers may be used. Hereinafter, the following steps will be described in the case where the semiconductor layer 100 includes the first semiconductor layer 110 and the second semiconductor layer 120.

Subsequently, as illustrated in FIG. 3, a mask layer 200 having a predetermined pattern is formed on the semiconductor layer 100. Mask layer 200 may be formed using an E-beam lithography technique. In detail, a mask layer 200 having a predetermined pattern may be formed by applying a resist and performing an electron beam exposure process and a development process. In this case, poly methyl methacrylate (PMMA) may be used as the resist. Alternatively, as the mask layer 200, a dielectric such as SiO ₂ , SiN _x (eg, Si ₃ N ₄ ), or a metal such as Cr or Ni may be used.

The mask layer 200 may be formed in a shape for patterning a source structure, a drain structure, and a plurality of channel structures connecting the source structure and the drain structure. 3 illustrates only portions corresponding to the plurality of channel structures without the source structure and the drain structure.

Thereafter, the semiconductor layer 100 under the mask layer 200 may be etched to form a source structure, a drain structure, and a plurality of channel structures 300 connecting the source structure and the drain structure. Dry etching may be performed with a plasma using a halogen gas such as chlorine (Cl ₂ ), bromine (Br ₂ ) or iodine (I ₂ ). For example, a transformer coupled plasma reactive ion etching (TCP-RIE) device may be used. 4 illustrates only a portion of the channel structure 300 without omitting the source structure and the drain structure portion.

The plurality of channel structures 300 may have a fin shape and may be referred to as a fin.

The plurality of channel structures 300 operate as a path through which electrons can move when the semiconductor device is in an on state, and conversely, when the semiconductor device is in an off state, the plurality of channel structures 300 prevent movement of electric charges to prevent leakage of current. It is a configuration that works.

As the width of the channel structure decreases, the electron moving area decreases, but the possibility of complete depletion in the off state increases, so that it is easy to implement a normally off operation. On the contrary, as the width of the channel structure becomes wider, the electron moving area becomes wider, but it may be disadvantageous to implement a normally off operation. Therefore, the width of the channel structure can be determined by considering these points comprehensively. In addition, the width of the channel structure may be selected in consideration of the spin coating of the resist described below. According to one embodiment, the width of the plurality of channel structures 300 may be, for example, about 50 nm to about 250 nm.

5 illustrates a view of the source structure 400, the drain structure 500, and the plurality of channel structures 300 formed by etching the semiconductor layer 100, and one channel structure 301 of the plurality of channel structures. The figure shows the view from the side.

In the case of the MOS structure, the gate insulating material may be deposited on the plurality of channel structures 300 by using a thin film evaporator, and in the case of the HEMT structure, this may be omitted.

A lithography process is then performed to form the T-type gate. Unlike the general planar gate, the T-type gate controls the current of the semiconductor device through the T-type gate and the foot region, which is the lower end of T, which is the gate length, and the upper end of the T, where the frequency characteristics are improved by reducing the gate resistance. It consists of an in-head area.

The prior art T-type gate fabrication process consists of foot formation through primary electron beam lithography followed by secondary rearrangement and head formation through electron beam lithography. That is, in order to fabricate a gate of a semiconductor device, a total of two stages of electron beam lithography techniques are used. Accordingly, there is a problem of high cost and low reproducibility due to exposure alignment that occur in an electron beam lithography process. In addition, existing technologies have a disadvantage in that it is difficult to apply to a device having a three-dimensional structure such as a multi-pin array. The fabrication technique proposed in the present disclosure is a process technique that can compensate for the problems of the existing techniques, and in particular, a T-type gate formation method applicable to a fin array having a three-dimensional structure.

Specifically, as shown in FIG. 6, a resist 600 is formed to cover the channel structure 300. 6 illustrates only a portion of one channel structure 300 among the plurality of channel structures for convenience of description, but the resist 600 is formed on the entire plurality of channel structures. Referring to FIG. 6, it can be seen that the resist 600 is formed to cover the channel structure 300. The resist 600 may be deposited by spin coating. Spin coating is a coating method using the principle that the fluid is unfolded by centrifugal force as the substrate rotates at a very high speed.

According to an embodiment of the present disclosure, the resist 600 may include a plurality of different types of resists stacked. For example, as illustrated in FIG. 6, the first resist 610, the second resist 620, and the third resist 630 may be sequentially stacked from the bottom. Specifically, the first resist 610 is formed by spin coating and baking, and the second resist 620 is formed by spin coating and baking on the first resist 610, and the second resist 620 is formed on the second resist 620. The 3 resist 630 may be formed by spin coating and baking. Although not shown, an E-spacer may be added to the third resist 630 to reduce the electron charging effect.

Since the plurality of channel structures 300 have tens to hundreds of fin structures in a row, the application condition of the resist 600 may be determined by three variables.

The first variable here is the spacing between the channel structures. If the spacing is very small, the resist 600 may not be sufficiently coated by the spin coating between the channel structures, causing voids, and when the gate material is deposited, it may not be possible to deposit to the lower ends between the channel structures. have. On the other hand, if the spacing between the channel structures is very wide, the number of channel structures that can be arranged in a certain space is reduced, so that the current characteristics may be degraded. When the ratio of the width of the channel structure and the spacing between the channel structures is at least 1: 2, it is confirmed that the above problems can be optimized.

The second variable is the thickness of the bottommost first resist 630 when applying a total of three layers of the first resist 610, the second resist 620, and the third resist 630. In the case of the first resist 630 to be applied to the lowest end, it can be said to be an important layer for determining the foot area of the T-type gate later. However, since the coating is applied on the plurality of protruding channel structures 300 instead of the plane, the thickness to be applied is different from the general plane.

Therefore, the first resist 610 must be applied to a thickness higher than the height of the channel structure 300 in order to form a T-type gate having a correct shape in both the upper end portion of the channel structure and the region between the channel structures. When the height of the first resist 610 is 1.25 to 1.5 times higher than the height of the channel structure 300, the researchers can form a T-shaped gate of the correct shape in both the upper end of the channel structure and the region between the channel structures. Found. For example, in order to form a T-type gate having a correct shape on a channel structure having a height of 200 nm, the first resist 610 is applied to 50-100 nm or more based on the upper end of the channel structure. That is, the first resist 610 is applied to a thickness of 250 ~ 300nm based on the lower end of the channel structure.

The third variable is the height of the channel structure. In general, the higher the height of the channel structure is better to reduce the leakage of the lower end of the fin-FET, but if the height of the channel structure is too high to form the foot of the T-gate The resist may not be coated to the bottom by spin coating. To solve this problem, there is a solution to increase the spacing between the channel structures at a considerably high rate instead of increasing the height of the channel structure. However, as described above, in the present device where the number of the channel structures is important, the number of the channel structures is reduced. This is undesirable since the current of the device is reduced. Therefore, based on the above-mentioned optimum ratio of 1: 2, in our experiment, the channel structure height of approximately 200nm to 250nm has no problem in resist coating and lower current leakage at the bottom. The optimal height is derived.

After the application of the resist 600, an electron beam exposure process for forming a T-type gate is performed. For example, as illustrated in FIG. 7, an electron beam exposure process for gate foot patterning and gate head patterning is performed on the resist 600. For example, gate foot patterning may be performed by line patterning, and gate head patterning may be performed by area patterning.

As such, since the gate foot and the gate head pattern can be formed by only one electron beam exposure operation, the cost and technical difficulty of the existing two exposure operations can be reduced to less than half.

According to an embodiment, the first resist 610, the second resist 620, and the third resist 630 may have different optical characteristics such as light absorption and sensitivity. For example, the first resist 610 is polymethyl methacrylate (PMMA), and the second resist 620 is a copolymer of a copolymer (eg, methyl methacrylate and methacrylic acid). ), And the third resist 630 may be a copolymer of α-chloromethacrylate and α-methylstyrene (ex. ZEP of manufacturer ZEON).

The dose (ie, the amount of exposure energy) of the electron beam exposure process for gate foot patterning and gate head patterning is appropriately considered in consideration of the optical characteristics of the first resist 610, the second resist 620, and the third resist 630. Can be selected. For example, gate foot patterning may be performed with electron beam exposure at higher dose than gate head patterning.

Subsequently, the gate foot pattern 710 and the gate head pattern 720 may be formed as shown in FIG. 8 by performing a developing process of removing the portion exposed by the electron beam exposure process.

9, the gate material 800 may be deposited on the gate foot pattern 710 and the gate head pattern 720. In this case, for example, Au / Ni metal may be deposited using an electron-beam evaporator as shown in FIG. 9. In addition, when the resist 600 is removed through a lift-off process, the T-type gate 810 may be formed.

10 illustrates a top view of the T-type gate 810 formed on the plurality of channel structures 300 and a side view of a portion of the channel structure.

Finally, as illustrated in FIG. 11, the process may be completed by depositing the source pad metal, the drain pad metal, and the gate pad metal and forming a passivation oxide.

12 illustrates a high frequency Fin-FET with a T-type gate manufactured according to the fabrication method of the present disclosure. Although Fin-FET based on AlGaN / GaN based high frequency thin film is shown, the actual semiconductor thin film can be replaced with various thin film materials such as silicon, germanium (Ge) and arsenic nitride (GaAs).

FIG. 13A illustrates an upper end SEM image of a fin-FET finally manufactured according to an exemplary embodiment of the present disclosure, wherein the upper end “A'-plane” of the channel structure and “B'-plane” between the channel structures are illustrated. Indicated. The width of the channel structure is 180 nm, the height is 200 nm, the distance between the channel structures is 400 nm, and the length of the channel structure is 2 μm. FIG. 13B is a cross section of the T-type gate in the A'-plane, and FIG. 13D is a cross section of the T-type gate in the B'-plane.

According to the semiconductor device manufacturing method according to the present disclosure, since the T-type gate can be applied to the Fin-FET, the high-frequency characteristics can be improved while preserving excellent electrical characteristics basically possessed by the Fin-FET. Therefore, it can be used for various fields such as 5G communication, satellite, military, missile, aviation, IoT as a high frequency semiconductor device.

Meanwhile, the T-type gate fabrication method described in the present disclosure may be applied to a two-dimensional planar structure as well as a three-dimensional structure such as a fin structure. An example of the manufacturing procedure in the two-dimensional planar structure is shown in Figs. 14A to 14F. The manufacturing method described with reference to FIGS. 1 to 11 may be identically applied except for the difference that the manufacturing method of FIG. 14 is not applied to a three-dimensional fin channel structure but to a two-dimensional (planar) channel structure. In the manufacturing method illustrated in FIG. 14, the channel structure is composed of GaN, PMMA, Copolymer, and ZEP are used as the first to third resists, and an E-spacer for reducing the electron charging effect is used. It is additionally used. The materials used in the manufacturing method of FIG. 14 are merely examples, but are not limited thereto. For example, the channel structure composed of GaN may be composed of other semiconductor materials such as silicon and arsenic nitride, and the resists may be composed of other kinds of materials.

FIG. 15 illustrates an aerial view (a) of a T-type gate and a cross-sectional SEM image (b) of a T-type gate manufactured in a two-dimensional channel structure according to the manufacturing method of FIG. 14.

According to the above-described embodiments of the present disclosure, it is possible to solve the problem of high cost and low reproducibility caused by lithography in manufacturing a T-type gate, and in particular, a T-type gate is applied to a device having a three-dimensional structure. It can overcome the disadvantages that are difficult to apply.

While the above has been illustrated and described with respect to preferred embodiments of the present disclosure, those skilled in the art to which the present invention pertains should preferably practice the present disclosure without departing from the spirit and scope of the present invention. Of course, the examples can be changed in various ways. Therefore, various modifications may be made without departing from the spirit of the invention as claimed in the claims, and such modifications should not be individually understood from the technical spirit or outlook of the invention.

Claims (8)

In the semiconductor device manufacturing method,
Preparing a semiconductor layer;
Etching the semiconductor layer to form a source structure, a drain structure, and a plurality of channel structures connecting the source structure and the drain structure;
Forming a resist to cover the plurality of channel structures;
Performing an electron beam exposure process on the resist for gate foot patterning and gate head patterning;
Removing a portion exposed by the electron beam exposure process to form a gate foot pattern and a gate head pattern;
Depositing a gate material on the gate foot pattern and the gate head pattern; And
Removing the resist;
The plurality of channel structures,
And a ratio of a width of the plurality of channel structures to an interval between the plurality of channel structures is about 1: 2. The method of claim 1,
Forming the resist,
A method of manufacturing a semiconductor device in which a first resist, a second resist, and a third resist having different optical characteristics are sequentially stacked from the bottom. The method of claim 2,
And a height of said first resist is higher than a height of said plurality of channel structures. The method of claim 2,
And a height of the first resist is 1.25 to 1.5 times higher than a height of the plurality of channel structures. The method of claim 2,
The first resist is poly methyl methacrylate (poly methyl methacrylate),
The second resist is a copolymer of methyl methacrylate and methacrylic acid,
The third resist is a copolymer of α-chloromethacrylate (α-chloromethacrylate) and α-methylstyrene (α-methylstyrene), a method of manufacturing a semiconductor device. delete The method of claim 1,
Preparing the semiconductor layer,
Providing a first semiconductor layer; And
Forming a second semiconductor layer on the first semiconductor layer, the second semiconductor layer inducing a two-dimensional electron gas (2DEG) in the first semiconductor layer. The method of claim 7, wherein
The first semiconductor layer is composed of GaN, the second semiconductor layer is AlGaN or AlN manufacturing method.

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