KR102042818B1 - Silicon electric connection substrate and method of fabricating the same - Google Patents

Abstract

The present invention comprises the steps of preparing a substrate comprising silicon; Forming a plurality of trenches downward from an upper surface of the substrate including silicon; And thermally oxidizing the substrate including the silicon having the plurality of trenches, thereby forming a thermal oxidation layer on an exposed surface of the substrate including the silicon, and simultaneously filling the spaces of the plurality of trenches. It provides a method for manufacturing a silicon electrical connection substrate comprising the step of forming a pattern.

Description

Silicon electric connection substrate and method of fabricating the same

The present invention relates to a substrate and a method for manufacturing the same, and more particularly to a silicon electrical connection substrate and a method for manufacturing the same.

In many fields of the semiconductor industry (microelectronics, micro-optics and micromechanics), there has been a need for the construction of components on both sides of a semiconductor wafer, such as a silicon wafer, for the manufacture of semiconductor devices such as sensors, micro mirror arrays. Wire bonding is a common technique in the prior art regarding the packaging and interconnection of such devices. However, wire bonding is uneconomical and in devices where many interconnect wiring is required, such as array devices, it may be impossible to attach the wiring at all.

Another technique in this technical field is based on providing a metallized portion in a hole formed through the wafer to make electrical contact between the two surfaces. Specifically, a process of first forming a via hole through the wafer and then filling the via hole with an appropriate material is applied. However, as the aspect ratio of the via hole increases in response to the demand for miniaturization and integration of the product, there is a problem that the filling process becomes more difficult.

Korean patent publication KR20140034713A (2014-03-20)

Disclosure of Invention The present invention has been made to solve various problems including the above problems, and an object thereof is to provide a silicon electrical connection substrate having a high quality insulating layer without using a via hole filling process, and a method of manufacturing the same. However, these problems are exemplary, and the scope of the present invention is not limited thereby.

Provided is a method of manufacturing a silicon electrical connection board according to one aspect of the present invention for solving the above problems. The method of manufacturing a silicon electrical connection substrate includes a first step of preparing a substrate including silicon; A second step of forming a plurality of trenches downward from an upper surface of the substrate including silicon; And thermally oxidizing the substrate including the silicon having the plurality of trenches, thereby forming a thermal oxidation layer on an exposed surface of the substrate including the silicon, and simultaneously filling the spaces of the plurality of trenches. Forming a pattern; It includes.

In the second step of the method for fabricating the silicon interconnection substrate, the plurality of trenches have a ratio (K / W) of a distance (W) between the trench and the immediately adjacent trench (K / W) of 1 / 1.174. It can be designed to be as follows.

The method of manufacturing a silicon interconnecting substrate may include removing a thermal oxide film formed on an upper surface and a lower surface of a substrate including silicon after the third step; Bonding the upper surface of the substrate including the silicon to the support substrate; Removing regions of the substrate including silicon except for regions corresponding to the heights of the insulating patterns; Removing a portion of the support substrate such that a bonding interface between the top surface of the substrate including silicon and the support substrate is exposed; Forming a wiring pattern on the support substrate and the substrate including the silicon; It may include.

In the method of manufacturing the silicon interconnection substrate, the support substrate is a glass support substrate, and the step of bonding the upper surface of the substrate including the silicon and the support substrate may include forming the upper surface of the substrate including the silicon and the glass support substrate. And anodic bonding.

In the method of manufacturing a silicon interconnection substrate, the support substrate is a silicon support substrate, and the step of bonding the upper surface of the substrate including the silicon and the support substrate may include forming the upper surface of the substrate including the silicon and the silicon support substrate. It may comprise the step of melt bonding.

In the method of manufacturing a silicon interconnection substrate, the step of removing the region of the remaining level except for the region corresponding to the height of the insulating pattern of the substrate containing silicon, wherein the insulating pattern comprises the silicon The via pattern penetrates the substrate.

In the method of manufacturing a silicon interconnection substrate, removing the portion of the support substrate to expose the junction interface between the top surface of the substrate including the silicon and the support substrate includes the silicon, not the insulating pattern. And removing a portion of the support substrate to expose the substrate.

The present invention provides a method for manufacturing a silicon electrical connection board according to another aspect of the present invention for solving the above problems. The method of manufacturing a silicon interconnection board may include preparing a silicon on insulator (SOI) wafer in which a silicon support layer, an insulating layer, and a silicon device layer are sequentially disposed; Forming a plurality of trenches penetrating the silicon device layer; And forming an insulating pattern by thermally oxidizing the silicon support layer having the plurality of trenches, thereby forming a thermal oxidation layer on an exposed surface of the silicon support layer and simultaneously filling the spaces of the plurality of trenches. Forming an opening penetrating the silicon support layer and the insulating layer and exposing the silicon device layer instead of the insulating pattern penetrating the silicon device layer; Forming a first passivation layer and a first wiring pattern formed on the silicon support layer including the openings; And forming a second passivation layer and a second wiring pattern formed on the silicon device layer. It includes.

Provided is a silicon electrical connection substrate according to another aspect of the present invention for solving the above problems. The silicon interconnect substrate includes a substrate comprising silicon; An insulating pattern penetrating the substrate including the silicon, the silicon oxide film oxidizing silicon by a thermal oxidation process; A support substrate bonded to the substrate including silicon, the support substrate having an opening for exposing the substrate including silicon instead of the insulating pattern; A first wiring pattern formed on the support substrate including the opening; And a second wiring pattern formed on the substrate including the silicon.

According to one embodiment of the present invention made as described above, it is possible to implement a silicon electrical connection substrate having a high quality insulating layer and a method of manufacturing the same without using a process for filling via holes. Of course, the scope of the present invention is not limited by these effects.

1 to 6 are diagrams sequentially illustrating a method of manufacturing a silicon electrical connection substrate according to an embodiment of the present invention.
7 is a diagram illustrating the structure of a silicon electrical connection substrate according to another embodiment of the invention.
8A to 8C are diagrams illustrating a design configuration of a plurality of trenches in a method of manufacturing a silicon interconnection board according to embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and the following embodiments are intended to complete the disclosure of the present invention, the scope of the invention to those skilled in the art It is provided to inform you completely. In addition, in the drawings, at least some of the components may be exaggerated or reduced in size. Like numbers in the drawings refer to like elements.

1 to 6 are diagrams sequentially illustrating a method of manufacturing a silicon electrical connection substrate according to an embodiment of the present invention.

Referring to FIG. 1, a method of manufacturing a silicon interconnection board according to an embodiment of the present invention may include preparing a substrate 100 including silicon (S100); A second step S200 of forming the plurality of trenches 140 below the upper surface 100a of the substrate 100 including silicon is first performed.

The substrate 100 including silicon may be, for example, a silicon wafer, a wafer containing silicon, or a silicon on insulator (SOI) wafer. In the following description, a case where the substrate 100 containing silicon is a silicon wafer will be described for convenience. The substrate 100 including silicon includes an upper surface 100a, a side surface 100b, and a lower surface 100c.

The plurality of trenches 140 may adjust the number of trenches according to the width of the insulation pattern to be subsequently implemented. In the drawing, for example, two trenches 140 may be provided to implement one insulation pattern. The case is shown. In this case, it may be understood that a part 130 of the silicon substrate is interposed between the plurality of trenches 140 spaced apart from each other. The trench 140 is implemented by removing a portion of the first portion 120 of the substrate 100 instead of penetrating the substrate 100 including silicon. Therefore, the trench 140 is not formed in the second portion 110, which is the remaining portion of the substrate 100.

Referring to FIG. 2, a thermal oxidation process is performed on a substrate 100 including silicon having a plurality of trenches 140 to thermally expose an exposed surface of the substrate 100 including silicon. A third step (S300) of forming an insulating pattern 210 is performed while filling the space of the plurality of trenches 140 while forming an oxidation layer.

Representative methods of forming a silicon oxide film include thermal oxidation, chemical vapor deposition (CVD), sputtering, and the like. On the other hand, since silicon reacts with oxygen very easily, even when the silicon wafer is left at room temperature, a natural oxide film (Natural Oxide, Native Oxide) can be easily formed in the air or in water.

Among these various types of silicon oxide films, silicon oxide films implemented by the thermal oxidation method have remarkably superior characteristics in terms of the occurrence of defects such as dielectric breakdown strength, crystal surface stability, oxide purity, and pinholes. In the method of manufacturing a silicon interconnection board according to an embodiment of the present invention, a silicon oxide film 200 implemented by thermal oxidation is applied.

For thermal oxidation of a silicon wafer, for example, when oxygen gas or oxygen gas and hydrogen gas are mixed and flowed into a high-temperature furnace on which a silicon wafer is loaded, silicon atoms on the surface of the silicon wafer and oxygen as a carrier gas It can be combined to form an oxide film.

Oxide film formation on a silicon wafer is carried out through the diffusion of the oxidant to the interface of the oxide-silicon wafer to cause oxidation, thereby forming an oxide film. The thicker the oxide film thus formed, the longer it takes for the oxidant to diffuse into the Si-SiO ₂ interface, so the oxide film grows slower as the oxide film becomes thicker. By this process, as the oxide film is grown (consumption of Si atoms), the Si-SiO ₂ interface moves (retreats) toward the silicon wafer.

Referring to FIG. 2, a thermal oxidation process is performed on the substrate 100 including silicon, thereby exposing the upper surface 100a, the side surface 100b, and the lower surface 100c, which are exposed surfaces of the substrate 100 including silicon. Since the first thermal oxide film 220 is formed and a portion of the substrate 100 including silicon corresponding to the sidewall and the bottom defining the space of the trench 140 is also exposed to the outside, the second thermal oxide film is thermally oxidized. The thermal oxide film 210 is formed.

In the second thermal oxide film 210, a portion of the substrate 100 including silicon corresponding to the sidewalls and the bottom of the plurality of trenches 140 is thermally oxidized to fill the space of the trench 140. An insulation pattern is formed.

3, after the third step S300, a step of removing the thermal oxide film formed on the upper surface 100a and the lower surface 100c of the substrate 100 including silicon (S400) is performed. do. The process of removing the thermal oxide film may be a planarization process, for example, a chemical mechanical polishing (CMP) process. Furthermore, the thermal oxide film formed on the side surface 100b of the substrate 100 may also be removed.

Referring to FIG. 4, an operation (S400) of bonding the upper surface 100a of the substrate 100 including silicon to the support substrate 300 may be performed.

For example, the support substrate 300 may be a glass support substrate, and the bonding of the upper surface 100a of the substrate 100 including silicon and the support substrate 300 may include an upper surface of the substrate including silicon and the upper surface of the substrate 100. And anodic bonding the glass support substrate. The purpose of removing the thermal oxide film formed on the upper surface 100a and the lower surface 100c of the substrate 100 in the third step S300 is to perform an anode bonding process.

As another example, the supporting substrate 300 is a silicon supporting substrate, and the step of bonding the upper surface 100a of the substrate 100 including silicon and the supporting substrate 300 to each other includes the upper surface of the substrate including the silicon and the silicon supporting substrate. And melt bonding the substrate.

In the bonding process, the bonding interface between the substrate 100 including silicon and the support substrate 300 includes an upper surface 100a of the substrate 100, and the lower surface 100c of the substrate 100 is exposed upward.

Referring to FIG. 5, except for the region (120 of FIG. 4) corresponding to the height of the insulating pattern 210, the remaining region (110 of FIG. 4) is removed from the substrate 100 including silicon ( S500). The removal step may use a grinding process. By performing step S500, the insulating pattern 210 may be implemented as a via pattern penetrating the substrate 120 including silicon. The via pattern referred to herein refers to a pattern penetrating the substrate up and down, regardless of whether it is electrically conductive or not.

Referring to FIG. 6, a step of removing a portion of the supporting substrate 300 to expose the bonding interface (S600) and forming wiring patterns 420 and 450 on the supporting substrate 300 and the substrate 120 including silicon. Step (S700); Can be performed.

The step S600 may include forming an opening 350 by removing a portion of the supporting substrate 300 such that the substrate 120 including silicon is exposed instead of the insulating pattern 210. The first wiring pattern 420 may be provided to cover the side surface and the bottom surface of the opening 350 and extend to a part of the support substrate 300. The second wiring pattern 450 may include a substrate including silicon ( It may be formed on the surface opposite to the bonding interface of the substrate 120 and the support substrate 300 containing silicon among the 120. A separate insulating layer 440 may be further formed on the insulating pattern 210 penetrating the substrate 120 including silicon.

The structure shown in FIG. 6 corresponds to a silicon interconnect substrate 500 in accordance with one embodiment of the present invention. The silicon electrical connection substrate 500 includes a substrate 120 including silicon; An insulating pattern 210 that penetrates the substrate 120 including silicon and is made of a silicon oxide film oxidized silicon by a thermal oxidation process; A support substrate 300 bonded to the substrate 120 including silicon and having an opening 350 for exposing the substrate 120 including silicon instead of the insulating pattern 210; A first wiring pattern 420 formed on the support substrate 300 including the opening 350; And a second wiring pattern 450 formed on the substrate 120 including silicon. Meanwhile, a passivation pattern may be disposed adjacent to the first wiring pattern 420 and / or the second wiring pattern 450 to prevent an electrical short circuit.

In the silicon interconnection substrate 500 illustrated in FIG. 6, the pair of insulating patterns 210 on the left side correspond to a cross section of one pattern forming a closed loop, and the pair of insulating patterns illustrated on the right side ( 210 may correspond to a cross section of another pattern forming a closed loop. In this case, the substrate 120 including silicon is positioned outside the silicon via pattern 120a and the insulation pattern 210 respectively forming the closed loop, respectively. It may be divided into a silicon base pattern 120b. The opening 350 of the support substrate 300 may be formed to expose the silicon via pattern 120a positioned inside the insulating pattern 210.

7 is a diagram illustrating the structure of a silicon electrical connection substrate according to another embodiment of the invention.

The structure shown in FIG. 7 corresponds to a silicon interconnect substrate 500 in accordance with another embodiment of the present invention. The silicon electrical connection substrate 500 includes a substrate 120a including silicon; An insulating pattern 210 that penetrates the substrate 120a including silicon and is made of a silicon oxide film oxidized silicon by a thermal oxidation process; A support substrate (300) bonded to the substrate (120a) containing silicon and having an opening (350) exposing the substrate (120a) including silicon instead of the insulating pattern (210); A first wiring pattern 420 formed on the support substrate 300 including the opening 350; And a second wiring pattern 450 formed on the substrate 120 including silicon. Meanwhile, a passivation pattern may be disposed adjacent to the first wiring pattern 420 and / or the second wiring pattern 450 to prevent an electrical short circuit.

In the silicon interconnection substrate 500 illustrated in FIG. 7, unlike the substrate of FIG. 6, the substrate including silicon is composed of only the silicon via pattern 120a. That is, in the silicon interconnection substrate 500 illustrated in FIG. 7, a plurality of trenches 140 are formed in a region of the silicon base pattern 120b illustrated in FIG. 6, and a thermal oxidation process is performed to form the insulating pattern 210. This area is relatively large.

Hereinafter, a configuration of designing the plurality of trenches 140 in order to effectively form the insulating pattern 210 in the second step (S200) of the method of manufacturing the silicon electrical connection substrate will be described.

8A to 8C are diagrams illustrating a design configuration of a plurality of trenches in a method of manufacturing a silicon interconnection board according to an embodiment of the present invention.

Referring to FIG. 8A, a plurality of trenches 140 are formed in a substrate 100 including silicon. In FIG. 8A, for example, a plurality of trenches 140 are composed of three trenches 140.

In order to effectively implement the insulating pattern 210 made of a silicon oxide film in a plurality of trenches 140 by thermally oxidizing a substrate 100 including silicon, the present inventors have a separation distance W between trenches and adjacent trenches. It was confirmed that it is preferable that the ratio (K / W) of the width (K) of the trenches) is designed to be 1 / 1.174 or less. In another aspect, the separation distance W between the trench and the immediately adjacent trench may be understood as the width of the protruding pattern 130 between the plurality of trenches 140, and the width K of the trench is the protruding pattern 130. It can also be understood as the distance between them. The protruding pattern 130 corresponds to a part of the substrate 100 including silicon.

Referring to FIG. 8B, when the ratio (K / W) between the trench and the immediately adjacent trench (K) is less than 1 / 1.174, an insulation pattern implemented by a thermal oxidation process ( It can be seen that 210a) is made of only silicon oxide.

In contrast, referring to FIG. 8C, when the ratio (K / W) of the separation distance (W) between the wrench and the immediately adjacent trench (K / W) is larger than 1 / 1.174, insulation implemented by a thermal oxidation process The pattern 210b may confirm that a portion 130a of the protruding pattern made of silicon remains inside. Of course, the insulating pattern 210b shown in FIG. 8C may not be a problem in terms of electrical insulation.

So far, the silicon electrical connection board and the manufacturing method thereof according to the embodiment of the present invention have been described. The above-described technical concept may be applied to a silicon on insulator (SOI) wafer as well as a silicon wafer. An SOI wafer is an artificially formed insulating layer between a silicon support layer, which is a substrate, and a silicon device layer, which is a device operation region, thereby removing the influence from the support substrate, thereby processing, efficiency, and characteristics of the high purity silicon layer formed on the insulator. It is a new material that can expect high integration, low power consumption, high speed, high breakdown voltage, high functional device, radiation resistance, and high added value by enabling ultra fine circuit processing by improving greatly and improving the performance of the completed semiconductor. That is, the SOI wafer may be a substrate on which a silicon support layer, an insulating layer, and a silicon device layer are sequentially disposed.

When the above-described technical spirit of the present invention is applied to the SOI wafer, the substrate 120 including silicon illustrated in FIG. 6 may correspond to the silicon device layer of the SOI wafer, and the support substrate illustrated in FIG. 6. 300 may correspond to a silicon support layer and an insulating layer of the SOI wafer.

Therefore, when the above-described technical spirit of the present invention is applied to the SOI wafer, only the steps of forming a plurality of trenches penetrating the silicon device layer and applying an thermal oxidation process to form an insulation pattern may include silicon. The process of anodic bonding and grinding the substrate and the supporting substrate separately may be unnecessary. However, in order to form the opening 350 shown in FIG. 6, a process of etching both the silicon support layer and the insulating layer of the SOI wafer may be performed.

In summary, the method for manufacturing the silicon interconnection substrate applied to the SOI wafer may include preparing a silicon on insulator (SOI) wafer in which a silicon support layer, an insulating layer, and a silicon device layer are sequentially disposed; Forming a plurality of trenches penetrating the silicon device layer; And forming an insulating pattern by thermally oxidizing the silicon support layer having the plurality of trenches, thereby forming a thermal oxidation layer on an exposed surface of the silicon support layer and simultaneously filling the spaces of the plurality of trenches. Forming openings penetrating the silicon support layer and the insulating layer to expose the silicon device layer, not the insulating pattern penetrating the silicon device layer; Forming a first passivation layer and a first wiring pattern formed on the silicon support layer including the openings; And forming a second passivation layer and a second wiring pattern formed on the silicon device layer. It includes.

The technical idea of the present invention described so far relates to a silicon electrical connection board for sealing packaging and a method of manufacturing the same, and provides a through silicon via (TSV) source technology which is an essential element of wiring and integration for 2.5D packaging of a MEMS sensor. do. Specifically, TSV technology having high reliability is provided through a via process using silicon, and two or more trenches are made, and a silicon conductive member is removed from the silicon wafer with a high quality insulating layer through an oxidation and planarization process. The insulated wafer process eliminates the need for an insulating material filling process, and has a feature of controlling the thickness of a high quality oxide insulating material using the number of trenches. The silicon interconnect substrate and the method of manufacturing the same according to an embodiment of the present invention are applicable to an interposer and wafer level package (WLP) for wiring of Hermetic packaging. The conductive member can be selectively reconfigured through bonding with glass substrates and processing of glass substrates, which is suitable for high vacuum and sealing packaging, and selectively reconfigurable conductive members can have low connection resistance through a metal layer after polishing and processing of glass substrates. have.

When the demand for low-cost, high-density packaging is expected to increase due to the miniaturization and low cost of high-performance MEMS sensors, the method of manufacturing a silicon interconnection board according to the technical concept of the present invention is an essential element of wiring and integration for 2.5D packaging of MEMS sensors. It is expected to provide differentiated high-reliability TSV technology as the need for TSV source technology can be secured, and the need for low-cost, highly integrated interposer technology increases due to high integration, miniaturization and low price of sensors.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

100: substrate containing silicon
140: multiple trenches
200, 210, 220: thermal oxide film
300: support substrate
350: opening
420, 450: wiring pattern

Claims (9)

A first step of preparing a substrate including silicon;
A second step of forming a plurality of trenches downward from an upper surface of the substrate including silicon; And
By thermally oxidizing the substrate including the silicon having the plurality of trenches, a thermal oxidation layer is formed on an exposed surface of the substrate including the silicon while filling the spaces of the plurality of trenches. Forming a third step; Including,
After the third step,
Removing the thermal oxide films formed on the upper and lower surfaces of the substrate including silicon;
Bonding a top surface of the substrate including the silicon to a support substrate;
Removing regions of the substrate including silicon except for regions corresponding to the heights of the insulating patterns;
Removing a portion of the support substrate such that a bonding interface between the top surface of the substrate including the silicon and the support substrate is exposed; And
Forming a wiring pattern on the support substrate and the substrate including the silicon;
Comprising a silicon electrical connection substrate. The method of claim 1,
In the second step, the plurality of trenches are designed such that the ratio (K / W) of the separation distance (W) between the trench and the immediately adjacent trench (K / W) is less than 1 / 1.174. ,
Method of manufacturing a silicon electrical connection substrate. delete The method of claim 1,
The support substrate is a glass support substrate,
Bonding the upper surface of the substrate including the silicon to the support substrate comprises anodizing the upper surface of the substrate including the silicon with the glass support substrate;
Method of manufacturing a silicon electrical connection substrate. The method of claim 1,
The support substrate is a silicon support substrate,
Bonding the upper surface of the substrate including silicon to the support substrate comprises melting bonding the upper surface of the substrate including silicon to the silicon support substrate;
Method of manufacturing a silicon electrical connection substrate. The method of claim 1,
By removing the region of the remaining level except for the region corresponding to the height of the insulating pattern of the substrate including the silicon, the insulating pattern is implemented as a via pattern penetrating the substrate containing the silicon A method for producing a silicon electrical connection substrate, characterized in that. The method of claim 1,
Removing the portion of the support substrate such that the bonding interface is exposed includes removing a portion of the support substrate so that the substrate including the silicon is exposed, not the insulating pattern. . Preparing a silicon on insulator (SOI) wafer in which a silicon support layer, an insulating layer, and a silicon device layer are sequentially disposed;
Forming a plurality of trenches penetrating the silicon device layer; And
Forming an insulating pattern by thermally oxidizing the silicon support layer having the plurality of trenches, a thermal oxidation layer being formed on an exposed surface of the silicon support layer, and simultaneously filling the spaces of the plurality of trenches;
Forming an opening penetrating the silicon support layer and the insulating layer and exposing the silicon device layer instead of the insulating pattern penetrating the silicon device layer;
Forming a first passivation layer and a first wiring pattern formed on the silicon support layer including the openings; And
Forming a second passivation layer and a second wiring pattern formed on the silicon device layer; Including,
Method of manufacturing a silicon electrical connection substrate. A substrate comprising silicon;
An insulating pattern penetrating the substrate including the silicon, the silicon oxide film oxidizing silicon by a thermal oxidation process;
A support substrate bonded to the substrate including silicon, the support substrate having an opening for exposing the substrate including silicon instead of the insulating pattern;
A first wiring pattern formed on the support substrate including the opening; And
A second wiring pattern formed on the substrate including silicon;
Including,
Silicon Electrical Substrates.

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