KR102018761B1 - Circuit for modulation gate pulse and display device including the same - Google Patents

Abstract

The present invention provides a gate pulse modulation circuit and a display device including the same, which can prevent a deterioration in image quality due to a kick-back voltage generated when the thin film transistor is turned off. A signal controller configured to generate the first switching signal according to a clock signal and a gate pulse modulated signal, and select one of the reference voltage and the ground voltage according to the gate pulse modulated signal and supply the voltage to the current sink unit And a voltage selector.

Description

Gate pulse modulation circuit and display device including the same {CIRCUIT FOR MODULATION GATE PULSE AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a display device, and more particularly, to a gate pulse modulation circuit and a display device including the same, which can prevent a deterioration in image quality due to a kick-back voltage generated when a thin film transistor is turned off.

The active matrix type liquid crystal display device or the organic light emitting display device includes a plurality of pixels formed in an intersection area of a plurality of data lines and a plurality of gate lines.

Each of the plurality of pixels is selected by the gate high voltage of the gate pulse supplied to the gate line to display an image corresponding to the data signal supplied from the data line. Each of the plurality of pixels may include at least one thin film transistor and at least one capacitor. The thin film transistor of each pixel is turned on according to the gate high voltage of the gate pulse supplied to the gate line to charge the capacitor with a data signal supplied to the data line. When the gate low voltage of the gate pulse is supplied to the gate line, the capacitor of each pixel maintains the turned-on state of the thin film transistor at the charged voltage.

As such, the voltage charged to the capacitor of each pixel is a kick-back voltage generated by the parasitic capacitance of the thin film transistor when the falling edge of the gate pulse, that is, the gate high voltage of the gate pulse falls to the gate low voltage. -back voltage). The kick-back voltage causes the voltage of the capacitor to fluctuate, resulting in deterioration of image quality such as flicker, afterimage, and color deviation in the display image.

To reduce the kick-back voltage, a gate pulse modulation circuit has been proposed that modulates the gate high voltage at the falling edge of the gate pulse.

1 is a view for explaining a conventional gate pulse modulation circuit.

Referring to FIG. 1, a conventional gate pulse modulation circuit includes first and second switching elements SW1 and SW2 and a resistor RE.

The first switching device SW1 outputs the gate high voltage VGH, which is switched according to the switching signal SCS, to the output node Tout. The second switching device SW2 is switched according to the second switching signal SCS2 to discharge the gate high voltage VGH of the output terminal Tout to the ground GND through the resistor RE. The resistor RE controls the discharge time for discharging the voltage on the output node Tout. The operation of the conventional gate pulse modulation circuit will be described as follows.

First, during the first period t1, the first switching element SW1 is turned on by the switching signal SCS, and the second switching element SW2 is turned off by the second switching signal SCS2. do. Accordingly, in the first period t1, the gate high voltage VGH is output to the output terminal Tout through the turned-on first switching device SW1.

Subsequently, during the second period t2, the first switching element SW1 is turned off by the switching signal SCS, and the second switching element SW2 is turned on by the second switching signal SCS2. do. Accordingly, in the second period t2, the output terminal Tout is connected to the ground GND through the resistor RE, so that the voltage on the output terminal Tout is turned on and the second switching element SW2 is turned on. By discharging to ground GND through resistor RE, the voltage on output terminal Tout goes to gate high modulation voltage VGH_GPM, which falls with a non-linear slope from gate high voltage VGH level to ground GND level. Is modulated.

The output voltage Vout of the conventional gate pulse modulation circuit is supplied to the gate driver, and the gate driver generates a gate pulse using the output voltage Vout of the gate pulse modulation circuit to control switching of the thin film transistor. . Accordingly, the falling edge of the gate pulse is modulated to a nonlinear slope by the gate high modulation voltage VGH_GPM, and thus the thin film transistor is gradually turned off, thereby improving image quality degradation due to the kick-back voltage.

However, according to the conventional gate pulse modulation circuit, since the falling edge of the gate pulse has a non-linear slope, there is a limit to improving image quality deterioration due to the kick-back voltage. There is a problem that must be replaced (RE).

The present invention has been made to solve the above-described problem, and to provide a gate pulse modulation circuit and a display device including the same that can prevent the degradation of the image quality due to the kick-back voltage generated when the thin film transistor is turned off. It is a task.

In addition to the technical task of the present invention mentioned above, other features and advantages of the present invention will be described below, or from such description and description will be clearly understood by those skilled in the art.

According to an aspect of the present invention, there is provided a gate pulse modulation circuit comprising: a first switching device configured to output a gate high modulation voltage having a voltage level equal to a gate high voltage input according to a first switching signal to an output terminal; A current sink to linearly reduce the gate high modulation voltage on the output terminal at the gate high voltage level through a current sink method; And a pulse modulation controller configured to generate the first switching signal to control switching of the first switching element and to supply a reference voltage or a ground voltage to the current sink.
The pulse modulation controller may include a signal controller generating the first switching signal according to a gate clock signal and a gate pulse modulation signal, and selecting any one of the reference voltage and the ground voltage according to the gate pulse modulation signal. And a voltage selector for supplying the current sink.

According to an aspect of the present invention, there is provided a display apparatus including a display panel including a pixel formed in each pixel region defined by an intersection of a plurality of gate lines and a plurality of data lines; A voltage generator configured to generate a gate high voltage and a gate low voltage by using an input power source; A gate high voltage modulator configured to output a gate high modulated voltage by modulating a gate high voltage supplied from the voltage generator; A data driver supplying a data voltage to the data line; A gate driver configured to generate a gate pulse using the gate high modulation voltage and the gate low voltage and sequentially supply the gate pulse to the plurality of gate lines; And a timing controller controlling the gate high voltage modulator, the data driver, and the gate driver, wherein the gate high voltage modulator includes the gate pulse modulation circuit.

The falling edge of the gate pulse is reduced by a linear slope from the gate high voltage level to the reference voltage level according to the gate high modulation voltage, and further reduced to the gate low voltage level.

The gate driver may include a shift register unit configured to sequentially output clock pulses according to a gate control signal supplied from the timing controller; And a level shifter unit configured to level shift the clock pulse using the gate high modulation voltage and the gate low voltage to generate the gate pulse and sequentially supply the gate pulse to the plurality of gate lines.

The timing controller supplies reference voltage setting data for setting the voltage level of the reference voltage to the gate high voltage modulator, and the pulse modulation controller of the gate high voltage modulator converts the reference voltage setting data into a digital-analog conversion. To generate the reference voltage and supply it to the current sink.

According to the gate pulse modulation circuit of the present invention and the display device including the same, the falling edge of the gate pulse has a linear slope to prevent image degradation due to the kick-back voltage generated when the thin film transistor is turned off. The effect is that the slope of the falling edge of the gate pulse can be set without replacing the resistor.

1 is a view for explaining a conventional gate pulse modulation circuit.
2 is a circuit diagram illustrating a gate pulse modulation circuit according to an embodiment of the present invention.
3 is a waveform diagram illustrating a falling slope of a gate high modulation voltage according to the present invention.
4 is a driving waveform diagram of a gate pulse modulation circuit according to an exemplary embodiment of the present invention.
5 is a view for explaining a display apparatus according to an exemplary embodiment.
FIG. 6 is a diagram for describing the gate driver illustrated in FIG. 5.
FIG. 7 is a waveform diagram of a gate pulse output from the gate driver shown in FIG. 5.

The meaning of the terms described herein will be understood as follows.

Singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and the terms “first”, “second”, and the like are intended to distinguish one component from another. The scope of the rights shall not be limited by these terms.

It is to be understood that the term "comprises" or "having" does not preclude the existence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

The term "at least one" should be understood to include all combinations which can be presented from one or more related items. For example, the meaning of "at least one of a first item, a second item, and a third item" means two items of the first item, the second item, and the third item, as well as two of the first item, the second item, and the third item, respectively. A combination of all items that can be presented from more than one.

Hereinafter, a preferred embodiment of a gate pulse modulation circuit and a display device including the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram illustrating a gate pulse modulation circuit according to an embodiment of the present invention, FIG. 3 is a waveform diagram illustrating a falling slope of a gate high modulation voltage according to the present invention, and FIG. 4 is an embodiment of the present invention. It is a drive waveform diagram of a gate pulse modulation circuit according to an example.

2 to 4, the gate pulse modulation circuit 10 according to an exemplary embodiment of the present invention may receive an input gate high based on a gate clock signal GCLK and a gate pulse modulation signal FLK supplied from the outside. The voltage VGH is modulated to the gate high modulation voltage VGH_GPM and output. To this end, the gate pulse modulation circuit 10 includes a pulse modulation controller 12, a first switching device SW1, and a current sink 14.

The pulse modulation controller 12 controls operations of the first switching element SW1 and the current sink 14 based on a gate clock signal GCLK and a gate pulse modulation signal FLK supplied from the outside. As a result, the output voltage Vout output to the output terminal Tout is controlled. To this end, the pulse modulation control unit 12 includes a signal control unit 12a, a reference voltage supply unit 12b, and a voltage selector 12c.

The signal controller 12a may be first only during the first period t1 based on a gate pulse modulation signal FLK and a gate clock signal GCLK supplied from a timing controller (not shown) of the display device. The first switching signal SCS1 for controlling the switching of the switching device SW is generated. For example, the signal controller 12a may include a first switching signal having a falling edge synchronized with the rising edge of the gate clock signal GCLK and a rising edge synchronized with the falling edge of the gate pulse modulation signal FLK. SCS1 may be generated. In this case, the first switching signal SCS1 has a low voltage level during the first period t1 and is high in periods other than the first period t1. It has a voltage level in a high state.

The reference voltage supply unit 12b digital-analog converts the reference voltage setting data RVSD supplied from the timing controller to generate a reference voltage Vref corresponding to the reference voltage setting data RVSD to generate a voltage selection unit 12c. To feed. Here, as shown in FIG. 3, the reference voltage setting data RVSD sets or varies the falling slope FS of the gate high modulation voltage VGH_GPM that decreases with a linear slope at the gate high voltage VGH level. It is to. Accordingly, according to the present invention, the polling slope FS and the gate high modulation voltage VGH_GPM of the gate high modulation voltage VGH_GPM are changed by changing the reference voltage setting data RVSD without replacing the resistor RE as in the related art. The lowest voltage level (Vgpm) can be adjusted.

On the other hand, the reference voltage supply unit 12b is not embedded in the pulse modulation control unit 12, and may generate the reference voltage Vref outside the pulse modulation control unit 12 to supply the voltage selection unit 12c. have.

The voltage selector 12c receives the ground voltage GND or the reference voltage Vref supplied from the reference voltage supply 12b according to the gate pulse modulation signal FLK supplied from the timing controller. Supplies). That is, when the gate pulse modulation signal FLK is in a high state, the voltage selector 12c selects and supplies the reference voltage Vref to the current sink 14 to supply the gate pulse. When the modulation signal FLK is in a low state, the ground voltage GND is selected and supplied to the current sink 14.

The first switching device SW1 is turned on according to the first switching signal SCS1 of the switch-on voltage supplied from the signal control unit 12a of the pulse modulation control unit 12 only during the first period t1. The gate high modulation voltage VGH_GPM having the same voltage level as the gate high voltage VGH supplied to the high voltage VGH line is output to the output terminal Tout. Accordingly, the gate high voltage VGH is charged in the load capacitor Cpanel connected to the output terminal Tout. For example, the first switching element SW1 is a P-type transistor, and is formed from a source terminal connected to a gate high voltage VGH line, a drain terminal connected to an output terminal Tout, and a pulse modulation controller 12. And a gate terminal to which the first switching signal SCS1 is supplied.

The current sink 14 is a gate high modulation voltage on the output terminal Tout in accordance with a current sink scheme based on the reference voltage Vref supplied from the voltage selector 12c of the pulse modulation controller 12. By discharging VGH_GPM to ground GND, the gate high modulation voltage VGH_GPM of the gate high voltage VGH is reduced with a linear slope. To this end, the current sink 14 includes a second switching element SW2, a resistor RE, and an operational amplifier OA.

The second switching element SW2 is switched according to the second switching signal SCS2 supplied from the operational amplifier OA to adjust the amount of current flowing from the output terminal Tout to the ground GND through the resistor RE. do. As described above, the second switching element SW2 is an N-type transistor, and includes a drain terminal connected to the output terminal Tout, a source terminal connected to the resistor RE, and a second switching signal from the operational amplifier OA. And a gate terminal to which the (SCS) is supplied.

The resistor RE is connected between the source terminal of the second switching element SW2 and the ground GND. The resistor RE discharges the current supplied from the output terminal Tout through the second switching element SW2 to the ground GND, thereby decreasing the gate high linearly at the gate high voltage VGH. The polling slope FS of the modulation voltage VGH_GPM is set. Here, the falling slope FS of the gate high modulation voltage VGH_GPM is determined by the capacitance of the load capacitor Cpanel, the resistance of the resistor RE, and the voltage level of the reference voltage Vref.

The operational amplifier OA includes an inverting input terminal (-) through which a feedback voltage Vfb is fed back from a feedback node Nf between the second switching element SW2 and the resistor RE, and the pulse modulation controller ( And a non-inverting input terminal (+) to which the reference voltage Vref or the ground voltage GND is supplied from the voltage selector 12c of 12. The operational amplifier OA outputs the second switching signal SCS2 according to the voltage supplied to the inverting input terminal (-) and the non-inverting input terminal (+), respectively, to switch the second switching element SW2. To control.

Specifically, when the ground voltage GND is supplied to the non-inverting input terminal (+), the operational amplifier OA outputs the second switching signal SCS2 of the switch-off voltage to the second switching element SW2. ) Is turned off so that the feedback voltage Vfb input to the inverting input terminal (-) becomes equal to the ground voltage GND.

In addition, when the reference voltage Vref is supplied to the non-inverting input terminal (+), the operational amplifier (OA) is inverted from the feedback node (Nf) according to the current flowing through the resistor (RE). The second resistor (Sf2) is controlled by outputting the second switching signal SCS2 of the switch-on voltage so that the feedback voltage Vfb is equal to the reference voltage Vref. The current flowing through RE) is made constant. Accordingly, as the current on the output terminal Tout is discharged to the ground GND through the turned-on second switching element SW2, the gate high modulation voltage VGH_GPM on the output terminal Tout becomes a gate high voltage. This decreases with a linear slope at the (VGH) level.

As described above, the operation of the gate pulse modulation circuit according to an embodiment of the present invention will be described.

First, in the first period t1, the first switching element SW1 is turned on and the second switching element SW2 is turned off so that the gate high voltage VGH supplied to the gate high voltage VGH line is provided. The gate high modulation voltage VGH_GPM of the same voltage level as is output to the output terminal Tout. That is, in the first period t1, the signal control unit 12a of the pulse modulation control unit 12 performs the low state based on the gate pulse modulation signal FLK and the gate clock signal GCLK. The first switching device SCS1 is generated to turn on the first switching device SW1. At the same time, the voltage selector 12c of the pulse modulation control unit 12 applies the ground voltage GND to the operational amplifier of the current sink 14 according to the gate pulse modulation signal FLK in a low state. The operational amplifier OA supplies the second switching signal SCS2 of the switch-off voltage according to the ground voltage GND supplied to the non-inverting input terminal +. And the second switching device SW2 is turned off.

Subsequently, in the second period t2, the first switching element SW1 is turned off and the second switching element SW2 is turned on so that the gate high modulation voltage VGH_GPM on the output terminal Tout is changed to the above state. It decreases with a linear slope at the gate high voltage (VGH) level. That is, in the second period t2, the signal control unit 12a of the pulse modulation control unit 12 changes high as the gate pulse modulation signal FLK in the low state changes to a high state. Generates a first switching signal SCS1 in a) state to turn off the first switching device SW1. At the same time, the voltage selector 12c of the pulse modulation control unit 12 selects the reference voltage Vref according to the gate pulse modulation signal FLK in a high state, thereby selecting the current sink 14. The feedback voltage is supplied to the non-inverting input terminal (+) of the operational amplifier (OA), and the operational amplifier (OA) is fed back from the feedback node (Nf) to the inverting input terminal (-) according to the current flowing through the resistor (RE). The switching of the second switching element SW2 is controlled such that Vfb is equal to the reference voltage Vref supplied to the non-inverting input terminal +. Accordingly, the current on the output terminal Tout is discharged to the ground GND through current paths leading to the output terminal Tout, the second switching element SW2, the resistor RE, and the ground GND. The gate high modulation voltage VGH_GPM on the output terminal Tout is reduced by a linear slope at the gate high voltage VGH level.

Then, when the gate pulse modulation signal FLK in the high state is changed to the low state, the voltage selector 12c of the pulse modulation control unit 12 is in the low state gate pulse modulation. The ground voltage GND is selected according to the signal FLK and supplied to the non-inverting input terminal + of the operational amplifier OA of the current sink 14, whereby the operational amplifier OA inputs the non-inverting input. The second switching device SW2 is turned off according to the ground voltage GND supplied to the terminal +. Accordingly, the gate high modulation voltage VGH_GPM decreasing with the linear slope is maintained at the polling voltage Vgpm at the polling time of the gate pulse modulation signal FLK. Here, the falling voltage Vgpm is determined by the capacitance of the load capacitor Cpanel and the resistance value of the resistor RE, the voltage level of the reference voltage Vref, and the pulse width of the gate pulse modulation signal FLK. Will be determined.

As described above, the gate pulse modulation circuit according to the embodiment of the present invention repeats the above operation based on the gate pulse modulation signal FLK and the gate clock signal GCLK.

5 is a view illustrating a display device according to an exemplary embodiment of the present invention, FIG. 6 is a view illustrating the gate driver illustrated in FIG. 5, and FIG. 7 is a gate output from the gate driver illustrated in FIG. 5. The waveform diagram of the pulse.

5 to 7, a display apparatus according to an exemplary embodiment of the present invention may include a display panel 110, a voltage generator 120, a timing controller 130, a data driver 140, and a gate high voltage modulator ( 150, and a gate driver 160.

The display panel 110 includes a plurality of pixels P formed for each pixel area defined by the intersection of the plurality of data lines DL and the plurality of gate lines GL. Each of the plurality of pixels P is selected by the gate pulse GP supplied to the gate line GL to display an image corresponding to the data signal Vdata supplied from the data line DL. Each of the plurality of pixels P may include at least one thin film transistor (not shown) and at least one capacitor (not shown). The thin film transistor of each pixel is turned on according to the gate high voltage VGH of the gate pulse GP supplied to the gate line GL to charge the capacitor with a data signal supplied to the data line DL. . When the gate low voltage VGL of the gate pulse GP is supplied to the gate line GL, the capacitor of each pixel P maintains the turned-on state of the thin film transistor at the charged voltage. The plurality of pixels P may be a liquid crystal cell driving liquid crystals according to the data voltage Vdata or a light emitting cell emitting light of the organic light emitting element according to a data current corresponding to the data voltage Vdata.

The voltage generator 120 uses the input power Vin, which is input from the outside, to the gate high voltage VGH for turning on the thin film transistor and the gate low voltage for turning off the thin film transistor. Generate and output each (VGL).

The timing controller 130 generates each of the data control signal DCS and the gate control signal GCS based on a timing synchronization signal TSS input from an external system main body (not shown) or a graphics card (not shown). The data driver 140 is controlled through the data control signal DCS, and the gate driver 160 is controlled through the gate control signal GCS to be synchronized with the data driver 140. Here, the data control signal may include a source start pulse, a source shift clock, a source output enable, and the like. The gate control signal GCS may include a gate start pulse Vst, a plurality of gate clock signals GSC, a gate pulse modulated signal FLK, and the like.

In addition, the timing controller 130 converts the digital input data RGB input from an external system main body (not shown) or a graphics card (not shown) into the display data DATA so as to be suitable for driving the display panel 110. The alignment is supplied to the data driver 140. The timing controller 130 supplies the reference voltage setting data RVSD stored in the memory (not shown) to the gate high voltage modulator 150.

The data driver 140 samples the display data DATA input according to the data control signal DCS supplied from the timing controller 130, and converts the gray voltage corresponding to the sampled data among the plurality of gray voltages into a data voltage. Selected as Vdata and supplied to the data line DL in units of horizontal periods of the display panel 110.

The gate high voltage modulator 150 is supplied from the power generator 120 according to the gate clock signal GSC and the gate pulse modulated signal FLK supplied from the timing controller 130. The voltage VGH is modulated to the gate high modulation voltage VGH_GPM and supplied to the gate driver 160. Since the gate high voltage modulator 150 is the gate pulse modulation circuit 10 according to the present invention described above with reference to FIGS. 2 to 4, description thereof will be omitted.

The gate driver 160 generates clock pulses CP1 to CPm sequentially shifted according to the gate control signal GCS supplied from the timing controller 130, and is supplied from the gate high voltage modulator 150. Level shifts the clock pulses CP1 to CPm to the gate pulses GP1 to GPm by using the gate high modulation voltage VGH_GPM and the gate low voltage VGL supplied from the power generator 120. Supply to line GL. To this end, the gate driver 160 includes a shift register unit 162 and a level shifter unit 164.

The shift register unit 162 starts to drive the gate control signal GCS, that is, the gate start pulse Vst, and sequentially selects the plurality of gate shift clocks GSC and outputs them as clock pulses CP1 to CPm. . To this end, the shift register unit 162 includes a plurality of stages ST1 to STm. Each of the plurality of stages ST1 to STm receives one of the plurality of gate shift clocks GSC according to the output signal of the gate start pulse Vst or the front stages ST1 to STm-1, and the clock pulses CP1 to CPm. Select to print.

The level shifter unit 164 is sequentially shifted from the shift register unit 162 as shown in FIG. 7 by using the gate low voltage VGL and the gate high modulation voltage VGH_GPM. Each of the pulses CP1 to CPm is level-shifted to the gate pulses GP1 to GPm to be supplied to the gate line GL. To this end, the level shifter unit 164 includes a plurality of level shifters LS1 to LSm. The gate low voltage VGL and the gate high modulation voltage VGH_GPM are respectively supplied to the plurality of level shifters LS1 to LSm. Accordingly, each of the plurality of level shifters LS1 to LSm includes the high level of the input clock pulses CP1 to CPm as the gate high modulation voltage VGH_GPM and the low level as the gate. Level-shift each to a low voltage (VGL). Therefore, the falling edge voltage of the gate pulse GP supplied to the gate line GL decreases with a linear slope during the falling time corresponding to the pulse width of the gate pulse modulation signal FLK at the gate high voltage VGH level. After that, the gate row voltage VGL level is further reduced.

As described above, according to the display device according to the exemplary embodiment of the present invention, the falling edge of the gate pulse has a linear slope to prevent deterioration of image quality due to the kick-back voltage generated when the thin film transistor is turned off. And the falling edge slope and voltage of the gate pulse can be changed without replacing the resistor RE.

Meanwhile, the display device of the present invention may be a liquid crystal display device, an organic light emitting display device, or an electrophoretic display device that sequentially supplies a gate pulse (or scan pulse) to the gate lines (or scan lines).

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical matters of the present invention. It will be evident to those who have knowledge of. Therefore, the scope of the present invention is represented by the following claims, and it should be construed that all changes or modifications derived from the meaning and scope of the claims and equivalent concepts thereof are included in the scope of the present invention.

10: gate pulse modulation circuit 12: pulse modulation control unit
12a: signal controller 12b: reference voltage supply
12c: voltage selector 14: current sink
SW1: first switching element SW2: second switching element
OA: Operational Amplifiers RE: Resistance
110: display panel 120: voltage generator
130: timing controller 140: data driver
150: gate high voltage modulator 160: gate driver
162: shift register section 164: level shifter section

Claims (10)

A first switching element configured to output a gate high modulation voltage having the same voltage level as the gate high voltage input according to the first switching signal to an output terminal;
A current sink to linearly reduce the gate high modulation voltage on the output terminal at the gate high voltage level through a current sink method; And
A pulse modulation controller configured to generate the first switching signal to control switching of the first switching element, and supply a reference voltage or a ground voltage to the current sink,
The pulse modulation control unit,
A signal controller configured to generate the first switching signal according to a gate clock signal and a gate pulse modulated signal; And
And a voltage selector configured to select one of the reference voltage and the ground voltage according to the gate pulse modulated signal and supply the selected voltage to the current sink. delete The method of claim 1,
And the reference voltage is varied at a voltage level between the gate high voltage and the ground voltage. The method of claim 1,
And the pulse modulation controller further comprises a reference voltage generator for digitally-analog converting reference voltage setting data supplied from the outside to generate the reference voltage and supply the reference voltage to the voltage selector. The method of claim 1,
The current sink unit,
A second switching element connected between the output terminal and ground;
A resistor connected between the second switching element and the ground; And
And an operational amplifier configured to generate a second switching signal according to a feedback voltage corresponding to a current flowing through the resistor and a voltage supplied from the voltage selector to control switching of the second switching element. Modulation circuit. The method of claim 5,
The operational amplifier,
When the ground voltage is supplied from the voltage selector, the second switching device is turned off,
And when the reference voltage is supplied from the voltage selector, controlling the switching of the second switching element such that the feedback voltage and the reference voltage are the same. A display panel including pixels formed in pixel areas defined by intersections of the plurality of gate lines and the plurality of data lines;
A voltage generator configured to generate a gate high voltage and a gate low voltage by using an input power source;
A gate high voltage modulator configured to output a gate high modulated voltage by modulating a gate high voltage supplied from the voltage generator according to a gate clock signal and a gate pulse modulated signal;
A data driver supplying a data voltage to the data line;
A gate driver configured to generate a gate pulse using the gate high modulation voltage and the gate low voltage and sequentially supply the gate pulse to the plurality of gate lines; And
A timing controller controlling each of the gate high voltage modulator, the data driver, and the gate driver;
7. The display device according to claim 1, wherein the gate high voltage modulator comprises the gate pulse modulation circuit according to any one of claims 1, 3, and 6. The method of claim 7, wherein
The falling edge of the gate pulse decreases from the gate high voltage level to a linear slope during the polling time corresponding to the pulse width of the gate pulse modulated signal according to the gate high modulation voltage, and then further decreases to the gate low voltage level. Display device characterized in that. The method of claim 7, wherein
The gate driver,
A shift register unit configured to sequentially output clock pulses according to a gate control signal supplied from the timing controller; And
And a level shifter unit configured to level shift the clock pulse using the gate high modulation voltage and the gate low voltage to generate the gate pulse and sequentially supply the gate pulse to the plurality of gate lines. The method of claim 7, wherein
The timing controller supplies reference voltage setting data for setting the voltage level of the reference voltage to the gate high voltage modulator,
And the pulse modulation controller of the gate high voltage modulator generates the reference voltage by digital-analog converting the reference voltage setting data and supplies the generated reference voltage to the current sink.

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