KR102003734B1 - Liquid crystal display device and method for driving the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof in which a low frequency drive reduces power consumption and heat generation while preventing display quality degradation.
In accordance with another aspect of the present invention, a method of driving a liquid crystal display device includes: selecting a driving frequency for displaying an image by analyzing input source image data; Controlling driving of a gate driver to generate a scan signal and a data driver to generate a data voltage based on the driving frequency selection; Supplying scan signals to the plurality of gate lines and supplying data voltages to the plurality of data lines in a first frame period of the plurality of frames; And maintaining the data voltage charged in all the pixels in the first frame period without supplying the scan signal and the data voltage in the second frame period.

Description

Liquid crystal display device and driving method thereof {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of driving the same, which reduce power consumption and heat generation and reduce display quality by low frequency driving.

Liquid crystal display devices are popularized due to the development of mass production technology, ease of driving means, low power consumption, high definition and large screen, and the field of application is continuously expanding.

In the liquid crystal panel, a plurality of gate lines GL and a plurality of data lines DL are formed to cross each other to define a pixel region, and each pixel region includes red (R), green (G), and blue (B) subpixels. Formed. Three color R, G, and B sub-pixels are combined to form one unit pixel P. As shown in FIG. The full color image is displayed by adjusting the transmittance of light irradiated to each sub-pixel from the backlight unit (not shown).

Liquid crystal display devices have developed high frequency driving technology to improve motion blur, afterimage, and flicker, which are factors that contribute to image quality deterioration. In addition to general 60Hz driving, high-frequency driving technologies such as 120Hz, 240Hz, and 480Hz have been developed to realize high image quality.

However, unlike TVs using commercial power, mobile devices such as mobile phones and IT products are powered by batteries and are sensitive to power consumption. In order to reduce power consumption, low frequency driving technology is drawing attention.

1 is a diagram illustrating a general dot inversion driving scheme, and FIG. 2 is a diagram illustrating a problem in which flicker is generated by low frequency driving. 1 illustrates a one-dot inversion scheme as an example.

1 and 2, the liquid crystal display device has polarities opposite to each other in a frame unit, a line unit, a column unit, or a dot unit to prevent pixel degradation. An inversion method that symmetrically applies a data voltage to a pixel is applied.

When driving at 30 Hz by applying low frequency driving, there is a problem in that flicker occurs due to the luminance difference between the nth frame and the n + 1th frame. In addition, when driving at a low frequency, the change in the transmittance of the pixel is increased due to leakage of the pixel voltage, and the deviation of the transmittance of the pixel occurs at the boundary point of the frames due to the offset of the common voltage Vcom, causing the flicker to deepen. There is this.

Disclosure of Invention The present invention has been made in view of the above-described problems, and it is an object of the present invention to provide a liquid crystal display device and a driving method thereof capable of preventing flicker generation due to low frequency driving.

Disclosure of Invention The present invention has been made in view of the above-described problems, and it is an object of the present invention to provide a liquid crystal display device and a driving method thereof capable of reducing power consumption without deteriorating image quality.

In addition to the technical task of the present invention mentioned above, other features and advantages of the present invention will be described below, or from such description and description will be clearly understood by those skilled in the art.

According to an exemplary embodiment of the present invention, a liquid crystal display includes: a liquid crystal panel having a plurality of pixels turned on by a scan signal supplied from a gate driver and to which a data voltage supplied from a data driver is applied; A mode selector configured to select a driving frequency to display an image by analyzing input source image data; And a timing controller for aligning image data based on selection of a driving frequency of the mode selector and controlling driving of the gate driver and the data driver, wherein the scan signal is lower than a driving frequency of the source image data. And generating the data voltage to display an image.

In accordance with another aspect of the present invention, a method of driving a liquid crystal display device includes: selecting a driving frequency for displaying an image by analyzing input source image data; Controlling driving of a gate driver to generate a scan signal and a data driver to generate a data voltage based on the driving frequency selection; Supplying scan signals to the plurality of gate lines and supplying data voltages to the plurality of data lines in a first frame period of the plurality of frames; And maintaining the data voltage charged in all the pixels in the first frame period without supplying the scan signal and the data voltage in the second frame period.

The liquid crystal display device and the driving method thereof according to the embodiment of the present invention can prevent the generation of flicker due to low frequency driving.

The liquid crystal display device and the driving method thereof according to the embodiment of the present invention can reduce power consumption without deterioration of image quality.

The liquid crystal display device and the driving method thereof according to the embodiment of the present invention can reduce the heat generation of the driving circuit unit through low frequency driving.

In addition to the features and effects of the present invention mentioned above, other features and effects of the present invention may be newly understood through the embodiments of the present invention.

1 is a diagram illustrating a general dot inversion driving method.
2 is a diagram illustrating a problem in which flicker is generated by low frequency driving.
3 is a diagram illustrating a liquid crystal display device according to an exemplary embodiment of the present invention.
4 and 5 are diagrams illustrating an example of a low frequency driving method of a liquid crystal display according to an exemplary embodiment of the present invention.
6 and 7 illustrate another example of a low frequency driving method of the liquid crystal display according to the exemplary embodiment of the present invention.

Various liquid crystal panels, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in plane switching (IPS) mode, and fringe field switching (FFS) mode, have been developed according to a method of adjusting the arrangement of the liquid crystal layer.

In the TN mode and the VA mode, the pixel electrode is disposed on the lower substrate, and the common electrode is disposed on the upper substrate to adjust the arrangement of the liquid crystal layer by a vertical electric field between the pixel electrode and the common electrode.

In the IPS mode and the FFS mode, the pixel electrode and the common electrode are disposed on the lower substrate. The IPS mode adjusts the arrangement of the liquid crystal layer by the horizontal electric field between the pixel electrode and the common electrode, and the FFS mode controls the arrangement of the liquid crystal layer in the fringe field between the pixel electrode and the common electrode.

In the liquid crystal display according to the exemplary embodiment, all of the above-described TN mode, VA mode, IPS mode, and FFS mode may be applied.

Hereinafter, a liquid crystal display device and a driving method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

3 is a diagram illustrating a liquid crystal display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a liquid crystal display device according to an exemplary embodiment of the present invention includes a liquid crystal panel 100 and a driving circuit unit for driving the liquid crystal panel 100. In addition, although not shown in the drawings, the liquid crystal panel 100 includes a backlight unit for supplying light and a power supply for supplying power for driving.

The liquid crystal panel 100 includes an upper substrate and a lower substrate bonded together with a liquid crystal layer interposed therebetween.

The upper substrate is formed with a matrix of red, green, and blue color filters for displaying a color image, and a black matrix is formed between the red, green, and blue color fills to distinguish each subpixel area. .

A plurality of gate lines GL and a plurality of data lines DL are formed on the lower substrate so that the pixel region is defined by the intersection of the gate lines and the data lines.

One pixel is composed of three red (R), green (G), and blue (B) subpixels. Each subpixel is formed with a thin film transistor (TFT) and a storage capacitor (Cst) as switching elements.

The liquid crystal panel includes a pixel electrode for supplying a data voltage to each pixel and a common electrode for supplying a common voltage Vcom.

Here, in order to adjust the arrangement of the liquid crystal layer, the pixel electrode may be formed on the lower substrate, and the common electrode may be formed on the lower substrate or the upper substrate. In the TN mode or the VA mode, the common electrode is formed on the upper substrate. Meanwhile, in the IPS mode or the FFS mode, the common electrode is formed on the lower substrate.

The liquid crystal panel 100 having the above-described configuration adjusts the arrangement of liquid crystals by using an electric field corresponding to the data voltage supplied to the subpixel, that is, the pixel voltage and the common voltage Vcom supplied to the common electrode. The transmittance is controlled by the light from the backlight unit through the arrangement of the liquid crystals. The light passing through the red, green, and blue color filters is emitted as a unique color light to display a color image.

The TFTs formed on the subpixels of the liquid crystal panel 100 vary in driving characteristics, reliability, and manufacturing processes depending on the materials for forming the semiconductor layers. Conventionally, a semiconductor layer of a TFT is formed of amorphous silicon or polycrystalline silicon, but amorphous silicon has advantages in that a film forming process is simple and production cost is low, but driving characteristics and reliability are not secured. Polycrystalline silicon is very difficult to apply a large area due to the high process temperature, there is a problem that the uniformity according to the crystallization method is not secured.

In the present invention, a TFT is formed of an oxide semiconductor having excellent operating characteristics and driving reliability. The oxide semiconductor applied to the present invention is an amorphous form and stable material, it is possible to manufacture the oxide TFT at a low temperature by using the existing process equipment without purchasing additional process equipment, various advantages such as the ion implantation process is omitted There is this.

As described above, the oxide TFT is applied as the switching element of the pixel, and the driving circuit unit and the driving method of the present invention described below are applied, so that even when the liquid crystal display device is driven at a low frequency of 30 Hz or less, the leakage of pixel voltage and the transmittance of the pixel are changed. By preventing or reducing the occurrence of flicker due to low frequency driving.

Referring back to FIG. 3, the driving circuit unit includes a gate driver 200, a data driver 300, a timing controller 400, and a mode selector 500.

The mode selector 500 selects a mode of the driving frequency to generate the scan signal and the data voltage at a driving frequency lower than the driving frequency of the input source image data, and the gate driver 200 and the data through the timing controller 400. The driving of the driver 300 may be controlled to display an image on the liquid crystal panel 100 with low frequency driving.

The mode selector 500 selects a driving mode by analyzing the input source image data. The mode selector 500 selects a driving frequency to display an image, generates a selection result of the driving frequency as a mode selection signal (MCS), and supplies the result to the timing controller 400. At this time, the driving frequency may be selected from 60Hz, 30Hz, 10Hz, 6Hz, 5Hz, 3Hz, 2Hz, 1Hz.

Here, the source image data may be input to the mode selector 500 at a driving frequency of 60 Hz, 100 Hz, 120 Hz, 200 Hz, 240 Hz, 400 Hz, 480 Hz, or 480 Hz or more.

Image data analysis of the mode selector 500 for selecting a driving frequency may be continuously performed every second, that is, every second. However, the present invention is not limited thereto, and the image data analysis of the mode selector 500 for selecting the driving frequency is performed in units of 1 second (1 sec) to 60 seconds (60 sec) or 1 minute (1 min) to 60 minutes (60 min). May also be achieved.

The mode selector 500 may select a mode of the driving frequency to display an image at 30 Hz when there are many screen changes as a result of analysis of the input image data.

On the other hand, the mode selector 500 may select a mode of the driving frequency to display an image in one of 10 Hz, 6 Hz, 5 Hz, 3 Hz, 2 Hz, and 1 Hz when the screen change is small as a result of analysis of the input image data. For example, when the input image data is a still image, the driving frequency may be selected as 1 Hz to scan the entire pixel only once for one second and supply the data voltage to all the pixels.

The mode selection signal MCS according to the driving frequency selection result of the mode selection unit 500 is supplied to the timing controller 400, and the timing controller 400 is based on the mode selection signal. Control the driving of 300).

The timing controller 400 converts the input image data data into digital image data R, G, and B in units of frames based on the input timing signal TS and the mode selection signal, and is arranged in units of frames. The digital image data is supplied to the data driver 300. The timing signal TS includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal CLK.

In addition, the timing controller 400 generates a gate control signal GCS for controlling the gate driver 200 and a data control signal DCS for controlling the data driver 300 according to the mode selection signal MCS. do. The gate control signal GCS is supplied to the gate driver 200, and the data control signal DCS is supplied to the data driver 300. In this case, the gate control signal GCS and the data control signal DCS are generated using the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the clock signal CLK.

The data control signal DCS includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE) and a polarity control signal (POL: polarity). It may include.

The gate control signal GCS may include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), and the like.

In addition, the timing controller 400 may control driving of the backlight driver based on the input image data and the timing signal TS.

The gate driver 200 generates a scan signal for driving the TFTs formed in each of the plurality of pixels based on the gate control signal (GCS) from the timing controller 400. . The generated scan signal is supplied to a plurality of gate lines formed in the liquid crystal panel 100 during one frame period.

The TFTs formed in each subpixel are turned on by the scan signal supplied to the gate line so that the data voltage can be supplied to the subpixels. In this case, the gate driver 200 does not generate a scan signal corresponding to a driving frequency of the image data input to the first system, for example, 60 Hz or 120 Hz, but instead is generated by the mode selection signal generated by the mode selector 500. Accordingly, a scan signal corresponding to one of driving frequencies of 30 Hz, 10 Hz, 6 Hz, 5 Hz, 3 Hz, 2 Hz, and 1 Hz may be generated and supplied to the gate line.

The data driver 300 includes a plurality of source drive ICs, and each source drive IC converts digital image data supplied from the timing controller 400 into analog image data, that is, data voltage. A plurality of horizontal voltages are formed on the liquid crystal panel 100 in accordance with the time point at which the TFTs of the respective subpixels are turned on based on the data control signal (DCS) from the timing controller 400. Supply to the data line.

That is, the data driver 300 does not generate a data voltage corresponding to a driving frequency of the image data input to the system, for example, 60 Hz or 120 Hz, but rather to the mode selection signal generated by the mode selector 500. Accordingly, a data voltage corresponding to one of the driving frequencies of 30 Hz, 10 Hz, 6 Hz, 5 Hz, 3 Hz, 2 Hz, and 1 Hz may be generated and supplied to the data line.

In addition, the common voltage Vcom is supplied to the common electrodes formed on the plurality of pixels formed in the liquid crystal panel 100. An electric field is formed in each pixel by the data voltage and the common voltage Vcom supplied to each of the plurality of pixels, and the light transmittance of each pixel can be controlled by arranging liquid crystals by the electric field.

4 and 5 are diagrams illustrating an example of a low frequency driving method of a liquid crystal display according to an exemplary embodiment of the present invention. An example of displaying an image at a 30 Hz driving frequency when the source image data is input to the system at a 60 Hz driving frequency is shown.

4 illustrates a scan signal for displaying an image at a 30 Hz driving frequency, and FIG. 5 illustrates a polarity signal POL, a common voltage Vcom, and a data voltage for displaying an image at a 30 Hz driving frequency.

4 and 5, as a result of analysis of the input image data of the mode selector 500, when there are many screen changes, the mode of the driving frequency may be selected to display the image at 30 Hz.

The timing controller 400 controls the driving of the gate driver 200 based on the mode selection signal according to the selection result of the driving frequency, and the gate driver 200 generates a scan signal to match the 30Hz driving frequency to generate the gate lines. Feed sequentially.

In addition, the timing controller 400 controls the driving of the data driver 300 to generate the image data at the 30 Hz driving frequency based on the mode selection signal according to the selection result of the driving frequency, and the data driver 300 controls the 30 Hz driving frequency. The data voltage is generated so as to supply the entire pixel through the data line.

In the case of a 60 Hz driving frequency, a scan signal was supplied to the entire gate line every frame. However, at the 30 Hz driving frequency, the scan signal is supplied to all the gate lines during the first frame period to scan all the pixels. The scan signal is not supplied to all the gate lines during the second frame period. At this time, the polarity signal POL is generated at 60 Hz in synchronization with the frequency of the source image data.

In the first frame period, a scan signal is normally generated to scan all pixels. In the first frame period, the data voltage of positive polarity is supplied to all the pixels according to the polarity signal, and the common voltage Vcom is supplied.

In the second frame period during which the scan signal is not supplied, that is, the holding frame period, the data voltage input to the pixel in the first frame period is maintained as it is. In this case, the source output enable (SOE) is turned off so that the data voltage is not supplied from the data driver 300 to the data line.

Here, even though the scan signal and the data voltage are not supplied to the pixel during the holding frame period, the image should be displayed, so that the gate low voltage VGL and the common voltage Vcom are normally supplied. On the other hand, the scan signal, the clock signal CLK, the gate high voltage VGH, and the source output enable (SOE) are turned off.

When the data voltage is charged to the pixel at the 30 Hz driving frequency, the charging time is made in one frame period (16.67 ms) equal to the 60 Hz driving frequency.

After charging the data voltage to the pixel, the previously input data voltage is maintained as it is without applying a new data voltage to the pixel for one frame period (16.67 ms).

That is, in the odd-numbered frame period, the scan signal may be supplied to all the gate lines to scan all the pixels, and the data voltage may be supplied to all the data lines to apply the data voltages to all the pixels. In the even-numbered frame period, the scan signal is not supplied to all the gate lines, and the data voltage is not supplied to all the data lines.

On the contrary, in even-numbered frame periods, scan signals may be supplied to all gate lines to scan all pixels, and data voltages may be applied to all data lines to apply data voltages to all pixels. The scan signal is not supplied to all the gate lines and the data voltage is not supplied to all the data lines in the odd frame period.

In this manner, even when driven at a 30 Hz driving frequency, the oxide TFT formed in the pixel has excellent leakage current characteristics, so that image data input in the previous frame period can be maintained without leaking in the holding frame period.

Here, during one second (1sec), the data voltage of positive polarity is applied to all the pixels so that the luminance difference due to the polarity imbalance of the liquid crystal voltage of the pixels does not occur and thus no flicker occurs.

However, if the data voltage of the same polarity is continuously applied to the pixel, afterimage may occur due to deterioration, thereby inverting the polarity of the data voltage every 1 second.

For example, during the initial 1 second time, a positive polarity data voltage is supplied to all pixels during a frame period in which scan signals and data voltages are supplied, and a scan signal and data voltage is not supplied to all pixels during a holding frame period. Keep it intact.

Thereafter, during the next 1 second time, the data voltage of negative polarity is supplied to all the pixels during the frame period in which the scan signal and the data voltage are supplied, and the scan signal and the data voltage are not supplied to all the pixels during the holding frame period. Keep it as it is.

In this way, the polarity of the pixels is balanced by reversing the polarities of the data voltages supplied to all the pixels in units of 1 second, thereby preventing afterimages from occurring due to polarization of the polarities.

6 and 7 illustrate another example of a low frequency driving method of the liquid crystal display according to the exemplary embodiment of the present invention. An example of displaying an image at a 10 Hz driving frequency when the source image data is input to the system at a 60 Hz driving frequency is shown.

6 illustrates a scan signal for displaying an image at a 10 Hz driving frequency, and FIG. 7 illustrates a polarity signal POL, a common voltage Vcom, and a data voltage for displaying an image at a 10 Hz driving frequency.

6 and 7, when the screen change is small as a result of analyzing the input image data of the mode selector 500, the mode of the driving frequency may be selected to display the image at 10 Hz.

The timing controller 400 controls the driving of the gate driver 200 based on the mode selection signal according to the result of the selection of the driving frequency, and the gate driver 200 generates a scan signal in accordance with the 10 Hz driving frequency to generate the gate lines. Feed sequentially.

In addition, the timing controller 400 controls the driving of the data driver 300 to generate image data at a 10 Hz driving frequency based on the mode selection signal according to the selection result of the driving frequency, and the data driver 300 controls the 10 Hz driving frequency. The data voltage is generated so as to supply the entire pixel through the data line.

Among the 60 frame periods, the scan signal and the data voltage are supplied to all the pixels in the first frame period, and the data voltages charged in all the pixels in the first frame period in the second to Nth frame periods after the first frame. Keep it.

Subsequently, scan signals and data voltages are supplied to all pixels in the N + 1 frame period, and N + 2 frames to 2N frames after the N + 1 frame maintain the data voltages charged in all pixels in the first frame period in this period. Let's do it.

Specifically, in the case of a 60 Hz driving frequency, the scan signal is supplied to all the gate lines every frame. However, at the 10 Hz driving frequency, the scan signal is supplied to all the gate lines during the first frame period to scan all the pixels. The scan signal is not supplied to all of the gate lines during the second to sixth frame periods. At this time, the polarity signal POL is generated at 60 Hz in synchronization with the frequency of the source image data.

Thereafter, during the seventh frame period, all pixels are scanned by supplying a scan signal to all of the gate lines. The scan signal is not supplied to all of the gate lines during the eighth to twelfth frame periods.

As described above, in the first frame period among the six frame periods, the scan signal is supplied to all the gate lines to scan all the pixels. Thereafter, the scan signal is not supplied to the entire gate line in five frame periods (second to sixth frames).

Specifically, among the six frames, a scan signal is normally generated in the first frame period to scan all pixels. In the first frame period, the data voltage of positive polarity is supplied to all the pixels according to the polarity signal, and the common voltage Vcom is supplied.

Thereafter, in the five frame periods (second to sixth frames) that are not supplied with the scan signal, that is, the holding frame period, the data voltage input to the pixel in the first frame period is divided into five frame periods (the second frame period). Frame to sixth frame). In this case, the source output enable (SOE) is turned off so that the data voltage is not supplied from the data driver 300 to the data line.

Here, even though the scan signal and the data voltage are not supplied to the pixel during the holding frame period, the image should be displayed, so that the gate low voltage VGL and the common voltage Vcom are normally supplied. On the other hand, the scan signal, the clock signal CLK, the gate high voltage VGH, and the source output enable (SOE) are turned off.

When the data voltage is charged to the pixel at the 10 Hz driving frequency, the charging time is made in one frame period (16.67 ms) equal to the 60 Hz driving frequency.

After charging the data voltage to the pixel, the previously input data voltage is maintained as it is without applying a new data voltage to the pixel for five frame periods (83.33 ms).

In this way, even when driven at a 10 Hz driving frequency, the oxide TFT formed in the pixel has excellent leakage current characteristics, so that image data input in the previous frame period can be maintained without leaking in the holding frame period.

During an initial 1 second time, a data period of positive polarity is supplied to all pixels in a frame period during which a scan signal and a data voltage are supplied, that is, a frame corresponding to 1/6 of a plurality of frames. During the holding frame period corresponding to 5/6 of the plurality of frames, scan signals and data voltages are maintained without being supplied to all pixels.

Subsequently, a data voltage of negative polarity is supplied to all pixels in a frame period during which a scan signal and a data voltage are supplied, that is, a frame corresponding to 1/6 of a plurality of frame periods, during the next 1 second time. During the holding frame period corresponding to 5/6 of the plurality of frame periods, the scan signal and the data voltage are not supplied to all the pixels, and are maintained.

In this way, the polarity of the pixels is balanced by reversing the polarities of the data voltages supplied to all the pixels in units of 1 second, thereby preventing afterimages from occurring due to polarization of the polarities.

Although not shown in the drawing, as a result of analysis of the input image data of the mode selector 500, in the case of a still image, the mode of the driving frequency may be selected to display the image at 1 Hz.

The timing controller 400 controls the driving of the gate driver 200 and the data driver 300 based on the mode selection signal according to the selection result of the driving frequency. The gate driver 200 generates a scan signal in accordance with the 1 Hz driving frequency and sequentially supplies the scan signal to the gate lines, and the data driver 300 generates a data voltage in accordance with the 1 Hz driving frequency and applies the data voltage to all pixels through the data line. Supply.

When the driving frequency is 1 Hz, a scan signal is supplied to all the gate lines during the first frame period to scan all the pixels among the 60 frames. The scan signal is not supplied to all of the gate lines during the second to sixtyth frame periods. At this time, the polarity signal POL is generated at 60 Hz in synchronization with the frequency of the source image data.

A scan signal is normally generated in the first frame period of the 60 frames to scan all the pixels. In the first frame period, the data voltage of positive polarity is supplied to all the pixels according to the polarity signal, and the common voltage Vcom is supplied.

Subsequently, in the 59 frame periods (second frame to 60th frame) in which the scan signal is not supplied, that is, the holding frame period, the data voltage input to the pixel in the first frame period is converted into 59 frame periods (the second frame period). Frame to 60th frame). In this case, the source output enable (SOE) is turned off so that the data voltage is not supplied from the data driver 300 to the data line.

Here, even though the scan signal and the data voltage are not supplied to the pixel during the holding frame period, the image should be displayed, so that the gate low voltage VGL and the common voltage Vcom are normally supplied. On the other hand, the scan signal, the clock signal CLK, the gate high voltage VGH, and the source output enable (SOE) are turned off.

After the data voltage is charged to all the pixels for one frame period (16.67 ms), the previously input data voltage is maintained as it is without applying a new data voltage to the pixels for the 59 frame periods (983.33 ms). In this way, even when driven at a 10 Hz driving frequency, the oxide TFT formed in the pixel has excellent leakage current characteristics, so that image data input in the previous frame period can be maintained without leaking in the holding frame period.

During the initial 1 second time, a data period of positive polarity is supplied to all pixels in a frame period during which a scan signal and a data voltage are supplied, that is, a frame corresponding to 1/60 of a plurality of frames. In the holding frame period corresponding to the remaining 59/60, the data voltage is maintained without being supplied.

The data voltage of negative polarity is supplied to all the pixels in the frame period during which the scan signal and the data voltage are supplied, that is, the frame corresponding to 1/60 of the plurality of frames during the next 1 second time. In the holding frame period corresponding to the remaining 59/60, the data voltage is maintained without being supplied.

In this way, the polarity of the pixels is balanced by reversing the polarities of the data voltages supplied to all the pixels in units of 1 second, thereby preventing afterimages from occurring due to polarization of the polarities.

The liquid crystal display device and the driving method thereof according to the embodiment of the present invention described above can prevent flicker caused by low frequency driving and reduce power consumption without degrading image quality.

Those skilled in the art to which the present invention pertains will understand that the above-described present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: liquid crystal panel 200: gate driver
300: data driver 400: timing controller
500: mode selector

Claims (13)

A liquid crystal panel which is turned on by the scan signal supplied from the gate driver and has a plurality of pixels to which the data voltage supplied from the data driver is applied;
A mode selector configured to select a driving frequency to display an image by analyzing input source image data; And
A timing controller for aligning image data based on a driving frequency selection of the mode selector and controlling driving of the gate driver and the data driver;
When the driving frequency of the source image data is 60 Hz, the mode selector generates a mode selection signal for changing the driving frequency to 30 Hz when the screen change is greater than a preset value, and transmits the mode selection signal to the timing controller.
When the screen change is smaller than the preset value, a mode selection signal for changing the driving frequency to 10 Hz is generated and transmitted to the timing controller.
In case of a still picture, a mode selection signal for changing the driving frequency to 1 Hz is generated and transmitted to the timing controller.
And the timing controller controls the gate driver and the data driver based on the mode selection signal. delete According to claim 1,
In a plurality of frame periods, a scan signal is supplied to all the pixels to be turned on in the first frame period, and then a data voltage is supplied.
And a data voltage input in the first frame period without maintaining the scan signal and the data voltage in all the pixels during the second frame period among the plurality of frame periods. According to claim 1,
The gate driver generates a scan signal and sequentially supplies the scan signal to a plurality of gate lines formed in the liquid crystal panel in a first frame period, and does not supply a scan signal to the plurality of gate lines in a second frame period. A liquid crystal display device, characterized in that. According to claim 1,
The data driver generates a data voltage and supplies the data voltage to a plurality of data lines formed in the liquid crystal panel in a first frame period, and does not supply a data voltage to the plurality of data lines in a second frame period. Liquid crystal display device. The method of claim 5,
And the data driver inverts the polarity of the data voltage supplied in the first frame period every predetermined time. Selecting a driving frequency to display an image by analyzing input source image data; And
Controlling driving of a gate driver for generating a scan signal and a data driver for generating a data voltage based on the driving frequency selection;
Selecting the driving frequency,
When the driving frequency of the source image data is 60 Hz, if the screen change is greater than a preset value, a mode selection signal for changing the driving frequency to 30 Hz is generated and transmitted to the timing controller.
When the screen change is smaller than the preset value, a mode selection signal for changing the driving frequency to 10 Hz is generated and transmitted to the timing controller.
And a mode selection signal for changing the driving frequency to 1 Hz in case of a still picture and transmitting the generated mode selection signal to the timing controller. The method of claim 7, wherein
A scan signal is supplied to the plurality of gate lines and a data voltage is supplied to the plurality of data lines in the first frame period of the plurality of frames,
And a data voltage charged in all the pixels in the first frame period without maintaining the scan signal and the data voltage in the second frame period. delete The method of claim 8,
And inverting the polarity of the data voltage supplied in the first frame period every predetermined time. The method of claim 8,
And a gate low voltage and a common voltage are supplied to all pixels during the second frame period, and a scan signal, a clock signal, a gate high voltage, and a source output enable are not supplied. The method of claim 7, wherein
Among the plurality of frames,
The scan signal and the data voltage are supplied to all pixels in a first frame period,
And a data voltage charged in all the pixels in the first frame period in the second to Nth frame periods after the first frame. The method of claim 7, wherein
Among the plurality of frames,
The scan signal and the data voltage are supplied to all pixels in a first frame period,
In the second to Nth frame periods after the first frame, a data voltage charged in all pixels is maintained in the first frame period.
In the N + 1 frame period, the scan signal and the data voltage are supplied to all pixels.
And a data voltage charged in all the pixels in the first frame period during the period of N + 2 frames to 2N frames after the N + 1 frame.

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