KR102000268B1 - Decoder and decoding method - Google Patents

Abstract

The present invention relates to a decoding apparatus and a decoding method, the decoding node including a check node and groups of bit nodes corresponding to a parity check matrix and generating soft information for the check node and the bit node; A variable interconnection network for receiving the soft information from the integrated node processor; And a plurality of cyclic shifters for cyclically shifting soft information output from the variable interconnection network according to the parity check matrix and outputting the soft information to the integrated node processor, wherein the variable interconnection network includes: To the interleaver in accordance with the parity check matrix.

Description

[0001] DECODER AND DECODING METHOD [0002]

The present invention relates to a decoding apparatus and a decoding method for decoding data.

Recently, LDPC codes show error correction performance closest to Shannon's channel performance limit on an AWGN channel, so that wireless such as IEEE 802.11n WLAN, IEEE 802.16e mobile WiMAX, DVB-T2 And is used as a channel coding technique in a communication system. In such a wireless communication system, it is necessary to perform coding and decoding using various coding rates and block lengths depending on the channel environment and the importance of transmission signals. Therefore, a decoder capable of supporting various code rates and block lengths is required. Also, due to the emergence of a communication system supporting a data rate of Gbps, a channel decoder also has to support Gbps throughput, which requires development of an LDPC decoder that operates at high speed.

An object of the present invention is to provide a decoding apparatus and a decoding method that support various coding rates and block lengths and operate at high speed.

The problems to be solved by the present invention are not limited to the above-mentioned problems. Other technical subjects not mentioned may be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, a decoding apparatus includes a check node and groups of bit nodes corresponding to a parity check matrix, and generates soft information for the check node and the bit node; A variable interconnection network for receiving the soft information from the integrated node processor; And a plurality of cyclic shifters for cyclically shifting soft information output from the variable interconnection network according to the parity check matrix and outputting the soft information to the integrated node processor. The variable interconnection network variably sets interconnection with the plurality of cyclic shifters according to the parity check matrix.

In one embodiment, the decoding apparatus further includes a parity check matrix storage unit storing a plurality of parity check matrices corresponding to a plurality of code rates or a plurality of code lengths, wherein the variable interconnection network includes: Interconnection with the plurality of cyclic shifters can be established according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length of the matrices.

In one embodiment, each group of the integrated node processors includes first registers of check nodes and second registers of bit nodes corresponding to a size of a sub-matrix of the parity check matrix, The second registers store the soft information generated according to a Sum-Product Algorithm from a broadcasting input received from bit nodes or check nodes, and the sub-matrix includes the parity check matrix And may be a square matrix.

In one embodiment, the unified node processor includes check and bit node processors operable with the check node and the bit node, wherein the variable interconnection network is operable to detect a corresponding one of the plurality of cyclic shifters according to the parity check matrix One or more cyclic shifters and interconnection switches for establishing the interconnection, and the interconnection switches may be connected in a one-to-one correspondence with the test and bit node processors.

In one embodiment, the interconnection switches may establish the interconnection with the at least one cyclic shifter based on information of the sub-matrices to which the check node and the bit node are connected among the parity check matrix.

In one embodiment, each interconnection switch may simultaneously transmit an input from the unified node processor to the one or more cyclic shifters.

In one embodiment, each of the plurality of cyclic shifters includes: a first cyclic shifter for cyclically shifting an input from the variable interconnection network in units of a first cycle according to cyclic information of a sub-matrix of the parity check matrix; And second cyclic shifters for cyclically shifting the output of the first cyclic shifter according to the cyclic information, the sub-matrix being a partial matrix part of the parity check matrix, the square matrix being a square matrix, Or a zero matrix, and the cyclic information may be a cyclic shift size of the cyclic matrix.

In one embodiment, the second cycle may have a smaller value than the first cycle unit.

In one embodiment, the first cyclic shifter includes a plurality of cyclic shift circuits that cyclically shift an input from the variable interconnection network in the first cycle unit, and selects an output of the plurality of cyclic shift circuits, And output to the second cyclic shifters.

According to another aspect of the present invention, there is provided a wireless communication system including a transmitter including an LDPC encoder for generating a codeword from data using a parity check matrix; And a receiving apparatus including an LDPC decoding apparatus for decoding the codeword using the parity check matrix to recover the data, wherein the LDPC decoding apparatus includes a check node corresponding to a parity check matrix, An integrated node processor for generating soft information for the check node and the bit node; A variable interconnection network for receiving the soft information from the integrated node processor; And a plurality of cyclic shifters for cyclically shifting soft information output from the variable interconnection network according to the parity check matrix and outputting the soft information to the integrated node processor, wherein the variable interconnection network includes: Can be variably set according to the parity check matrix.

The LDPC decoding apparatus may further include a parity check matrix storage unit for storing a plurality of parity check matrices corresponding to a plurality of code rates or a plurality of code lengths, The interconnection with the plurality of cyclic shifters can be established according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length in the check matrix.

In one embodiment, each of the plurality of cyclic shifters includes: a first cyclic shifter for cyclically shifting an input from the variable interconnection network in units of a first cycle according to cyclic information of a sub-matrix of the parity check matrix; And second cyclic shifters for cyclically shifting the output of the first cyclic shifter according to the cyclic information, the sub-matrix being a partial matrix part of the parity check matrix, the square matrix being a square matrix, Or a zero matrix, and the cyclic information may be a cyclic shift size of the cyclic matrix.

According to another aspect of the present invention, there is provided a decoding method comprising: generating soft information for a check node and a bit node corresponding to a parity check matrix by an integrated node processor; Varying an interconnection with a plurality of cyclic shifters according to the parity check matrix by a variable interconnection network; And cyclically moving a signal input from the variable interconnection network according to the parity check matrix by the plurality of cyclic shifters and outputting the cyclic shift message to the integrated node processor, The interconnection between the variable interconnection network and the plurality of circular movement units may be variably set according to the parity check matrix.

According to an embodiment, the step of variably setting the interconnection may include a step of setting the interconnection to be variable according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length among the plurality of parity check matrixes, The interconnection between the moving units can be set.

In one embodiment of the present invention, the step of outputting to the integrated node processor comprises: a step of outputting, by the plurality of cyclic shifting units, a signal input from the variable interconnection network according to cyclic information of a sub-matrix of the parity check matrix, ; ≪ / RTI > And cyclically shifting a signal circulated in the first cycle unit by a second cycle according to the cyclic information by the plurality of cyclic shifting units, wherein the sub-matrix is a partial matrix that is a part of the parity check matrix , A square matrix, a unit matrix circulation matrix or a zero matrix, and the circulation information may be a circular movement size of the circulation matrix.

According to an embodiment of the present invention, a decoding apparatus capable of supporting various coding rates and block lengths is provided.

Also, according to the embodiment of the present invention, decoding can be performed at high speed.

1 is a configuration diagram of a wireless communication system according to an embodiment of the present invention.
2 is a diagram illustrating a parity check matrix.
FIG. 3 is a diagram showing the matrix shown in Equation (6) in the form of a bipartite graph.
4 is a block diagram of an LDPC decoding apparatus according to an embodiment of the present invention.
5 is a configuration diagram of an integrated node processor that configures an LDPC decoding apparatus according to an embodiment of the present invention.
6 is a configuration diagram of an interconnection switch unit of a variable interconnection network constituting an LDPC decoding apparatus according to an embodiment of the present invention.
7 is a diagram illustrating an exemplary parity check matrix of an LDPC code.
FIG. 8 is a block diagram of a cyclic shifting unit included in an LDPC decoding apparatus according to an embodiment of the present invention.
9 is a configuration diagram of the first cyclic shifter shown in FIG.
10 is a configuration diagram of each second cyclic shifter shown in FIG.

Other advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

Unless defined otherwise, all terms (including technical or scientific terms) used herein have the same meaning as commonly accepted by the generic art in the prior art to which this invention belongs. Terms defined by generic dictionaries may be interpreted to have the same meaning as in the related art and / or in the text of this application, and may be conceptualized or overly formalized, even if not expressly defined herein I will not.

The decoding apparatus according to the embodiment of the present invention can support various coding rates and block lengths through variable control of the interconnection network between the bit node and the check node operating on various parity check matrices. The decoding apparatus according to the embodiment of the present invention can reduce the complexity in the case of the pre-array processing by integrating the bit nodes and the check nodes and sharing the operation units operating in different clock cycles. The decoding apparatus according to an embodiment of the present invention uses an efficient cyclic shifter logic for low-complexity parallel processing.

1 is a configuration diagram of a wireless communication system according to an embodiment of the present invention. Referring to FIG. 1, a wireless communication system includes a transmitting apparatus 40 and a receiving apparatus 80. The transmitting apparatus 40 includes an LDPC coding apparatus 50 and a modulator 60. [ The LDPC encoding apparatus 50 receives the data m and encodes the received data m to output a codeword c. The modulator 60 receives the codeword c from the LDPC encoder 50 and wirelessly modulates the codeword c. The radio-modulated codeword is transmitted to the receiving apparatus 80 via the antenna. The receiving apparatus 80 includes a demodulator 90 and an LDPC decoding apparatus 100. The demodulator 90 receives the radio-modulated codeword through an antenna, and demodulates it into a codeword c. LDPC decoding apparatus 100 receives codeword c and decodes codeword c to output data m.

1 wirelessly encodes the data m into codewords c using the LDPC encoder 50 and encodes the codeword c using the LDPC encoder 100 using the LDPC encoder 100. [ c to the data m to stably transmit and receive the data m. The LDPC decoding apparatus 100 can determine whether there is an error in the codeword c using the parity check matrix H, for example, according to Equation (1) below. Here, the parity check matrix means a matrix for checking whether an error is included in the codeword (c) received by the LDPC decoding apparatus 100.

[Equation 1]

H c ^T = 0

If the matrix operation value between the codeword c and the parity check matrix is '0', it is determined that there is no error in the codeword c, and if it is not '0', the codeword c is in error .

2 is a diagram illustrating a parity check matrix. 2, a parity check matrix H used in a quasi-cyclic LDPC code to be described later will include a plurality of sub-matrices. Each sub-matrix is a square matrix, either a circulant matrix of the identity matrix or a zero matrix. The parity check matrix H can be divided into a first matrix H1 and a second matrix H2 as shown in Equation (2) below. At this time, the second matrix H2 is a square matrix having an inverse matrix.

&Quot; (2) "

H = [H1, H2]

Referring to Equation (3) below, the codeword c generated by the LDPC encoder 50 may be divided into data m and parity bit p.

&Quot; (3) "

c = [m, p]

The parity bit p for encoding the data m in the LDPC encoding apparatus 50 is derived using the parity check matrix H. [ For example, the parity check matrix H consists of one column and p (p = l-n) rows. The first matrix H1 includes p rows and n columns and includes a plurality of sub-matrices. The second matrix H2 consists of p (p = l-n) rows and p columns.

The above-mentioned equations (1) to (3) can derive Equation (4).

&Quot; (4) "

[H1, H2] · [m , p] T = H1 · m T + H2 · p T = 0

p ^T = - H ^{1 -1} H ¹ m ^T

In the wireless communication system 10, a plurality of parity check matrices are used to support various code rates and block lengths of codewords. For example, in the case of an IEEE 802.11n system, twelve parity check matrices are defined.

If random elements of the parity check matrix are randomly generated, a large amount of memory space is required to store the information of the parity check matrix. However, by using a quasi-cyclic LDPC code, a low density parity check (LDPC) ) Encoding and decoding, it is possible to reduce the amount of memory for storing the parity check matrix and to simplify the calculation process.

In the quasi-cyclic LDPC code, the parity check matrix is divided into several small square matrices as shown in FIG. The parity check matrix H of the quasi-cyclic LDPC code can be expressed by Equation (5) below.

&Quot; (5) "

In the parity check matrix H, each h _{i , j} represents a circulation matrix or a zero matrix of the unit matrix. Due to the characteristics of the structured LDPC code, the size of the memory for storing the parity check matrix in the hardware structure can be effectively reduced. The process of decoding a codeword of an LDPC code can be described through a bipartite graph. Equation (6) below represents a matrix corresponding to the bisection graph.

&Quot; (6) "

FIG. 3 is a diagram showing the matrix shown in Equation (6) in the form of a bipartite graph. As shown in FIG. 3, the bipartite graph may be composed of a left bit node and a right check node. The number of bit nodes is equal to the number of columns in the parity check matrix and the number of check nodes is equal to the number of rows in the parity check matrix.

In the matrix of Equation (6), the element " 1 " represents an edge connecting the bit node and the check node corresponding to each other in the half graph. For example, since the element (3, 5) of the matrix shown in Equation (6) is '1', the fifth bit node and the third check node in FIG. 3 are connected to the edge. In this way, an interconnection is formed between the bit node and the check node.

The decoding process of the codeword encoded according to the parity check matrix is performed by a message passing algorithm. The message passing algorithm is a process of decoding a codeword while exchanging soft information between a bit node connected to an edge and a check node. In general, since the soft information is repeatedly exchanged, the decoding process is performed through a plurality of iterations. The process of the message passing algorithm is as follows.

When the length of the sign bit of the LDPC code is N and the length of the information bit is K, the length of the parity bit is set to NK. A codeword _{c = [c 1, c 2} , ..., c N] to indicate, the relationship codeword symbol sequence by _{(x i = 1-2c i) (} x = [x 1, x 2,. ..., _xN ]). The transmission symbol x is received by the receiving end through an additive white Gaussian noise (AWGN) channel, and the received symbol sequence is called "y = [y ₁ , y ₂ , ..., y _N ] .

와

로 정의한다.

는 j번째 비트 노드에서 생성되어 i번째 검사 노드로 전송되는 소프트 정보(soft information)를 나타내고,

는 i번째 검사 노드에서 생성되어 j번째 비트 노드로 전송되는 소프트 정보를 나타낸다. LDPC 복호화를 위한 대표적인 반복 메시지 패싱 알고리즘(iterative message passing algorithm)인 합-곱 알고리즘(SPA; Sum-Product Algorithm)에 대해 설명하면 다음과 같다.soft information that occurs in the kth iteration

Wow

.

Denotes soft information generated at the j-th bit node and transmitted to the ith check node,

Denotes soft information generated at the ith check node and transmitted to the jth bit node. A Sum-Product Algorithm (SPA), which is an iterative message passing algorithm for LDPC decoding, will now be described.

For initialization, intrinsic information is calculated when j = 1, 2, ..., N (N is the number of bit nodes). The unique information can be obtained from the symbol value passed through the channel. The number of unique information is the same as the number of bit nodes. The unique information can be expressed as a log likelihood ratio (LLR) from the received symbol as shown in Equation (7) below.

&Quot; (7) "

Iterative decoding will be described. First, intrinsic information generated through initialization is transmitted as a first soft information from a bit node to a check node. The check node receiving the unique information from the bit node generates soft information and transmits the soft information to the connected bit node.

는 예를 들어 아래의 수학식 8과 같다. 이때, N(i)는 i번째 검사 노드에 연결된 비트 노드 집합이다.The operation of the check node will be described with reference to the soft information generated for i = 1, 2, ..., NK (where N is the length of the sign bit, K is the length of the information bits and NK is the number of check nodes)

For example, Equation 8 below. In this case, N (i) is a bit node set connected to the ith check node.

&Quot; (8) "

는 예를 들어 아래의 수학식 9와 같다.Bit node operation, soft information generated for j = 1, 2, ..., N (where N is the length of a sign bit)

For example, the following equation (9).

&Quot; (9) "

는 j번째 비트 노드와 연결된 i' 번째 검사 노드로 다시 전송되는 소프트 정보(soft information)이다. 비트 결정을 할 때 필요한 소프트 정보

는 예를 들어 아래의 수학식 10으로 나타낼 수 있다.In Equation (9), M (j) is a set of check nodes connected to the j-th bit node,

Is soft information that is transmitted back to the ith check node connected to the jth bit node. Soft information required for bit determination

Can be expressed, for example, by the following equation (10).

&Quot; (10) "

의 값이 0보다 크면, 부호어의 j번째 비트를 0으로, 0보다 작으면 1로 결정한다. LDPC 복호화 장치(100)는 수학식 10에 의하여, 매 반복(iteration)마다 복호된 부호어를 얻을 수 있다.In Equation (10)

Is greater than 0, the j < th > bit of the codeword is set to 0, and if it is less than 0, The LDPC decoding apparatus 100 can obtain the decoded codeword for every iteration by Equation (10).

The LDPC decoding apparatus 100 determines that the decoded codeword c satisfies the condition of Equation (1) mentioned above and decides it to be a correctly decoded codeword, and extracts information bits from the codeword. If the decoded codeword c does not satisfy the condition of Equation (1), it iterates again.

In the LDPC decoding apparatus 100, a sum-product algorithm (SPA), which is an iterative message passing algorithm used for decoding an LDPC code, Information is transmitted.

At this time, for high-speed operation, the check node must simultaneously transmit soft information of Equation (8) to a plurality of bit nodes connected to the check node, and the bit node transmits soft information of Equation (9) Should be transmitted. Accordingly, an interconnection for connecting one bit node and a plurality of check nodes is indispensably required. An interconnection that connects one check node and several bit nodes is also required.

The interconnection device that connects hundreds to thousands of bit nodes and check nodes in an LDPC decoding device has high complexity. When the broadcasting scheme is used in the LDPC decoding apparatus, the complexity of the interconnection apparatus can be reduced. According to the broadcasting-based message passing algorithm, Equation (1) is changed as shown in Equation (11) below.

&Quot; (11) "

Equation (11) differs from Equation (8) in that the ith check node delivers the same soft information to the bit nodes. The broadcasting-based message passing algorithm reduces the complexity of the interconnection device transmitting data from the check node to the bit node because the information transmitted from the plurality of check nodes to the bit node is the same. However, since the data to be transmitted from the original check node to the bit node must be generated within the bit node, the complexity of the bit node increases.

The above-mentioned Equation 9 can also be modified as shown in Equation 12 below.

&Quot; (12) "

As in the case of the check node, the bit node can also reduce the complexity of the interconnection device connected to the check node from the bit node by changing the information transmitted to the plurality of check nodes to the same value. However, even in this case, since the information of the bit node of Equation (9) to be originally transmitted must be generated at the check node instead of the bit node, the complexity of the check node may increase.

의 크기를 다양하게 정의하여 다양한 부호 길이를 지원할 수 있다. 따라서, 다양한 부호 길이 및 부호율을 지원하기 위하여, LDPC 복호화 장치는 다양한 패리티 검사 행렬에 대하여 유동적으로 동작할 수 있어야 한다. 이하에서 설명되는 본 발명의 실시 예는 다양한 패리티 검사 행렬, 즉 다양한 l과 p의 값을 가지며 다양한 서브 행렬

를 갖는 패리티 검사 행렬에 대응하여 유연하게 동작할 수 있는 LDPC 복호화 장치를 제시한다.Various parity check matrices may be defined to support various code rates and code lengths. For example, in the case of a semi-circulating LDPC code, a parity check matrix can be expressed as Equation 5. In order to support various code rates, l and p can have various values. Also, the sub-matrix of the parity check matrix of Equation (5)

Can be variously defined to support various code lengths. Therefore, in order to support various code lengths and coding rates, the LDPC decoding apparatus must be able to operate flexibly with respect to various parity check matrices. The embodiment of the present invention described below has various parity check matrices, i.e., various l and p values, and various sub-matrices

The LDPC decoding apparatus according to the present invention is an LDPC decoding apparatus that can flexibly operate in response to a parity check matrix having a parity check matrix.

4 is a block diagram of an LDPC decoding apparatus according to an embodiment of the present invention. The LDPC decoding apparatus 100 according to an embodiment of the present invention includes an integrated node processor 110, a variable interconnection network 120, a circulating units 130, a parity check matrix storage unit 140, And an LDPC decoding control unit 150 for controlling the LDPC code.

A combined check and variable node process 110 processes and outputs check nodes and bit nodes. The flexible interconnect network 120 receives the processing result from the integrated node processor 110 and controls the parity check matrix stored in the parity check matrix storage unit 140 under the control of the LDPC decoding control unit 150. [ The code rate or the code length. The parity check matrix storage unit 140 may store parity check matrices corresponding to various code rates or code lengths. The circulating units 130 cyclic-shift the output of the variable interconnection network 120. [

In the embodiment of the present invention shown in FIG. 4, the LDPC decoding apparatus 100 transmits soft information generated by all bit nodes at the same clock by fully parallel processing to a check node . Likewise, the check node may also operate on the same clock and deliver the generated soft information to the bit node.

In the case of partially parallel processing, there is a limit to achieving high throughput because the number of clock cycles required for exchanging messages between the bit node and the check node is large. On the contrary, full duplex processing is effective in achieving a high throughput of several Gbps or more because the number of clock cycles required in transmitting a message between the bit node and the check node is small. However, the hardware complexity increases in proportion to the number of bit nodes and check nodes. Using a sum-of-product algorithm (SPA) with a broadcasting scheme as a message-passing algorithm, the complexity of increasing interconnection can be reduced by using the pre-array processing.

In the existing SPA, the operations to be performed by the bit node and the check node are clearly distinguished, so that each has only necessary hardware resources. However, as the broadcasting technique is applied to the SPA in the embodiment of the present invention, The bit node must support some of the actions that the check node must perform, and the check node must support some of the actions that the bit node must perform. In addition, each bit node and check node must also support the functionality that must originally be supported by the SPA.

Therefore, in the case of the LDPC decoding using the SPA with the broadcasting technique, the hardware complexity of the bit node and the check node increases. Accordingly, in order to reduce the complexity of the hardware while the broadcasting technique is applied, the integrated node processor 110 of the LDPC decoding apparatus 100 according to the embodiment of the present invention integrates a bit node and a check node in each group And can be implemented as a combined variable and check node processor.

The integrated node processor 110 may be composed of N CVP groups (CVP groups 1 through N). Each CVP block contains several CVPs (CVP1-Z). Each CVP has both a variable node processor and a check node processor. When the sub-matrix of the parity check matrix has various sizes to support various code rates and code lengths, the number of CVPs used in one CVP group may vary. For example, if the size of the sub-matrix of the parity check matrix is 10, 10 CVPs are required. If the size of the sub-matrix is 20, 20 CVPs are required.

In order to support various sub-matrix sizes, a CVP of the largest sub-matrix is required. For the mentioned example, 20 CVPs are needed, and 10 sub-matrixes can be supported by using only 10 of them and not using the remaining 10. That is, the number of CVPs in a CVP group is related to the support of various sub-matrices.

In the parity check matrix of Equation (5), columns and rows of a parity check matrix are defined through p sub-matrices and l sub-matrices. At this time, p sub-matrices determine the codeword length of the parity check matrix. Also, when p sub-matrices are determined, l determines the code rate. Therefore, in order to support the parity check matrix having a sub-matrix of p, the p number of CVP group is necessary in order to decode the code words generated by the parity check matrix, in other words having a p sub-matrix.

For example, if p is 24, you need 24 CVP groups, and if p is 20, you need 20 CVP groups. Therefore, the number of the CVP groups can be determined according to the parity check matrix having the largest value of p among the parity check matrixes to be supported. In the example mentioned, the number of CVP groups is determined to be 24. If a parity check matrix with p = 20 is decoded, only 20 CVP groups may be used, and the remaining four may not be used. In this way, decoding can be performed corresponding to various codeword lengths.

If the bit node and the check node are separately implemented, the complexity of the hardware increases to about twice. In the case where broadcasting is applied, the integrated node processor 110 constituting the embodiment of the present invention uses a single processor to perform a message passing algorithm Can be implemented.

5 is a configuration diagram of an integrated node processor that configures an LDPC decoding apparatus according to an embodiment of the present invention. 5, the integrated node processor 110 includes bit node registers 111, check node registers 112, a first logic 113, an adder 114, a second logic 115, . Each bit node register 1111 corresponds to one of the N bit nodes, and each check node register 1121 corresponds to one of M bit nodes. According to the parity check matrix, one bit node or check node is connected to several check nodes or bit nodes. The bit node receives broadcast input data from a plurality of check nodes connected thereto, and the check node receives broadcast input data from a plurality of bit nodes.

In the embodiment shown in FIG. 5, N broadcasting input data from N check nodes or bit nodes are input to the first logic 113. The process of generating broadcasting output data from broadcasting input data is as follows. The first logic 113 generates SPA data according to the same method as that of the existing SPA using the multiplexer 1131 and the mapping unit 1132 and outputs the generated SPA data to the adder 114. The mapping unit 1132 can detect the mapping data corresponding to the input using, for example, a look-up table (LUT). The adder 114 adds all of the SPA data through an addition operation to generate a broadcasting output.

When a broadcasting scheme is applied, each node (bit node or check node) needs to generate and store the same data as that generated by the existing SPA. Broadcasting input data differs from the data received from the existing SPA, so it must be made from the data received from the existing SPA. This can be performed using a multiplexer 1151 of the second logic 115 and a lookup table (LUT) of the mapping unit 1152 connected to the output terminal side of the adder 114.

At the end of this process, each node (bit node or check node) has the same data that it would receive from the existing SPA. The result computed in the second logic 115 is stored in corresponding registers 111 and 112 depending on whether it is a bit node operation or a check node operation. Thereafter, each node generates a broadcast output again and delivers it to the connected node, and the broadcast output is used in the operation of the clock cycle.

In the case of pre-processing, the time required for the bit node and the check node to operate is always different. Therefore, necessary logic can be time-shared. In the embodiment of the present invention, the hardware complexity of the check node and the bit node is equal to that of the existing SPA by the combined check and check node processor while operating at a high speed by supporting the broadcasting technique .

In a fully parallel architecture, when bit nodes and check nodes are hardwired by circuit connection, it becomes difficult to support various parity check matrices. That is, the connection between the bit node and the check node is different according to the parity check matrix. In the case of the conventional hardwired interconnection method, it is possible to perform a connection operation between a check node or a bit node in a specific parity check matrix However, the connection between the bit node and the check node can not be changed in response to the change of the parity check matrix.

Accordingly, the variable interconnection network 120 constituting the LDPC decoding apparatus 100 according to the embodiment of the present invention is provided to support various parity check matrices. The variable interconnection network 120 is implemented as a reconfigurable interconnection network according to a parity check matrix.

6 is a configuration diagram of an interconnection switch unit of a variable interconnection network constituting an LDPC decoding apparatus according to an embodiment of the present invention. Referring to FIG. 4 and FIG. 6, an interconnection switch unit 121 of a flexible interconnection network 120 is included. Each interconnection switch unit 121 has a one-to-one correspondence to one check and bit node processor CVP of the unified node processor 110, and outputs a broadcasting output via an input port to a corresponding check and bit node And receives input from the processor. In order to support various parity check matrices, broadcasting output data from one CVP can be connected to a maximum of 24 CVP groups according to a parity check matrix.

Connecting each of the 24 CVP groups of one CVP group increases the complexity of the interconnection network. In the embodiment of the present invention, the variable interconnection network 120 can perform interconnection by grouping several CVP groups into one large group. FIG. 6 shows an example in which four CVP groups are grouped into one large group.

The interconnection switch unit 121 can perform the interconnection using the switches 1211 to 1215 receiving the two control signals CTRL0 and CTRL1. Each of the switches 1211 to 1215 includes two transfer gates TG1 and TG2. The two transfer gates TG1 and TG2 generate two outputs (output 0 and output 1) in accordance with the control signals CTRL0 and CTRL1 corresponding to a common input. For example, if there is no need to connect CVP groups (groups 1 to 4) for a check node or a bit node, control signals may be adjusted so that CVP groups 1 to 4 do not send broadcast output data, 8 < / RTI >

As another example, if there is no need to connect to CVP groups 1 through 8, CVP groups 1 through 8 can control the control signal to not send data. These control signals may be generated differently depending on the parity check matrix. Accordingly, it is possible to control the switches 1211 to 1215 according to the parity check matrix to variably connect or block the CVP group, and to support various parity check matrices.

7 is a diagram illustrating an exemplary parity check matrix of an LDPC code. This shows the parity check matrix of the quasi-cyclic LDPC code used in the IEEE 802.11n WLAN system. The parity check matrix is divided into a first matrix H1 and a second matrix H2. The first matrix H1 is composed of four rows and twenty columns, and the second matrix H2 is composed of four rows and four columns. In addition, each sub-matrix is implemented as a recursive matrix or a zero matrix of the identity matrix. One square represents a sub-matrix. When the size of the sub-matrix is 81, 81 bit nodes and 81 check nodes form a group.

In FIG. 7, the numbers in each sub-matrix represent the magnitude of cyclic shift of the identity matrix. The number '13' in the first column of the first row of the parity check matrix, ie, the (1,1) sub-matrix, has interconnection between 1 to 81 bit nodes and 1 to 81 check nodes, 13 'cyclic shift to connect the bit node and the check node. That is, the first bit node is connected to the check node 14, the second bit node is connected to the check node 15, and the 81 bit node is connected to the check node 13 in the same manner. At this time, the clic shifter, . '-' represents a zero matrix, meaning there is no interconnection.

The cyclic shifter 130 is connected to the output of the variable interconnection network 120 as shown in FIG. 7, when data is sent from the first bit node group to the interconnection switch unit 121 of the variable interconnection network 120, data is transmitted through the interconnection switch unit 121 to the first bit node group To the fourth check node group.

In the case of the embodiment shown in FIG. 7, the interconnection switch unit 121 will transmit data only to the CVP groups 1 to 4 because it is outside the fourth check node group. The cyclic shifter 130 cyclically shifts the transmitted data by values of '13', '69', '51', and '16', and transmits the cyclic shift to each CVP group. That is, the cyclic shifter 130 generates four cyclic shift outputs corresponding to one input.

FIG. 8 is a configuration diagram of a cyclic shifter that configures an LDPC decoding apparatus according to an embodiment of the present invention. Referring to FIG. 8, the circulator 130 includes a first stage cyclic shifter 131 and a second stage cyclic shifter 132. That is, the circulating and moving unit 130 has a two-stage cyclic shifter structure.

In the first column of the parity check matrix shown in FIG. 7, it can be seen that the cyclic shift values vary in size by '13', '69', '51' and '16'. In order to support this simultaneously, four cyclic shifters are required. If cyclic shifters are connected by simply connecting four cyclic shifters, the complexity may increase.

Accordingly, the first cyclic shifter 131 performs a cyclic shift in a predetermined cyclic shift unit (for example, 16 cycles). Accordingly, the first cyclic shifter 131 performs a cyclic shift operation in a predetermined range to output the output to the second cyclic shifters 132. The second cyclic shifters 132 perform a cyclic shift by an amount insufficient after the cyclic shift performed in the first stage by the first cyclic shifter 131.

In one embodiment, when the broadcast data is connected in units of four CVP groups in the variable interconnection network 120, one cyclic shifter can support four different cyclic shift sizes do. Accordingly, the second cyclic shifters 132 are arranged in a parallel cyclic shifter structure to perform parallel processing.

9 is a configuration diagram of the first cyclic shifter shown in FIG. As shown in Fig. 9, the first cyclic shifter 131 includes cyclic shift circuits 1311 to 1315 for circulating an input in a specific cycle (for example, 16 cycles). The first cyclic shifter 131 may be implemented by serially connecting the first to fifth cyclic shift circuits 1311 to 1315.

The first cyclic shifter 131 may select an output point according to a cyclic shift value defined in the parity check matrix and pass the data to the second cyclic shifters 132. When the length of the data is one of 27, 54, and 81, the cyclic shift circuit 1311 can be divided into 27 (16 + 11) three regions and can be implemented to support all cases through the selection of a multiplexer have. Although the multiplexer exists in the first cyclic shifter 131, since the cyclic shift unit is basically one unit of 16, the complexity of the logic is not high.

In the case where the cyclic shift unit of the first cyclic shifter 131 is '16', for example, in the first column of the parity check matrix shown in FIG. 7, the first cyclic shift value is '13' , The first cyclic shifter 131 directly sends the second cyclic shifter 132 without shifting the input. Thereafter, 13 cyclic shifts are performed by the second cyclic shifters 132.

In the first column of the parity check matrix shown in FIG. 7, since the second cyclic shift value is '69', the first cyclic shifter 131 cyclically shifts to '64' ), And sends it to the second cyclic shifters 131. Accordingly, the second cyclic shifters 132 may perform only five cyclic shifts.

Since the third cyclic shift value is '51' in the first column of the parity check matrix shown in FIG. 7, the first cyclic shifter 131 cyclically shifts '48' ), And sends it to the second cyclic shifters 131. Accordingly, the second cyclic shifters 132 need only perform three cycles of cyclic shift. In the first column of the parity check matrix shown in FIG. 7, since the fourth cyclic shift value is '16', the first cyclic shifter 131 performs 16 cyclic shifts. At this time, the second cyclic shifters 132 do not operate and can be directly outputted to the output.

10 is a configuration diagram of each second cyclic shifter shown in FIG. Referring to FIGS. 8 and 10, each second cyclic shifter 1321 of the second cyclic shifters 132 is composed of four blocks of cyclic shift circuits 1321a to 1314d.

Since the second cyclic shifter 1321 performs a cyclic shift only on the basis of the result of cyclic shifting in the first cyclic shifter 131, the second cyclic shifter 1321 shifts the size of the cyclic shift Is smaller than a cyclic shift unit (for example, 16) of the first cyclic shifter 131. If the first cyclic shifter 131 is not provided, the second cyclic shifter 1321 must support all the cyclic shifts from 1 to 80. However, in the embodiment of the present invention, the second cyclic shifter 1321 Only the cyclic shift from 1 to 15 can be supported, so that the complexity of the circulating unit 130 can be greatly reduced.

For example, the first circuit 1321a performs a one-step cyclic shift. Two cycles in the second circuit 1321b, four cycles in the third circuit 1321c, and eight cycles in the fourth circuit 1321d. The second cyclic shifter 1321 may be divided into three parts in the same manner as the first cyclic shifter 131 in order to support both cyclic shifts of data of various lengths such as 27, 54, and 81.

If the length of the cyclic shift to be performed in the second cyclic shifter 1321 is '5', cyclic shift can be performed only in the first and third stages. In this case, in the second and fourth steps, the data can be transferred to the next step without cyclic shift. According to the embodiment of the present invention, since the cyclic shifting is performed in a specific unit (for example, 16 units) in the first cyclic shifter 131, the cyclic shift, which should be performed in the second cyclic shifter 1321, Is limited to 15 or less. Therefore, the overall complexity of the circulator 130 can be reduced compared to the conventional cyclic shifter.

As described above, the LDPC decoding apparatus according to the embodiment of the present invention can support various code rates and code lengths and implement reconfigurable interconnection. The LDPC decoding apparatus according to the embodiment of the present invention is implemented in a structure with a low complexity, which is suitable for parallel operation processing of a circular movement unit required in the message passing process of the sub-circulating LDPC code. Accordingly, it is possible to reduce the complexity of the bit node and the check node and the complexity of the interconnection network, and to support the throughput of several Gbps in the case of the full duplex processing.

It is to be understood that the above-described embodiments are provided to facilitate understanding of the present invention, and do not limit the scope of the present invention, and it is to be understood that various modifications may be made within the scope of the present invention. For example, each component shown in the embodiment of the present invention may be distributed and implemented, and conversely, a plurality of distributed components may be combined. Therefore, the technical protection scope of the present invention should be determined by the technical idea of the claims, and the technical protection scope of the present invention is not limited to the literary description of the claims, The invention of a category.

10: wireless communication system 40: transmitting device
50: LDPC encoder 60: modulator
80: Receiver 90: Demodulator
100: LDPC decoding apparatus 110: Integrated node processor
120: variable interconnection network 130:
140: Parity check matrix storage unit 150: LDPC decoding control unit

Claims (15)

An integrated node processor including a check node and groups of bit nodes corresponding to a parity check matrix and generating soft information for the check node and the bit node;
A variable interconnection network for receiving the soft information from the integrated node processor; And
And a plurality of cyclic shifters for cyclically shifting soft information output from the variable interconnection network according to the parity check matrix and outputting the soft information to the integrated node processor,
Wherein the variable interconnection network variably sets interconnection with the plurality of cyclic shifters according to the parity check matrix. The method according to claim 1,
And a parity check matrix storage unit for storing a plurality of parity check matrices corresponding to a plurality of code rates or a plurality of code lengths,
The variable interconnection network comprising:
And sets an interconnection with the plurality of cyclic shifters according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length among the plurality of parity check matrixes. The method according to claim 1,
Wherein each group of the integrated node processors includes first registers of check nodes and second registers of bit nodes corresponding to a size of a sub-matrix of the parity check matrix,
The first registers and the second registers store the soft information generated according to a Sum-Product Algorithm from a broadcasting input received from bit nodes or check nodes,
Wherein the sub-matrix is a partial matrix that is a part of the parity check matrix and is a square matrix. The method of claim 3,
Wherein the unified node processor comprises check and bit node processors operable with the check node and the bit node,
Wherein the variable interconnection network includes interconnection switches for setting the interconnection with the corresponding one or more of the plurality of cyclic shifters according to the parity check matrix,
Wherein the interconnection switches are connected in a one-to-one correspondence with the inspection and bit node processors. 5. The method of claim 4,
Wherein the interconnection switches establish the interconnection with the at least one cyclic shifter based on the information of the submatrices to which the check node and the bit node are connected among the parity check matrix,
Wherein each of the sub-matrices is a partial matrix that is a part of the parity check matrix, and is a square matrix. 6. The method of claim 5,
Each of the interconnection switches,
And simultaneously transmits the input from the integrated node processor to the at least one cyclic shifter. The method according to claim 1,
Wherein each of the plurality of circular movement units comprises:
A first cyclic shifter for circulating input from the variable interconnection network in a first cycle unit according to cyclic information of a sub-matrix of the parity check matrix; And
And second cyclic shifters for cyclically shifting the output of the first cyclic shifter by a second cycle according to the cyclic information,
Wherein the sub-matrix is a partial matrix that is a part of the parity check matrix and is a square matrix, a cyclic matrix or a zero matrix of an identity matrix, and the cyclic information is a cyclic shift size of the cyclic matrix. 8. The method of claim 7,
And the second cycle has a smaller value than the first cycle unit. 9. The method of claim 8,
Wherein the first cyclic shifter includes a plurality of cyclic shift circuits for cyclically shifting an input from the variable interconnection network in the first cycle unit and selecting an output of the plurality of cyclic shift circuits, . A transmitting apparatus including an LDPC encoding apparatus for generating a codeword from data using a parity check matrix; And
And an LDPC decoder for decoding the codeword using the parity check matrix to recover the data,
The LDPC decoding apparatus includes:
An integrated node processor including a check node and groups of bit nodes corresponding to a parity check matrix and generating soft information for the check node and the bit node;
A variable interconnection network for receiving the soft information from the integrated node processor; And
And a plurality of cyclic shifters for cyclically shifting soft information output from the variable interconnection network according to the parity check matrix and outputting the soft information to the integrated node processor,
Wherein the variable interconnection network variably sets an interconnection with the plurality of cyclic shifters according to the parity check matrix. 11. The method of claim 10,
Wherein the LDPC decoding apparatus further comprises a parity check matrix storage unit for storing a plurality of parity check matrices corresponding to a plurality of code rates or a plurality of code lengths,
The variable interconnection network comprising:
And establishes an interconnection with the plurality of cyclic shifters according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length among the plurality of parity check matrixes. 11. The method of claim 10,
Wherein each of the plurality of circular movement units comprises:
A first cyclic shifter for circulating input from the variable interconnection network in a first cycle unit according to cyclic information of a sub-matrix of the parity check matrix; And
And second cyclic shifters for cyclically shifting the output of the first cyclic shifter by a second cycle according to the cyclic information,
Wherein the sub-matrix is a partial matrix that is a part of the parity check matrix and is a square matrix and a circulation matrix or a zero matrix of an identity matrix, and the circulation information is a circular movement size of the circulation matrix. Generating soft information for a check node and a bit node corresponding to a parity check matrix by an integrated node processor;
Varying an interconnection with a plurality of cyclic shifters according to the parity check matrix by a variable interconnection network; And
And cyclically shifting a signal input from the variable interconnection network according to the parity check matrix by the plurality of cyclic shifters and outputting the cyclic shifter to the integrated node processor,
Wherein the step of variably setting the interconnection comprises variably setting interconnection between the variable interconnection network and the plurality of cyclic shifters according to the parity check matrix. 14. The method of claim 13,
Wherein the step of variably setting the interconnection comprises:
And setting the interconnection between the variable interconnection network and the plurality of circular movement units according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length among the plurality of parity check matrixes. 14. The method of claim 13,
Wherein the step of outputting to the integrated node processor comprises:
Cyclically moving a signal input from the variable interconnection network in units of a first cycle according to cyclic information of a sub-matrix of the parity check matrix by the plurality of cyclic shifting units; And
And cyclically moving, by the plurality of cyclic shifters, a signal cyclically cyclic in the first cycle according to the cyclic information by a second cycle,
Wherein the sub-matrix is a partial matrix that is a part of the parity check matrix and is a square matrix, a cyclic matrix of a unit matrix or a zero matrix, and the cyclic information is a cyclic shift size of the cyclic matrix.

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