KR20130092441A - Decoder and decoding method - Google Patents

Abstract

PURPOSE: A decoder and a decoding method have various decoding rate and support a block length. CONSTITUTION: An integrated node processor (110) includes groups of an inspection node and a bit node corresponding to a parity inspection matrix. The integrated node processer generates soft information about the inspection node and the bit node. A variable interconnection network (120) variably set an interconnection about groups varying with the parity inspection matrix. A circulation moving unit (130) circulates and moves the output of the variable interconnection network according to the parity inspection matrix. A parity inspection matrix storage part (140) stores a plurality of parity inspection matrixes corresponding to the plurality of decoding rates and decoding lengths. [Reference numerals] (110) Integrated node processor; (120) Variable interconnection network; (121,DD,EE,FF,GG,HH,II) Interconnection switch part; (140) Parity inspection matrix storage part; (150) LDPC decoding controller; (AA) CVP group 1; (BB) CVP group 2; (CC) CVP group 3; (JJ,MM) Circulation movement part 1; (KK,NN) Circulation movement part 2; (LL,OO) Circulation movement part 6

Description

Decoding device and decoding method {DECODER AND DECODING METHOD}

The present invention relates to a decoding apparatus and a decoding method for decoding data.

Recent LDPC codes show error correction performance closest to Shannon's channel performance limit in AWGN channels, enabling wireless such as IEEE 802.11n WLAN, IEEE 802.16e mobile WiMAX, and DVB-T2. It is used as a channel coding technique in communication systems. In such a wireless communication system, it is necessary to perform encoding and decoding using various code rates and block lengths according to the channel environment and the importance of a transmission signal. Therefore, a decoder that can support various code rates and block lengths is required. In addition, with the emergence of a communication system supporting a Gbps data rate, a channel decoder also needs to support Gbps throughput, so a technology development of an LDPC decoder that operates at high speed is required.

An object of the present invention is to provide a decoding apparatus and decoding method that support various code rates and block lengths and operate at high speed.

The problems to be solved by the present invention are not limited to the above-mentioned problems. Other technical subjects not mentioned may be clearly understood by those skilled in the art from the following description.

A decoding apparatus according to an aspect of the present invention includes an integrated node processor including groups of check nodes and bit nodes corresponding to a parity check matrix, and generating soft information about the check node and the bit node; A variable interconnection network which receives the soft information from the integrated node processor and variably sets the interconnections for the groups according to the parity check matrix; And a circular moving unit for circularly moving the output of the variable interconnection network according to the parity check matrix.

According to an embodiment, the decoding apparatus may further include a parity check matrix storage unit configured to store a plurality of parity check matrices corresponding to a plurality of code rates or a plurality of code lengths, and the variable interconnection network may include the plurality of parity checks. The interconnection for the groups may be established according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length in a matrix.

In one embodiment, each group of integrated node processors includes registers of bit nodes and registers of bit nodes corresponding to the size of a sub-matrix of the parity check matrix, wherein the registers are from bit nodes or check nodes. Store the soft information generated according to the sum-product algorithm from the received broadcasting input.

In one embodiment, the variable interconnection network corresponds one-to-one with the registers, and interconnection switches configured to establish the interconnection with one or more cyclic shifters of the plurality of cyclic shifters according to the parity check matrix. It may include.

In example embodiments, the interconnection switches may configure the interconnection with the one or more cyclic shifters based on information of sub-matrixes to which the check node and the bit node of the parity check matrix are connected.

In one embodiment, each interconnection switch has two outputs for one input in accordance with a control signal and simultaneously inputs the inputs from the integrated node processor to a plurality of circular moving parts corresponding to a set of the plurality of groups. Can transmit

The cyclic shifter may include: a first cyclic shifter cyclically moving the input from the variable interconnection network in units of first cycles according to cyclic information of a sub-matrix of the parity check matrix; And second cyclic shifters that cyclically move the output of the first cyclic shifter by a second cycle according to the cyclic information.

In an embodiment, the second cycle may have a smaller value than the first cycle unit.

In an embodiment, the first cyclic shifter includes a plurality of cyclic shift circuits circulating the input in the first cycle unit, and selects outputs of the plurality of cyclic shift circuits to the second cyclic shifters. You can print

According to another aspect of the present invention, there is provided a wireless communication apparatus including: a transmission apparatus including an LDPC encoding apparatus generating a codeword from data using a parity check matrix; And a receiving device including an LDPC decoding device for decoding the codeword by using the parity check matrix to restore the data, wherein the LDPC decoding device includes a group of check nodes and bit nodes corresponding to the parity check matrix. An integrated node processor for generating soft information for the check node and the bit node; A variable interconnection network which receives the soft information from the integrated node processor and variably sets the interconnections for the groups according to the parity check matrix; And a cyclic shifter cyclically moving the output of the variable interconnection network according to the parity check matrix.

The LDPC decoding apparatus may further include a parity check matrix storage unit configured to store a plurality of parity check matrices corresponding to a plurality of code rates or a plurality of code lengths, and the variable interconnection network may include the plurality of parity. The interconnection for the groups may be established according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length of the check matrix.

The cyclic shifter may include: a first cyclic shifter cyclically moving the input from the variable interconnection network in units of first cycles according to cyclic information of a sub-matrix of the parity check matrix; And second cyclic shifters that cyclically move the output of the first cyclic shifter by a second cycle according to the cyclic information.

According to another aspect of the present invention, a decoding method includes generating soft information about a check node and a bit node corresponding to a parity check matrix; Variably setting an interconnection between the check node and the bit node according to the parity check matrix; And cyclically moving a signal input according to the variably set interconnection according to the parity check matrix.

According to an embodiment, the step of variably setting the interconnection may include: interworking between the check node and the bit node according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length among a plurality of parity check matrices. You can set up a connection.

In an embodiment, the cyclic shifting may include: cyclically shifting the input signal in units of a first cycle according to cyclic information of a sub-matrix of the parity check matrix; And cyclically moving the signal circulated in the first cycle unit by a second cycle according to the circulation information.

According to an embodiment of the present invention, a decoding apparatus capable of supporting various code rates and block lengths is provided.

In addition, according to an embodiment of the present invention, decoding can be performed at high speed.

1 is a block diagram of a wireless communication system according to an embodiment of the present invention.
2 is a diagram illustrating a parity check matrix by way of example.
3 is a diagram illustrating a matrix shown in Equation 6 in the form of a bipartite graph.
4 is a block diagram of an LDPC decoding apparatus according to an embodiment of the present invention.
5 is a configuration diagram of an integrated node processor constituting an LDPC decoding apparatus according to an embodiment of the present invention.
6 is a block diagram of an interconnection switch unit of a variable interconnection network constituting an LDPC decoding apparatus according to an embodiment of the present invention.
7 is a diagram illustrating an exemplary parity check matrix of an LDPC code.
8 is a configuration diagram of a cyclic shifter constituting an LDPC decoding apparatus according to an embodiment of the present invention.
FIG. 9 is a configuration diagram of the first cyclic shifter illustrated in FIG. 8.
FIG. 10 is a configuration diagram of each second circulation shifter illustrated in FIG. 8.

Other advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

Unless defined otherwise, all terms (including technical or scientific terms) used herein have the same meaning as commonly accepted by the generic art in the prior art to which this invention belongs. Terms defined by generic dictionaries may be interpreted to have the same meaning as in the related art and / or in the text of this application, and may be conceptualized or overly formalized, even if not expressly defined herein I will not.

The decoding apparatus according to the embodiment of the present invention may support various code rates and block lengths through variable control of an interconnection network between a bit node and a check node that operate on various parity check matrices. The decoding apparatus according to the embodiment of the present invention can reduce the complexity that is increased during the parallel processing by integrating the bit node and the check node and sharing the operation units that operate in different clock cycles. The decoding apparatus according to the embodiment of the present invention uses cyclic shifter logic that is effective for low complexity parallel processing.

1 is a configuration diagram of a wireless communication system according to an embodiment of the present invention. Referring to FIG. 1, a wireless communication system includes a transmitting device 40 and a receiving device 80. The transmission device 40 includes an LDPC encoding device 50 and a modulator 60. The LDPC encoding apparatus 50 receives data m, encodes the received data m, and outputs a codeword c. The modulator 60 receives the codeword c from the LDPC encoder 50 and radio modulates the codeword c. The radio modulated codeword is transmitted to the receiving device 80 through an antenna. The receiving device 80 includes a demodulator 90 and an LDPC decoding device 100. The demodulator 90 receives a radio-modulated codeword through an antenna and demodulates it into a codeword (c). The LDPC decoding apparatus 100 receives a codeword c, decodes the codeword c, and outputs data m.

As described above, the wireless communication system 10 shown in FIG. 1 encodes the data m into the codeword c using the LDPC encoding apparatus 50, and uses the LDPC decoding apparatus 100 to encode the codeword ( By decoding c) into data m, data m is transmitted and received stably. The LDPC decoding apparatus 100 may determine whether there is an error in the codeword c by using the parity check matrix H, for example, according to Equation 1 below. Here, the parity check matrix means a matrix for checking whether an error is included in the codeword c received by the LDPC decoding apparatus 100.

[Equation 1]

H-c ^T = 0

In Equation 1, if the matrix operation value between the codeword (c) and the parity check matrix is '0', it is determined that the codeword (c) has no error, and if it is not '0', the codeword (c) has an error. To judge.

2 is a diagram illustrating a parity check matrix by way of example. As shown in FIG. 2, the parity check matrix H used in a quasi-cyclic LDPC code described below will include a plurality of sub-matrices. Each submatrix is a square matrix and is either a cyclic or zero matrix of unitary matrices. The parity check matrix H may be divided into a first matrix H1 and a second matrix H2 as shown in Equation 2 below. In this case, the second matrix H2 is a square matrix having an inverse matrix.

&Quot; (2) "

H = [H1, H2]

Referring to Equation 3 below, the codeword c generated by the LDPC encoding apparatus 50 may be divided into data m and parity bit p.

&Quot; (3) "

c = [m, p]

The parity bit p for encoding the data m in the LDPC encoding apparatus 50 is derived using the parity check matrix H. For example, the parity check matrix H consists of l columns and p (p = l-n) rows. The first matrix H1 is composed of p rows and n columns, and includes a plurality of sub matrices. The second matrix H2 is composed of p (p = l-n) rows and p columns.

Equations 1 to 3 mentioned above may derive Equation 4 below.

&Quot; (4) "

[H1, H2] · [m, p] ^T = H1 · m ^T + H2 · p ^T = 0

p ^T =-H2 ^{-1H1m T}

In order to support various code rates and block lengths of codewords in the wireless communication system 10, a plurality of parity check matrices are used. For example, for an IEEE 802.11n system, twelve parity check matrices are defined.

When randomly generating elements of the parity check matrix, a large amount of memory space is required to store the information of the parity check matrix. However, a low density parity check (LDPC) using a quasi-cyclic LDPC code is used. When encoding and decoding are performed, the amount of memory for storing the parity check matrix may be reduced, and the operation process may be simplified.

In the quasi-cyclic LDPC code, the parity check matrix is divided into several small square matrices as shown in FIG. The parity check matrix H of the quasi-cyclic LDPC code may be expressed by Equation 5 below.

&Quot; (5) "

In the parity check matrix H, each h _{i , j} represents a cyclic matrix or a zero matrix of the unit matrix. Due to this characteristic of the structural LDPC code, the size of the memory storing the parity check matrix in the hardware structure can be effectively reduced. The decoding of the codeword of the LDPC code can be described through a bipartite graph. Equation 6 below shows a matrix corresponding to a bipartite graph.

&Quot; (6) "

3 is a diagram illustrating a matrix shown in Equation 6 in the form of a bipartite graph. As shown in FIG. 3, the bipartite graph may include a bit node on the left side and a check node on the right side. The number of bit nodes is equal to the number of columns in the parity check matrix, and the number of check nodes is equal to the number of rows in the parity check matrix.

In the matrix of Equation 6, an element '1' represents an edge connecting bit nodes and check nodes corresponding to each other in a bipartite graph. For example, since the element of (3,5) of the matrix shown in Equation 6 is '1', the fifth bit node and the third check node in FIG. 3 are connected by an edge. In this way, an interconnection is formed between the bit node and the check node.

The decoding process of the codeword coded according to the parity check matrix is performed by a message passing algorithm. The message passing algorithm is a process of decoding codewords while bit nodes connected by edges and check nodes exchange soft information. In general, since soft information is repeatedly transmitted and received, the decoding process is performed through several iterations. The process of the message passing algorithm is as follows.

When the length of the code bit of the LDPC code is N and the length of the information bit is K, the length of the parity bit is set to NK. A codeword _{c = [c 1, c 2} , ..., c N] to indicate, the relationship codeword symbol sequence by _{(x i = 1-2c i) (} x = [x 1, x 2,. .., x _N ]). The transmission symbol x is received at the receiving end through an Additive White Gaussian Noise (AWGN) channel and receives the received symbol sequence "y = [y ₁ , y ₂ , ..., y _N ]". It can be represented as.

와

로 정의한다.

는 j번째 비트 노드에서 생성되어 i번째 검사 노드로 전송되는 소프트 정보(soft information)를 나타내고,

는 i번째 검사 노드에서 생성되어 j번째 비트 노드로 전송되는 소프트 정보를 나타낸다. LDPC 복호화를 위한 대표적인 반복 메시지 패싱 알고리즘(iterative message passing algorithm)인 합-곱 알고리즘(SPA; Sum-Product Algorithm)에 대해 설명하면 다음과 같다.Soft information that occurs at the k iteration

Wow

.

Represents soft information generated at the j th bit node and transmitted to the i th check node,

Represents soft information generated at the i th check node and transmitted to the j th bit node. A sum-product algorithm (SPA), which is a typical iterative message passing algorithm for LDPC decoding, will be described as follows.

For initialization, the intrinsic information when j = 1, 2, ..., N (where N is the number of bit nodes) is calculated. Unique information can be obtained from the symbol value passed through the channel. The number of unique information is equal to the number of bit nodes. The unique information may be represented by Equation 7 below in the form of a log likelihood ratio (LLR) from the received symbol.

[Equation 7]

Iterative decoding will be described. First, intrinsic information generated through initialization is transmitted from the bit node to the check node as first soft information. Upon receiving the unique information from the bit node, the test node generates soft information and delivers the soft information back to the connected bit node.

는 예를 들어 아래의 수학식 8과 같다. 이때, N(i)는 i번째 검사 노드에 연결된 비트 노드 집합이다.Looking at the operation of the check node, soft information generated for i = 1, 2, ..., NK (N is the length of the sign bit, K is the length of the information bit, NK is the number of check nodes).

For example, Equation 8 below. In this case, N (i) is a set of bit nodes connected to the i th check node.

[Equation 8]

는 예를 들어 아래의 수학식 9와 같다.Looking at the bit node operation, soft information generated for j = 1, 2, ..., N, where N is the length of the sign bit.

For example, Equation 9 below.

&Quot; (9) "

는 j번째 비트 노드와 연결된 i' 번째 검사 노드로 다시 전송되는 소프트 정보(soft information)이다. 비트 결정을 할 때 필요한 소프트 정보

는 예를 들어 아래의 수학식 10으로 나타낼 수 있다.In Equation 9, M (j) is a set of check nodes connected to the j th bit node,

Is soft information transmitted back to the i'th check node connected to the j th bit node. Soft information needed when making bit decisions

For example, may be represented by Equation 10 below.

&Quot; (10) "

의 값이 0보다 크면, 부호어의 j번째 비트를 0으로, 0보다 작으면 1로 결정한다. LDPC 복호화 장치(100)는 수학식 10에 의하여, 매 반복(iteration)마다 복호된 부호어를 얻을 수 있다.In Equation (10)

If the value of is greater than 0, the j th bit of the codeword is set to 0, and if it is smaller than 0, it is set to 1. The LDPC decoding apparatus 100 may obtain a decoded codeword every iteration according to equation (10).

The LDPC decoding apparatus 100 determines that the decoded codeword c is a decoded codeword if it satisfies the condition of Equation 1 described above, and extracts an information bit from the codeword. If the decoded codeword c does not satisfy the condition of Equation 1, iteration is performed again.

In the LDPC decoding apparatus 100, a sum-product algorithm (SPA), which is an iterative message passing algorithm used for decoding an LDPC code, is soft between a corresponding bit node and a check node at each iteration. The information is sent.

In this case, for the high speed operation, the test node must simultaneously transmit soft information of Equation 8 to the plurality of bit nodes connected thereto, and the bit node simultaneously transmits the soft information of Equation 9 to the plurality of test nodes connected thereto. Should be sent. Accordingly, an interconnection that connects one bit node and several check nodes is required. An interconnect that connects one check node and several bit nodes is also required.

In the LDPC decoding device, an interconnect device that connects hundreds to thousands of bit nodes and check nodes has a high complexity. When the broadcasting technique is used in the LDPC decoding apparatus, the complexity of the interconnection apparatus may be reduced. According to the broadcasting based message passing algorithm, Equation 1 is changed to Equation 11 below.

&Quot; (11) "

Unlike Equation 8, the i th check node delivers the same soft information to the bit nodes. The broadcasting-based message passing algorithm reduces the complexity of the interconnection apparatus for transmitting data from the check node to the bit node because the information transmitted from the check nodes to the bit nodes is the same. However, the complexity of the bit node increases because the data that must be transmitted from the original check node to the bit node must be generated within the bit node.

Equation 9 mentioned above may also be changed to Equation 12 below.

&Quot; (12) "

Like the check node, the bit node may reduce the complexity of the interconnection device connected from the bit node to the check node by changing the information transmitted to the plurality of check nodes to the same value. However, even in this case, since the information of the bit node of Equation 9, which should be originally transmitted, must be generated by the check node instead of the bit node, the complexity of the check node may increase.

의 크기를 다양하게 정의하여 다양한 부호 길이를 지원할 수 있다. 따라서, 다양한 부호 길이 및 부호율을 지원하기 위하여, LDPC 복호화 장치는 다양한 패리티 검사 행렬에 대하여 유동적으로 동작할 수 있어야 한다. 이하에서 설명되는 본 발명의 실시 예는 다양한 패리티 검사 행렬, 즉 다양한 l과 p의 값을 가지며 다양한 서브 행렬

를 갖는 패리티 검사 행렬에 대응하여 유연하게 동작할 수 있는 LDPC 복호화 장치를 제시한다.Various parity check matrices can be defined to support various code rates and code lengths. For example, in the case of a quasi-cyclic LDPC code, the parity check matrix may be expressed as Equation 5. In order to support various code rates, l and p may have various values. In addition, the sub-matrix of the parity check matrix of Equation 5

By varying the size of, we can support various code lengths. Therefore, in order to support various code lengths and code rates, the LDPC decoding apparatus should be able to operate flexibly for various parity check matrices. Embodiments of the present invention described below have various parity check matrices, that is, various values of l and p and various submatrices.

An LDPC decoding apparatus capable of flexibly operating in correspondence with a parity check matrix having a λ is provided.

4 is a block diagram of an LDPC decoding apparatus according to an embodiment of the present invention. The LDPC decoding apparatus 100 according to an embodiment of the present invention may include an integrated node processor 110, a variable interconnection network 120, a cyclic shifters 130, a parity check matrix storage 140, and respective components. LDPC decoding control unit 150 for controlling.

The combined check and variable node process 110 processes and outputs a check node and a bit node. The flexible interconnect network 120 receives the processing result from the integrated node processor 110, and the parity check matrix stored in the parity check matrix storage 140 under the control of the LDPC decoding control unit 150. The code rate may vary depending on the code rate or the code length. The parity check matrix storage unit 140 may store parity check matrices corresponding to various code rates or code lengths. The cyclic shifters 130 cyclically shift the output of the variable interconnection network 120.

In the embodiment of the present invention illustrated in FIG. 4, the LDPC decoding apparatus 100 may transmit soft information generated by all bit nodes operating at the same clock to a test node by fully parallel processing. Can be. Similarly, the check node can also operate on the same clock and pass the generated soft information to the bit node.

In the case of partial parallel processing, there is a limit in achieving high throughput because of the large number of clock cycles required for sending and receiving messages between bit nodes and check nodes. In contrast, all-parallel processing is effective in achieving high throughput of several Gbps or more because the number of clock cycles required in transferring a message between bit nodes and check nodes is small. However, in the case of all parallel processing, hardware complexity increases in proportion to the number of bit nodes and check nodes in the hardware implementation. Using the sum-product algorithm (SPA) with the broadcasting technique as the message passing algorithm can reduce the complexity of the interconnection that increases with the use of pre-parallel processing.

In the existing SPA, the operations that the bit node and the check node need to perform are clearly distinguished, and each of them needs to have only the necessary hardware resources. The bit node must support some of the operations that the check node must perform, and the check node must also support some of the operations that the bit node should perform. In addition, each bit node and check node must also support the functionality that the original SPA must support.

Therefore, in the case of LDPC decoding using SPA to which broadcasting technique is applied, hardware complexity of bit node and check node is increased. Accordingly, in order to reduce the complexity of the hardware increased as the broadcasting technique is applied, the integrated node processor 110 of the LDPC decoding apparatus 100 according to the embodiment of the present invention integrates a bit node and a check node in each group. It may be implemented as a combined variable and check node processor.

The integrated node processor 110 may be composed of N CVP groups (CVP groups 1 to N). Each CVP block contains several CVPs (CVP1 ~ Z). Each CVP has both a variable node processor and a check node processor. When the sub-matrix of the parity check matrix has various sizes to support various code rates and code lengths, the number of CVPs used in one CVP group may vary. For example, if the size of the sub-matrix of the parity check matrix is 10, 10 CVPs are required. If the size of the sub-matrix is 20, 20 CVPs are needed.

In order to support the sizes of the various submatrices, the CVP is required as much as the largest submatrices. For the example mentioned, 20 CVPs are required, and only 10 of them can be used, and the remaining 10 can be used to support submatrices of size 10. That is, the number of CVPs in a CVP group is related to the support of various submatrices.

Also, in the parity check matrix of Equation 5, columns and rows of the parity check matrix are defined through p sub matrices and l sub matrices. At this time, p sub-matrix determines the length of the codeword of the parity check matrix. Further, when p submatrices are determined, l determines the code rate. Therefore, in order to support the parity check matrix having a sub-matrix of p, the p number of CVP group is necessary in order to decode the code words generated by the parity check matrix, in other words having a p sub-matrix.

For example, if p is 24, you will need 24 CVP groups. If p is 20, you will need 20 CVP groups. Therefore, the number of CVP groups may be determined according to the parity check matrix having the largest value p among the parity check matrices to be supported. In the example mentioned, the number of CVP groups is determined to be 24. When decoding the parity check matrix having p of 20, only 20 CVP groups may be used and the remaining 4 may not be used. In this manner, decoding can be performed corresponding to various codeword lengths.

If the bit node and check node are implemented separately, the complexity of the hardware is doubled. In the case where broadcasting is applied, the integrated node processor 110 constituting an embodiment of the present invention uses a single processor to generate a message passing algorithm using most similar types of logic used in the check node and the bit node. Can be implemented.

5 is a configuration diagram of an integrated node processor constituting an LDPC decoding apparatus according to an embodiment of the present invention. As shown in FIG. 5, the integrated node processor 110 may remove the bit node registers 111, the check node registers 112, the first logic 113, the adder 114, and the second logic 115. Include. Each bit node register 1111 corresponds to one of the N bit nodes, and each check node register 1121 corresponds to one of the M bit nodes. According to the parity check matrix, one bit node or check node is connected with several check nodes or bit nodes. The bit node receives broadcast input data from a plurality of check nodes connected thereto, and the check node receives broadcast input data from a plurality of bit nodes.

In the embodiment shown in FIG. 5, N broadcasting input data are input to the first logic 113 from N check nodes or bit nodes. The process of generating broadcasting output data from broadcasting input data is as follows. The first logic 113 generates SPA data using the multiplexer 1131 and the mapping unit 1132 in the same manner as the existing SPA, and outputs the SPA data to the adder 114. The mapping unit 1132 may detect mapping data corresponding to the input using, for example, a lookup table (LUT). The adder 114 adds all the SPA data through an add operation to produce a broadcasting output.

When the broadcasting technique is applied, each node (bit node or check node) needs to generate and store the same data generated by the existing SPA. Since the broadcasting input data is different from the data received from the existing SPA, it should be made into the data received from the existing SPA. This may be performed by using the multiplexer 1151 of the second logic 115 connected to the output terminal side of the adder 114 and the lookup table LUT of the mapping unit 1152.

At the end of this process, each node (bit node or check node) has the same data that it would receive in the existing SPA. The result calculated by the second logic 115 is stored in the registers 111 and 112 according to whether it is a bit node operation or a check node operation. Thereafter, each node generates a broadcasting output again and delivers it to the connected node, and the delivered broadcasting output is used when performing a calculation of a clock cycle.

In the case of pre-parallel processing, the time required for the bit node and the check node are always different, so the necessary logics can be time shared. While the embodiment of the present invention supports a broadcasting scheme and operates at a high speed, the hardware complexity of the check node and the bit node by the combined variable and check node processor is the same as that of the existing SPA. I can keep it.

In a fully parallel architecture, when the bit node and the check node are hardwired by circuit connection, it becomes difficult to support various parity check matrices. That is, the connection between the bit node and the check node is different according to the parity check matrix. In the conventional hardwired interconnection scheme, it is possible to perform a connection operation between the check node or the bit node in one specific parity check matrix. However, in response to the change of the parity check matrix, the connection of the bit node and the check node cannot be changed.

Accordingly, the variable interconnection network 120 constituting the LDPC decoding apparatus 100 according to an embodiment of the present invention is provided to support various parity check matrices. The variable interconnection network 120 is implemented as a flexible interconnection network reconfigurable according to a parity check matrix.

6 is a block diagram of an interconnection switch unit of a variable interconnection network constituting an LDPC decoding apparatus according to an embodiment of the present invention. 4 and 6, the interconnection switch units 121 of the flexible interconnection network 120 are included. Each interconnection switch unit 121 corresponds to one test and bit node processor (CVP) of the integrated node processor 110 one-to-one, and the test and bit node corresponding to the broadcast output through the input port (input port) It receives input from the processor. In order to support various parity check matrices, broadcasting output data from one CVP may be connected to up to 24 CVP groups according to the parity check matrix.

Connecting to 24 CVP groups in one CVP group increases the complexity of the interconnection network. In an embodiment of the present invention, the variable interconnection network 120 may perform interconnection by grouping several CVP groups into one large group. 6 shows an example in which four CVP groups are grouped into one large group.

The interconnection switch unit 121 may perform interconnection using the switches 1211 to 1215 receiving two control signals CTRL0 and CTRL1. Each switch 1211 to 1215 includes two transmission gates TG1 and TG2. The two transfer gates TG1 and TG2 generate two outputs (output 0 and output 1) according to the control signals CTRL0 and CTRL1 in response to a common input. For example, if you do not need to connect CVP groups 1 to 4 for a check node or a bit node, adjust the control signal to send CVP groups 5 to 4 without sending broadcast output data to CVP groups 1 to 4. You can send the broadcast output data to 8.

As another example, if there is no need to connect to CVP groups 1-8, the control signal can be adjusted so that no data is sent to CVP groups 1-8. Such a control signal may be generated differently according to the parity check matrix. Accordingly, the switches 1211 to 1215 may be controlled according to the parity check matrix to variably connect or block the CVP group, and support various parity check matrices.

7 is a diagram illustrating an exemplary parity check matrix of an LDPC code. This shows the parity check matrix of the quasi-cyclic LDPC code used in the IEEE 802.11n WLAN system. The parity check matrix is divided into a first matrix H1 and a second matrix H2. The first matrix H1 consists of four rows and twenty columns, and the second matrix H2 consists of four rows and four columns. In addition, each sub-matrix is implemented as a cyclic matrix or a zero matrix of the unit matrix. One square represents a submatrix. When the size of the sub-matrix is 81, 81 bit nodes and 81 check nodes form a group.

In FIG. 7, the numbers indicated in each sub-matrix represent the magnitude of the cyclic shift of the unit matrix. In the parity check matrix, the number '13' described in the first column of the first row, that is, the (1,1) sub-matrix, has an interconnection between the bit nodes of 1-81 and the check nodes of 1-81, This means that the bit node and the check node are connected by cyclic shift by 13 '. That is, bit 1 node is connected to check node 14, bit 2 node is connected to check node 15, and bit node 81 is connected to check node 13 in the same manner, where a cyclic shifter is used. Need. '-' Represents a zero matrix, meaning no interconnection.

The circular movement unit 130 is connected to the output of the variable interconnection network 120 as shown in FIG. Taking the parity check matrix shown in FIG. 7 as an example, when data is sent from the first bit node group to the interconnection switch unit 121 of the variable interconnection network 120, the first connection is performed through the interconnection switch unit 121. Is sent to the fourth check node group.

In the case of the embodiment illustrated in FIG. 7, since only the fourth test node group exists, the interconnection switch unit 121 may transmit data only to the CVP groups 1 to 4. The cyclic shifter 130 cyclically shifts the transmitted data by the values '13', '69', '51', and '16' and transmits the data to each CVP group. That is, the cyclic shift unit 130 generates four cyclic shift outputs in response to one input.

8 is a configuration diagram of a cyclic shifter constituting an LDPC decoding apparatus according to an embodiment of the present invention. Referring to FIG. 8, the cyclic shifter 130 includes a first stage cyclic shifter 131 and second cyclic shifters 132. That is, the cyclic shifter 130 has a two-stage cyclic shifter structure.

Looking at the first column of the parity check matrix shown in Figure 7 it can be seen that the size of the cyclic shift value (cyclic shift value) is '13', '69', '51', '16'. In order to support this simultaneously, four cyclic shifters are required. If cyclic shifts are implemented by simply connecting four cyclic shifters in parallel, complexity may increase.

Accordingly, the first cyclic shifter 131 performs a cyclic shift in a predetermined cyclic shift unit (for example, 16 cycles). Accordingly, the first cyclic shifter 131 outputs the output to the second cyclic shifters 132 by performing a cyclic shift operation by a predetermined range. The second cyclic shifters 132 perform a cyclic shift by an insufficient amount after the cyclic shift performed in the first stage by the first cyclic shifter 131.

In one embodiment, when the broadcasting data is connected in units of four CVP groups in the variable interconnection network 120, one cyclic shifter should be able to support four different cyclic shift sizes. do. Accordingly, the second cyclic shifters 132 are arranged in a parallelized cyclic shifter structure to perform parallel processing.

FIG. 9 is a configuration diagram of the first cyclic shifter illustrated in FIG. 8. As shown in FIG. 9, the first cyclic shifter 131 includes cyclic shift circuits 1311-1315 for circulating the input in a specific cycle (eg, 16 cycles). The first cyclic shifter 131 may be implemented by connecting the first to fifth cyclic shift circuits 1311 to 1315 in serial.

The first cyclic shifter 131 may select an output point according to a cyclic shift value defined in the parity check matrix and pass data to the second cyclic shifters 132. When the length of data is one of 27, 54, and 81, the cyclic shift circuit 1311 may be divided into three regions of 27 (16 + 11), and may be implemented to support all cases through the selection of a multiplexer. have. Although the multiplexer is present in the first cyclic shifter 131, the complexity of the logic is not high because basically one cyclic shift unit is 16 units.

For example, when the cyclic shift unit of the first cyclic shifter 131 is '16', in the first column of the parity check matrix illustrated in FIG. 7, the first cyclic shift value is '13'. The first cyclic shifter 131 sends the input directly to the second cyclic shifters 132 without shifting the input. Thereafter, thirteen cyclic shifts are performed by the second cyclic shifters 132.

In the first column of the parity check matrix shown in FIG. 7, since the second cyclic shift value is '69', the first cyclic shifter 131 cyclic shifts to '64' through four steps in units of 16 cycles. ) Is sent to the second cyclic shifters 131. Accordingly, the second cyclic shifters 132 only need to perform five more cyclic shifts.

In the first column of the parity check matrix shown in FIG. 7, since the third cyclic shift value is '51', the first cyclic shifter 131 performs cyclic shifts to '48' through three steps in units of 16 cycles. ) Is sent to the second cyclic shifters 131. Accordingly, the second cyclic shifters 132 only need to perform three more cyclic shifts. Further, in the first column of the parity check matrix shown in FIG. 7, since the fourth cyclic shift value is '16', the first cyclic shifter 131 performs 16 cyclic shifts. In this case, the second cyclic shifters 132 may be directly outputted without being operated.

FIG. 10 is a configuration diagram of each second circulation shifter illustrated in FIG. 8. 8 and 10, each of the second cyclic shifters 1321 of the second cyclic shifters 132 includes four blocks of the cyclic shift circuits 1321a ˜ d.

Since the second cyclic shifter 1321 performs a cyclic shift only by an insufficient amount on the basis of the result of the cyclic shift in the first cyclic shifter 131, the maximum cyclic shift is the size of the cyclic shift. Is smaller than the cyclic shift unit (eg, 16) of the first cyclic shifter 131. If there is no first cyclic shifter 131, the second cyclic shifter 1321 should support all of the cyclic shift (cyclic shift) from 1 to a maximum of 80, the second cyclic shifter 1321 in the embodiment of the present invention Since only the cyclic shift from 1 to 15 need to be supported, the complexity of the cyclic shift unit 130 can be greatly reduced.

For example, the first circuit 1321a performs a cyclic shift of one step. A cyclic shift is performed by two steps in the second circuit 1321b, four steps in the third circuit 1321c, and eight steps in the fourth circuit 1321d. The second cyclic shifter 1321 may also be divided into three parts like the first cyclic shifter 131 to support all of the cyclic shift of data of various lengths such as 27, 54, and 81.

If the length of the cyclic shift to be performed in the second cyclic shifter 1321 is '5', the cyclic shift may be performed only in the first and third steps. In this case, in the second and fourth steps, data may be transferred to the next step without performing a cyclic shift. According to an embodiment of the present invention, since the cyclic shift is performed in a specific unit (for example, 16 units) in the first cyclic shifter 131, the cyclic shift to be performed in the second cyclic shifter 1321. The size of is limited to 15 or less. Therefore, the overall complexity of the cyclic shifter 130 can be reduced compared to the conventional cyclic shifter.

As described above, the LDPC decoding apparatus according to the embodiment of the present invention can support various code rates and code lengths, and implement reconfigurable interconnection. The LDPC decoding apparatus according to the embodiment of the present invention is implemented in a structure having a low complexity and suitable for parallel operation processing of a cyclic shifter required in a message passing process of a quasi-cyclic LDPC code. Therefore, it is possible to reduce the complexity of the bit node and the check node and the complexity of the interconnection network and to support throughput of several Gbps.

It is to be understood that the above-described embodiments are provided to facilitate understanding of the present invention, and do not limit the scope of the present invention, and it is to be understood that various modifications may be made within the scope of the present invention. For example, each component shown in the embodiment of the present invention may be distributed and implemented, and conversely, a plurality of distributed components may be combined. Therefore, the technical protection scope of the present invention should be determined by the technical idea of the claims, and the technical protection scope of the present invention is not limited to the literary description of the claims, The invention of a category.

10: wireless communication system 40: transmitting device
50: LDPC encoder 60: modulator
80: receiver 90: demodulator
100: LDPC decoding device 110: integrated node processor
120: variable interconnection network 130: circular moving unit
140: parity check matrix storage unit 150: LDPC decoding control unit

Claims (15)

An integrated node processor including groups of check nodes and bit nodes corresponding to a parity check matrix, the soft node generating soft information for the check node and the bit node;
A variable interconnection network which receives the soft information from the integrated node processor and variably sets the interconnections for the groups according to the parity check matrix; And
And a cyclic shift unit cyclically moving the output of the variable interconnection network according to the parity check matrix. The method according to claim 1,
A parity check matrix storage unit for storing a plurality of parity check matrices corresponding to a plurality of code rates or a plurality of code lengths;
The variable interconnection network,
And setting the interconnection for the groups according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length among the plurality of parity check matrices. The method according to claim 1,
Each group of the integrated node processor includes registers of check nodes and registers of bit nodes corresponding to a size of a sub-matrix of the parity check matrix,
And the registers store the soft information generated according to a sum-product algorithm from a broadcasting input received from bit nodes or check nodes. The method of claim 3,
And the variable interconnection network corresponds one-to-one with the registers, and includes interconnection switches configured to establish the interconnection with one or more cyclic shifters of a plurality of cyclic shifters according to the parity check matrix. 5. The method of claim 4,
And the interconnection switches are configured to establish the interconnection with the one or more cyclic shift units based on information of sub-matrices of the parity check matrix to which the check node and the bit node are connected. 6. The method of claim 5,
Each interconnection switch
2. The decoding apparatus having two outputs for one input according to a control signal, and simultaneously transmitting inputs from the integrated node processor to a plurality of circular moving units corresponding to a plurality of sets of groups. The method according to claim 1,
The circular moving unit,
A first cyclic shifter cyclically moving the input from the variable interconnection network in units of first cycles according to cyclic information of a sub-matrix of the parity check matrix; And
And second cyclic shifters cyclically moving the output of the first cyclic shifter by a second cycle according to the cyclic information. The method of claim 7, wherein
And the second cycle has a smaller value than the first cycle unit. The method of claim 8,
The first cyclic shifter includes a plurality of cyclic shift circuits cyclically moving the input in units of the first cycle, and selects and outputs outputs of the plurality of cyclic shift circuits to the second cyclic shifters. A transmission device including an LDPC encoding device for generating a codeword from data using a parity check matrix; And
And a receiving device including an LDPC decoding device for decoding the codeword by using the parity check matrix to restore the data.
The LDPC decoding apparatus,
An integrated node processor including groups of check nodes and bit nodes corresponding to a parity check matrix, the soft node generating soft information for the check node and the bit node;
A variable interconnection network which receives the soft information from the integrated node processor and variably sets the interconnections for the groups according to the parity check matrix; And
And a cyclic shifter cyclically moving the output of the variable interconnection network according to the parity check matrix. The method of claim 10,
The LDPC decoding apparatus further includes a parity check matrix storage unit for storing a plurality of parity check matrices corresponding to a plurality of code rates or a plurality of code lengths.
The variable interconnection network,
And establishing the interconnection for the groups according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length of the plurality of parity check matrices. The method of claim 10,
The circular moving unit,
A first cyclic shifter cyclically moving the input from the variable interconnection network in units of first cycles according to cyclic information of a sub-matrix of the parity check matrix; And
And second cyclic shifters cyclically moving the output of the first cyclic shifter by a second cycle according to the cyclic information. Generating soft information for the check node and the bit node corresponding to the parity check matrix;
Variably setting an interconnection between the check node and the bit node according to the parity check matrix; And
And cyclically moving a signal input according to the variably set interconnection according to the parity check matrix. The method of claim 13,
Variably setting the interconnection,
And setting the interconnection between the check node and the bit node according to the parity check matrix corresponding to a predetermined code rate or a predetermined code length among a plurality of parity check matrices. The method of claim 13,
The circular movement step,
Cyclically moving the input signal in units of a first cycle according to cyclic information of a sub-matrix of the parity check matrix; And
And cyclically moving the signal circulated in the first cycle unit by a second cycle according to the cyclic information.

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