WO2019107912A1

WO2019107912A1 - Ldpc encoding device and method which have low latency and high reliability characteristics

Info

Publication number: WO2019107912A1
Application number: PCT/KR2018/014814
Authority: WO
Inventors: 김광순; 전기준
Original assignee: 연세대학교 산학협력단
Priority date: 2017-11-29
Filing date: 2018-11-28
Publication date: 2019-06-06

Abstract

An LDPC encoding device and method which have low latency and high reliability characteristics are disclosed. The disclosed device comprises: a parity generating matrix storage unit for storing a parity generating matrix which can be divided according to section (1); a first parity bit calculation unit for calculating parity intermediate variables and a first parity bit if l=2 through a permutation operation and an accumulator operation by using given codewords and the parity generating matrix; and a second parity bit calculation unit for calculating a second parity bit by using the parity intermediate variables if l=1, 3 and 4, wherein sub matrices divided by section from the parity generating matrix are matrices set to enable RU encoding. The disclosed device and method satisfy LMDG characteristics, thereby being suitable for low latency communication because of low complexity while guaranteeing high reliability.

Description

LDPC encoding apparatus and method having low delay and high reliability characteristics

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LDPC coding method and apparatus, and more particularly, to an LDPC coding method and apparatus having low latency and high reliability characteristics.

Research on LDPC (Low Density Parity Check) has been actively pursued because of its approximate optimal performance, efficient coding and decoding capability based on parallel processing, and ease of hardware design.

Recently, research on a fifth generation mobile communication system is under way, and fifth generation mobile communication requires more stringent reliability and low delay characteristics than conventional LDPC codes.

Also, in the next generation sensor network, it is necessary to transmit and receive a large amount of data in real time with low power without delay, and thus a code design capable of ensuring high reliability and capable of low complexity coding is needed.

Known LDPC codes include RU (Richardson-Urbanke) codes, RMA (Repeat Multiple Accumulate) codes, ARA (Accumulate Repeat Accumulate) codes and ARJA (Accumulate Repeat Jagged Accumulate) codes.

These codes have the following problems in order to satisfy high reliability and low ductility at the same time.

The RU code can be efficiently encoded, but the decoding threshold and the error floor characteristics are inferior, so that high reliability can not be guaranteed, and such a phenomenon has a problem in that the coding rate becomes worse as the coding rate becomes lower.

The RMA code can be efficiently encoded and has excellent error floor performance due to the linear minimum distance growth (LMDG) characteristic. However, since the decoding threshold characteristic is low and the reliability is not guaranteed, the lower the coding rate There was a problem of further deepening.

The ARA code has very good decoding threshold and low complexity coding, but it lacks the LMDG characteristic and has a problem of poor reliability due to poor error flooring characteristics.

ARJA code satisfies high decoding threshold and LMDG characteristics and guarantees high reliability, but coding complexity is large and there is a problem in low delay communication.

The present invention proposes an LDPC encoding apparatus and method suitable for low-delay communication due to low complexity while ensuring high reliability by satisfying LMDG characteristics.

According to an aspect of the present invention, there is provided a parity generation apparatus, comprising: a parity generation matrix storage unit for storing a parity generation matrix divisible by sections (1); A first parity operation unit for calculating a parity intermediate variable and a first parity bit in case of l = 2 using permutation operation and accumulator operation using a given codeword and the parity generation matrix; and a second parity operation unit for calculating a second parity bit using the parity intermediate variable when l = 1, 3, 4, wherein the submatrices divided by sections in the parity generation matrix are matrixes Is provided.

Wherein the parity generation matrix is generated through lifting for an adjacent matrix obtained from a photograph, and in the lifting process, for a predetermined element of the adjacent matrix,

Performs the operation,

Is an operation for performing a left cyclic shift operation for i with respect to the identity matrix I, and performing zero masking for converting a column of the first row and ((Ni) _N ) to zero.

Wherein the second parity operation unit comprises: a subvector accumulator for performing a subvector accumulation operation on the parity intermediate variable; A bit accumulator for performing a bit accumulation operation on the bits of the output of the sub-vector accumulator; A conditional summation unit for conditionally summing the output of the bit accumulator and the parity intermediate variable; And an accumulator for performing an accumulation operation on the output of the conditional summation unit.

The parity intermediate variable

Is calculated according to the following equation.

In the above equation, when the codeword to be encoded is x _i ,

Lt; / RTI >

Is a set of variable nodes,

Denotes the i-th element in the variable node set,

Denotes the j-th element from the i-th element in the variable node set, H denotes the parity generating matrix,

Lt;

The

And the i-th length of N denotes a subvector.

The first parity operation unit computes a first parity using the parity intermediate variable when l = 2, as in the following equation.

In the above equation, p _{2, k} is

Length according to

The permutation order vector.

The second parity operation unit calculates a second parity bit according to the following equation.

In the above equation,

ego,

Lt;

ego,

, P _{l, k} and q _{l, k} are

Are permutation order vectors according to.

The conditional summation unit performs conditional summation as shown in the following equation.

The second parity bit

Is stored in the memory according to the permutation order vector q _{l, k} .

According to another aspect of the present invention, there is provided a method comprising: (a) storing a parity generation matrix storing a parity generation matrix divisible by sections (1); (B) calculating a parity intermediate variable using a permutation operation and an accumulator operation using a given codeword and the parity generation matrix, and a first parity bit for l = 2; (c) calculating a second parity bit by using the parity intermediate variable when l = 1, 3 and 4, wherein the submatrices divided by sections in the parity generation matrix are matrixes set to enable RU encoding Is provided.

The LDPC encoding apparatus and method according to an embodiment of the present invention are advantageous for low delay communication due to low complexity while ensuring high reliability by satisfying LMDG characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a photograph of an LDPC encoding apparatus and method according to an embodiment of the present invention; FIG.

2 illustrates an example of an adjacency matrix obtained from a photograph in accordance with an embodiment of the present invention.

3 is a diagram illustrating an example of a parity generation matrix according to an embodiment of the present invention.

4 is a diagram illustrating a structure of an LDPC encoding apparatus having low delay and high reliability characteristics according to an embodiment of the present invention.

5 is a diagram illustrating an overall flow of an LDPC encoding method according to an embodiment of the present invention.

FIG. 6 illustrates elements of an adjacent matrix obtained from a photo graph of an LDPC encoding apparatus according to an embodiment of the present invention; FIG.

FIG. 7 is a photograph showing the photograph of FIG. 6 more simply.

FIG. 1 is a diagram illustrating a photographed image of an LDPC encoding apparatus and method according to an embodiment of the present invention. Referring to FIG.

The present invention is based on the encoding apparatus and method of Korean Patent Application No. 2016-0036335 proposed and filed by the present inventor, and the content of the corresponding domestic patent application can be referred to for the understanding of the present invention, The present invention relates to a specific coding method in an LDPC coding apparatus having a photograph structure as shown in FIG.

Referring to FIG. 1, an LDPC encoding apparatus according to an embodiment of the present invention includes a first outer encoding module 300, a second outer encoding module 310, a first inner encoding module 320, (330).

1 shows a first outer code part 400 showing the protocol connection state of the first outer encoding module 300, a second outer code part 400 showing the protocol connection state of the second outer encoding module 310, A first inner code part 420 showing the protocol connection state of the first inner code module 320, a second inner code part 420 showing the protocol connection state of the second inner code module 330, (430) are shown.

The first outer encoding module 300 and the second outer encoding module 310 receive information bit streams for encoding. A part of the information bit stream is input to the first outer encoding module 300 and the remaining information bit stream is input to the second outer encoding module 310

The first outer encoding module 300 outputs a precoding bit stream for generating a parity bit stream using the input information bit stream. The first outer encoding module 300 outputs a precoding bit string for generating a parity bit string through an accumulator operation.

Referring to FIG. 1, the first outer encoding module 300 includes a plurality of variable nodes, a plurality of check nodes, and inter-node connection lines.

The leftmost variable nodes among the plurality of variable nodes are the nodes to which the information bit stream is input and the variable nodes on the right are the precoded parity bit streams from the information bit stream to the punctured variable nodes.

The variable nodes and check nodes of the first outer encoding module 300 have a zigzag closed loop connection state of connection degree-2. As described above, when the accumulator-based encoding is performed through the connection structure of the accumulator, Lt; / RTI >

The second outer encoding module 310 receives the remaining information bit string that is not input to the first outer encoding module 300 and the output bit string of the first outer encoding module 300, It includes a number of variable nodes along with punctured variable nodes.

The second outer encoding module 310 performs repetition and replacement operations to obtain the encoding gain and the interleaving gain in the first inner encoding module 320 and the second inner encoding module 330.

The variable nodes of the second outer encoding module 310 are connected to the check nodes of the first inner encoding module 320 and the second inner encoding module 330 to have a connection state of multiple connection degree closed loop.

The first outer coding module 300 and the second outer coding module 310 are connected to the first inner coding module 320 and the second inner coding module 330 and the output bits of the second outer coding module 310 The columns are input to the check nodes of the first inner encoding module 320 and the second inner encoding module 330.

The first inner encoding module 320 and the second inner encoding module 330 generate the final parity bit streams using the bit strings output from the second outer encoding modules 310.

The check nodes of the first inner encoding module 320 and the second inner encoding module 330 are connected to variable nodes of the second outer encoding module 310 and receive output bit strings.

The first internal encoding module 320 generates most of the parity bit streams through a single parity check operation. However, some of the parity bit streams of the first inner encoding module 320 are generated through a single parity check operation and an accumulator operation.

Referring to FIG. 1, the first inner encoding module 320 can confirm that a check node and a part of a variable node have a connection line 425 having a connection degree-2, unlike the ARA code and the ARJA code, The nodes connected through the connection lines output parity bit strings through a single parity check operation and an accumulator operation.

The first inner encoding module 320 outputs a parity bit sequence through a single parity check operation and an accumulator operation to a part of the parity bit string output from the second inner encoding module 330, And outputs a parity bit string.

Referring to FIG. 1, a check node of the first internal encoding module 320 and a part of variable nodes of the second internal encoding module 430 are connected through an external connection line 450.

The second inner encoding module 330 outputs the parity bit sequences through the variable nodes using a single parity check operation and an accumulator operation on the bit strings input from the second outer encoding module 310.

The inner connection line of the first inner coding module 320 and the outer connection line between the second inner coding module 330 and the first inner coding module 320 in the LDPC code according to an embodiment of the present invention satisfy the LMDG characteristic .

In addition, since the accumulator operation structure is maintained in the second inner encoding module 330, encoding can be performed with low complexity unlike the ARJA code. In the first inner encoding module 320, only a single parity check operation and an accumulator operation are performed, thereby enabling encoding with low complexity.

In the first inner encoding module 320, a part of the parity bit streams are sequentially output through a single parity check operation, and a part of the parity bit streams are output as part of the parity bit streams output from the second inner encoding module 430 And output through the accumulator operation.

FIG. 6 is a diagram illustrating a check node and a variable node obtained from a photo graph of an LDPC encoding apparatus according to an embodiment of the present invention, and FIG. 7 is a simplified graph of the photo graph of FIG.

6 and 7, a node indicated by white is a punctured variable node, a node indicated by black is a variable node (information + parity) actually transmitted, and a node including a cross is internally included It is a node that defines a check node and defines an operation between variable nodes.

Referring to FIGS. 6 and 7, variable nodes are classified into 0, 1, 2, 3, and 4, and check nodes are divided into 1, 2, 3, and 4. In the variable node, a variable node divided by 0 corresponds to the information node. As a result, the variable node is divided into five sections of 0 to 4, and the check node is divided into four sections of 1 to 4. As a result, it can be seen that, when having the photograph structure of the present invention as shown in FIGS. 6 and 7, it is possible to divide sections into four check nodes and five variable nodes.

2 is a diagram illustrating an example of an adjacency matrix obtained from a photograph according to an exemplary embodiment of the present invention.

Since the check node and the variable node of the base photo graph can be divided into four and five sections, respectively, the adjacent matrix obtained from the base photo graph is also divided into four rows and five columns. In this specification, Index, and k is an index indicating the number of loops. P _l represents the number of loops in the lth section,

.

Denotes a set of variable nodes,

Denotes a set of check nodes, and it is confirmed that the adjacent matrix obtained from the photograph has a structure divided by each section (l).

6 and 7, the variable nodes and the check nodes including the respective parities are divided into l = 1, 2, 3, and 4, respectively. This is because the photograph of the present invention has four independent encoding modules .

The division structure of the adjacent matrix can be expressed by the following equation (1).

At this time, it is preferable that the adjacent matrix satisfies the following condition, and it is possible to perform RU (Richardson Urbanke) coding for each sub matrix to be described later when the following three conditions are satisfied.

Are defined as adjacent matrices obtained from the photograph and the adjacency matrix is constructed using the extension (B), the three conditions are as follows.

(1) Expansion Condition

With respect to extension (B)

ego,

Lt;

Represents the maximum degree of connection between the check node and the variable node. Here, Z ⁺ represents a natural number.

(2) Coding structure condition

l = 1, 3, 4,

Quot;

ego,

The

&Lt; / RTI >

(3) Decoding condition

ego,

to be.

here,

H " denotes the maximum column weight of the matrix A.

here,

The

Lt; / RTI >

The

to be. Also,

The

And the number of layers extracted from the check nodes in the following equation.

The parity generation matrix is a matrix in which lifting is performed on an adjacent matrix as shown in FIG. In the parity generation matrix, I _i means a matrix in which the NXN identity matrix I is left cyclically shifted by i from 0 to N-1, and I _-1 denotes an NXN zero matrix.

On the other hand,

Means a modified cyclic shift operation, which differs from existing lifting in that a modified cyclic shift operation is used for the operation of the adjacent matrix.

Masking operation that performs a left cyclic shift operation by i but transforms the column of the first row and (Ni) _N) to zero. Where the subscript N refers to a modular operation.

Referring to FIG. 3, the lifted parity generation matrix H from the adjacent matrix also has a structure that can be divided into sections,

.

here,

Lt; / RTI >

The

. &Lt; / RTI >

A sub-matrix divided from the parity generation matrix (H)

Can be expressed as the following equation.

Equation (2) indicates that each sub-matrix constituting the parity generation matrix is RU-coded. The RU encoding for each sub-matrix becomes possible when the condition for the adjacent matrix and the condition for the lifting operation are satisfied together as described above. It is mathematically provable that RU encoding is possible when the condition is satisfied.

On the other hand, the RU encoding is performed by T.J. Richardson and R.L. Urbanke, "Efficient encoding of low density parity check codes," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 638-656. Feb. 2001 and S.Myung, K. Yang, and J. Kim, "Quasi-cyclic LDPC codes for fast encoding," IEEE Transactions on Information Theory, vol. 51, pp. 2894-2901, Aug. 2005, and the contents of these papers can be referred to in understanding RU encoding of the present invention.

Hereinafter, the encoding apparatus and method of the present invention for generating parity bits from a given codeword using a parity generation matrix having an exemplary structure as shown in FIG. 3 will be described in detail.

4 is a diagram illustrating a structure of an LDPC encoding apparatus having low-latency and high-reliability characteristics according to an embodiment of the present invention, and FIG. 5 is a flowchart illustrating an overall operation of an LDPC encoding method according to an embodiment of the present invention FIG.

4, an LDPC encoder according to an exemplary embodiment of the present invention includes a controller 400, an information bit memory 402, a first parity memory 402, a second A parity-2 memory 406, a H memory, a first parity operation unit 410, and a second parity operation unit 412. The parity-

A code word to be encoded is stored in the information bit memory 402, and information on a parity generation matrix obtained from the photograph (see FIG. 1) is stored in the parity generation matrix memory 408. As described above, the parity generation matrix has a structure divisible by sections (1), and each sub-matrix has a structure capable of RU encoding through lifting proposed in the present invention.

The first parity operation unit 410 calculates a parity bit in the case of l = 2 (check node and variable node with l = 2 in Fig. 2). The first parity operation unit 410 computes a first parity using a parity generation matrix and a code word. The calculated first parity is stored in the first parity memory 404.

The second parity operation unit 412 computes parity bits for l = 1, 3, and 4. The second parity operation unit 412 computes a second parity using the parity generation matrix and the value output from the first parity operation unit 410. The calculated second parity is stored in the second parity memory.

The operations of the first parity operation unit 410 and the second parity operation unit 412 are performed only by a permutation operation, an accumulation operation and an add operation, This is because it is set to enable encoding.

The control unit 400 controls the overall operation of each element described above.

The operation of the encoding apparatus shown in FIG. 4 will be described in more detail with reference to FIG.

When x _i is defined as a partial binary code word column vector of length N,

Lt; / RTI >

Is a set of variable nodes.

Denotes the i-th element in the variable node set,

Denotes the j-th element from the i-th element in the variable node set,

Denotes a variable node connected to a check node i connected to a set of variable nodes,

Denotes a check node connected to a variable node j in the check node set.

In the present invention,

Satisfy

However,

Means a set of check nodes.

As a result, the encoding of the present invention can be expressed by the following Equation (3).

In Equation (3), xxx can be calculated as Equation (4).

Equation (4) is divided into (a) part and (b) part, and the present invention computes the parity bit corresponding to the codeword x part after (a)

In this specification, the operation result of the part (a) is defined as a parity intermediate variable.

Referring to FIG. 5, a parity intermediate variable is calculated using a parity generation matrix and a given codeword (step 500).

According to a preferred embodiment of the present invention,

Can be calculated by the following equation (5).

here,

Lt;

The

Denotes an N-th sub-vector.

The operation of the parity intermediate variable as shown in Equation (4) is performed in the first parity operation unit 410. The first parity operation unit 410 includes a multiplexer 600, a left cyclic shift shifter 610, and an accumulator 620, and the operation of Equation (8) can be performed by only the above shifter and accumulator operation.

In case of l = 2, since the parity bit is set to be output only by the single parity check operation and the accumulator operation, the parity bit can be calculated in the case of l = 2 by simply outputting the parity intermediate variable according to the permutation order have.

If l = 2, the parity bit may be calculated as Equation (6) using the parity intermediate variable to be computed.

In Equation (6), p _{2, k}

Length according to

The first parity operation unit 410 transforms the order of the parity intermediate variable corresponding to l = 2 in the parity intermediate variables according to the permutation order vector by performing a permutation operation according to the permutation order vector, And outputs a parity bit. The output first parity bit is stored in the first parity memory 404 (step 504).

On the other hand, the second parity bit, which is the parity bit in the case of l = 1, 3 and 4, is calculated by the second parity operation unit 412. The second parity operation unit 412 also computes a second parity bit using the parity intermediate variable computed by the first parity operation unit 410.

The second parity operation unit 412 includes a subvector accumulator 630 and a bit accumulator 640. The subvector accumulator 630 performs the accumulation operation on the subvector using the parity intermediate variable xxxx, and the bit accumulator 640 performs the bit accumulation operation on the parity intermediate variable (step 506).

The second parity operation unit 412 adds the parity intermediate variable < RTI ID = 0.0 >

And the conditional summation unit 660 performs conditional summation of the parity intermediate variable and the output bit of the bit accumulator 640 (step 508).

The second parity operation unit 412 includes a temporary memory 670 and stores the output bits of the conditional summation unit 660 in the temporary memory 670 according to the permutation order vector P _{l, k} (step 510).

The second parity operation unit 412 includes an accumulator 680. The accumulator 680 outputs a second parity bit through a predetermined accumulation operation on the bits stored in the temporary memory 670, The second parity bit is stored in the second parity memory 404 (step 512).

In the case of l = 1, 3, and 4, the operation of the second parity bit according to Equation (4) is performed as shown in Equation (7).

In Equation (7) above,

Is defined by the following equation (8).

In the above Equations (7) and (8)

ego,

Lt;

ego,

to be. . p _{l, k} and q _{l, k} are

Are permutation order vectors according to the following equation.

The output of the second parity bit accumulator 640 is

And the conditional summation of the FIFO 650 and the output of the bit accumulator 640 is

to be.

The output of the conditional summation unit 660

Is stored in the temporary memory 670 according to p _{l, k} ,

In the second parity memory 406 according to q _{l, k} .

As a result, according to the present invention, RU coding can be performed for each sub-matrix divided by sections in the parity generation matrix, and coding with low complexity can be performed with excellent error floor performance owing to this coding structure.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be.

It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

Claims

A parity generation matrix storage unit for storing a parity generation matrix which is divisible by sections (l);

A first parity operation unit for calculating a parity intermediate variable and a first parity bit in case of l = 2 using permutation operation and accumulator operation using a given codeword and the parity generation matrix;

and a second parity operation unit for calculating a second parity bit using the parity intermediate variable when l = 1, 3, 4,

Wherein the sub-matrices divided by the section in the parity generation matrix are matrixes set to enable RU coding.
The method according to claim 1,

Wherein the parity generation matrix is generated through lifting for an adjacent matrix obtained from a photograph, and in the lifting process, for a predetermined element of the adjacent matrix,
Performs the operation,
Is an operation for performing a left cyclic shift operation by i for an identity matrix I, and performing zero masking for converting a column of the first row and ((Ni) N ) to zero.
The method according to claim 1,

Wherein the second parity operation unit comprises: a subvector accumulator for performing a subvector accumulation operation on the parity intermediate variable;

A bit accumulator for performing a bit accumulation operation on the bits of the output of the sub-vector accumulator;

A conditional summation unit for conditionally summing the output of the bit accumulator and the parity intermediate variable;

And an accumulator for accumulating the output of the conditional summation unit.
The method according to claim 1,

The parity intermediate variable
Is calculated according to the following equation.

In the above equation, when the codeword to be encoded is x i ,
Lt; / RTI >
Is a set of variable nodes,
Denotes the i-th element in the variable node set,
Denotes the j-th element from the i-th element in the variable node set, H denotes the parity generating matrix,
Lt;
The
And the i-th length of N denotes a subvector.
5. The method of claim 4,

Wherein the first parity operation unit computes a first parity using the parity intermediate variable when l = 2 according to the following equation.

In the above equation, p 2, k is
Length according to
The permutation order vector.
6. The method of claim 5,

Wherein the second parity operation unit calculates a second parity bit according to the following equation.

In the above equation,
ego,
Lt;
ego,
, P l, k and q l, k are
Are permutation order vectors according to.
The method according to claim 6,

Wherein the conditional summation unit performs conditional summation according to the following equation.
8. The method of claim 7,

The second parity bit
Is stored in a memory according to a permutation order vector q l, k .
(A) storing a parity generation matrix storing a parity generation matrix that is divisible by sections (l);

(B) calculating a parity intermediate variable using a permutation operation and an accumulator operation using a given codeword and the parity generation matrix, and a first parity bit for l = 2;

(c) calculating a second parity bit using the parity intermediate variable when l = 1, 3, 4,

Wherein the submatrices divided by the section in the parity generation matrix are matrixes set to enable RU coding.
10. The method of claim 9,

Wherein the parity generation matrix is generated through lifting for an adjacent matrix obtained from a photograph, and in the lifting process, for a predetermined element of the adjacent matrix,
Performs the operation,
Is an operation for performing a left cyclic shift operation on i for the identity matrix I, and performing zero-masking for converting a column of the first row and ((Ni) N ) to zero.
10. The method of claim 9,

The step (c)

Performing a subvector accumulation operation on the parity intermediate variable;

Performing a bit accumulation operation on bits output according to the subvector accumulation operation;

Performing an output of the bit accumulation operation and conditional summation on the parity intermediate variable; And

And performing an accumulation operation on the output of the conditional summation unit.
10. The method of claim 9,

The parity intermediate variable
Is calculated according to the following equation.

In the above equation, when the codeword to be encoded is x i ,
Lt; / RTI >
Is a set of variable nodes,
Denotes the i-th element in the variable node set,
Denotes the j-th element from the i-th element in the variable node set, H denotes the parity generating matrix,
Lt;
The
And the i-th length of N denotes a subvector.
13. The method of claim 12,

Wherein the step (b) calculates a first parity using the parity intermediate variable in the case of l = 2, as in the following equation.

In the above equation, p 2, k is
Length according to
The permutation order vector.
14. The method of claim 13,

Wherein the step (c) computes a second parity bit according to the following equation.

In the above equation,
ego,
Lt;
ego,
, P l, k and q l, k are
Are permutation order vectors according to.
15. The method of claim 14,

Wherein the conditional summation is performed according to the following equation.
16. The method of claim 15,

The second parity bit
Is stored in a memory according to a permutation order vector q l, k .