WO2019107912A1 - Dispositif et procédé de codage ldpc présentant des caractéristiques de fiabilité élevée et de faible latence - Google Patents

Dispositif et procédé de codage ldpc présentant des caractéristiques de fiabilité élevée et de faible latence Download PDF

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Publication number
WO2019107912A1
WO2019107912A1 PCT/KR2018/014814 KR2018014814W WO2019107912A1 WO 2019107912 A1 WO2019107912 A1 WO 2019107912A1 KR 2018014814 W KR2018014814 W KR 2018014814W WO 2019107912 A1 WO2019107912 A1 WO 2019107912A1
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parity
bit
matrix
variable
accumulator
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PCT/KR2018/014814
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English (en)
Korean (ko)
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김광순
전기준
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연세대학교 산학협력단
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Priority claimed from KR1020180149579A external-priority patent/KR102067912B1/ko
Publication of WO2019107912A1 publication Critical patent/WO2019107912A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Definitions

  • the present invention relates to an LDPC coding method and apparatus, and more particularly, to an LDPC coding method and apparatus having low latency and high reliability characteristics.
  • fifth generation mobile communication requires more stringent reliability and low delay characteristics than conventional LDPC codes.
  • next generation sensor network it is necessary to transmit and receive a large amount of data in real time with low power without delay, and thus a code design capable of ensuring high reliability and capable of low complexity coding is needed.
  • LDPC codes include RU (Richardson-Urbanke) codes, RMA (Repeat Multiple Accumulate) codes, ARA (Accumulate Repeat Accumulate) codes and ARJA (Accumulate Repeat Jagged Accumulate) codes.
  • the RU code can be efficiently encoded, but the decoding threshold and the error floor characteristics are inferior, so that high reliability can not be guaranteed, and such a phenomenon has a problem in that the coding rate becomes worse as the coding rate becomes lower.
  • the RMA code can be efficiently encoded and has excellent error floor performance due to the linear minimum distance growth (LMDG) characteristic.
  • LMDG linear minimum distance growth
  • the ARA code has very good decoding threshold and low complexity coding, but it lacks the LMDG characteristic and has a problem of poor reliability due to poor error flooring characteristics.
  • ARJA code satisfies high decoding threshold and LMDG characteristics and guarantees high reliability, but coding complexity is large and there is a problem in low delay communication.
  • the present invention proposes an LDPC encoding apparatus and method suitable for low-delay communication due to low complexity while ensuring high reliability by satisfying LMDG characteristics.
  • the parity generation matrix is generated through lifting for an adjacent matrix obtained from a photograph, and in the lifting process, for a predetermined element of the adjacent matrix, Performs the operation, Is an operation for performing a left cyclic shift operation for i with respect to the identity matrix I, and performing zero masking for converting a column of the first row and ((Ni) N ) to zero.
  • the second parity operation unit comprises: a subvector accumulator for performing a subvector accumulation operation on the parity intermediate variable; A bit accumulator for performing a bit accumulation operation on the bits of the output of the sub-vector accumulator; A conditional summation unit for conditionally summing the output of the bit accumulator and the parity intermediate variable; And an accumulator for performing an accumulation operation on the output of the conditional summation unit.
  • the second parity operation unit calculates a second parity bit according to the following equation.
  • ego, Lt; ego, , P l, k and q l, k are Are permutation order vectors according to.
  • the conditional summation unit performs conditional summation as shown in the following equation.
  • the LDPC encoding apparatus and method according to an embodiment of the present invention are advantageous for low delay communication due to low complexity while ensuring high reliability by satisfying LMDG characteristics.
  • FIG. 1 is a photograph of an LDPC encoding apparatus and method according to an embodiment of the present invention
  • FIG. 2 illustrates an example of an adjacency matrix obtained from a photograph in accordance with an embodiment of the present invention.
  • FIG. 3 is a diagram illustrating an example of a parity generation matrix according to an embodiment of the present invention.
  • FIG. 4 is a diagram illustrating a structure of an LDPC encoding apparatus having low delay and high reliability characteristics according to an embodiment of the present invention.
  • FIG. 5 is a diagram illustrating an overall flow of an LDPC encoding method according to an embodiment of the present invention.
  • FIG. 6 illustrates elements of an adjacent matrix obtained from a photo graph of an LDPC encoding apparatus according to an embodiment of the present invention
  • FIG. 7 is a photograph showing the photograph of FIG. 6 more simply.
  • FIG. 1 is a diagram illustrating a photographed image of an LDPC encoding apparatus and method according to an embodiment of the present invention. Referring to FIG. 1
  • the present invention is based on the encoding apparatus and method of Korean Patent Application No. 2016-0036335 proposed and filed by the present inventor, and the content of the corresponding domestic patent application can be referred to for the understanding of the present invention,
  • the present invention relates to a specific coding method in an LDPC coding apparatus having a photograph structure as shown in FIG.
  • an LDPC encoding apparatus includes a first outer encoding module 300, a second outer encoding module 310, a first inner encoding module 320, (330).
  • first outer code part 400 showing the protocol connection state of the first outer encoding module 300
  • second outer code part 400 showing the protocol connection state of the second outer encoding module 310
  • a first inner code part 420 showing the protocol connection state of the first inner code module 320
  • a second inner code part 420 showing the protocol connection state of the second inner code module 330, (430) are shown.
  • the first outer encoding module 300 and the second outer encoding module 310 receive information bit streams for encoding. A part of the information bit stream is input to the first outer encoding module 300 and the remaining information bit stream is input to the second outer encoding module 310
  • the first outer encoding module 300 outputs a precoding bit stream for generating a parity bit stream using the input information bit stream.
  • the first outer encoding module 300 outputs a precoding bit string for generating a parity bit string through an accumulator operation.
  • the first outer encoding module 300 includes a plurality of variable nodes, a plurality of check nodes, and inter-node connection lines.
  • the leftmost variable nodes among the plurality of variable nodes are the nodes to which the information bit stream is input and the variable nodes on the right are the precoded parity bit streams from the information bit stream to the punctured variable nodes.
  • variable nodes and check nodes of the first outer encoding module 300 have a zigzag closed loop connection state of connection degree-2. As described above, when the accumulator-based encoding is performed through the connection structure of the accumulator, Lt; / RTI >
  • the second outer encoding module 310 receives the remaining information bit string that is not input to the first outer encoding module 300 and the output bit string of the first outer encoding module 300, It includes a number of variable nodes along with punctured variable nodes.
  • the second outer encoding module 310 performs repetition and replacement operations to obtain the encoding gain and the interleaving gain in the first inner encoding module 320 and the second inner encoding module 330.
  • variable nodes of the second outer encoding module 310 are connected to the check nodes of the first inner encoding module 320 and the second inner encoding module 330 to have a connection state of multiple connection degree closed loop.
  • the first outer coding module 300 and the second outer coding module 310 are connected to the first inner coding module 320 and the second inner coding module 330 and the output bits of the second outer coding module 310
  • the columns are input to the check nodes of the first inner encoding module 320 and the second inner encoding module 330.
  • the first inner encoding module 320 and the second inner encoding module 330 generate the final parity bit streams using the bit strings output from the second outer encoding modules 310.
  • the check nodes of the first inner encoding module 320 and the second inner encoding module 330 are connected to variable nodes of the second outer encoding module 310 and receive output bit strings.
  • the first internal encoding module 320 generates most of the parity bit streams through a single parity check operation. However, some of the parity bit streams of the first inner encoding module 320 are generated through a single parity check operation and an accumulator operation.
  • the first inner encoding module 320 can confirm that a check node and a part of a variable node have a connection line 425 having a connection degree-2, unlike the ARA code and the ARJA code,
  • the nodes connected through the connection lines output parity bit strings through a single parity check operation and an accumulator operation.
  • the first inner encoding module 320 outputs a parity bit sequence through a single parity check operation and an accumulator operation to a part of the parity bit string output from the second inner encoding module 330, And outputs a parity bit string.
  • a check node of the first internal encoding module 320 and a part of variable nodes of the second internal encoding module 430 are connected through an external connection line 450.
  • the second inner encoding module 330 outputs the parity bit sequences through the variable nodes using a single parity check operation and an accumulator operation on the bit strings input from the second outer encoding module 310.
  • the inner connection line of the first inner coding module 320 and the outer connection line between the second inner coding module 330 and the first inner coding module 320 in the LDPC code according to an embodiment of the present invention satisfy the LMDG characteristic .
  • the accumulator operation structure is maintained in the second inner encoding module 330, encoding can be performed with low complexity unlike the ARJA code.
  • the first inner encoding module 320 only a single parity check operation and an accumulator operation are performed, thereby enabling encoding with low complexity.
  • a part of the parity bit streams are sequentially output through a single parity check operation, and a part of the parity bit streams are output as part of the parity bit streams output from the second inner encoding module 430 And output through the accumulator operation.
  • FIG. 6 is a diagram illustrating a check node and a variable node obtained from a photo graph of an LDPC encoding apparatus according to an embodiment of the present invention
  • FIG. 7 is a simplified graph of the photo graph of FIG.
  • a node indicated by white is a punctured variable node
  • a node indicated by black is a variable node (information + parity) actually transmitted
  • a node including a cross is internally included It is a node that defines a check node and defines an operation between variable nodes.
  • variable nodes are classified into 0, 1, 2, 3, and 4, and check nodes are divided into 1, 2, 3, and 4.
  • a variable node divided by 0 corresponds to the information node.
  • the variable node is divided into five sections of 0 to 4
  • the check node is divided into four sections of 1 to 4.
  • FIG. 2 is a diagram illustrating an example of an adjacency matrix obtained from a photograph according to an exemplary embodiment of the present invention.
  • the adjacent matrix obtained from the base photo graph is also divided into four rows and five columns.
  • Index, and k is an index indicating the number of loops.
  • P l represents the number of loops in the lth section, .
  • the division structure of the adjacent matrix can be expressed by the following equation (1).
  • the adjacent matrix satisfies the following condition, and it is possible to perform RU (Richardson Urbanke) coding for each sub matrix to be described later when the following three conditions are satisfied.
  • Lt Represents the maximum degree of connection between the check node and the variable node.
  • Z + represents a natural number.
  • H &quot denotes the maximum column weight of the matrix A.
  • FIG. 3 is a diagram illustrating an example of a parity generation matrix according to an embodiment of the present invention.
  • the parity generation matrix is a matrix in which lifting is performed on an adjacent matrix as shown in FIG.
  • I i means a matrix in which the NXN identity matrix I is left cyclically shifted by i from 0 to N-1, and I -1 denotes an NXN zero matrix.
  • Means a modified cyclic shift operation which differs from existing lifting in that a modified cyclic shift operation is used for the operation of the adjacent matrix.
  • the lifted parity generation matrix H from the adjacent matrix also has a structure that can be divided into sections, .
  • a sub-matrix divided from the parity generation matrix (H) can be expressed as the following equation.
  • Equation (2) indicates that each sub-matrix constituting the parity generation matrix is RU-coded.
  • the RU encoding for each sub-matrix becomes possible when the condition for the adjacent matrix and the condition for the lifting operation are satisfied together as described above. It is mathematically provable that RU encoding is possible when the condition is satisfied.
  • the RU encoding is performed by T.J. Richardson and R.L. Urbanke, "Efficient encoding of low density parity check codes,” IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 638-656. Feb. 2001 and S.Myung, K. Yang, and J. Kim, "Quasi-cyclic LDPC codes for fast encoding,” IEEE Transactions on Information Theory, vol. 51, pp. 2894-2901, Aug. 2005, and the contents of these papers can be referred to in understanding RU encoding of the present invention.
  • FIG. 4 is a diagram illustrating a structure of an LDPC encoding apparatus having low-latency and high-reliability characteristics according to an embodiment of the present invention
  • FIG. 5 is a flowchart illustrating an overall operation of an LDPC encoding method according to an embodiment of the present invention
  • an LDPC encoder includes a controller 400, an information bit memory 402, a first parity memory 402, a second A parity-2 memory 406, a H memory, a first parity operation unit 410, and a second parity operation unit 412.
  • a code word to be encoded is stored in the information bit memory 402, and information on a parity generation matrix obtained from the photograph (see FIG. 1) is stored in the parity generation matrix memory 408.
  • the parity generation matrix has a structure divisible by sections (1), and each sub-matrix has a structure capable of RU encoding through lifting proposed in the present invention.
  • the first parity operation unit 410 computes a first parity using a parity generation matrix and a code word.
  • the calculated first parity is stored in the first parity memory 404.
  • the second parity operation unit 412 computes a second parity using the parity generation matrix and the value output from the first parity operation unit 410.
  • the calculated second parity is stored in the second parity memory.
  • the operations of the first parity operation unit 410 and the second parity operation unit 412 are performed only by a permutation operation, an accumulation operation and an add operation, This is because it is set to enable encoding.
  • the control unit 400 controls the overall operation of each element described above.
  • x i is defined as a partial binary code word column vector of length N, Lt; / RTI > Is a set of variable nodes.
  • Equation (3) xxx can be calculated as Equation (4).
  • Equation (4) is divided into (a) part and (b) part, and the present invention computes the parity bit corresponding to the codeword x part after (a)
  • the operation result of the part (a) is defined as a parity intermediate variable.
  • a parity intermediate variable is calculated using a parity generation matrix and a given codeword (step 500).
  • Lt Lt
  • N N-th sub-vector
  • the operation of the parity intermediate variable as shown in Equation (4) is performed in the first parity operation unit 410.
  • the first parity operation unit 410 includes a multiplexer 600, a left cyclic shift shifter 610, and an accumulator 620, and the operation of Equation (8) can be performed by only the above shifter and accumulator operation.
  • the parity bit may be calculated as Equation (6) using the parity intermediate variable to be computed.
  • the output first parity bit is stored in the first parity memory 404 (step 504).
  • the second parity operation unit 412 also computes a second parity bit using the parity intermediate variable computed by the first parity operation unit 410.
  • the second parity operation unit 412 includes a subvector accumulator 630 and a bit accumulator 640.
  • the subvector accumulator 630 performs the accumulation operation on the subvector using the parity intermediate variable xxxx, and the bit accumulator 640 performs the bit accumulation operation on the parity intermediate variable (step 506).
  • the second parity operation unit 412 includes a temporary memory 670 and stores the output bits of the conditional summation unit 660 in the temporary memory 670 according to the permutation order vector P l, k (step 510).
  • the second parity operation unit 412 includes an accumulator 680.
  • the accumulator 680 outputs a second parity bit through a predetermined accumulation operation on the bits stored in the temporary memory 670, The second parity bit is stored in the second parity memory 404 (step 512).
  • Equation (7) the operation of the second parity bit according to Equation (4) is performed as shown in Equation (7).
  • Equation (7) Is defined by the following equation (8).
  • the output of the second parity bit accumulator 640 is And the conditional summation of the FIFO 650 and the output of the bit accumulator 640 is to be.
  • the output of the conditional summation unit 660 Is stored in the temporary memory 670 according to p l, k , In the second parity memory 406 according to q l, k .
  • RU coding can be performed for each sub-matrix divided by sections in the parity generation matrix, and coding with low complexity can be performed with excellent error floor performance owing to this coding structure.
  • each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

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Abstract

L'invention concerne un dispositif et un procédé de codage LDPC qui présentent des caractéristiques de fiabilité élevée et de faible latence. Le dispositif de l'invention comprend : une unité de stockage de matrice de génération de parité servant à stocker une matrice de génération de parité qui peut être divisée selon la section (1) ; une première unité de calcul de bit de parité servant à calculer des variables intermédiaires de parité et un premier bit de parité si l=2 au moyen d'une opération de permutation et d'une opération d'accumulateur à l'aide de mots de code donnés et de la matrice de génération de parité ; et une seconde unité de calcul de bit de parité servant à calculer un second bit de parité à l'aide des variables intermédiaires de parité si l=1, 3 et 4, des sous-matrices divisées par section de la matrice de génération de parité étant des matrices réglées pour permettre un codage RU. Le dispositif et le procédé de l'invention satisfont des caractéristiques LMDG, ce qui leur permet d'être appropriés pour une communication à faible latence en raison d'une faible complexité tout en garantissant une fiabilité élevée.
PCT/KR2018/014814 2017-11-29 2018-11-28 Dispositif et procédé de codage ldpc présentant des caractéristiques de fiabilité élevée et de faible latence WO2019107912A1 (fr)

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KR10-2017-0161202 2017-11-29
KR20170161202 2017-11-29
KR10-2018-0149579 2018-11-28
KR1020180149579A KR102067912B1 (ko) 2017-11-29 2018-11-28 저지연 및 고신뢰도 특성을 가지는 ldpc 부호화 장치 및 방법

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090130183A (ko) * 2007-03-09 2009-12-18 콸콤 인코포레이티드 저밀도 패리티 체크(ｌｄｐｃ) 코드들의 인코딩 및 디코딩
KR20110123637A (ko) * 2010-05-07 2011-11-15 삼성전자주식회사 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서 채널 부호/복호 방법 및 장치
KR20130092441A (ko) * 2012-02-10 2013-08-20 연세대학교 산학협력단 복호화 장치 및 복호화 방법
KR20150121966A (ko) * 2014-04-22 2015-10-30 아주대학교산학협력단 저밀도 패리티 검사 코드의 복호화 방법 및 그 장치
KR101742430B1 (ko) * 2016-01-19 2017-05-31 연세대학교 산학협력단 고신뢰도 및 저지연 통신에 적합한 ldpc 부호화를 위한 장치 및 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090130183A (ko) * 2007-03-09 2009-12-18 콸콤 인코포레이티드 저밀도 패리티 체크(ｌｄｐｃ) 코드들의 인코딩 및 디코딩
KR20110123637A (ko) * 2010-05-07 2011-11-15 삼성전자주식회사 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서 채널 부호/복호 방법 및 장치
KR20130092441A (ko) * 2012-02-10 2013-08-20 연세대학교 산학협력단 복호화 장치 및 복호화 방법
KR20150121966A (ko) * 2014-04-22 2015-10-30 아주대학교산학협력단 저밀도 패리티 검사 코드의 복호화 방법 및 그 장치
KR101742430B1 (ko) * 2016-01-19 2017-05-31 연세대학교 산학협력단 고신뢰도 및 저지연 통신에 적합한 ldpc 부호화를 위한 장치 및 방법

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