KR101963725B1 - 자기 수정 코드에 하드웨어 지원을 제공하는 방법 및 장치 - Google Patents

자기 수정 코드에 하드웨어 지원을 제공하는 방법 및 장치 Download PDF

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KR101963725B1
KR101963725B1 KR1020167031653A KR20167031653A KR101963725B1 KR 101963725 B1 KR101963725 B1 KR 101963725B1 KR 1020167031653 A KR1020167031653 A KR 1020167031653A KR 20167031653 A KR20167031653 A KR 20167031653A KR 101963725 B1 KR101963725 B1 KR 101963725B1
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code
guest
cache
hardware buffer
processor
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KR20160145696A (ko
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모하매드 압달라
카시케얀 아부다이야판
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인텔 코포레이션
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
    • G06F9/45516—Runtime code conversion or optimisation
    • G06F9/45525—Optimisation or modification within the same instruction set architecture, e.g. HP Dynamo

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020167031653A 2014-05-12 2015-05-12 자기 수정 코드에 하드웨어 지원을 제공하는 방법 및 장치 Expired - Fee Related KR101963725B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201461991951P 2014-05-12 2014-05-12
US61/991,951 2014-05-12
PCT/US2015/030411 WO2015175555A1 (en) 2014-05-12 2015-05-12 Method and apparatus for providing hardware support for self-modifying code

Publications (2)

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KR20160145696A KR20160145696A (ko) 2016-12-20
KR101963725B1 true KR101963725B1 (ko) 2019-04-01

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US (1) US9946538B2 (enExample)
EP (1) EP3143496B1 (enExample)
JP (1) JP2017516228A (enExample)
KR (1) KR101963725B1 (enExample)
CN (1) CN106796506B (enExample)
WO (1) WO2015175555A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9436476B2 (en) 2013-03-15 2016-09-06 Soft Machines Inc. Method and apparatus for sorting elements in hardware structures
US9582322B2 (en) 2013-03-15 2017-02-28 Soft Machines Inc. Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping
US20140281116A1 (en) 2013-03-15 2014-09-18 Soft Machines, Inc. Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits
US9627038B2 (en) 2013-03-15 2017-04-18 Intel Corporation Multiport memory cell having improved density area
CN104679480A (zh) * 2013-11-27 2015-06-03 上海芯豪微电子有限公司 一种指令集转换系统和方法
KR101963725B1 (ko) 2014-05-12 2019-04-01 인텔 코포레이션 자기 수정 코드에 하드웨어 지원을 제공하는 방법 및 장치
US10176001B2 (en) * 2015-05-28 2019-01-08 Mitsubishi Electric Corporation Simulation device, simulation method, and computer readable medium
CN106933537B (zh) * 2016-04-20 2019-03-08 上海兆芯集成电路有限公司 侦测自修正程序码的处理器与方法
CN106919367B (zh) * 2016-04-20 2019-05-07 上海兆芯集成电路有限公司 侦测自修正程序码的处理器与方法
US9798675B1 (en) * 2016-04-20 2017-10-24 Via Alliance Semiconductor Co., Ltd. System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructions
CN106933538B (zh) * 2016-04-20 2019-03-01 上海兆芯集成电路有限公司 侦测自修正程序码的处理器与方法
US11193803B2 (en) 2018-02-02 2021-12-07 Analog Devices International Unlimited Company Measurement system
CN109890082B (zh) * 2019-03-08 2022-05-24 中国航空工业集团公司洛阳电光设备研究所 一种时间触发的tt帧报文传输方法
CN114416450B (zh) * 2022-01-18 2022-09-27 深圳市百泰实业股份有限公司 一种pcba生产测试管理方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080216073A1 (en) * 1999-01-28 2008-09-04 Ati International Srl Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US20120198157A1 (en) * 2011-01-27 2012-08-02 Soft Machines, Inc. Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor
US20140059262A1 (en) * 2012-08-21 2014-02-27 Lenovo (Singapore) Pte. Ltd. Task scheduling in big and little cores

Family Cites Families (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053952A (en) 1987-06-05 1991-10-01 Wisc Technologies, Inc. Stack-memory-based writable instruction set computer having a single data bus
US5630157A (en) 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
US5265260A (en) 1991-06-26 1993-11-23 International Business Machines Corporation High performance sort hardware for a database accelerator in a data processing system
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5826055A (en) 1991-07-08 1998-10-20 Seiko Epson Corporation System and method for retiring instructions in a superscalar microprocessor
JP3637920B2 (ja) 1992-05-01 2005-04-13 セイコーエプソン株式会社 スーパースケーラマイクロプロセサに於て命令をリタイアさせるシステム及び方法
IL110181A (en) 1994-06-30 1998-02-08 Softchip Israel Ltd Install microprocessor and peripherals
US5659721A (en) 1995-02-14 1997-08-19 Hal Computer Systems, Inc. Processor structure and method for checkpointing instructions to maintain precise state
US5751982A (en) 1995-03-31 1998-05-12 Apple Computer, Inc. Software emulation system with dynamic translation of emulated instructions for increased processing speed
US5870584A (en) 1995-09-20 1999-02-09 Fore Systems, Inc. Method and apparatus for sorting elements
US5826073A (en) * 1995-10-06 1998-10-20 Advanced Micro Devices, Inc. Self-modifying code handling system
US5784638A (en) 1996-02-22 1998-07-21 International Business Machines Corporation Computer system supporting control transfers between two architectures
US5892934A (en) 1996-04-02 1999-04-06 Advanced Micro Devices, Inc. Microprocessor configured to detect a branch to a DSP routine and to direct a DSP to execute said routine
JP2000507016A (ja) 1996-11-04 2000-06-06 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ メモリの命令を読み出す処理装置
US5905876A (en) 1996-12-16 1999-05-18 Intel Corporation Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
US6052777A (en) 1997-06-25 2000-04-18 Sun Microsystems, Inc. Method for delivering precise traps and interrupts in an out-of-order processor
US6049868A (en) 1997-06-25 2000-04-11 Sun Microsystems, Inc. Apparatus for delivering precise traps and interrupts in an out-of-order processor
JPH1124929A (ja) 1997-06-30 1999-01-29 Sony Corp 演算処理装置およびその方法
US5870575A (en) 1997-09-22 1999-02-09 International Business Machines Corporation Indirect unconditional branches in data processing system emulation mode
US6061785A (en) 1998-02-17 2000-05-09 International Business Machines Corporation Data processing system having an apparatus for out-of-order register operations and method therefor
US6167508A (en) 1998-06-02 2000-12-26 Compaq Computer Corporation Register scoreboard logic with register read availability signal to reduce instruction issue arbitration latency
US6412067B1 (en) 1998-08-11 2002-06-25 Intel Corporation Backing out of a processor architectural state
EP1151374B1 (en) * 1999-01-28 2017-08-02 Advanced Silicon Technologies, LLC Executing programs for a first computer architecture on a computer of a second architecture
US6385676B1 (en) 1999-07-12 2002-05-07 Hewlett-Packard Company Coherent ordering queue for computer system
US6363336B1 (en) * 1999-10-13 2002-03-26 Transmeta Corporation Fine grain translation discrimination
US6557095B1 (en) 1999-12-27 2003-04-29 Intel Corporation Scheduling operations using a dependency matrix
US6615300B1 (en) 2000-06-19 2003-09-02 Transmeta Corporation Fast look-up of indirect branch destination in a dynamic translation system
US6711672B1 (en) 2000-09-22 2004-03-23 Vmware, Inc. Method and system for implementing subroutine calls and returns in binary translation sub-systems of computers
US6826681B2 (en) 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
US6851011B2 (en) 2001-08-09 2005-02-01 Stmicroelectronics, Inc. Reordering hardware for mass storage command queue
US6964043B2 (en) 2001-10-30 2005-11-08 Intel Corporation Method, apparatus, and system to optimize frequently executed code and to use compiler transformation and hardware support to handle infrequently executed code
US20030115578A1 (en) * 2001-12-18 2003-06-19 Igor Liokumovich PC platform simulation system employing efficient memory access simulation in a direct execution environment
US6813704B1 (en) 2001-12-20 2004-11-02 Lsi Logic Corporation Changing instruction order by reassigning only tags in order tag field in instruction queue
US6898699B2 (en) 2001-12-21 2005-05-24 Intel Corporation Return address stack including speculative return address buffer with back pointers
US7032101B2 (en) 2002-02-26 2006-04-18 International Business Machines Corporation Method and apparatus for prioritized instruction issue queue in a processor
US7113510B2 (en) 2002-03-01 2006-09-26 Xinming Allen Lin Hardware self-sorting scheduling queue
US6779092B2 (en) 2002-05-15 2004-08-17 Hewlett-Packard Development Company, L.P. Reordering requests for access to subdivided resource
US7127592B2 (en) 2003-01-08 2006-10-24 Sun Microsystems, Inc. Method and apparatus for dynamically allocating registers in a windowed architecture
GB0309056D0 (en) 2003-04-22 2003-05-28 Transitive Technologies Ltd Block translation optimizations for program code conversion
US7536682B2 (en) 2003-04-22 2009-05-19 International Business Machines Corporation Method and apparatus for performing interpreter optimizations during program code conversion
JP4186768B2 (ja) 2003-09-16 2008-11-26 沖電気工業株式会社 マルチポート半導体メモリ
US7096345B1 (en) 2003-09-26 2006-08-22 Marvell International Ltd. Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof
US7290253B1 (en) 2003-09-30 2007-10-30 Vmware, Inc. Prediction mechanism for subroutine returns in binary translation sub-systems of computers
US7373637B2 (en) 2003-09-30 2008-05-13 International Business Machines Corporation Method and apparatus for counting instruction and memory location ranges
US7315935B1 (en) 2003-10-06 2008-01-01 Advanced Micro Devices, Inc. Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots
US7441101B1 (en) 2003-12-10 2008-10-21 Cisco Technology, Inc. Thread-aware instruction fetching in a multithreaded embedded processor
US7434031B1 (en) 2004-04-12 2008-10-07 Sun Microsystems, Inc. Execution displacement read-write alias prediction
US8443171B2 (en) 2004-07-30 2013-05-14 Hewlett-Packard Development Company, L.P. Run-time updating of prediction hint instructions
US7647589B1 (en) * 2005-02-07 2010-01-12 Parallels Software International, Inc. Methods and systems for safe execution of guest code in virtual machine context
US8195922B2 (en) 2005-03-18 2012-06-05 Marvell World Trade, Ltd. System for dynamically allocating processing time to multiple threads
US7461237B2 (en) 2005-04-20 2008-12-02 Sun Microsystems, Inc. Method and apparatus for suppressing duplicative prefetches for branch target cache lines
JP4912016B2 (ja) 2005-05-23 2012-04-04 ルネサスエレクトロニクス株式会社 半導体記憶装置
US20070033385A1 (en) 2005-08-02 2007-02-08 Advanced Micro Devices, Inc. Call return stack way prediction repair
US7483332B2 (en) 2005-08-11 2009-01-27 Texas Instruments Incorporated SRAM cell using separate read and write circuitry
US8024522B1 (en) 2005-09-28 2011-09-20 Oracle America, Inc. Memory ordering queue/versioning cache circuit
US20070186081A1 (en) 2006-02-06 2007-08-09 Shailender Chaudhry Supporting out-of-order issue in an execute-ahead processor
WO2007091541A1 (ja) 2006-02-08 2007-08-16 Renesas Technology Corp. 半導体記憶装置
US7478190B2 (en) 2006-02-10 2009-01-13 University Of Utah Technology Commercialization Office Microarchitectural wire management for performance and power in partitioned architectures
US20080126771A1 (en) 2006-07-25 2008-05-29 Lei Chen Branch Target Extension for an Instruction Cache
US7716460B2 (en) 2006-09-29 2010-05-11 Qualcomm Incorporated Effective use of a BHT in processor having variable length instruction set execution modes
US8677105B2 (en) 2006-11-14 2014-03-18 Soft Machines, Inc. Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines
US7721076B2 (en) 2006-12-18 2010-05-18 Intel Corporation Tracking an oldest processor event using information stored in a register and queue entry
US7783869B2 (en) 2006-12-19 2010-08-24 Arm Limited Accessing branch predictions ahead of instruction fetching
TW200833002A (en) 2007-01-31 2008-08-01 Univ Nat Yunlin Sci & Tech Distributed switching circuit having fairness
US7813163B2 (en) 2007-09-05 2010-10-12 International Business Machines Corporation Single-ended read and differential write scheme
TWI346338B (en) 2007-10-23 2011-08-01 Nat Univ Tsing Hua Access unit for a static random accesss memory
US8782384B2 (en) 2007-12-20 2014-07-15 Advanced Micro Devices, Inc. Branch history with polymorphic indirect branch information
US7945764B2 (en) 2008-01-11 2011-05-17 International Business Machines Corporation Processing unit incorporating multirate execution unit
US8015362B2 (en) 2008-02-15 2011-09-06 International Business Machines Corporation Method and system for handling cache coherency for self-modifying code
TWI368165B (en) 2008-08-13 2012-07-11 Faraday Tech Corp Processor and method for recovering global history shift register and return address stack thereof
GB2463278B (en) 2008-09-05 2012-05-16 Advanced Risc Mach Ltd Scheduling control within a data processing system
US7848131B2 (en) 2008-10-19 2010-12-07 Juhan Kim High speed ferroelectric random access memory
US8074060B2 (en) 2008-11-25 2011-12-06 Via Technologies, Inc. Out-of-order execution microprocessor that selectively initiates instruction retirement early
US8219784B2 (en) 2008-12-09 2012-07-10 International Business Machines Corporation Assigning and pre-decoding group ID and tag ID prior to dispatching instructions in out-of-order processor
US8078854B2 (en) 2008-12-12 2011-12-13 Oracle America, Inc. Using register rename maps to facilitate precise exception semantics
US8332854B2 (en) 2009-05-19 2012-12-11 Microsoft Corporation Virtualized thread scheduling for hardware thread optimization based on hardware resource parameter summaries of instruction blocks in execution groups
US8799879B2 (en) * 2009-06-30 2014-08-05 Oracle America, Inc. Method and apparatus for protecting translated code in a virtual machine
US8281110B2 (en) 2009-07-15 2012-10-02 Via Technologies, Inc. Out-of-order microprocessor with separate branch information circular queue table tagged by branch instructions in reorder buffer to reduce unnecessary space in buffer
US8217813B2 (en) 2010-04-29 2012-07-10 Advanced Micro Devices, Inc. System and method for low-latency data compression/decompression
CN102262590B (zh) 2010-05-31 2014-03-26 国际商业机器公司 一种用于对硬件加速器的请求队列重排的方法和系统
US8959094B2 (en) 2010-05-28 2015-02-17 Oracle International Corporation Early return of partial sort results in a database system
US20110320784A1 (en) * 2010-06-24 2011-12-29 International Business Machines Corporation Verification of processor architectures allowing for self modifying code
US20120117335A1 (en) 2010-11-10 2012-05-10 Advanced Micro Devices, Inc. Load ordering queue
WO2012103367A2 (en) * 2011-01-27 2012-08-02 Soft Machines, Inc. Guest to native block address mappings and management of native code storage
US8516197B2 (en) * 2011-02-11 2013-08-20 International Business Machines Corporation Write-through cache optimized for dependence-free parallel regions
KR101620676B1 (ko) 2011-03-25 2016-05-23 소프트 머신즈, 인크. 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 레지스터 파일 세그먼트
US9690583B2 (en) 2011-10-03 2017-06-27 International Business Machines Corporation Exploiting an architected list-use operand indication in a computer system operand resource pool
CN105122206B (zh) 2013-03-15 2018-11-09 英特尔公司 用于支持推测的访客返回地址栈仿真的方法和装置
US9582322B2 (en) 2013-03-15 2017-02-28 Soft Machines Inc. Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping
US20140281116A1 (en) 2013-03-15 2014-09-18 Soft Machines, Inc. Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9627038B2 (en) 2013-03-15 2017-04-18 Intel Corporation Multiport memory cell having improved density area
US9436476B2 (en) 2013-03-15 2016-09-06 Soft Machines Inc. Method and apparatus for sorting elements in hardware structures
KR101963725B1 (ko) 2014-05-12 2019-04-01 인텔 코포레이션 자기 수정 코드에 하드웨어 지원을 제공하는 방법 및 장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080216073A1 (en) * 1999-01-28 2008-09-04 Ati International Srl Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US20120198157A1 (en) * 2011-01-27 2012-08-02 Soft Machines, Inc. Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor
US20140059262A1 (en) * 2012-08-21 2014-02-27 Lenovo (Singapore) Pte. Ltd. Task scheduling in big and little cores

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EP3143496A4 (en) 2018-01-24
JP2017516228A (ja) 2017-06-15
WO2015175555A1 (en) 2015-11-19
US20150324213A1 (en) 2015-11-12
CN106796506A (zh) 2017-05-31
KR20160145696A (ko) 2016-12-20
US9946538B2 (en) 2018-04-17
EP3143496A1 (en) 2017-03-22
CN106796506B (zh) 2019-09-27
EP3143496B1 (en) 2021-07-14

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