KR101960887B1 - Apparatus for measuring temperature - Google Patents

Abstract

The present invention relates to an apparatus for measuring temperature using a clock signal. A temperature measuring apparatus according to the present invention includes: a temperature sensing unit for delaying an external clock signal according to an ambient temperature to output a delayed clock signal; A signal modulator for outputting the external clock signal and an output signal activated in response to the delayed clock signal; And a temperature calculation unit for calculating the ambient temperature in response to whether the output signal is active or not.

Description

Apparatus for measuring temperature < RTI ID = 0.0 >

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a temperature measuring apparatus, and more particularly to an apparatus for measuring temperature using a clock signal.

A thermometer is required to measure the temperature. Since a typical thermometer is mechanically structured and bulky, it is difficult to use for small or bulky products. Recently, many devices for measuring temperature using an electric circuit have been developed.

In the case of a time domain thermometer using electrical signals, the method of measuring the temperature difference is different, but the temperature measuring method is similar. That is, the delay difference generated through the TDD (Temperature Dependent Delay Line), which causes a delay depending on the temperature, is used based on the TIDL (Temperature Independent Delay Line) in which no delay occurs even when the temperature changes.

For example, there is a general time-domain thermometer and a circuit in which an additional bias circuit is additionally required in the inverter chain of the TDDL. Since the temperature measuring apparatuses of these two methods differ in the method of obtaining the temperature, the form of the information about the required temperature is also different. In order to measure these temperatures, a delay line (corresponding to TDDL) whose delay varies with temperature and a delay line (corresponding to TIDL) whose delay does not vary with temperature are used.

As described above, in the conventional temperature measuring apparatus, temperature is measured by comparing with TDDL by additionally using a separate TIDL circuit when measuring the temperature.

The present invention provides an apparatus for measuring temperature using a clock signal having a periodic pulse without using a Temperature Independent Delay Line (TIDL).

According to an aspect of the present invention,

A temperature sensing unit for delaying an external clock signal according to a temperature to output a delayed clock signal; A signal modulator for receiving the external clock signal and the delayed clock signal and determining whether the output signal is active according to a delay of the delayed clock signal; And a temperature calculation unit that receives the signal output from the signal modulation unit and calculates an ambient temperature of the temperature sensing unit.

The temperature sensing unit may delay the output clock signal much when the ambient temperature rises, and may delay the output clock signal when the ambient temperature falls.

The temperature calculator may calculate the ambient temperature by counting the number at which the signal output from the signal modulator is activated.

Wherein the signal modulator inputs the clock signal, the delayed clock signal, and the output signal of the signal modulator, outputs a falling signal when the output signal of the signal modulator is in an active state, a signal size setting unit for outputting a rising signal when inactive; A capacitor; A charge pump connected between the capacitor and the signal size setting unit and adjusting a voltage applied to the capacitor according to a signal output from the signal size setting unit; And an output signal generator for generating an output signal of the signal modulator by comparing the voltage of the capacitor with a reference voltage.

Wherein the signal size setting unit outputs a rising signal having a pulse width corresponding to the delay time of the delayed clock signal when the output signal of the signal modulating unit is in an inactive state, It is possible to output a falling signal having a pulse width obtained by subtracting the delay time of the delayed clock signal from the pulse width of the clock signal.

The charge pump may charge the capacitor when the rising signal is output from the signal size setting unit and may discharge the voltage of the capacitor when the falling signal is output from the signal size setting unit.

The output signal generator may activate the output signal of the signal modulator if the voltage of the capacitor is higher than the reference voltage and inactivate the output signal of the signal modulator if the voltage of the capacitor is lower than the reference voltage.

Wherein the signal size setting unit receives the external clock signal, the delayed clock signal, the output signal of the signal modulating unit, and a reset signal, and outputs, when the reset signal is active, A rising signal generating unit for outputting an inactive rising signal in response to an output signal of the modulation unit and for resetting the rising signal when the reset signal is inactive; And a control unit for receiving the external clock signal, the delayed clock signal, the output signal of the signal modulator, and the reset signal, and when the reset signal is active and the output signal of the signal modulator and the external clock signal are active, And a falling signal generator for activating a falling signal in response to the delayed clock signal and inactive in response to an output signal of the signal modulating unit and resetting the falling signal when the reset signal is inactive.

Wherein the rising signal generating unit comprises: a NOR gate for receiving an inverted signal of the external clock signal and the delayed clock signal, and performing NOR operation on the inverted signal and the delayed clock signal; A first AND gate for receiving an output signal of the NOR gate and the reset signal and logically multiplying them; And an output signal of the first AND gate and an output signal of the signal modulator and a ground voltage and outputs one of the output signal of the first AND gate and the ground voltage in response to the output signal of the signal modulator A first multiplexer; And a first buffer for buffering the output signal of the first multiplexer and outputting the rising signal.

Wherein the falling signal generator comprises: a second AND gate for receiving the external clock signal and the delayed clock signal and logically multiplying them; A third AND gate for receiving the output signal of the second AND gate and the reset signal and logically multiplying them; And an output signal of the third AND gate and an output signal of the signal modulator and the ground voltage and outputs one of the output signal of the third AND gate and the ground voltage in response to the output signal of the signal modulator Gt; And a second buffer for buffering the output signal of the second multiplexer and outputting the falling signal.

The temperature measuring apparatus according to the present invention can measure the temperature using a clock signal which is generally used without using a temperature independent delay line (TIDL).

As described above, since the temperature measuring apparatus according to the present invention does not use the TIDL, the area of the circuit is greatly reduced and the power consumption is also greatly reduced.

1 is a block diagram of a temperature measuring apparatus according to a preferred embodiment of the present invention.
2 is a detailed block diagram of the signal modulation unit shown in FIG.
3 is a circuit diagram of the signal size setting unit shown in FIG.
Fig. 4 is a timing diagram of the signals shown in Figs. 1 to 3. Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. Like reference numerals in the drawings denote like elements.

1 is a block diagram of a temperature measuring apparatus according to a preferred embodiment of the present invention. Referring to FIG. 1, the temperature measuring apparatus 101 includes a temperature sensing unit 110, a signal modulating unit 120, and a temperature calculating unit 130.

The temperature sensing unit 110 delays the external clock signal CLK according to the temperature to output a delayed clock signal SEN. That is, when the ambient temperature rises, the temperature sensing unit 110 outputs the delayed clock signal SEN in a state in which the external clock signal CLK is greatly delayed. When the ambient temperature falls, the temperature sensing unit 110 outputs the external clock signal CLK And outputs the delayed clock signal SEN with a small delay. Thus, the delay time of the delayed clock signal SEN is determined according to the ambient temperature of the temperature sensing unit 110. In other words, the delay time of the delayed clock signal SEN becomes longer when the ambient temperature of the temperature sensing unit 110 rises, and becomes shorter when the ambient temperature of the temperature sensing unit 110 falls. The temperature sensing unit 110 may be one of a temperature sensing unit, a temperature sensing integrated circuit unit, and a temperature sensing circuit.

The signal modulator 120 is connected to the temperature sensing unit 110. The signal modulator 120 receives the external clock signal CLK and the delayed clock signal SEN output from the temperature sensing unit 110. The signal modulator 120 determines whether the output signal OUT is active according to the delay of the delayed clock signal SEN and outputs the output signal OUT. That is, when the delay time of the delayed clock signal SEN is long, the signal modulator 120 increases the number of times the output signal OUT is activated, and when the delay time of the delayed clock signal SEN becomes short, the output signal OUT ) Is activated. The output signal OUT of the signal modulator 120 is generated, for example, as a pulse when it is activated. Accordingly, the output signal OUT of the signal modulator 120 increases the number of pulses of the output signal OUT when the ambient temperature of the temperature sensing unit 110 rises, and decreases when the ambient temperature of the temperature sensing unit 110 falls The pulse number of the output signal OUT is reduced. The configuration of the signal modulator 120 will be described in more detail with reference to FIG.

The temperature calculating unit 130 receives the signal output from the signal modulating unit 120 and calculates the ambient temperature of the temperature sensing unit 110. The temperature calculation unit 130 may include a counter. Accordingly, the temperature calculator 130 counts the number of pulses, that is, the number of pulses, in which the signal output from the signal modulator 120 is activated, using the counter. The temperature calculating unit 130 determines that the ambient temperature of the temperature sensing unit 110 is high when the number of pulses of the signal output from the signal modulating unit 120 increases and outputs the pulse of the signal output from the signal modulating unit 120 If the number is decreased, it is determined that the ambient temperature of the temperature sensing unit 110 is low. The temperature calculation unit 130 can accurately measure the ambient temperature of the temperature sensing unit 110 by converting the pulse number of the signal output from the signal modulation unit 120 to a temperature. The method of converting the pulse number of the output signal OUT of the signal modulator 120 to the temperature by the temperature calculator 130 may be a generally known method, and a detailed description thereof will be omitted. A reset signal RE is applied to the temperature calculation unit 130. [ When the reset signal RE is activated, the temperature calculating unit 130 resets, deletes all of the temperature-related data calculated previously, and starts a new count to calculate the temperature. That is, every time the temperature is measured, the reset signal RE is activated and the temperature calculating unit 130 is reset.

2 is a detailed block diagram of the signal modulator 120 shown in FIG. 2, the signal modulator 120 includes a signal size setting unit 122, a capacitor 126, a charge pump 124, and an output signal generator 128 .

The signal size setting unit 122 receives the external clock signal CLK and the delayed clock signal SEN and the output signal OUT of the signal modulation unit 120 and outputs the rising signal UP or the falling signal DN Output. The signal size setting unit 122 outputs the falling signal DN when the output signal OUT of the signal modulator 120 is active and outputs the falling signal DN when the output signal OUT of the signal modulator 120 is inactive inactive state, it outputs a rising signal UP. The rising signal UP and the falling signal DN are determined according to the delay time of the delayed clock signal SEN. That is, the rising signal UP is generated as a signal having a pulse width corresponding to the delay time of the delayed clock signal SEN when the output signal OUT of the signal modulator 120 is in the inactive state, The signal DN is generated as a signal having a pulse width obtained by subtracting the delay time of the delayed clock signal SEN from the pulse width of the external clock signal CLK when the output signal OUT of the signal modulation unit 120 is active .

3, when the output signal OUT of the signal modulator 120 is in an inactive state as a logic low, the rising signal UP is a logic high signal when the external clock signal CLK is at a logic high level. (logic high). < / RTI > Then, when the delay clock signal SEN rises to a logic high, the rising signal UP transitions to a logic low. Thus, the rising signal UP is generated as one pulse signal.

The falling signal DN is activated when the external clock signal CLK is active as a logic high when the output signal OUT of the signal modulator 120 is active as a logic high and then the delayed clock signal SEN is logic It is generated as a logic high when activated as high. And then transitions to a logic low when the external clock signal CLK is inactive as a logic low. Accordingly, the falling signal DN is generated as one pulse signal.

Thus, the pulse width of the rising signal UP becomes longer when the delay time of the delayed clock signal SEN is longer, and becomes shorter when the delay time of the delayed clock signal SEN is shorter. Conversely, the pulse width of the falling signal DN becomes shorter when the delay time of the delayed clock signal SEN is longer, and becomes longer when the delay time of the delayed clock signal SEN is shorter.

The capacitor 126 is connected between the charge pump 124 and the output signal generator 128 and charges or discharges the voltage Vcap.

The charge pump 124 is connected between the capacitor 126 and the signal size setting section 122. The charge pump 124 adjusts the voltage Vcap of the capacitor 126 according to the signal output from the signal size setting unit 122. [ That is, the charge pump 124 charges the capacitor 126 with the voltage Vcap when the rising signal UP is outputted from the signal size setting unit 122, and outputs the falling signal DN from the signal size setting unit 122, The voltage Vcap of the capacitor 126 is discharged. Accordingly, the capacitor 126 has a longer charging time as the pulse width of the rising signal UP is larger, and a longer discharging time as the pulse width of the falling signal DN is wider. In other words, the capacitor 126 has a longer charging time as the ambient temperature of the temperature sensing part 110 is higher, and a longer discharge time as the ambient temperature of the temperature sensing part 110 is lower. As the charging time of the capacitor 126 becomes longer, the voltage Vcap of the capacitor becomes higher and the voltage Vcap of the capacitor becomes lower as the charging time of the capacitor 126 becomes shorter.

The output signal generating unit 128 is connected to the capacitor 126 and receives the reference voltage Vref and generates the output signal OUT of the signal modulating unit 120. The output signal generator 128 compares the voltage Vcap of the capacitor 126 with the reference voltage Vref and outputs the output signal OUT of the signal modulator 120 according to the result. For example, the output signal generator 128 activates the output signal OUT of the signal modulator 120 as a logic high signal when the voltage Vcap of the capacitor 126 is higher than the reference voltage Vref, The output signal OUT of the signal modulator 120 is inactivated by a logic low when the voltage Vcap of the signal modulator 120 is lower than the reference voltage Vref.

The output signal generating unit 128 can operate in synchronization with the external clock signal CLK. The output signal generator 128 checks the voltage Vcap of the capacitor 126 at the rising edge of the external clock signal CLK and outputs the output signal OUT of the signal modulator 120 accordingly, . For example, when the voltage Vcap of the capacitor 126 is higher than the reference voltage Vref at the rising edge of the external clock signal CLK, the output signal generator 128 outputs the output signal OUT of the signal modulator 120 And makes the output signal OUT of the signal modulator 120 logically low when the voltage Vcap of the capacitor 126 is lower than the reference voltage Vref at the rising edge of the external clock signal CLK Inactive.

As described above, the output signal OUT of the signal modulator 120 becomes active when the delay time of the delayed clock signal SEN becomes long, that is, when the ambient temperature of the temperature sensing unit 110 becomes high, And becomes inactive as a logic low when the delay time of the delayed clock signal SEN becomes short, that is, when the ambient temperature of the temperature sensing unit 110 becomes low. The frequency of occurrence of the output signal OUT of the signal modulator 120 increases as the ambient temperature of the temperature sensor 110 increases and decreases as the ambient temperature of the temperature sensor 110 decreases .

3 is a circuit diagram of the signal size setting unit 122 shown in FIG. Referring to FIG. 3, the signal size setting unit 122 includes a rising signal generating unit 301 and a falling signal generating unit 302.

The rising signal generating section 301 receives the external clock signal CLK, the delayed clock signal SEN, the output signal OUT of the signal modulating section and the reset signal RE and outputs the rising signal UP . The rising signal generating unit 301 outputs a rising signal UP having a pulse width corresponding to the delay time of the delayed clock signal SEN. That is, the rising signal generating unit 301 outputs an inactive rising signal in response to the external clock signal CLK in response to the reset signal RE and in response to the output signal OUT of the signal modulating unit , And resets the rising signal UP when the reset signal RE is inactive. The rising signal generating unit 301 includes a NOR gate 311, a first AND gate 313, a first multiplexer 315, and a first buffer 317.

The NOR gate 311 receives the external clock signal CLK and the delayed clock signal SEN, performs NOR operation on the signals, and outputs the result. That is, the NOR gate 311 outputs the external clock signal CLK as it is when the delayed clock signal SEN is logic low. If the delayed clock signal SN is logic high, And outputs a logic low regardless of the signal CLK. The NOR gate 311 has an inverter 311a for inverting the external clock signal CLK and a NOR gate 311b for inputting the delayed clock signal SEN and the output signal of the inverter 311a.

The first AND gate 313 receives the output signal of the NOR gate 311 and the reset signal RE. Therefore, the first AND gate 313 outputs the output signal of the NOR gate 311 as it is if the reset signal RE is logic high, and outputs the output signal of the NOR gate 311 when the reset signal RE is logic low. And outputs a logic low signal irrespective of the output signal. The first AND gate 313 includes a NAND gate 313a for inputting the output signal of the NOR gate 311 and the reset signal RE and an inverter 313b for inverting the output signal of the NAND gate 313a, Respectively.

The first multiplexer 315 receives the output signal of the first AND gate 313, the ground voltage GND, and the output signal OUT of the signal modulator. The first multiplexer 315 outputs the output signal of the first AND gate 313 when the output signal OUT of the signal modulator is logic low and the output signal OUT of the signal modulator outputs a ground voltage GND ).

The first buffer 317 buffers an output signal of the first multiplexer 315 and outputs a rising signal UP. The first buffer 317 has two serially connected inverters 317a and 317b.

The falling signal generating unit 302 receives the external clock signal CLK, the delayed clock signal SEN, the output signal OUT of the signal modulating unit, and the reset signal RE and outputs the falling signal DN. The falling signal generating unit 302 outputs a falling signal having a pulse width obtained by subtracting the delay time of the delayed clock signal SEN from the pulse width of the external clock signal CLK. That is, the falling signal generating unit 302 activates the falling signal in response to the delayed clock signal, in a state in which the reset signal is active and the output signal of the signal modulating unit and the external clock signal are active, Inactive in response to an output signal, and resets the falling signal when the reset signal is inactive. The falling signal generating unit 302 includes second and third AND gate gates 321 and 323, a second multiplexer 325, and a second buffer 327.

The second AND gate 321 receives the external clock signal CLK and the delayed clock signal SEN. The second AND gate 321 outputs the external clock signal CLK as it is when the delayed clock signal SEN is logic high and outputs the external clock signal CLK when the delayed clock signal SEN is logic low, And outputs a logic low signal without the logic low signal. The second AND gate 321 has a NAND gate 321a for inputting the external clock signal CLK and the delayed clock signal SEN and an inverter 321b for inverting the output signal of the NAND gate 321a do.

The third AND gate 323 receives the output signal of the second AND gate 321 and the reset signal RE. Thus, the third AND gate 323 outputs the output signal of the second AND gate 321 as it is when the reset signal RE is logic high, and outputs the output signal of the second AND gate 322 when the reset signal RE is logic low. And outputs a logic low signal irrespective of the output signal of the signal processing circuit 321. The third AND gate 323 includes a NAND gate 323a for inputting an output signal of the second AND gate 321 and a reset signal RE and an inverter for inverting the output signal of the NAND gate 323a 323b.

The second multiplexer 325 inputs the ground voltage GND, the output signal of the third AND gate 323, and the output signal OUT of the signal modulator. The second multiplexer 325 outputs the ground voltage GND when the output signal OUT of the signal modulator is logic low and the output of the third AND gate 323 when the output signal OUT of the signal modulator is logic high. And outputs a signal.

The second buffer 327 buffers the output signal of the second multiplexer 325 and outputs a down signal DN. The second buffer 327 has two serially connected inverters 327a and 327b.

Hereinafter, with reference to Fig. 4, the operation of measuring the temperature by the temperature measuring apparatus 101 of the present invention shown in Figs. 1 to 3 will be described.

The output signal OUT of the signal modulator 120 is held in the inactive state at a logic low before the external clock signal CLK is initially applied.

When the external clock signal CLK is input to the temperature sensing unit 110, the temperature sensing unit 110 senses the ambient temperature, delays the external clock signal CLK according to the sensed ambient temperature, and outputs the delayed clock signal SEN ). That is, the delayed clock signal SEN is output after a predetermined time delay as compared with the external clock signal CLK as a result of the temperature sensed by the temperature sensing unit 110 being reflected. That is, it has a delay time of a predetermined length as shown in Fig. The delay clock signal SEN is applied to the signal size setting unit 122. [

The signal size setting unit 122 receives the external clock signal CLK, the delayed clock signal SEN, and the output signal OUT of the signal modulation unit 120. The signal size setting unit 122 outputs the rising signal UP since the output signal OUT of the signal modulation unit 120 is in the inactive state. At this time, the rising signal UP has a pulse width corresponding to the delay time of the delayed clock signal SEN. For example, when the external clock signal CLK rises to a logic high level, the signal size setting unit 122 generates a rising signal UP having a logic high level accordingly. Then, when the delayed clock signal SEN rises to a logic high level, the signal size setting unit 122 lowers the rising signal UP to a logic low level. Therefore, the rising signal UP has a pulse width corresponding to the delay time of the delayed clock signal SEN.

As the rising signal UP occurs, the charge pump 124 charges the capacitor 126 with the voltage Vcap. Therefore, the voltage Vcap of the capacitor 126 becomes higher than before.

The output signal generating unit 128 compares the voltage Vcap of the capacitor 126 with the reference voltage Vref to generate the output signal OUT. When the voltage Vcap of the capacitor 126 increases and becomes larger than the reference voltage Vref, the output signal generating unit 128 outputs the output signal OUT of the signal modulating unit 120 in an active state, And outputs it.

As described above, when the output signal OUT of the signal modulator 120 is activated, the operation of the signal size setting unit 122 is different from that before. Specifically, the following description will be given.

The signal size setting unit 122 outputs the falling signal DN since the output signal OUT of the signal modulator 120 is in an active state. At this time, the falling signal DN has a pulse width corresponding to a time obtained by subtracting the delay time of the delayed clock signal SEN from the external clock signal CLK. For example, when the delay clock signal SEN rises to a logic high level, the signal size setting unit 122 generates a falling signal DN having a logic high level accordingly. Then, when the external clock signal CLK falls to a logic low level, the signal size setting unit 122 lowers the falling signal DN to a logic low level. Therefore, the falling signal DN has a pulse width corresponding to a time obtained by subtracting the delay time of the delayed clock signal SEN from the external clock signal CLK.

As the falling signal DN is generated, the charge pump 124 discharges the voltage Vcap of the capacitor 126. Therefore, the voltage Vcap of the capacitor 126 becomes smaller than before.

The output signal generating unit 128 compares the voltage Vcap of the capacitor 126 with the reference voltage Vref to generate the output signal OUT. If the voltage Vcap of the capacitor 126 decreases and becomes lower than the reference voltage Vref, the output signal generating unit 128 outputs the output signal OUT of the signal modulating unit 120 in an inactive state, Make it low level and output.

Although the present invention has been described with reference to the embodiments shown in the drawings, it is to be understood that various modifications and equivalent embodiments may be made by those skilled in the art without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (10)

A temperature sensing unit for receiving the external clock signal and outputting the delayed clock signal by delaying the external clock signal by a delay time determined according to the ambient temperature;
A signal modulator for outputting an external clock signal and an output signal active in response to the delayed clock signal; And
And a temperature calculation unit for calculating the ambient temperature in response to whether the output signal is active,
Wherein the signal modulator comprises:
Generating a rising signal having a first pulse width in an inactive state of the output signal and generating a falling signal having a second pulse width in an active state of the output signal, A signal size setting unit corresponding to the delay time and the second pulse width corresponding to a time obtained by subtracting the delay time from a pulse width of the external clock signal;
A charge pump for supplying a voltage for the delay time corresponding to the first pulse width when the rising signal is inputted and supplying a ground voltage for the time corresponding to the second pulse width when the falling signal is inputted;
A capacitor charging the charge when the voltage is supplied from the charge pump and discharging the charge when the ground voltage is supplied; And
Comparing the voltage of the capacitor with a reference voltage and activating the output signal when the voltage of the capacitor is higher than the reference voltage and outputting the output signal to inactivate the output signal when the voltage of the capacitor is lower than the reference voltage. And a generating unit for generating a temperature signal. The apparatus of claim 1, wherein the temperature sensing unit
Wherein the control unit increases the delay amount of the external clock signal when the ambient temperature rises and decreases the delay amount of the external clock signal when the ambient temperature falls, and outputs the delayed clock signal. The apparatus of claim 1, wherein the temperature calculator
And counts the number of times the output signal is activated to calculate the ambient temperature. delete 2. The apparatus of claim 1, wherein the signal size setting unit
And when the output signal is in an inactive state, the delayed clock signal outputs a rising signal having the first pulse width corresponding to a delay time from the external clock signal, and when the output signal is active, And outputs a falling signal having the second pulse width which is equal to the width of the first pulse width excluding the first pulse width. The charge pump according to claim 1, wherein the charge pump
And charges the voltage to the capacitor in response to the rising signal, and discharges the voltage of the capacitor in response to the falling signal. delete 2. The apparatus of claim 1, wherein the signal size setting unit
And an inactive clock signal, the delayed clock signal, the output signal, and a reset signal, the reset signal being active in response to the external clock signal, in response to the output signal of the signal modulator, A rising signal generator for outputting a rising signal to reset the rising signal while the reset signal is inactive; And
And wherein when the output signal and the external clock signal are active when the reset signal is active, the external clock signal, in response to the delay clock signal, is activated in response to the external clock signal, the delayed clock signal, the output signal, And a falling signal generator for outputting the falling signal that is active and inactive in response to the output signal and for resetting the falling signal when the reset signal is inactive. 9. The apparatus of claim 8, wherein the rising signal generator
A NOR gate for receiving an inverted signal of the external clock signal and the delayed clock signal and for performing NOR operation on the inverted signal and the delayed clock signal;
A first AND gate for receiving an output signal of the NOR gate and the reset signal and logically multiplying them;
A first multiplexer for inputting the output signal of the first AND gate and the output signal and the ground voltage and outputting one of the output signal of the first AND gate and the ground voltage in response to the output signal; And
And a first buffer for buffering the output signal of the first multiplexer and outputting the rising signal. 9. The apparatus of claim 8, wherein the falling signal generator
A second AND gate for receiving the external clock signal and the delayed clock signal and logically multiplying them;
A third AND gate for receiving the output signal of the second AND gate and the reset signal and logically multiplying them;
A second multiplexer for inputting the output signal of the third AND gate and the output signal and the ground voltage and outputting one of the output signal of the third AND gate and the ground voltage in response to the output signal; And
And a second buffer for buffering an output signal of the second multiplexer and outputting the falling signal.

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