KR100995240B1 - A circuit for measuring a capacitance - Google Patents

Abstract

The present invention relates to a capacitance sensing circuit, and in particular, when a current amount charged and discharged to a capacitor is changed, the circuit operates in a manner of detecting a value of the capacitance of the capacitor based on a change in voltage across the capacitor.

The capacitance sensing circuit detects the capacitance of the capacitor by measuring the time until the voltage across the capacitor changes from the reference value to the reference value again by varying the magnitude of the current charged in the capacitor and the discharged current. The capacitive sensing circuit includes a variable pulse signal generator for generating a pulse signal; A current driving capability controller configured to receive a pulse signal and charge or discharge a capacitor based on the level of the pulse signal; A signal converter which receives a voltage applied to the capacitor as a signal, selects one of two different levels based on a range of voltages, and outputs a digital signal having the selected level; And a first counter for receiving a digital signal and measuring a time for which the digital signal lasts at a first level among two different levels, wherein the capacitance of the capacitor is estimated based on the time measured by the counter.

Capacitance, Current Drive, Capacitor, MOSFET

Description

Capacitance Detection Circuits {A CIRCUIT FOR MEASURING A CAPACITANCE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance sensing circuit, and more particularly, to a circuit operating in a manner of detecting a value of a capacitance of a capacitor based on a change in voltage across both ends of a capacitor when a current amount charged and discharged to a capacitor is changed. It is about.

Various methods exist for measuring the capacitance of a capacitor.

A well known conventional method of measuring capacitance is to use an AC bridge circuit. AC bridge circuits typically include four arms, galvanometers, and sine wave generators. In the first and second arms the resistance is placed, and in the third arm the reference capacitor is known whose capacitance value is known. In the fourth arm, the capacitance to be measured is located, and the equilibrium condition is observed through the galvanometer by adjusting the frequency of the sine wave. Based on the detected conditions, the capacitance of the fourth capacitor to be measured can be measured.

As another prior art, US Patent No. 3,824,459 discloses a method for measuring capacitance. In this document, the time required for discharge of charge from the reference capacitor in the RC primary circuit composed of the reference capacitor and the first reference resistor is measured, and the unknown capacitor in the RC primary circuit composed of the unknown capacitor and the second reference resistor is measured. After measuring the time it takes for the charge to discharge from, the capacitance of the unknown capacitor is measured based on the two measurement times and the value of the known capacitor resistance.

In the above-described AC bridge circuit and the detection method of US Patent No. 3,824,459, two resistors and one reference capacitor are required. In other words, the circuit should be provided with an analog element other than the capacitor to be measured. However, because analog devices can change their characteristic values due to ambient conditions (temperature, humidity, operating conditions, etc.), it is difficult to accurately measure capacitance, and it is difficult to miniaturize circuits by taking up a lot of space. There is this.

In the capacitance measuring circuit, only by reducing the number of analog elements, accurate and accurate capacitance measurement is possible, and the circuit can be miniaturized. There is a need for a resistor that is an analog device and a method for obtaining capacitance of a capacitor without using a capacitor.

A capacitive sensing circuit according to the present invention includes a variable pulse signal generator for generating a pulse signal; A current driving capability controller configured to receive a pulse signal and charge or discharge a capacitor based on the level of the pulse signal; A signal converter which receives a voltage applied to the capacitor as a signal, selects one of two different levels based on a range of voltages, and outputs a digital signal having the selected level; And a first counter for receiving a digital signal and measuring a time for which the digital signal lasts at a first level among two different levels, wherein the capacitance of the capacitor is estimated based on the time measured by the counter.

Preferably, in the capacitive sensing circuit according to the present invention, the variable pulse signal generator comprises: a second counter for receiving a clock signal and outputting an N-bit signal representing the number of clocks; A mux for selecting one bit signal among N bit signals and outputting the pulse signal; And an edge detector that receives the pulse signal and detects an edge of the pulse signal, and when the edge detector detects the edge, the edge detector disables the second counter.

Preferably, in the capacitive sensing circuit according to the present invention, the variable pulse signal generator comprises: a second counter for receiving a clock signal and outputting an N-bit signal representing the number of clocks; A mux for selecting one bit signal among N bit signals and outputting the pulse signal; A first inverter for inverting and outputting a signal output from the mux; A first AND gate for performing an AND operation on the signal output from the inverter and the counter enable signal to output a pulse signal; An edge detector receiving a pulse signal to detect an edge of the pulse signal and outputting an edge detection signal indicating whether the edge is detected; And an RS flip-flop that receives an edge detector signal of the edge detector as a reset, receives a pulse start signal as a set, and operates in synchronization with a clock signal, wherein the counter enable signal is an RS flip-flop. Is an output signal from and the second counter operates or stops in response to the counter enable signal and is reset based on the pulse start signal.

Preferably, in the capacitive sensing circuit according to the present invention, the edge detector includes: a second inverter for receiving a pulse signal and inverting the pulse signal; A D flip-flop that receives a pulse signal and outputs a delayed pulse signal according to a clock signal; And a second AND gate for performing an AND operation on the output signal of the second inverter and the delayed pulse signal to output the edge detection signal.

Preferably, in the capacitive sensing circuit according to the present invention, the current drive capability regulator includes: a current charger for charging the capacitor with charging current when the pulse signal is at a second level based on the pulse signal; And a current discharger for discharging the capacitor with the discharge current when the pulse signal is at the third level based on the pulse signal.

Preferably, in the capacitive sensing circuit according to the invention, the current charger comprises a first switching element for switching between a capacitor and an operating potential, and the current discharger comprises a second switching element for switching between a capacitor and a ground potential. The first switching element and the second switching element are switched based on the pulse signal.

Preferably, in the capacitance sensing circuit according to the present invention, the magnitude of the charging current is larger than the discharge current.

Preferably, in the capacitive sensing circuit according to the invention, the first switching element comprises a high-current driving PMOS, the second switching element comprises a low-current driving NMOS, the gate of the high-current driving PMOS and The pulse signal is input to the gate of the low-current driving NMOS.

Preferably, in the capacitive sensing circuit according to the present invention, the first switching element comprises a high-current driving PMOS, and the second switching element is a resistor connecting the high-current driving NMOS and the high-current driving NMOS with a capacitor. And a pulse signal is input to the gate of the high-current driving PMOS and the gate of the high-current driving NMOS, and the resistance causes the discharge current to be less than the charging current.

Preferably, in the capacitance sensing circuit according to the present invention, the charging current is smaller than the discharge current.

Preferably, in the capacitive sensing circuit according to the invention, the first switching element comprises a low-current driving PMOS, the second switching element comprises a high-current driving NMOS, and the gate of the low-current driving PMOS. And a pulse signal is input to the gate of the high-current driving NMOS.

Preferably, in the capacitive sensing circuit according to the present invention, the first switching element comprises a high-current driving PMOS and a resistor connecting the high-current driving PMOS and a capacitor, and the second switching element comprises a high-current driving NMOS. And a pulse signal is input to the gate of the high-current driving PMOS and the gate of the high-current driving NMOS, and the resistance causes the charging current to be smaller than the discharge current.

Preferably, in the capacitive sensing circuit according to the present invention, the first switching element comprises a plurality of PMOSs and a plurality of logic sum gates corresponding to each of the plurality of PMOSs, and the second switching element comprises a plurality of NMOSs and a plurality of A plurality of AND gates corresponding to each of the NMOSs, wherein each of the plurality of PMOS switches between an operating potential and a capacitor, each of the plurality of NMOS switches between a ground potential and a capacitor, and Each of the plurality of logic gates receives a logic signal and a corresponding PMOS enable signal, and outputs the result to the gate of the corresponding PMOS, and each of the plurality of AND gates receives the logic signal and performs a logical multiplication on the corresponding NMOS enable signal. Output to the gate of the PMOS to adjust the magnitude of the charge current by adjusting the PMOS enable signal, NMOS enable signal And the control can adjust the size of the discharge current.

Preferably, in the capacitive sensing circuit according to the present invention, the signal converter selects the third level as a digital signal if the voltage across the capacitor is greater than the first level, and if the voltage across the capacitor is less than the second level, Four levels are selected as digital signals, the second level being less than or equal to the first level, and the fourth level being less than the third level.

Preferably, in the capacitive sensing circuit according to the present invention, the signal converter includes a comparator that implements the first level and the second level equally.

Preferably, in the capacitive sensing circuit according to the present invention, the signal converter includes a Schmitt trigger that implements the first level and the second level differently.

Since the capacitive sensing circuit does not use the reference resistor and the reference capacitor, it has the effect of reducing the chip area when implementing a semiconductor chip and operating without additional components when implementing the system, and the temperature, humidity, operating voltage, etc. It is possible to prevent the detection accuracy of the circuit from being lowered by the same external condition.

In the present invention, the capacitor to be measured may be an electric device such as a capacitor, a capacitor, or the like, or may be a human finger. That is, any form that can store charge can be in any form. In addition, capacitance refers to the amount of charge that is charged when a unit potential is applied to both ends of a capacitor.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

1 shows a functional block diagram of a capacitive sensing circuit 190. The basic operating principle of the capacitive sensing circuit 190 is to measure the time when the current in the capacitor 140 is charged or discharged. Since the difference between the current charged in the capacitor 140 and the magnitude of the discharged current is different, the length of the charging time and the discharging time is different, and the longer of these is measured to detect the capacitance of the capacitor 140. do.

A detailed configuration of the capacitance sensing circuit 190 shown in FIG. 1 is as follows. The capacitive sensing circuit 190 receives the clock signal 180 and receives the variable pulse signal generator 100 that generates a variable pulse signal var_pulse and the pulse signal var_pulse, and the level of the pulse signal var_pulse. According to the current driving capability regulator 110, which drives the different amount of current according to the voltage (cur_drv_sig) applied to the capacitor 140, based on the range of its magnitude of any one of two different magnitude levels A signal converter 120 that outputs a digital signal conv_out that becomes a level, and a counter that receives a digital signal conv_out and measures the time while the digital signal conv_out maintains one of the two levels above. 130, the capacitor 140 is charged or discharged according to the current output from the current drive capability regulator 110.

The variable pulse signal generator 100 outputs a variable pulse signal var_pulse. The meaning of 'variable' above means that the duration of the pulse can be changed. The current driving capability controller 110 charges a charge by flowing a certain amount of current to the capacitor 140 when the magnitude of the pulse signal var_pulse is the first level, and charges the capacitor when the pulse signal var_pulse is the second level. 140 absorbs current and discharges charge. For convenience of explanation, it is assumed that the first level is low in circuit logic (ground potential) and the second level is high in circuit logic (source potential or operating potential of the circuit). This assumption is illustrative and is not intended to limit the scope of the invention. One of ordinary skill in the art can easily change the low and high in the circuit logic into a circuit that performs the same function, and the low signal of the circuit logic can be modified so as to correspond to the source potential or the operating potential, and the high corresponds to the ground potential. . Such modifications are included in the scope of protection of the present invention.

The magnitude of the charging current that the current drive capability regulator 110 flows to the capacitor 140 when the pulse signal var_pulse is low (first level), and the current when the pulse signal var_pulse is high (second level). The magnitude of the discharge current absorbed from the capacitor 140 by the drive capability regulator 110 may be different from each other. That is, the magnitude of the charging current may be larger than the magnitude of the discharge current, and the magnitude of the charging current may be smaller than the magnitude of the discharge current.

Assuming that the capacitance of the capacitor 140 is C, the magnitude of the voltage across both ends is V, and the amount of charged charge is Q, the relationship Q = C * V is established. Differentiating the above expression with respect to time leads to the following equation.

Arranging Equation 1 with respect to C, the following equation is derived.

Referring to (Equation 2), it can be seen that when charging or discharging the capacitor 140 by flowing a current of a constant magnitude, the size C of the capacitor 140 is inversely proportional to the speed at which the voltage changes. Therefore, when the capacitor 140 is charged with a current having a constant magnitude, the time required until the voltage reaches a second voltage larger than the first voltage at the first voltage is proportional to the capacitance of the capacitor 140. It can be seen that. This applies equally to the case of not only charging the capacitor 140 with a constant magnitude of current, but also discharging with a constant magnitude of current. Further, even if the magnitudes of the charge current and the discharge current vary slightly with time, the capacitance can be estimated roughly. As a result, the capacitance of the capacitor 140 may be estimated by measuring the charge time and / or the discharge time between the first voltage and the second voltage greater than the first voltage.

The signal converter 120 receives a voltage (cur_drv_sig) applied to the capacitor 140. The signal converter 120 outputs a digital signal conv_out which becomes one of two different magnitude levels based on the magnitude range of the input voltage cur_drv_sig. In one embodiment, as signal converter 120, a comparator or a Schmitt trigger may be used. When using the comparator as the signal converter 120, if the voltage (cur_drv_sig) applied to the capacitor 140 is greater than a predetermined level, the digital signal conv_out having a third level (e.g., circuit logic high) is outputted. If smaller than the predetermined level, the digital signal conv_out having the fourth level (for example, a circuit logic low) can be output.

In another embodiment, the Schmitt trigger may be used as the signal converter 120. Schmitt when the voltage (cur_drv_sig) applied to the capacitor 140 when the output signal (conv_out) of the Schmitt trigger is a third level (e.g. 0V or low) becomes greater than a predetermined fifth level value (e.g. 3V) The output signal conv_out of the trigger is changed to the fourth level (eg, 5V, high). When the output signal conv_out of the Schmitt trigger is at the fourth level (eg, high), a value that the voltage (cur_drv_sig) applied to the capacitor 140 is smaller than the predetermined sixth level value (eg, 2V) is obtained. At the moment, the output signal of the Schmitt trigger (conv_out) is changed to the third level (0V, low).

The counter 130 receives the digital signal conv_out and counts the number of clocks (proportional to time) at which the signal is maintained at a constant level (either the third level or the fourth level). Since the time for which the digital signal conv_out is maintained at a constant level is proportional to the time when the current is charged or discharged in the capacitor 140, the number of clocks measured by the counter 130 is ultimately dependent on the size of the capacitor 140. For a plurality of capacitors 140 with known capacitances, if the above clock number is measured in advance, and stored therein, the unknown capacitor 140 is measured for a time that is maintained at a constant level. , The value of the capacitor 140 can be measured. Therefore, since the capacitance sensing circuit 190 has the configuration as shown in FIG. 1, the capacitance of the capacitor 140 can be measured.

2 shows a circuit diagram of a variable pulse signal generator 100 included in the capacitive sensing circuit 190. The variable pulse signal generator 100 receives a clock signal clk and counts the number of clocks, and outputs the number of clocks as an N bit signal, based on a counter 200 and a selection signal var_pulse. The edge detector 220 selects MUX and outputs a pulse signal var_pulse and outputs a pulse signal var_pulse, and detects any one of a rising edge and a falling edge. When the edge detector 220 detects an edge from the pulse signal var_pulse, the edge detector 220 outputs a signal for disabling the counter 200, and the counter 200 stops operating. Edge detector 220 is shown in the form of a functional block diagram, a detailed operation will be described below with reference to other drawings.

3 shows a circuit diagram of the pulse signal generator 100, and the detailed configuration of the edge detector 220 is shown. 4 shows a timing diagram of the pulse signal generator 100.

In FIG. 3, the output of the mux 210 is output mux_out to the first inverter 300, and the first AND gate 310 is the output signal mux_inv and the counter enable of the first interlock 300. It receives a signal (cnt_en). The output signal var_pulse of the first AND gate 310 is the same as the pulse signal var_pulse input to the current driving capability controller 110 in FIG. 1. The pulse signal var_pulse is also input to the edge detector 220, specifically to the second inverter 320 and the D flip-flop 340. Meanwhile, the second AND gate 330 receives the output signal mux_inv of the second inverter 320 and the output signal var_pulse_delay of the D flip-flop 340. The output signal edge_detect from the second AND gate 330 is a signal indicating whether an edge (which may be a rising edge or a falling edge) is detected in the pulse signal var_pulse. In this embodiment, an example will be described when the falling edge is detected. The edge detection signal edge_detect is input to the reset signal of the RS flip-flop 350 to stop the operation of the counter 200 through the counter enable signal cnt_en when an edge is detected. The stopped counter 200 changes its counter enable signal cnt_en to high by a counter reset signal cnt_reset input as a set signal of the RS flip-flop 350, and then operates again.

Referring to FIG. 4, since the counter reset signal cnt_reset is high before (a), the counter 200 is in a reset state and the output of the counter 200 becomes zero. In (a), the counter reset signal cnt_reset turns low, and this signal is applied as the set signal of the RS flip-flop 350, so that the counter enable signal cnt_en, which is the output of the RS flip-flop 350, Turns high at the moment. Therefore, the counter 200 starts to operate from (a). In addition, the counter enable signal cnt_en becomes an input of the first AND gate 310. In (a) to (c), since the counter enable signal cnt_en is high, the first AND gate 310 is generated. The pulse signal var_pulse, which is the output of, has the same waveform as the output mux_inv of the first inverter 300.

The counter 200 increments the number of clocks which are its outputs by one for each rising edge of the clock signal 180. The mux 210 receives the clock number of the counter 200 bit by bit. Based on the selection signal mux_sel of the mux 210, it is possible to determine which bit of the counter 200 is the output signal mux_out of the mux 210. In this embodiment, the select signal mux_sel is set to select the fourth bit of the counter 200 output. Then, the mux output signal 200 goes high between (b) and (c), where the output of the counter 200 changes from 15 to 16. By the inverter 300 which inverts the mux output signal mux_out, the first inverter output signal mux_inv is high in the interval (a) to (b), but is zero in the interval of (b) to (c). 1 The inverter output signal (mux_inv) goes low. As described above, the counter enable signal cnt_en remains high between (a) and (c), and the RS flip-flop (350) is applied because the high is applied to the edge detection signal (edge_detect) in (c). As it is reset and turned low, the pulse signal var_pulse outputting the first inverter output signal mux_inv and the counter enable signal cnt_en through the first AND gate 310 is output as shown in FIG. ) To (b) and have a high value, after which it turns low.

Therefore, the length (pulse width) of the pulse signal var_pulse can be adjusted by changing the output bit of the counter 210 by changing the selection signal mux_sel.

5A shows a functional block diagram of one embodiment of a current drive capability regulator 110. The current driving capability controller 110 receives the pulse signal var_pulse and charges or discharges a current in the capacitor 140 according to the magnitude level of the pulse signal var_pulse. In order to perform this function, the current drive capability regulator 110 of FIG. 5A includes a variable current charger 510 and a variable current discharger 520.

The variable current charger 510 receives the pulse signal var_pulse and outputs a current to charge the capacitor 140 when the magnitude of the pulse signal var_pulse is at a first level (eg, low, 0V). When the magnitude of the pulse signal var_pulse is at the second level (for example, high, operating potential), no current flows. The variable current discharger 520 receives the pulse signal var_pulse and absorbs a current when the magnitude of the pulse signal var_pulse is the second level to discharge the charge charged in the capacitor. That is, the variable current charger 510 charges the capacitor 140 when the magnitude of the pulse signal var_pulse is at the first level, and the variable current discharger 520 is charged when the magnitude of the pulse signal var_pulse is at the second level. The capacitor 140 is discharged. The magnitudes of the charge current and the discharge current may be different, and the magnitude may be changed according to a setting.

As described above, the signal converter 120 receives the voltage value cur_drv_sig applied to the capacitor 140 and outputs a digital signal conv_out that is one of two different magnitude levels based on its range. Then, the size of the capacitor 140 is detected based on the number of clocks measured by the counter 130.

5B and 5C show functional block diagrams of other embodiments of current drive capability regulator 110.

The current drive capability regulator 110 of FIG. 5B includes a low current charger 530 instead of the variable current charger 510 and a high current discharger 540 instead of the variable current discharger 520. To indicate that the magnitude of the current supplied by the low current charger 530 when charging the capacitor 140 is less than the magnitude of the current that the high current discharger 540 absorbs when discharging the capacitor 140. Respectively referred to as low current charger 530 and high current discharger 540. In addition, hereinafter, a current for charging the capacitor 140 will also be referred to as a charging current and a current for discharging the capacitor 140.

The current drive capability regulator 110 of FIG. 5C includes a high current charger 550 and a low current discharger 560 as opposed to the case of FIG. 5B. The magnitude of the charging current supplied by the high current charger 550 is greater than the magnitude of the discharge current absorbed by the low current discharger 560.

6A and 6B are circuit diagrams showing the specific circuit configuration of the current drive capability regulator 110 including the low current charger 530 and the high current discharger 540 of FIG. 5B, respectively.

Referring to FIG. 6A, low current charger 530 is a low current drive PMOS and high current discharger 540 is a high current drive NMOS. They each receive a pulse signal var_pulse and operate as a switch element. When the pulse signal var_pulse is low, since the low current driving PMOS 530 is turned on and the high current driving NMOS 540 is turned off, the source current is transferred to the capacitor 140 through the low current driving PMOS 530. An electric current flows in and the capacitor 140 is charged. On the other hand, when the pulse signal var_pulse is high, since the low current driving PMOS 530 is turned off and the high current driving NMOS 540 is turned on, the capacitance (a) through the high current driving NMOS 540 ( Current flows from the 140 to the ground, and the capacitor 140 is discharged.

The current driving capability of the MOS is adjustable according to the channel width between the drain and source of the MOS. The high current driving MOS has a large channel width between the drain and the source, so that a large amount of current flows. On the other hand, the low current driving MOS causes a small amount of current to flow by making the channel width between the drain and the source small. This applies simultaneously to PMOS and NMOS. Thus, the low current driven PMOS 530 of FIG. 6A drives a smaller amount of current than the high current driven NMOS 540. Since the discharge current is larger than the charging current, the time (charge time) required until the voltage (cur_drv_sig) applied to the capacitor 140 reaches a predetermined second voltage larger than the first voltage from the predetermined first voltage is determined. It becomes larger than the time (discharge time) it takes until it reaches a 1st voltage from 2 voltages. Therefore, the length of time from the first voltage to the first voltage is determined mainly by the length of the charging time.

Meanwhile, referring to FIG. 6B, in the current driving capability regulator 110, the low current charger 530 includes a high current driving PMOS 610 and a current limiting resistor 600, and the high current charger 540 includes a high current. Drive NMOS 540. Although the amount of current may be adjusted by adjusting the channel width between the drain and the source, the current limiting resistor 600 may adjust the magnitude of the charging current or the discharge current while using the PMOS and the NMOS having the same amount of current. This can be clearly understood from Ohm's law that the current flowing through a resistor is inversely proportional to the magnitude of the resistor when the voltage across the resistor is constant.

7A and 7B are circuit diagrams showing the specific circuit configuration of the current drive capability regulator 110 including the high current charger 550 and the low current discharger 560 of FIG. 5C, respectively.

Referring to FIG. 7A, high current charger 550 is a high current drive PMOS and high current discharger 560 is a low current drive NMOS. They receive the pulse signal var_pulse, respectively, and switch between the operating voltage and the capacitor or between ground and the capacitor. Meanwhile, referring to FIG. 7B, in the current driving capability regulator 110, the low current charger 550 is the high current driving PMOS 540, and the high current discharger 560 is the current driving NMOS 700 and the current limiting resistor ( 710). The operation of the circuits of Figs. 7A and 7B is the same as Figs. 6A and 6B, and differs in that the magnitudes of the currents flowing through the PMOS and the NMOS (that is, the charge current and the discharge current) are opposite.

FIG. 8 is a circuit diagram showing a specific circuit configuration of the current drive capability regulator 110 including the variable current charger 510 and the variable current discharger 520 shown in FIG. 5A.

Referring to FIG. 8, the variable current charger 510 and the variable current discharger 520 of the current driving capability regulator 110 include a plurality of PMOS and NMOS, respectively. The gates of each of the plurality of PMOSs are connected to an output obtained by ORing the pulse signal var_pulse and the PMOS selection signal 810. Gates of each of the plurality of NMOSs are connected to an output obtained by logically multiplying the pulse signal var_pulse and the NMOS selection signal by 820. Therefore, by adjusting the PMOS selection signal and the NMOS selection signal, the number of operating PMOS or NMOS can be adjusted, so that the magnitudes of the charge current and the discharge current can be adjusted.

Meanwhile, in one embodiment, the signal converter 120 of FIG. 1 may include a comparator. When using the comparator as the signal converter 120, if the magnitude of the voltage (cur_drv_sig) applied to the capacitor 140 is larger than a predetermined level, the digital signal conv_out having a third level (for example, high) is outputted. If it is smaller than the predetermined level, the digital signal conv_out having the fourth level (eg, low) may be output. For example, when the ground potential is 0 V and the maximum operating voltage of the circuit is 5 V, the output of the comparator 120 when the voltage (cur_drv_sig) applied to the capacitor 140 is greater than 2.5 V (the predetermined level) ( When conv_out) is 5 V (high, third level), and the voltage (cur_drv_sig) applied to the capacitor 140 is less than 2.5 V, the output (conv_out) of the comparator 120 is 0 V (low, fourth level). May be Alternatively, when the voltage (cur_drv_sig) applied to the capacitance 140 is greater than 2.5 V, the output (conv_out) of the comparator 120 becomes 0 V (third level). The output conv_out of 120 may be 5 V (fourth level).

In another embodiment, the signal converter 120 may include a Schmitt trigger. When the Schmitt trigger is used as the signal converter 120, the voltage applied to the capacitor 140 when the output signal conv_out of the Schmitt trigger 120 is low is a predetermined fifth level value (eg, 3 V). At higher values, the Schmitt trigger's output signal goes high. On the contrary, if the output signal conv_out of the Schmitt trigger 120 is high (5V), the Schmitt trigger occurs at the instant when the voltage (cur_drv_sig) applied to the capacitor 140 becomes smaller than the sixth level value (for example, 2V). The output signal conv_out of 120 is turned low.

Although the signal converter 120 lists embodiments that include comparators or Schmitt triggers, this is for the purpose of clarity of understanding and the present invention is not limited in its configuration.

On the other hand, the counter 130 counts the time that the output signal conv_out of the signal converter 120 is maintained at a constant level and outputs it (conv_out). In an embodiment, the output signal conv_out of the signal converter 120 may be connected to the enable input of the counter 130 to perform the above operation.

Thus far, the functional block diagram of the capacitance correction circuit 190 shown in FIG. 1 and the specific circuit configuration of each functional block have been described. Hereinafter, the operation of the capacitance sensing circuit 190 will be described with reference to FIGS. 9 to 12.

9 shows a first operation timing diagram of the capacitive sensing circuit 190. The setting of the capacitive sensing circuit 190 showing the operation in the timing diagram of FIG. 9 is as follows. The current drive capability regulator 110 has a low current charger 530 and a high current discharger 540, as shown in FIG. 6A or 6B, and the signal converter 120 includes the 'signal conversion criteria' of FIG. 9. Is used as a reference voltage value, and the counter 130 counts the number of clocks (time) when the output of the signal converter (comparator) 120 is high.

1 and 9, at time a, the variable pulse signal generator 100 applies high to the pulse signal var_pulse and outputs it to the current driving capability controller 110. Accordingly, the current drive capability regulator 110 begins to charge the capacitor 140 with current. One voltage conv_out of the capacitor 140 increases exponentially. When the charging current of the current driving capability regulator 110 is a constant value that does not change with time, the voltage conv_out may increase in proportion to time. At a time (b) where the voltage conv_out has a value greater than the 'signal conversion criterion', the signal converter 120 applies a high to the output conv_out. The counter 130 receives the clock clk and the output conv_out of the signal converter 120 to count the number of clocks at which the cnffur signal conv_out is kept high. In (c) the variable pulse signal generator 100 turns the pulse signal var_pulse low. Thereafter, the current drive capability regulator 110 begins to discharge the charge from the capacitor 140.

In the circuit setting of FIG. 9, since the current drive capability regulator 110 includes the low current charger 530 and the high current discharger 540, the magnitude of the discharge current is larger than that of the charge current. Accordingly, a waveform such as the voltage (cur_drv_sig) applied to the capacitor 140 of FIG. 9 appears. The counter 130 counts the number of clocks until the voltage cur_drv_sig becomes less than the 'signal conversion reference'. In FIG. 9, this clock number is referred to as N.

The operating waveforms of the circuits in (d) to (iii) indicate when the capacitance of the capacitor 140 to be measured is smaller than that in (a) to (c). Since the capacitance is smaller, the charging speed of the capacitance 140 becomes faster. Therefore, the voltage conv_out of the capacitor 140 reaches the signal conversion criterion faster than when the capacitance is large. The counter 130 counts the number of clocks until the voltage cur_drv_sig becomes less than the 'signal conversion reference'. In FIG. 9, this clock number was set to M. FIG.

The number M of clocks of the counter 130 when the magnitude of the capacitance is small is greater than the number N of clocks of the counter 130 when the magnitude of the capacitance is large. The reason for this is that since the current charged in the capacitor 140 is smaller than the discharged current, the charging speed is slower than the discharged rate, so that the voltage (cur_drv_sig) of the capacitor 140 becomes a 'signal' from the time when discharge starts. This is because the interval up to the point of time at which the conversion criterion is reached is not significantly different even if the capacitance of the capacitor 140 is changed. Therefore, the number of clocks is the period from when the magnitude of the voltage (cur_drv_sig) exceeds the 'signal conversion criteria' until the pulse signal var_pulse turns low (that is, from (b) to (c) of FIG. 9). It can be seen that it is almost determined by the length of the interval, or () from () to ().

10 shows a second operation timing diagram of the capacitive sensing circuit 190. The setting of the capacitance sensing circuit 190 showing the operation in the timing diagram of FIG. 10 is as follows. The current drive capability regulator 110 has a high current charger 550 and a low current discharger 560, as shown in FIG. 7A or 7B, and the signal converter 120 includes the 'signal conversion criteria' of FIG. 10. Is used as a reference voltage value, and the counter 130 counts the number of clocks when the output of the signal converter (comparator) 120 is high.

1 and 10, in (a), the variable pulse signal generator 100 applies high to the pulse signal var_pulse and outputs it to the current driving capability controller 110. Accordingly, the current drive capability regulator 110 begins to charge the capacitor 140 with current. In the voltage conv_out having a value greater than the 'signal conversion criterion', the signal converter 120 applies a high to the output conv_out. The counter 130 receives the clock clk and the output conv_out of the signal converter 120 to count the number of clocks at which the output conv_out is kept high. On the other hand, since the high current charger is used in this embodiment, the charging time is shorter than in the case of Fig. 9, and therefore the pulse signal var_pulse of the variable pulse signal generator 100 is much shorter than in the case of Fig. 9. A low is applied to the pulse signal var_pulse, and the current driving capability regulator 110 starts discharging the charge from the capacitor 140.

In the circuit setting of FIG. 10, since the current drive capability regulator 110 includes the low current discharger 560, the magnitude of the discharge current is smaller than that of the charge current. Accordingly, the voltage cur_drv_sig of the capacitor 140 of FIG. 10 decreases more slowly than it increases. Intervals (d) to (iii) show the case where the size of capacitor 140 is smaller.

The clock number N is greater than the clock number L. In FIG. 10, since the discharge current is smaller, the discharge time occupies most of the clocking time, and the larger the size of the capacitor 140, the longer the discharge time.

11 shows a third operation timing diagram of the capacitive sensing circuit 190. The setting of the capacitance sensing circuit 190 showing the operation in the timing diagram of FIG. 11 is as follows. The current drive capability regulator 110 has a high current charger 550 and a low current discharger 560, as shown in FIG. 7A or 7B, and the signal converter 120 includes the 'signal conversion criteria' of FIG. 10. Is used as a reference voltage value, and the counter 130 counts the number of clocks (time) when the output of the signal converter (comparator) 120 is low.

1 and 11, at time a, the variable pulse signal generator 100 applies a low to the pulse signal var_pulse and outputs it to the current driving capability controller 110. Accordingly, the current drive capability regulator 110 begins to discharge the capacitor 140. At a time (b) where the voltage conv_out has a value less than the 'signal conversion reference', the signal converter 120 applies a low to the output conv_out. The counter 130 receives the clock clk and the output conv_out of the signal converter 120 to count the number of clocks at which conv_out is kept low. On the other hand, in this embodiment, since the low current discharger is used, the time for discharging the capacitor 140 is longer than the time for charging. Therefore, the number of clocks counted in the case where the magnitude of the capacitance is smaller (section (a) to (c)) than the number of clocks counted in the case of large capacitance (section (a) to (c)). Less than M

12 shows a fourth operation timing diagram of the capacitive sensing circuit 190. The setting of the capacitance sensing circuit 190 showing the operation in the timing diagram of FIG. 12 is as follows. The current drive capability regulator 110 has a low current charger 530 and a high current discharger 540, as shown in FIG. 6A or 6B, and the signal converter 120 includes the 'signal conversion criteria' of FIG. 10. Is used as a reference voltage value, and the counter 130 counts the number of clocks (time) when the output of the signal converter (comparator) 120 is low.

1 and 12, at time a, the variable pulse signal generator 100 applies a low to the pulse signal var_pulse and outputs it to the current driving capability controller 110. Accordingly, the current drive capability regulator 110 begins to discharge the capacitor 140. Since the discharge current is large, discharge occurs within a short time, and thus the length of the section where the pulse signal var_pulse is low is relatively short. When the pulse signal var_pulse becomes high, the capacitor 140 starts to charge again, and the counter 130 increases the number of clocks until the voltage conv_out of the capacitor 140 reaches the 'signal conversion reference'. Counting. When the number of clocks when the size of the capacitor 140 is large is N and the number of clocks when the size of the capacitor 140 is small is L, N is larger than L. In the embodiment of Figure 12 can be seen as measuring the time the current is charged, because the larger the capacitor 140, the longer the charging time.

In the above, various embodiments of the present invention have been described.

Various modifications to these embodiments will be apparent to those skilled in the art, and the unique principles defined herein may be applied to other embodiments that do not utilize the operation of the invention. That is, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and novel features described herein.

1 shows a functional block diagram of a capacitive sensing circuit 190.

2 shows a circuit diagram of a variable pulse signal generator 100 of a capacitive sensing circuit 190.

3 shows a circuit diagram of the edge detector 220 of the pulse signal generator 100.

4 shows a timing diagram of the pulse signal generator 100.

5A, 5B, and 5C show functional block diagrams of embodiments of current drive capability regulator 110.

6A and 6B show a circuit diagram of the current drive capability regulator 110 with the low current charger 530 and the high current discharger 540 of FIG. 5B, respectively.

7A and 7B show a circuit diagram of the current drive capability regulator 110 with the high current charger 550 and low current discharger 560 of FIG. 5C, respectively.

FIG. 8 shows a circuit diagram of a current drive capability regulator 110 having a variable current charger 510 and a variable current discharger 520, shown in FIG. 5A.

9 shows a first operation timing diagram of the capacitive sensing circuit 190.

10 shows a second operation timing diagram of the capacitive sensing circuit 190.

11 shows a third operation timing diagram of the capacitive sensing circuit 190.

12 shows a fourth operation timing diagram of the capacitive sensing circuit 190.

* Description of the main parts of the drawing

180: clock 100: variable pulse signal generator

110: current drive capability regulator 120: signal converter

130: counter 140: capacitance

Claims (16)

A variable pulse signal generator for generating a pulse signal; A current driving capability controller configured to receive the pulse signal and charge or discharge a capacitor based on the level of the pulse signal; A signal converter that receives a voltage applied to the capacitor as a signal, selects one of two different levels based on the range of the voltage, and outputs a digital signal having the selected level. Is a logic low and a logic high; And A first counter which receives the digital signal and measures a time for which the digital signal lasts at one of the two different levels, Wherein the capacitance of the capacitor is estimated from the time measured by the first counter and a constant value of current used to charge or discharge the capacitor. The method of claim 1, The variable pulse signal generator, A second counter that receives a clock signal and outputs an N bit signal representing a clock number; A mux for selecting one bit signal among the N bit signals and outputting the bit signal; And An edge detector receiving the pulse signal and detecting an edge of the pulse signal; If the edge detector detects an edge, the edge detector disables the second counter. The method of claim 1, The variable pulse signal generator, A second counter that receives a clock signal and outputs an N bit signal representing a clock number; A mux for selecting one bit signal among the N bit signals and outputting the bit signal; A first inverter for inverting and outputting the signal output from the mux; A first AND gate to perform an AND operation on the signal output from the inverter and the counter enable signal to output the pulse signal; An edge detector configured to receive the pulse signal and detect an edge of the pulse signal, and output an edge detection signal indicating whether the edge is detected; And An RS flip-flop configured to receive the edge detection signal of the edge detector as a reset, a pulse start signal as a set, and operate in synchronization with the clock signal; The counter enable signal is an output signal from the RS flip-flop, And the second counter operates or stops in response to the counter enable signal and is reset based on the pulse start signal. The method of claim 3, wherein The edge detector may include a second inverter that receives the pulse signal and inverts and outputs the pulse signal; A D flip-flop that receives the pulse signal and outputs a delayed pulse signal according to the clock signal; And And a second AND gate for performing an AND operation on the output signal of the second inverter and the delayed pulse signal to output the edge detection signal. The method of claim 1, The current drive capability regulator, A current charger configured to charge the capacitor with a charging current when the pulse signal is at a second level based on the pulse signal; And A current discharger configured to discharge the capacitor with discharge current when the pulse signal is at a third level based on the pulse signal, Wherein the second level is one of logic low and logic high, and the third level is the other of logic low and logic high. The method of claim 5, The current charger includes a first switching element for switching between the capacitor and an operating potential, The current discharger includes a second switching element for switching between the capacitor and ground potential, And the first switching element and the second switching element are switched based on the pulse signal. The method of claim 6, And the magnitude of the charging current is greater than the discharge current. The method of claim 7, wherein The first switching element comprises a high-current driven PMOS, The second switching element comprises a low-current driving NMOS, And the pulse signal is input to the gate of the high-current drive PMOS and the gate of the low-current drive NMOS. The method of claim 7, wherein The first switching element comprises a high-current driven PMOS, The second switching element includes a high-current driving NMOS and a resistor connecting the high-current driving NMOS and the capacitor, The pulse signal is input to the gate of the high-current drive PMOS and the gate of the high-current drive NMOS, Wherein the resistance causes the discharge current to be less than the charge current. The method of claim 6, And the charge current is less than the discharge current. The method of claim 10, The first switching element comprises a low-current driving PMOS, The second switching element comprises a high-current driving NMOS, And the pulse signal is input to the gate of the low-current drive PMOS and the gate of the high-current drive NMOS. The method of claim 10, The first switching element includes a high-current driving PMOS and a resistor connecting the high-current driving PMOS and the capacitor, The second switching element is a high-current driving NMOS, The pulse signal is input to the gate of the high-current drive PMOS and the gate of the high-current drive NMOS, Wherein the resistance causes the charging current to be less than the discharge current. The method of claim 6, The first switching element includes a plurality of PMOSs and a plurality of logical sum gates corresponding to each of the plurality of PMOSs, The second switching element includes a plurality of NMOSs and a plurality of AND gates corresponding to each of the plurality of NMOSs, Each of the plurality of PMOS switches between an operating potential and the capacitor, Each of the plurality of NMOS switches between a ground potential and the capacitor, Each of the plurality of logical sum gates receives the pulse signal and the corresponding PMOS enable signal, logically sums them, and outputs them to the gates of the corresponding PMOS, Each of the plurality of AND gates receives the AND signal and multiplies the pulse signal and the corresponding NMOS enable signal, and outputs the AND signal to the corresponding PMOS gate. The magnitude of the charging current may be adjusted by adjusting the PMOS enable signal. And adjust the magnitude of the discharge current by adjusting the NMOS enable signals. The method of claim 1, The signal converter selects a third level as the digital signal when the voltage applied to the capacitor is greater than the first level, and selects a fourth level as the digital signal when the voltage applied to the capacitor is smaller than the second level. Wherein the second level is less than or equal to the first level, the third level is one of logic low and logic high, and the fourth level is the other of logic low and logic high. The method of claim 14, The signal converter includes a comparator that implements the first level and the second level equally. The method of claim 14, The signal converter includes a Schmitt trigger that implements the first level and the second level differently.

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