KR101951729B1 - A method, apparatus, and system for distributed pre-processing of touch data and display region control - Google Patents

Abstract

In one embodiment, the system includes a peripheral controller that interfaces with a touch controller and communicates mapping information that identifies the primary and secondary regions of the display. The touch controller includes logic for filtering the touch data when the touch data is for a touch in the secondary area and for communicating the touch data to the peripheral controller when the touch data is for a user touch in the primary area. In one embodiment, the display logic may determine when and how to use the display bezel region for displaying content via a combination of criteria. The decision vector (sensor, device configuration, content type, primary display activity, etc.) can enable / disable the display area for rendering with independent control of each side of the bezel. The content may be rendered based on the primary display content, environment, other devices and user preferences. Other embodiments are also described and claimed.

Description

Field of the Invention [0001] The present invention relates to a method, an apparatus, and a system for dispersed pre-processing of touch data and control of a display area,

This application claims the benefit of US Provisional Application No. 61 / 749,386, filed January 6, 2013.

This disclosure relates generally to computing systems and, more particularly, to controlling display content and power consumption of a computing device.

As technology advances, users become accustomed to having greater amounts of features and functionality in smaller packages. These trends dominate consumer electronics, and users are seeking the latest in a compact, lightweight form factor for computing and communications, while many devices converge into a single system with computing and communication capabilities. Nonetheless, current systems have drawbacks or trade-offs about capabilities, form factors, or both.

Many current systems are configured to receive user input by a touch mechanism. Some of these mechanisms are relatively primitive and do not receive accurate touch information effectively, requiring significant processing. Typically, the user touch processing is performed in a processor of a system such as a central processing unit (CPU). Thus, this process consumes resources that could otherwise be covered in other situations.

Another problem with various form factor devices is that if the display configuration is typically fixed or adjustable, then the configuration is user controlled by the user. This control interferes with flexibility when a given device is used in a variety of different form factor modes and / or situations. In addition, requiring a user to reconfigure the display mode for a variety of different situations can increase complexity and frustrate users. Also, bezel areas in the current clamshell and tablet client form factors are not used for display rendering.

Figure 1A illustrates one embodiment of a computing system.
Figure IB illustrates another embodiment of a computing system.
1C depicts yet another embodiment of a computing system.
Figure ID shows another embodiment of a computing system.
Figure IE shows another embodiment of a computing system.
1F illustrates another embodiment of a computing system.
Figure 1G illustrates another embodiment of a computing system.
Figure 1 h illustrates another embodiment of a computing system.
Figure 2 illustrates one embodiment of a top view of the placement of some exemplary components within the base portion of the chassis.
Figure 3 illustrates one embodiment of a cross-sectional view of an embodiment of a computing system.
4 shows an embodiment of a block diagram of components present in a computing system.
Figure 5 illustrates another embodiment of a block diagram of components present in a computing system.
Figure 6 illustrates another embodiment of a block diagram of components present in a computing system.
Figure 7 illustrates another embodiment of a block diagram of components present in a computing system.
Figure 8 illustrates another embodiment of a block diagram of components present in a computing system.
Figure 9 illustrates another embodiment of a block diagram of components present in a computing system.
Figure 10 illustrates another embodiment of a block diagram of components present in a computing system.
Figure 11 shows another embodiment of components present in a computing system.
12A shows an embodiment of a block diagram of a processor.
12B shows an embodiment of a core of a processor.
Figure 13 shows another embodiment of a block diagram for a processor.
Figure 14 shows another embodiment of a block diagram for a processor.
FIG. 15A is a block diagram of a portion of a system that illustrates invalid touch region processing according to an embodiment of the present invention. FIG.
FIG. 15B is a block diagram of a part of a system showing effective touch area processing according to an embodiment of the present invention. FIG.
15C is a block diagram of a haptic feedback control in accordance with another embodiment of the present invention.
16 is a flowchart of a method for pre-processing touch data according to an embodiment of the present invention.
17 is an illustration of a display including an active display region and a virtual bezel region including a plurality of softbuttons according to an embodiment of the present invention.
Figures 18A-D are graphical illustrations of dynamic control of content rendering in different regions of a display according to various embodiments.
19 is a graphical illustration of the smooth interaction between a secondary display region and a primary display region according to an embodiment.

In the following description, in order to provide a thorough understanding of the present invention, it is appreciated that certain types of processors and system configurations, specific hardware architectures, specific architectures and microarchitecture details, specific register configurations, specific UltrabookTM characteristics, Numerous specific details such as components, specific measurements / heights, specific processor pipeline stages and operations, and the like are disclosed. However, it will be apparent to those skilled in the art that these specific details need not be employed to practice the present invention. In other examples, specific and alternative process architectures, specific logic circuits / codes for the described algorithms, specific firmware code, specific interconnect operations, specific logic configurations, specific fabrication techniques and materials, specific compiler implementations, Known components and methods of operation, such as, for example, representation, specific power interruption and gating techniques / logic, and other specific operational details of a computer system, have not been described in detail in order not to unnecessarily obscure the present invention.

While the following embodiments may be described with reference to energy savings and energy efficiency in a particular integrated circuit, such as in a computing platform or microprocessor, other embodiments may be applied to other types of integrated circuit and logic devices. Similar techniques and teachings of the embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy savings. For example, the disclosed embodiments are not limited to desktop computer systems or UltrabookTMs, but may also be used in other devices such as handheld devices, tablets, other thin notebooks, system on chip (SOC) devices, and embedded applications . Some examples of handheld devices include cellular telephones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on chip, a network computer (NetPC), a set top box, a network hub, a wide area network (WAN) switch, ≪ / RTI > In addition, the apparatuses, methods, and systems described herein are not limited to physical computing devices, but may also be related to software optimization for energy conservation and efficiency. As is readily apparent in the following description (with reference to hardware, firmware, software or a combination thereof), embodiments of the methods, apparatus and systems described herein are essential to the 'green technology' future balanced with performance considerations .

In addition, while the following embodiments are sometimes described with reference to a processor, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments of the present invention can be applied to other types of circuits or semiconductor devices that benefit from higher pipeline throughput and improved performance. The teachings of embodiments of the present invention are applicable to any processor or machine that performs data manipulation. However, the present invention is not limited to a processor or machine that performs 512-bit, 256-bit, 128-bit, 64-bit, 32-bit or 16-bit data operations and may be implemented on any processor and machine Can be applied. In addition, the following description provides examples, and the accompanying drawings show various examples for the purpose of illustration. These examples, however, should not be construed in a limiting sense because they are merely examples of embodiments of the invention rather than providing an exhaustive list of all possible implementations of the embodiments of the present invention.

While some of the following examples illustrate instruction handling and distribution in the context of execution units and logic circuits, other embodiments of the present invention provide that when executed by a machine, it is possible for a machine to comply with at least one embodiment of the present invention Readable, < / RTI > type of medium that causes the computer to perform the functions of < / RTI > In one embodiment, the functions associated with embodiments of the present invention are implemented with machine-executable instructions. The instructions may be used to cause a general purpose or special purpose processor programmed with these instructions to perform the method of the present invention. Embodiments of the present invention include a machine or machine-readable medium having stored thereon instructions that can be used to program a computer (or other electronic device) to perform one or more operations in accordance with embodiments of the present invention May be provided as a computer program product or software that may be used to perform the functions described herein. Alternatively, embodiments of the method of the present invention may be implemented by specific hardware components including fixed-function logic for performing the steps, or by any combination of programmed computer components and fixed-function hardware components . ≪ / RTI >

The methods and apparatus described herein are described below with reference to ultra-thin and / or ultra-thin notebook / laptop primarily Ultrabook ™. However, the apparatus and methods described herein may be implemented in connection with any integrated circuit device, electronic device, or computing device, and thus are not so limited.

Referring now to FIG. 1A, an illustration of an embodiment of a computing device / system is shown. Various commercial implementations of the system 10 may be provided. As an example, the system 10 may be an Ultrabook ™, Apple® MacBook Air, Acer® Aspire, LG® Xnote, Dell® Inspiron, Dell® XPS, NEC® LaVie, MSI® S20, Asus® Transformer, Sony® VAIO, Other ultra-light and ultra-thin computing devices, or any known and / or available ultra-lightweight, ultra-thin, ultra-thin computing device, such as HP® EliteBook, HP® Folio, Toshiba® Protege, Asus® Zenbook, Asus® TaiChi, Lenovo® Ideapad, Lenovo® Yoga ™ And / or < / RTI > As a first example, the ultra-idle computing device may be a computing device, such as a thin and / or light notebook, a laptop, an e-reader, a tablet and a hybrid thereof (e.g., And / or light devices capable of performing tasks (e.g., user input / output, execution of instructions / code, or network access, etc.). However, the hypervisor computing device or system is not limited to the examples provided above. In fact, as computing systems become more compact and more efficient, now thin, lightweight, and portable can later be interpreted as large and heavy. Thus, in one embodiment, being thin and light is seen in terms of the current market for a small computing device or a known future market. Alternatively, the thin and light weight may be viewed at the time the interpretation of the present disclosure is made.

For example, in one embodiment, the Ultrabook ™ includes one or more of the following characteristics: (1) thinner than 18 mm for displays of less than 14 inches, thinner than 21 mm for displays of 14 inches or more, Or less than 23 mm for switchable versions; (2) For example, in an ACPI specification (see Advanced Configuration and Power Interface Specification, revision 3.0b, Oct. 10, 2006), a random range of 1-7 seconds from a hibernation such as power state S4-S8, Wake-up; Power on button operation A screen display that is switched on within 3 seconds; At least 7 days of standby battery life with Always Fresh Data; The minimum value of any range of battery life within 5-24 hours as measured by a common industrial tool; One or more touch screen displays; Specific hardware, software and / or firmware (e.g., Intel® Management Engine, Intel® Anti-Theft Technology, Intel® Identify Protection Technology, Intel® Smart Connect Technology, etc.); Certain types of storage or hard drives (including solid-state drives and / or drives having a minimum transfer rate of any amount in the range of 80-1000MB / S and any minimum size within the range of 16GB to 10TB).

In one embodiment, one or more of the illustrated properties are part of the Ultrabook ™ definition. Note that these properties are purely examples based on the current market view. As previously mentioned, embodiments of the Ultrabook ™ can be similarly tuned to accommodate future market conditions that potentially redefine the definition of the Ultrabook ™ (thus, its characteristics and range may be reduced (or decreased) based on a changing computing ecosystem Depending on the metric).

Referring to FIG. 1A, the system 10 includes, in one embodiment, a base portion 20 that can be constructed through a lightweight chassis. By way of example, the base portion includes substantially all of the electronic circuitry of the system; This is not required because different components may be located in different compartments of system 10 (e.g., display 40, lid portion 30, or other known compartments of ultra-thin, lightweight computing devices) . In the case of a user interface, a keyboard 25 and a touch pad 28 are provided in the base portion 20. However, any known device for providing input to a computing system or computing device may be used. For example, the sensors described herein may be used in combination with (or in place of) a keyboard, a mouse, etc. to receive input from a user and perform computing tasks. It also includes a universal serial bus (USB) port, a Thunderbolt ™ port, a video port (for example, a micro high definition media interface (HDMI) or mini video graphics adapter (VGA) Various ports for receiving peripheral devices, such as a memory card port, such as a card port, and an audio jack, may generally be present at a location 22 on the side of the chassis (in other embodiments, user- May be on opposite chassis side surfaces or other surfaces of system 10). Also, a power port may be provided to receive DC power through an AC adapter (not shown in FIG. 1A). Note that these ports are purely examples. As the size of the ultra busy computing device becomes smaller, fewer external ports can be provided. Instead, communications can be performed via wireless communication technologies similar to Bluetooth, Near Field Communication, Wi-Fi sensors, and the like. In addition, power may be received via alternative connections (or even wireless in some embodiments).

As further appreciated, lid portion 30 may be coupled to base portion 20 and may include one or more display (s), which in different embodiments may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) (40). However, any display technology, such as an e-ink screen, may be used as the display 40. In addition, in the area of the display 40, a touching function may be provided in one embodiment to allow the user to provide user input via a touch panel located with the display 40. In another embodiment not illustrated, a plurality of displays may be provided (e.g., traditional and e-ink screens, different display types, or multiple displays of the same type). The lid portion 30 may further include various capture devices including a camera device 50 capable of capturing video and / or still information. In addition, there may be one or more microphones, such as dual microphones 55a and 55b, to receive user input via user input. Although shown in this position in FIG. 1A, the microphone, which may be one or more omni-directional microphones, may be in a different position in other embodiments.

As described further below, the system 10, in one embodiment, is comprised of specific components and circuits that enable a high-end user experience through a combination of hardware and software of the platform. For example, using available hardware and software, perceptual computing can enable a user to interact with the system in a voice, gesture, touch, and other ways. Here, different sensors are potentially included and can be used to detect information (e.g., visual, auditory, olfactory, kinesthetic, taste, 3D perception, temperature, pressure, gas / liquid / solid chemical / Or any other known sensors). The processing of sensors and this information is discussed in more detail below.

This user experience also enables advanced features such as instant on and instant access (also known as Alway On Always Connected) while providing high performance and low power capability, allowing the system to be in a low power state (e.g., , Or other known low power mode) and can be woken up directly to allow the user to be very lightweight (e.g., in a low, It can be delivered in a thin form factor system. Also, in one embodiment, such a wake-up system is connected to a network such as a local network, a Wi-Fi network, the Internet, etc.; Performance similar to that available on smartphone and tablet computers, lacking the user experience and processing of a full feature system such as that of FIG. 1A. Of course, it should be understood that additional components, such as a loudspeaker, additional display, capture device, environmental sensor, etc., may be present in the system, although these are illustrated at such a high level in the example of FIG.

Referring now to FIG. 1B, an exemplary computing system in accordance with an embodiment of the present invention is illustrated. As shown in FIG. 1B, the system 10 can be used with any of the following systems: Ultrabook ™, Apple® MacBook Air, Acer® Aspire, LG® Xnote, Dell® Inspiron, Dell® XPS, NEC® LaVie, MSI® S20, Asus® Transformer, Other ultra-lightweight and ultra-thin computing devices, or any known and / or available ultra-lightweight devices, such as Sony® VAIO, HP® EliteBook, HP® Folio, Toshiba® Protege, Asus® Zenbook, Asus® TaiChi, Lenovo® Ideapad, Lenovo® Yoga Thin, and / or ultra-thin computing platforms. The system is relatively small and lightweight. For example, in one embodiment, the system is formed in an ultra-thin and lightweight monolithic aluminum (or carbon) configuration and weighs less than three pounds, has a width of about 12.8 inches, a depth of 8.9 inches, And a tapered design such that the height at the front edge is less than about 0.1 inches. In one embodiment, the system 10 includes an Intel®-based processor and includes an integrated graphics processor with 2/4/8/12/16/32/64 GB of system memory.

As can be seen in FIG. 1B, the display can occupy substantially all of the lid portion 102. As can be seen, the bezel of this lid portion 102 includes an integrated camera 108. By way of example, the camera 108 includes an integrated FaceTime camera. 1B, in the view 100A, the base portion 104 may include a keyboard 105 (typical) and a touchpad 106. As shown in FIG. In some implementations, the keyboard 105 is backlit and leverages environmental sensors, such as ambient light sensors, to detect changes in lighting conditions and adjust the display and keyboard brightness accordingly.

As can be seen in the side view 100B of FIG. 1B, the base portion has a profile that is tapered from a relatively thin leading front edge to a wider back edge. As can be seen, the external port can be adapted in this illustrated side face. In the illustrated embodiment, port 112 includes (typically) a Thunderbolt (TM) port, a USB 2.0 port, and a card reader port (which may be used to accommodate, for example, an SD card). In an embodiment, at least one of the ports is an I / O port that provides 10 gigabits per second (Gbps) of full-duplex bandwidth per channel. This port can support data at the same time (for example via PCIe ™) over a single cable and display the connection (for example, via the display port). The peripheral product is typically connected to this port using an electrical or optical cable. With these ports, multiple high performance PCIe (TM) (TM) and DisplayPort devices are attached to the platform via a single physical connector. With such an interconnect, a user adds a high performance feature to the platform over a cable and daisy-chains multiple devices, including one or more displays, storage devices, video capture devices, and the like. On the other side portion, additional ports may also be provided, including another USB port, a headphone port, a microphone, and a power adapter.

View 100C shows an open view of the platform. Although such a high-level example is shown in FIG. 1B, it should be appreciated that additional features may be present in other embodiments. In some embodiments, the touchpad 106 may include a multi-touch trackpad to receive various user inputs (e.g., different numbers of fingers, different types of movements, gestures, etc.) that are converted to different user commands . In one embodiment, the trackpad is implemented as at least a translucent window. However, the touchpad 106 (and even the keyboard 105) may be replaced or omitted as the sensory user input is advanced.

Referring now to Figure 1C, another example of another ultra-thin form factor device according to an embodiment of the present invention is shown. As shown in the various figures, the system 120 in one representation may be an Ultrabook ™, Apple® MacBook Air, Acer® Aspire, LG® Xnote, Dell® Inspiron, Dell® XPS, NEC® LaVie, MSI® S20, Asus® Transformer, Sony® VAIO, HP® EliteBook, HP® Folio, Toshiba® Protege, Asus® Zenbook, Asus® TaiChi, Lenovo® Ideapad, Lenovo® Yoga Other lightweight and thin computing devices, or any known and / Ultra-thin, < / RTI > and / or ultra-fast computing platforms available. As can be seen, the system 120 includes a lid portion and a base portion, the lid portion includes a display, and the base portion includes a keyboard and a touch pad. In comparison with FIGS. 1A and 1B having a tapered base design, the system 120 has a more uniform base height.

In one embodiment, the system 120 includes one or more of the following features: a diagonal display size of 10 to 14 inches, a backlit chiclet keyboard, a height of 0.4 to 1 inch, a length of 10 to 14 inches , 5 to 10 inches wide, USB port, headphone / microphone jack, HDMI port, AC power port, expansion slot, rated battery life of over 7 hours, 64GB to 512GB solid state drive, integrated graphics chip, SODIMM memory slot , And a weight of 1-4 pounds.

Referring now to FIG. 1d, an example of an exemplary switchable form factor ultra-thin system according to an embodiment of the present invention is shown. As shown in the various figures, the system 130 in one representation may be an Ultrabook ™, Apple® MacBook Air, Acer® Aspire, LG® Xnote, Dell® Inspiron, Dell® XPS, NEC® LaVie, MSI® S20, Asus® Transformer, Sony® VAIO, HP® EliteBook, HP® Folio, Toshiba® Protege, Asus® Zenbook, Asus® TaiChi, Lenovo® Ideapad, Lenovo® Yoga, or any other ultra- Or ultra-light, ultra-thin, and / or ultra-fast computing platforms available. Lenovo® IdeaPad Yoga, Samsung® Series 5 and more recent series, Dell® Duo, Dell® XPS 12, and Asus® Transformer are just some of the systems that work as switchable form factors that provide both a laptop and tablet computing environment This is a concrete example. Some of them include a foldable design, while others achieve a transition between ultra-thin notebooks and tablets, including flip, fold, slide, or removable designs. By way of example, the system has a relatively slim size and weight, for example, a thickness much less than one inch, e.g., about 0.67 inch thick, and a weight of about three pounds. The screen size can be 10-14 inches in size and can generally be extended to the full width and length of the system.

To further illustrate the switchable nature, the folding design is shown as a transition between 130A and 130C. As seen in first view 130A, the system includes a lid portion 132 and a base portion 134, the lid portion including a display and the base portion including a keyboard and a touchpad. In addition to this conventional view and mode of operation, the system is also operable in the stand mode shown in view 130B through rotation of the hinge assembly to make the display more comfortable. As an alternative (not shown), the surface 134 with the trackpad and keyboard may face down while the display 132 may be folded to provide another stand mode towards the user. As illustrated, the camera 138 is present in the back portion of the lid portion 132. However, a camera may be provided on surface 132 to provide features such as video and camera when system 130B is in stand-by mode. As can be seen in view 130C, there may be various indicator LEDs 139 on the front portion of the base portion 134. [ A variety of buttons, switches, and ports (such as those described above) may be present on the width sides of the base portion 134.

In one embodiment, the system 130A-130C includes one or more of the following features: a 12-14 inch display, a capacitive multi-touch display, a resolution of at least 1600x900, a thickness of less than 17mm, 128 to 512 GB solid state drive, high definition (HD) webcam, USB port, wireless LAN access module, Bluetooth access module, and rated battery life of at least 6 hours.

Figure IE shows an example of another ultra-thin system according to an embodiment of the present invention. As shown in FIG. 1E, the system 140 includes, in one sense, an Ultrabook ™, Apple® MacBook Air, Acer® Aspire, LG® Xnote, Dell® Inspiron, Dell® XPS, NEC® LaVie, MSI® S20, Asus® Transformer, Sony® VAIO, HP® EliteBook, HP® Folio, Toshiba® Protege, Asus® Zenbook, Asus® TaiChi, Lenovo® Ideapad, Lenovo® Yoga, or any other ultra- Or ultra-light, ultra-thin, and / or ultra-fast computing platforms available. The system 140 may have a very thin profile and may have a Z-height of 3 mm at the front side of the base portion 144 and may have a Z-height of 9 mm at the back portion of the base portion 144, as can be seen in various examples. Lt; RTI ID = 0.0 > Z-height. In this way, a streamlined design is provided.

In one embodiment, system 140 includes one or more of the following features: a height of less than 10 mm, a system memory of 4, 6, 8, or 12 GB, a screen size of between 10-12 inches, Miniature VGA port, USB port, micro HDMI port, 128, 256, or 512 GB solid state drive, rated battery for over 5 hours of operation, digital microphone, dimmer keyboard, and HD camera.

Referring now to FIG. 1F, an illustration of a desktop computer 150 in accordance with an embodiment of the present invention is shown. The view of Figure 1F is a back view showing various ports and other features of the system. As can be seen, in the power supply portion 152, a power cord adapter is provided, along with a power switch and a fan plate. In the connection portion 154, various adapters that provide external connections to various peripherals, including peripherals including displays, printers, networks, audio, video, etc., also include one or more parallel ports, a serial port, a USB port, / RJ45 port and so on. Also, a plurality of slots for an expansion card may be provided.

Referring now to FIG. 1G, an illustration of a tablet computer according to an embodiment of the present invention is shown. In one embodiment, the tablet computer 160 may be an Apple iPad ™, an iPad ™, a new iPad, an Apple® iPad ™ such as the iPad2 ™, a Samsung® Galaxy ™ Tablet, an Asus® Eee Pad, and Acer® Aspire, Acer® Iconia, Amazon® Kindle , Barnes and Noble® Nook, Asus® table, Dell® Streak, Google® Nexus, Microsoft® Surface, Sony® tablet, and Android ™ -based tablet, Windows®-based tablet, or any other known tablet device . As can be seen in the front view 162, there may be more than one input / interface button. There may also be a speaker 165 and a camera 169, which in one embodiment may be an iSight (TM) camera (e.g., a 5 megapixel camera), an HD camera, or other known camera. Note that the display shown in front view 162 may be a retina display or any other known tablet display providing high resolution. FIG. 1G also shows a back view 164 and a side view 166. FIG. Note that rear surface 164 also has a camera. Here, the cameras 169 and 167 may be provided for taking pictures, video, or live video feeds.

Referring now to FIG. 1h, an illustration of a smartphone 170 in accordance with an embodiment of the present invention is shown. In the example of FIG. 1h, the smartphone 170 may be an iPhone® (eg, iPhone 3GS, iPhone 4, iPhone 4S, iPhone 5, Blackberry ™ Samsung® smartphone (eg, Samsung® Galaxy ™ S3) , Motorola® Droid ™ and HTC One ™, Intel® Orange ™, Android ™ -based, Windows®-based, or other well known smartphone. As seen in front view example 172, smartphone 170 A speaker 173, a front camera module 174 and one or more input buttons 171. Similarly, a back camera 176 may be provided as shown in the back view 175. Various controls (E.g., power, volume, mute) are not shown in the side view 178, although such control buttons may exist.

Referring now to FIG. 2, a top view of an exemplary arrangement of defining components within a base portion of a chassis in accordance with an embodiment of the present invention is shown. As shown in FIG. 2, the base portion 20 includes, in one embodiment, a plurality of electronic circuits in the system other than those associated with a display panel and any touch screen. Of course, the view shown in Figure 2 is purely exemplary; Thus, in other embodiments, it is to be understood that different arrangements of components and other arrangements may occur, including different components, different sizes and locations of components.

In general, the view of Figure 2 is components within the chassis other than keyboards and touch pads, generally adapted and arranged over the components shown in Figure 2 (the keyboard is on the upper portion of the view of Figure 2, 2 < / RTI > of the view).

The motherboard 60 includes various integrated circuits (ICs) and / or circuits. Here, the mother board 60 electronically, wirelessly, and / or communicatively couples a processor, a system memory, and other ICs, such as a central processing unit (CPU). Additional ICs and other circuitry are implemented on the daughter board 70, which, in one embodiment, may be similarly electrically or communicatively coupled to the motherboard 60. The daughterboard 70 includes a port 81, 82, and 83 that potentially corresponds to exemplary ports: USB, Ethernet, Firewire, Thunderbolt, or any other type of user-accessible connection in one scenario. , Various ports and interfaces to other peripheral connectors. An add-in card 68 coupled to the daughter board 70 (also via a next generation form factor (NGFF) connector, for example) is also shown. Such a connector according to the NGFF design can provide a single type of connection used for different sized add-in cards with potentially different keying structures ensuring that only the proper add-in cards are inserted into these connectors. In the illustrated embodiment, the add-in card 68 includes, for example, a radio access circuit for a 3G / 4G / LTE circuit.

Similarly, the motherboard 60 may, in some embodiments, include any other user accessible port; I. E., Provide interconnects to ports 84 and 85 in the example. In addition, several add-in cards 65 and 66 may also be coupled to the motherboard 60. In the illustrated embodiment, the add-in card 65 includes a solid state drive (SSD) coupled to the motherboard 60 via a connector, such as an NGFF connector 59. The add-in card 66 includes any known computing add-in component such as a wireless local area network (WLAN), an audio device, a video device, a network controller, and the like.

It should be noted that FIG. 2 illustrates a configuration with a motherboard 60 that couples a plurality of ICs, circuits, and / or devices together, as described above. However, as semiconductor manufacturing is improved, the ability to place more transistors on a single die and / or package is also improved. As a result, in some embodiments, some (and potentially all of these) of these devices may be integrated into a single IC, die, chip, package, or the like. For example, the memory controller hub was a separate integrated circuit controller that was previously coupled to the central processor via a front-side-bus that resides on the motherboard 60. However, as manufacturing technology evolved, memory controller hubs have now begun to integrate onto CPUs, packages, and / or die. In addition, as other systems become more integrated, much of the aforementioned 'system' circuitry is provided on a single integrated circuit to form a system on a chip (SOC). As a result, the embodiments described herein are equally applicable to ultra-low latency computing devices including SOCs.

Returning to the discussion of the embodiment shown in FIG. 2, in order to provide cooling, some implementations may include one or more fans. In the illustrated embodiment, these two fans 47 are provided. Here, the fan 47 conducts heat away from the CPU and other electronic circuits via thermal fins 88a and 88b. As an example, heat is transferred to the vent in the chassis or directly to the chassis. However, other embodiments may also be used to reduce power consumption of the CPU and other components, other known heat dissipating elements, other known ventilation elements, or any other known or use for transferring heat from one space / It is also possible to provide a fanless system in which cooling is achieved by a possible mechanism.

To provide advanced audio characteristics, in one embodiment, a plurality of speakers 78a and 78b are provided. In one scenario, the speakers 78a and 78b are diverted from the top of the chassis through a net or other vented pattern to provide an enhanced acoustic experience. A pair of hinges 95a and 95b are provided to enable interconnection between the base portion 20 and the lid portion (not shown in FIG. 2 for the sake of simplicity of illustration). In addition to providing a hinge function, these hinges may further include, in one embodiment, a path that provides a connection between the circuit base portions 20 within the lid portion. For example, a wireless antenna, a touch screen circuit, a display panel circuit, etc. all can communicate through the adapted connector through these hinges. In addition, the hinge can assist or support switching between form factors in a hybrid environment. As an example, the hinge allows the system to switch from laptop / notebook to tablet form. As is readily apparent, the hinge is not the only mechanism for coupling the display to the chassis. As a result, any known physical coupling can be used to connect the display to the chassis or electronic circuitry of the computing system 10, whether or not the computing system 10 is switchable between form factors.

As will be further appreciated, a battery 45 is present. In one embodiment, the battery 45 includes a lithium-ion or other known / available high capacity battery. Although shown in Fig. 2 with particular implementations and circuitry of these components, the scope of the invention is not limited in this respect. That is, for a given system design, there may be a trade-off to more efficiently consume the available X-Y-Z space in the chassis.

Referring now to FIG. 3, there is shown a cross-sectional view of a computer system in accordance with an embodiment of the present invention. As shown in Figure 3, the system 10 corresponds to a clamshell-based ultra-thin laptop computer with a low-profile and lightweight design. The view of Figure 3 is a cross-sectional view through the substantial midpoint of the system and is intended to illustrate a high level view of the vertical stack-up or layout of components within the chassis.

Generally, the chassis is divided into a lid portion 30 and a base portion 20. Here, the lid portion 30 includes the display, associated circuitry, and components, while the base portion 20 includes the main processing elements with the battery and keyboard. However, in other implementations of the clamshell design, virtually all of the components other than the keyboard are adapted within the lid, so that a detachable, removable, or convertible lid portion can be used as a tablet-based form factor computer do.

The lid portion 30 includes the display panel 40 in one embodiment. In one embodiment, the display panel 40 includes an LCD, or other type of thin display, such as an OLED. As an example, the display panel 40 is coupled to the display circuit board 33. In addition, the touch screen 34 may be adapted (or disposed), in one embodiment, above, below, or integrated with the display panel 40. In an embodiment, the touch screen 34 is implemented through a capacitive sensing touch array constructed along the substrate. By way of example, the substrate includes glass, plastic, and other known or otherwise available transparent substrates. In turn, the touch screen 34 is interlocked with the touch panel circuit board 35. It should be noted that any known touch display technique may be used or used in conjunction with the display.

As further shown, the lid portion 30 also includes a camera module 50. In one embodiment, camera module 50 includes image data; And a high-definition camera capable of capturing both types of still images and moving images. The camera module 50 is, in some implementations, coupled to a circuit board 38. It is noted that all of these components of lid portion 30 may, in other embodiments, be constructed, disposed, or present within a chassis including a cover assembly. The cover assembly can be made using any known or available material suitable for providing a chassis, such as plastic or metal materials. As a specific example, such a cover assembly is made of or comprises a magnesium aluminum (Mg-Al) composition.

Still referring to FIG. 3, many of the processing circuits of system 10 are shown as being in base portion 20. However, as discussed in the embodiments that provide the detachable lid portion, these components may instead be implemented in the lid portion.

From the view with the top portion of the base portion 20 down, a keyboard 25, which may be of various types enabling a thin profile device and which may include a chisel-type key or other thin form factor key, is included. Further, the touch pad 28 is provided as another user interface.

The multiple components are configured on a circuit board 60, which may be a motherboard, such as a Type IV motherboard, including various integrated circuits coupled / adapted to the circuit board in various ways, including solder, surface mount, . 3, a CPU 55, such as an ultra low power multi-core processor, may be adapted to the circuit board 60 via, for example, a socket or other type of connection. As will be appreciated, to provide a thermal solution, the heat sink 56 may, in one embodiment, heat the heat from the processor and / or other components to the CPU 55, such as, for example, In close proximity to the heat pipes 57 that deliver to the various cooling positions of the heat exchanger. The circuit board 60 is also shown with an inductor 58 and an NGFF edge connector 59 configured. Although not shown for ease of illustration, it should be appreciated that the add-in card, in some embodiments, is coupled to the connector 59 to provide additional components. By way of example, these components may include a wireless solution and a solid state device (SSD), among other peripheral devices.

As further seen in FIG. 3, the battery 45 is included in or associated with the base portion 20. Here, the battery 45 is in a very close relationship with a part of the cooling solution such as the fan 47 and the like. Although shown in this particular implementation in the example of FIG. 3, the placement and inclusion of such components is not limited, as additional and different components may be present in other embodiments. For example, instead of providing mass storage by the SSD, a hard drive may be implemented within base portion 40. For this purpose, a mini serial SATA (serial advanced technology attach) connector is further coupled to circuit board 60 to enable connection of this hard drive to a processor and other components adapted on circuit board 60 do. In addition, the components may be placed at different locations to more efficiently utilize (or reduce) the Z-space.

In one embodiment, Ultrabook ™ refers to the maximum height based on the size of the screen 40 (ie, the diagonal size of the screen 40). As an example, the Ultrabook ™ includes a combined base portion 20 of 18 mm and a maximum height for the lid portion 30 for a display 40 of 13.3 inches or less. As a second example, the Ultrabook ™ includes a combined base portion 20 of 21 mm and a maximum height for the lid portion 30 for a display 14 of 14 inches or more. Also as yet another example, the Ultrabook ™ has a combined base portion 20 of 23 mm for the switchable or hybrid display (i.e. switchable between the notebook / laptop and tablet) and a maximum height for the lid portion 30 . However, as the overall size of all market segments (desktops, notebooks, Ultrabook ™, tablets and phones) decreases, the height range for Ultrabook ™ can also be reduced. Thus, in one embodiment, the maximum height for the Ultrabook ™ may vary between the tablet and the notebook based on market conditions.

Referring now to FIG. 4, a block diagram of components present in a computer system according to an embodiment of the invention is shown. As shown in FIG. 4, the system 400 may include any combination of components. These components may be implemented as ICs, portions thereof, discrete electronic devices, or other modules, logic, hardware, software, firmware, or combinations thereof adapted to a computer system, or in any other manner within the chassis of a computer system May be implemented as embedded components. It should also be noted that the block diagram of Figure 4 is intended to illustrate a high-level view of many components of a computer system. It should be understood, however, that in other implementations, some of the illustrated components may be omitted, additional components may be present, and that different arrangements of the illustrated components may occur.

As shown in FIG. 4, processor 410, in one embodiment, includes a microprocessor, a multi-core processor, a multi-threaded processor, an ultra-low voltage processor, an embedded processor, or other known processing elements. In the illustrated implementation, the processor 410 serves as the main processing unit and central hub for communication with many different components of the system 400. As an example, the processor 410 is implemented as a system on a chip (SoC). As a specific example, processor 410 may be an Intel® Architecture Core ™ -based processor, such as CA, Santa Clara, i3, i5, i7 from Intel Corporation, or another such processor. However, other embodiments, such as the Apple A5 processor, the Qualcomm Snapdragon processor, and the TI OMAP processor, may instead use a low-power processor from Advanced Micro Devices (AMD), Inc. of Sunnyvale, CA, ARM Holdings, Or its ARM-based design or CA, MIPS Technologies, Inc. of Sunnyvale. Or there may be a MIPS-based design of the licensee or borrower. Certain details regarding the architecture and operation of processor 410 in one implementation will be discussed further below.

The processor 410, in one embodiment, communicates with the system memory 415. By way of example, system memory 415 is implemented through a plurality of memory devices or modules to provide a predetermined amount of system memory. In one embodiment, the memory is a JEDEC low power double data rate (LPDDR) -based design such as the current LPDDR2 according to Joint Electron Devices Engineering Council (JEDEC) JESD 209-2E (published April 2009) Generation LPDDR standard, referred to as LPDDR3 or LPDDR4, which increases bandwidth by providing an extension to the < RTI ID = 0.0 > By way of example, there may be 2/4/8/12/16 gigabytes (GB) of system memory and may be coupled to the processor 410 via one or more memory interconnects. In various implementations, the individual memory devices may be of different package types, such as a single die package (SDP), a dual die package (DDP), or a quad die package (QDP). These devices, in some embodiments, are directly soldered to the motherboard to provide a low power profile solution, while in other embodiments these devices are configured as one or more modules that are in turn coupled to the motherboard by a given connector. Other memory implementations are possible, such as dual inline memory modules (DIMMs) of different variants, including, but not limited to, other types of memory modules, such as microDIMMs, MiniDIMMs. In a particular embodiment, the memory may be configured as an LPDDR2 or LPDDR3 memory or DDR3LM package sized from 2 GB to 16 GB and soldered onto the motherboard via a ball grid array (BGA).

Mass storage 420 may also be coupled to processor 410 to provide persistent storage of information such as data, applications, one or more operating systems, and the like. In various embodiments, this mass storage can be implemented via an SSD, in addition to improving system responsiveness, to enable thinner and lighter system designs. However, in other embodiments, mass storage is primarily a non-volatile storage of non-volatile storage of this information other than the context state during a power down event, so that a smaller capacity And can be implemented using a hard disk drive (HDD) having SSD storage. As also shown in FIG. 4, the flash device 422 may be coupled to the processor 410 via, for example, a serial peripheral interface (SPI). The flash device may provide non-volatile storage of system firmware, including basic input / output software (BIOS), as well as other firmware in the system.

In various embodiments, the mass storage of the system may be implemented as an SSD alone, or as a disk, optical or other drive with an SSD cache. In some embodiments, the mass storage is implemented as an SSD or as an HDD with an RST (restore) cache module. In various implementations, the HDD provides more than 320 GB to 4 terabytes (TB) of storage while the RST cache is implemented as an SSD with capacities from 24 GB to 256 GB. Note that this SSD cache may be configured as a single level cache (SLC) or a multi-level cache (MLC) option to provide an appropriate level of responsiveness. In the SSD-only option, the module can be accommodated in various locations, such as within an mSATA or NGFF slot. As an example, an SSD has a capacity in the range of 120 GB - 1 TB.

Various input / output (IO) devices may be present in the system 400. In the embodiment of FIG. 4, a display 424, which may be a high-definition LCD or LED panel configured in the lid portion of the chassis, is shown in particular. The display panel may also be provided with a touch screen 425 that is externally adapted, for example, over a display panel such that user interaction with the touch screen provides user input to the system, , Display of information, access to information, and the like. In one embodiment, the display 424 may be coupled to the processor 410 via a display interconnect that may be implemented as a high performance graphics interconnect. The touchscreen 425 may be coupled to the processor 410 via another interconnect, which in one embodiment may be an I2C interconnect. 4, in addition to the touch screen 425, user input by touch may also occur through the touch pad 430, and the touch pad 430 may be configured within the chassis and may also be coupled to the touch screen 425 RTI ID = 0.0 > I2C < / RTI >

The display panel may operate in a plurality of modes. In the first mode, the display panel can be arranged in a transparent state in which the display panel is transparent to visible light. In various embodiments, the plurality of display panels may be a display other than a bezel in the vicinity of the periphery. When the system operates in the notebook mode and the display panel operates in a transparent state, the user can see the object behind the display while viewing the information presented in the display panel status. In addition, the information displayed on the display panel can be viewed by the user located behind the display. Or the operation state of the display panel may be an opaque state in which visible light can not pass through the display panel.

In tablet mode, the system is folded so that the rear display surface of the display panel is in an outward facing position towards the user when the bottom surface of the base panel is on one surface or is retained by the user. In the tablet mode of operation, the rear display surface acts as a display and user interface, since this surface has a touch screen function and can perform other known functions of a conventional touch screen device such as a tablet device. For this purpose, the display panel may include a transparency-adjusting layer positioned between the touch screen layer and the front display surface. In some embodiments, the transparency-adjusting layer may be a electrochromic (EC), LCD layer, or a combination of EC and LCD layers.

In various embodiments, the display may be a different size, e.g., 11.6 "or 13.3" screen, with a 16: 9 aspect ratio, and at least 300 nits brightness. The display may also be a high definition resolution (at least 1920 x 1080p), compatible with an embedded display port (eDP), or may be a low power panel with panel self-refresh.

In terms of touch screen capabilities, the system can provide a display multi-touch panel that is multi-touch capacitive and at least five finger capable. In some embodiments, the display may be 10 finger-enabled. In one embodiment, the touch screen is accommodated in low-friction damage and scratch-resistant glass and coatings (e.g., Gorilla Glass (TM) or Gorilla Glass 2) to reduce " finger burn &Quot; finger skipping " To provide an enhanced touch experience and responsiveness, the touch panel may, in some embodiments, provide multi-touch functionality such as less than two frames (30 Hz) per static view during pinch zoom, and multi- To-touch function of less than 1 cm per frame with a delay of about < RTI ID = 0.0 > The display, in some implementations, has a minimal screen bezel that is parallel to the panel surface and supports edge-to-edge glass with limited IO interference in the use of multi-touch.

For perceptual computing and other purposes, various sensors may reside within the system and be coupled to the processor 410 in a different manner. Certain inertial and environmental sensors may be coupled to the processor 410 via a sensor hub 440, for example, via an I < 2 > C interconnect. 4, these sensors may include an accelerometer 441, an ambient light sensor (ALS) 442, a compass 443, and a gyroscope 444. In the embodiment shown in FIG. Other environmental sensors may include, in some embodiments, one or more thermal sensors 446 coupled to the processor 410 via a system management bus (SMBus) bus.

Using a variety of inertial and environmental sensors present in the platform, many different use cases can be realized. These use cases enable advanced computing operations including perceptual computing and also allow for improvements in power management / battery life, security, and system responsiveness.

As an example of a power management / battery life problem, based on information from the ambient light sensor, at least in part, the ambient light conditions at a given location of the platform are determined and the intensity of the display is controlled accordingly. Thus, the power consumed to operate the display is reduced in the predetermined light state.

With respect to security operations, it may be determined, based on context information obtained from a sensor, such as location information, that the user is allowed to access a given secured document. For example, a user may be allowed to access such documents at work or at home. However, the user is prohibited from accessing such documents when the platform is in a public place. This determination is based, in one embodiment, on location information determined, for example, through the camera recognition of a GPS sensor or a landmark. Other security operations may include providing paired devices within close proximity to each other, e.g., the portable platform described herein, with a user's desktop computer, mobile phone, and the like. The predetermined sharing is realized, in some embodiments, via near field communication when these devices are thus paired. However, if the devices are beyond a certain range, such sharing may be disabled. Also, when pairing the smartphone with the platform described herein, an alert may be configured to trigger when the devices are in a public location and move away from each other a predetermined distance. In contrast, when these paired devices are in a secure location, e. G., Work or home, devices may exceed this predetermined limit without triggering this warning.

Responsiveness can also be improved using sensor information. For example, even when the platform is in a low power state, the sensors may still be enabled to run at a relatively low frequency. Thus, any change in the position of the platform determined by, for example, an inertial sensor, a GPS sensor, or the like is determined. If no such change is registered, then a faster connection to a previous wireless hub, such as a Wi-Fi ™ access point or a similar wireless enabler, occurs, since in this case there is no need to scan for available wireless network resources. Thus, a greater level of responsiveness during wake-up from a lower power state is achieved.

It should be appreciated that many other use cases can be enabled using sensor information obtained through an integrated sensor within the platform described herein, and that the above examples are for illustrative purposes only. Using the system described herein, the perceptual computing system may allow for the addition of alternative input forms, including gesture recognition, and enable the system to sense user actions and intentions.

In some embodiments, there may be one or more infrared or other thermal sensing elements, or any other element for sensing the presence or movement of a user. These sensing elements may comprise a plurality of different elements that operate together, operate sequentially, or both. For example, the sensing elements may provide initial sensing of light or sound projection, and the like, followed by an ultrasonic time of flight camera or a patterned light camera, for example. And includes elements that provide sensing for the detection of a gesture.

Also in some embodiments, the system includes a light generator that produces an illuminated line. In some embodiments, the line provides a visual cue for the virtual boundary, i.e., a machining or virtual location in space, and the user's behavior of passing or breaking this virtual boundary or plane is intended to be part of the computing system Is interpreted. In some embodiments, the illuminated line may change color as the computing system transitions to a different state with respect to the user. The illuminated line can be used to provide the user with a visual clue of the virtual boundary in space and can be used to determine a transition in the state of the computer with respect to the user including determining when the user wishes to participate in the computer ≪ / RTI >

In some embodiments, the computer is operative to sense the user location and interpret the movement of the user's hand passing through the virtual boundary as a gesture that indicates the intention of the user to participate in the computer. In some embodiments, the light generated by the light generator may change as the user passes through a virtual line or plane, thereby providing a visual feedback to the user that the user has entered an area for providing a gesture that provides input to the computer .

The display screen may provide a visual indication of a transition of the computing system state with respect to the user. In some embodiments, the first screen is provided in a first state in which the presence of the user is sensed by the system, such as through the use of one or more sensing elements.

In some implementations, the system operates to detect the user's identity, such as by facial recognition. Here, the transition to the second screen may be provided in a second state in which the computing system has recognized the user identity, and in this second state, the screen provides a visual feedback to the user that the user has transitioned to the new state. The transition to the third screen may occur in a third state where the user confirms the user's perception.

In some embodiments, the computing system may use a transition mechanism to determine the location of the virtual boundary for the user, wherein the location of the virtual boundary may vary depending on the user and context. The computing system may generate light, such as an illuminated line, to indicate a virtual boundary for participation in the system. In some embodiments, the computing system may be in a waiting state and light may be generated in a first color. The computing system may detect whether a user has reached a virtual boundary, such as by using a sensing element to detect the presence and movement of the user.

In some embodiments, if a user is detected to cross a virtual boundary (such as a user's hand closer to the computing system than a virtual boundary), the computing system may transition to a state for receiving a gesture input from the user, The indicating mechanism may include light indicative of a virtual boundary changing to a second color.

In some embodiments, the computing system may determine whether a gesture motion is detected. When a gesture motion is detected, the computing system proceeds to a gesture recognition process, and the gesture recognition process may include the use of data from a data library that is present in memory within the computing device or otherwise accessible by the computing device .

Once the user's gesture is recognized, the computing system can perform the function in response to the input and return to receive additional gestures if the user is within the virtual boundary. In some embodiments, if the gesture is not recognized, the computing system may transition to an error state, where the mechanism for indicating an error state may include light representing a virtual boundary that changes to a third color, Returns to receive the additional gesture if the user is within the virtual boundary for participating in the computing system.

As mentioned above, in another embodiment, the system may be configured as a switchable tablet system that may be used in at least two different modes, i.e., tablet mode and notebook mode. The switchable system has two panels, a display panel and a base panel, and in tablet mode, two panels are stacked on top of each other. In tablet mode, the display panel can provide a touch screen function facing outward and visible on conventional tablets. In notebook mode, the two panels can be arranged in an open clamshell configuration.

In various embodiments, the accelerometer may be a three-axis accelerometer having a data rate of at least 50 Hz. A gyroscope may also be included and may be a 3-axis gyroscope. There may also be an e-compass / magnetometer. In addition, one or more proximity sensors may be provided (e.g., such that an open lid detects when a person is proximate (not present) to the system). For some operating systems, sensor fusion capabilities, including accelerometers, gyroscopes, and compasses, may provide improved features. Also, through a sensor hub with a real-time clock (RTC), wake-up from the sensor mechanism can be realized to receive the sensor input when the remainder of the system is in a low power state.

In some embodiments, an internal lid / display open switch or sensor indicating when the lid is closed / open may be used to place the system in a connected standby or automatically wake up from a connected standby state. Other system sensors may include an internal processor, memory, and an ACPI sensor for skin temperature monitoring to enable changes to the processor and system operating conditions based on the sensed parameters.

In an embodiment, the OS may be a Microsoft? Windows? 8 OS that implements an attached standby (also referred to herein as Win8 CS). Another OS with Windows 8 Connected Standby or similar status provides very low super idle power through the platform described here to keep the application connected to the cloud-based location with very low power consumption, for example. . The platform has three power states: a screen-on (normal); A connected standby (as the default " off "state); And shutdown (power consumption zero watt). Thus, in the connected standby state, the platform is logically turned on (at the minimum power level) even if the screen is off. In such a platform, power management can be made unknowingly by the application and, in part, maintains a constant connection due to offload technology that allows the lowest powered components to perform operations.

As can also be seen in FIG. 4, various peripheral devices may be coupled to the processor 410 via a low pin count (LPC) interconnect. In the illustrated embodiment, various components may be combined via the embedded controller 435. [ These components may include a keyboard 436 (e.g., coupled via a PS2 interface), a fan 437, and a thermal sensor 439. In some embodiments, the touchpad 430 may also be coupled to the EC 435 via the PS2 interface. A secure processor, such as the TPM 438, according to Trusted Computing Group (TCG) Trusted Platform Module (TPM) Specification Version 1.2, dated October 2, 2003, may also be coupled to the processor 410 via this LPC interconnect. However, the scope of the present invention is not limited in this respect, and the security processing and storage of security information may be in another protected location, such as a static random access memory (SRAM) in the secure coprocessor, or in secure enclave processor mode Lt; / RTI > may be present as an encrypted data blob that is decrypted only when it is protected by the < RTI ID = 0.0 >

In certain implementations, the peripheral ports may be a high definition media interface (which may be a full-size, a different form factor such as mini or micro); Size external port according to the USB Revision 3.0 specification (November 2008), and at least one of the USB ports may be in a standby state in which the system is connected and plugged into an AC wall power source Phone, etc.) for charging the USB device. In addition, one or more Thunderbolt ™ ports may be provided. Other ports may include an externally accessible card reader such as a full-size SD-XC card reader and / or a SIM card reader (e.g., an 8-pin card reader) for WWAN. For audio, there may be a 3.5 mm jack with stereo sound and microphone functionality (e.g., combinatorial function) and support for jack detection (e.g., headphone or cable with support for use of the microphone in the lid Headphones with a microphone). In some embodiments, the jack is reworkable between a stereo headphone and a stereo microphone input. Also, a power jack may be provided for coupling to an AC brick.

The system 400 can communicate with external devices in a variety of ways, including wireless. In the embodiment shown in FIG. 4, there are various wireless modules, each of which may correspond to a wireless device configured for a particular wireless communication protocol. One way for short range wireless communication, such as in a near field, may be in one embodiment using a near field communication unit (NFC) 445 capable of communicating with the processor 410 via the SMBus. It is noted that devices that are very close to each other can communicate through this NFC unit 445. For example, the user can allow the system 400 to adapt two devices in close proximity to one another and enable transmission of data such as identification information, payment information, image data, etc., It is possible to enable communication with another (for example) portable apparatus. Wireless power transmission using an NFC system can also be performed.

With the NFC unit described herein, users can place devices side by side for leveraging near-field coupling capabilities (such as near field communication and wireless power transmission (WPT)) by leveraging the coupling between the coils of one or more devices can do. More specifically, embodiments provide strategically shaped and arranged ferrite material to the devices to provide a better combination of coils. Each coil has an associated inductance that can be selected in conjunction with the resistive, capacitive, and other characteristics of the system to enable a common resonant frequency for the system.

As further seen in FIG. 4, additional wireless units may include other short range wireless engines, including WLAN unit 450 and Bluetooth unit 452. Wi-Fi communication in accordance with certain IEEE (Institute of Electrical and Electronics Engineers) 802.11 standards can be realized using the WLAN unit 450 while using the Bluetooth unit 452 to perform short- Can occur. These units may communicate with the processor 410 via, for example, a USB link or a universal asynchronous receiver transmitter (UART) link. Or these units may be connected to the PCI Express ™ Specification Base Specification Version 3.0 (published January 17, 2007), or the serial data input / output (SDIO) standard, in accordance with the Peripheral Component Interconnect Express Lt; / RTI > may be coupled to the processor 410 via an interconnect according to another such protocol. Of course, the actual physical connection between these peripherals, which may be configured on one or more add-in cards, may be due to a motherboard-adapted NGFF connector.

Also, for example, wireless wide area communication in accordance with cellular or other wireless wide area protocols may occur through a WWAN unit 456 that may be coupled to a subscriber identity module (SIM) 457. Also, a GPS module 455 may also be present to enable reception and use of location information. 4, an integrated capture device such as a WWAN unit 456 and a camera module 454 can communicate via a USB 2.0 or 3.0 link or via a predetermined USB protocol such as a UART or I2C protocol Please note. Once again, the actual physical connection of these units can be through adaptation of the NGFF add-in card to the NGFF connector configured on the motherboard.

In certain embodiments, wireless functionality may be provided modularly, for example, by a WiFi ™ 802.11ac solution (eg, an add-in card that is backward compatible with IEEE 802.11abgn) with support for Windows 8 CS have. This card may be configured in an internal slot (e.g., via an NGFF adapter). Additional modules can provide Intel® Wireless Display functionality as well as Bluetooth capabilities (for example, backward compatible Bluetooth 4.0). NFC support may also be provided through a separate device or multifunction device and may be located, for example, in the front right portion of the chassis for easy accessibility. Another additional module may be a WWAN device capable of providing support for 3G / 4G / LTE and GPS. This module may be implemented in an internal (e.g., NGFF) slot. Integrated antenna support for WiFi ™, Bluetooth, WWAN, NFC and GPS provides seamless transitions from WiFi ™ to wireless gigabit (WiGig) according to the WWAN Wireless, Wireless Gigabit Specification (July 2010) It is possible to do the opposite.

As described above, an integrated camera may be included in the lid. As an example, the camera may be a high resolution camera, for example, having a resolution of at least 2.0 megapixels (MP) and extending beyond 6.0 MP.

An audio processor may be implemented via a digital signal processor (DSP) 460 that may be coupled to the processor 410 via an HDA link to provide audio input and output. Similarly, the DSP 460 may communicate with an integrated CODEC and amplifier 462 that may be coupled to an output speaker 463, which may be implemented within the chassis. Likewise, the amplifier and CODEC 462 may be combined to provide a high-quality audio input (e. G., A digital microphone array) to enable implementation of voice-activated control of various operations within the system Lt; RTI ID = 0.0 > 465. < / RTI > Note that the audio output may be provided from the amplifier / CODEC 462 to the headphone jack 464. Although shown in conjunction with these specific components in the embodiment of FIG. 4, it should be understood that the scope of the present invention is not limited in this respect.

In certain embodiments, the digital audio codec and amplifier may drive a stereo headphone jack, an internal microphone array, and a stereo speaker. In a different implementation, the codec may be integrated into an audio DSP or coupled to a peripheral controller hub (PCH) via an HD audio path. In some implementations, in addition to an integrated stereo speaker, one or more bass speakers may be provided, and a speaker solution may support DTS audio.

In some implementations, the processor 410 may be powered by an external voltage regulator (VR) integrated within a processor die, called a fully integrated voltage regulator (FIVR), and a plurality of internal voltage regulators. The use of a plurality of FIVRs in a processor allows grouping of components into separate power planes so that power is regulated by the FIVR and fed only to those components in the group. During power management, a given power plane of one FIVR may be powered off or powered off when the processor is placed in a predetermined low power state, while another power plane of another FIVR may be active or fully powered Can be maintained.

In some embodiments, during some deep sleep states, I / O for several I / O signals, such as an interface between the processor and the PCH, an interface with an external VR, and an interface with the EC 435, A sustain power plane may be used to supply power to the pins. This persistent power plane also powers on-die voltage regulators that support onboard SRAM or other cache memory where the processor context is stored in the sleep state. The holding power plane is also used to power the wake up logic of the processor to monitor and process the various wake up source signals.

During power management, the power planes remain powered to support the aforementioned components while the other power planes are powered off or powered off when the processor enters a predetermined deep sleep state. However, this may cause unnecessary power consumption or dissipation when these components are not needed. For this purpose, embodiments may provide a connected standby sleep state that maintains the processor context using a dedicated power plane. In one embodiment, the connected standby sleep state may facilitate processor wakeup using the resources of the PCH, which may exist in packages with the processor. In one embodiment, the connected standby sleep state facilitates maintaining processor structural functions within the PCH until the processor wake-up, so that during a deep sleep state, the previously powered up unwanted processor, including turning off all clocks, Allows you to turn off all of the components. In one embodiment, the PCH includes a time stamp counter (TSC) and connected standby logic for controlling the system during the connected standby state. An integrated voltage regulator for the holding power plane may also be present on the PCH.

In an embodiment, during the connected standby state, the integrated voltage regulator may be powered by a power supply to support a dedicated cache memory in which the processor context, such as critical state variables, is stored when the processor enters deep sleep and connected standby states. And can function as a dedicated power plane that is maintained as it is. This critical state may include structural, micro-structured, state variables associated with the debug state, and / or similar state variables associated with the processor.

The wake up source signal from EC 435 may be sent to the PCH instead of the processor during the connected standby state so that the PCH can manage the wake up process on behalf of the processor. In addition, the TSC is maintained within the PCH to facilitate maintaining processor architectural functions. Although shown in conjunction with these specific components in the embodiment of FIG. 4, the scope of the present invention is not limited in this respect.

Power control within the processor can lead to improved power savings. For example, power can be dynamically allocated between cores, individual cores can change frequency / voltage, and multiple deep low power states can be provided to enable very low power consumption. In addition, dynamic control of cores or independent core portions can provide reduced power consumption by powering off components when components are not being used.

Some implementations may provide a specific power management IC (PMIC) to control the platform power. With this solution, the system may be in a standby state, such as a Win8 connected standby state, (For example, at 150 nit) for a very low (e.g., less than 5%) battery degradation in the Win 8 idle state (e.g., for 16 hours) Long battery life can be realized, for example, for a minimum of 6 hours, full HD video playback can occur. In one implementation, the platform < RTI ID = 0.0 > Can have an energy capacity of, for example, 35 Watts (WHr) in the case of Win8 CS with SSD, for example, and 40-44 WHr in case of Win8 using HDD with (for example) RST cache configuration have.

Certain implementations can provide support for the nominal CPU thermal design power (TDP) of 15W, with a configurable CPU TDP up to a design point of about 25W thermal design power (TDP). The platform may include a minimum vent due to the thermal characteristics described above. In addition, the platform is pillow-friendly (in that hot air is not infused to the user). Different maximum temperature points can be realized depending on the chassis material. In one embodiment of a plastic chassis (with at least a plastic lid or base portion), the maximum operating temperature may be 52 degrees C (C). For metal chassis implementations, the maximum operating temperature may be 46 ° C.

In a different implementation, a security module, such as a TPM, may be integrated within the processor or it may be a separate device such as a TPM 2.0 device. By means of an integrated security module called Platform Trust Technology (PTT), the BIOS / firmware can be used with security commands such as security keyboard and display, security commands, security boot, Intel® Anti-Theft Technology, Intel® Identity Protection Technology , Intel® Trusted Execution Technology (TXT), and Intel® Manageability Engine Technology.

Although a few embodiments of the present invention have been described, many modifications and variations will be apparent to those skilled in the art. The appended claims are intended to cover all such modifications and variations as fall within the true spirit and scope of the invention.

Referring now to FIG. 5, a block diagram of components present in a second computer system according to an embodiment of the present invention is shown. As shown in FIG. 5, the system 500 may include any combination of components. These components may be implemented as ICs, portions thereof, discrete electronic devices, or other modules, logic, hardware, software, firmware, or combinations thereof adapted to a computer system, or in any other manner within the chassis of a computer system May be implemented as embedded components. It should also be noted that the block diagram of Figure 5 is intended to illustrate a high-level view of many components of a computer system. It should be understood, however, that in other implementations, some of the illustrated components may be omitted, additional components may be present, and that different arrangements of the illustrated components may occur.

As shown in FIG. 5, processor 510, in one embodiment, includes a microprocessor, a multi-core processor, a multi-threaded processor, an ultra-low voltage processor, an embedded processor, or other known processing elements. In the illustrated implementation, processor 510 serves as the main processing unit of system 500. As a specific example, processor 510 may be any of the aforementioned processors available from Intel Corporation, AMD, ARM-based design, MIPS-based design, Qualcomm, Tl, or other such manufacturers. Certain details regarding the architecture and operation of processor 510 in one implementation will be discussed further below.

Processor 510, in one embodiment, communicates with system memory 551 and 552. [ By way of example, a plurality of memory communication paths may be provided through memory interconnects 550a and 550b. As one such example, each of the memory devices (and interconnects) can be at different speeds and can be controllably powered based on the LPDDR2 or the predetermined power consumption goals of the next generation LPDDR standard. By way of example, these memory devices, which may be the SDP, DDP or QDP form factor, may be provided with 2/4/8 gigabytes (GB) of system memory and may be connected to the motherboard in some way.

5, the processor 510 may be coupled to the chipset 515 via a plurality of interfaces including a direct media interface (DMI) 512 and a flexible display interface (FDI) . Although shown with these particular interconnects to the chipset 515 in the embodiment of FIG. 5, the connection to the chipset may be done in different ways in different embodiments. In some embodiments, the chipset 515 is also referred to as a peripheral controller hub (PCH) because it provides an interface to various peripherals of the system.

The SSD 531 may be coupled to the chipset 515 via a serial advanced technology attach (SATA) interconnect 530 to provide permanent storage of information such as data, applications, and one or more operating systems. Although shown as being implemented via SSD, in other embodiments, the mass storage is primarily configured to enable nonvolatile storage of this information, which is different from the context state during a power down event, so that the SSD And can be implemented using an HDD having a smaller capacity SSD storage serving as a cache.

As also shown in FIG. 5, the flash device 541 may be coupled to the processor 510 via, for example, a serial peripheral interface (SPI) 555. The flash device can provide nonvolatile storage of system firmware, including BIOS, as well as other firmware in the system.

Various IO devices may be present in the system 500. In the embodiment of FIG. 5, a display 521, which may be a high-definition LCD configured in the lid portion of the chassis, is shown in particular. The display panel may be coupled to the chipset 515 via a low voltage differential signaling (LVDS) interconnect 520. Although shown with this particular type of interconnect and LCD type display, other types of displays and different interconnect arrangements may be provided, such as LEDs or other types of displays.

As further seen, the additional video interface may be through a display port interconnect 525 coupled to a display adapter 526, which in one embodiment may be a Mini DisplayPort adapter (miniDP) Next, the adapter is connected to an external video output device via an HDMI device 527, which may be various types of flat panel television displays, such as plasma devices, LED devices, LCD devices, .

Still referring to FIG. 5, the touch screen 574 may also be externally adapted, e.g., over a display panel, to allow user input to be provided to the system through user interaction with the touch screen, , Access to information, and the like. Touch screen 574 may be coupled to processor 510 via USB2 interconnect 570C.

As can also be seen in FIG. 5, various peripheral devices may be coupled to the chipset 515 via a low pin count (LPC) interconnect 545. In the illustrated embodiment, various components may be combined through the embedded controller 551. [ These components may include a keyboard 552 (e.g., coupled via a PS2 interface). In some embodiments, the touchpad 553 may be coupled to the chipset 515 via the USB2 interconnect 550 and also to the EC 551 via the PS2 interface. A secure processor, such as TPM 546, may also be coupled to chipset 515 (and embedded controller 551) via this LPC interconnect 545.

As further seen in FIG. 5, a serial input / output (SIO) module 547 may also be coupled to the LPC interconnect 545 to provide for the communication of serial data. Other interconnects that may be coupled to the chipset 515 in certain implementations may include one or more system management devices that may be coupled via a system management (SM) bus with one or more general purpose IO devices via a GPIO interconnect.

The system 500 can communicate with external devices in a variety of ways, including wireless. In the embodiment shown in FIG. 5, the wireless module 561 may include one or more radios configured for a particular wireless communication protocol. In the illustrated embodiment, these wireless devices of module 561 may include a short-range wireless engine including a WLAN unit and a Bluetooth unit 552. With the WLAN unit, Wi-Fi ™ communication according to the predetermined IEEE 802.11 standard can be realized, while using the Bluetooth unit, short-range communication via the Bluetooth protocol can occur. These units may communicate with the chipset 515 via the PCIe (TM) protocol or the USB2 protocol along the interconnect 560. Of course, the actual physical connection between these peripherals, which may be configured on one or more add-in cards, may be due to a motherboard-adapted NGFF connector.

To provide audio input and output, CODEC 536 may be coupled to chipset 515 via HD audio interconnect 535. As can be seen, the CODEC 536 can provide coding and decoding of audio information in both the input and output directions. The output audio data decoded at the CODEC 536 may be provided as an output via the speaker 537. [ Next, the incoming audio information may be received via the microphone array 538, which is also coupled to the CODEC 536. [

The stereo camera module 581 includes a stereo card 566 that may be coupled to the chipset 515 via a PCIe ™ interconnect 565 to provide input of video data, Lt; RTI ID = 0.0 > LVDS < / RTI > Of course, in different implementations, different ways of interconnecting the camera module may occur. Camera module 581 may include a plurality of capture devices to provide a stereo effect and may be implemented by one or more cameras configured within the lid portion of the system and in some embodiments may be a 2.0-8.0 MP camera have.

In order to provide an improved gesture and authentication operation, an eye-gaze tracking module 571 may be provided. As will be appreciated, this module may be coupled to the chipset 515 via an interconnect 570a, which in one embodiment may be USB2 for interconnect. Eye eye tracking module 571 may be used to track a user's eye movements that may be used for gesture input purposes and provide a dynamic display to a user. The information from this module can also be used for power management purposes to reduce power consumption when the user is not participating in the system.

In one embodiment, additional gesture information may be received via the hand sensor 573, which may be coupled to a microcontroller 572 coupled to the chipset 515 via an interconnect 570b, which may be a USB2 interconnect. In the illustrated embodiment, microcontroller 572 may be an 8051-based microcontroller that receives hand information received via hand sensor 573. This gesture information may likewise be used by the system to perform various actions in response to the user's gesture.

As can be further seen, one or more notification LEDs 591 may be coupled to the microcontroller 572 via one or more GPIO interconnects 590.

To provide an interconnect for various peripherals, a plurality of external USB ports 576 may be provided, which allow the user to capture, via the physical interconnect, storage devices, media devices, playback devices, May be coupled to the chipset 515 through an interconnect 575, which in one embodiment may be a USB3 interconnect. It should be appreciated that while this embodiment is illustrated at such a high level, in other embodiments the system may include many other alternatives and options.

6 is a block diagram of an exemplary computer system formed with a processor including an execution unit for executing an instruction in accordance with an embodiment of the present invention. System 600 includes components, such as processor 602, that employs an execution unit that includes logic to perform algorithms for processing data, such as the embodiments described herein, in accordance with the present invention. System 600 represents a processing system based on PENTIUM III, PENTIUM 4, Intel® Xeon®, Itanium®, and / or Intel XScale® microprocessors available from Intel Corporation of Santa Clara, Calif. , Other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In one embodiment, the sample system 600 may run one version of the WINDOWS® operating system available from Microsoft® Corporation of Redmond, WA, but may include other operating systems (eg, UNIX and Linux), embedded software , And / or a graphical user interface may also be used. Thus, embodiments of the invention are not limited to any particular combination of hardware circuitry and software.

Embodiments are not limited to computer systems. Alternative embodiments of the present invention may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular telephones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. An embedded application may include a microcontroller, a digital signal processor (DSP), a system-on-a-chip, a network computer (NetPC), a set top box, a network hub, a wide area network (WAN) switch, And the like.

6 is a block diagram of a computer system 600 formed with a processor 602 that includes one or more execution units 608 that perform algorithms to perform at least one instruction in accordance with one embodiment of the present invention. While an embodiment may be described in the context of a single processor desktop or server system, alternative embodiments may be included in a multiprocessor system. System 600 is an example of a " hub " system architecture. Computer system 600 includes a processor 602 for processing data signals. The processor 602 may be a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor , A processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor. The processor 602 is coupled to a processor bus 610 that is capable of transferring data signals between the processor 602 and other components within the system 600. [ The elements of system 600 perform their conventional functions known to those skilled in the art.

In one embodiment, the processor 602 includes a level one (L1) internal cache memory 604. Depending on the architecture, the processor 602 may have a single internal cache or multiple levels of internal cache. Alternatively, in another embodiment, the cache memory may be external to the processor 602. [ Other embodiments may also include combinations of both internal and external caches, depending on the particular implementation and needs. The register file 606 may store different types of data in various registers, including integer registers, floating point registers, status registers, and instruction pointer registers.

Execution unit 608, which also includes logic for performing integer and floating-point operations, is also present in processor 602. The processor 602 also includes a microcode (ucode) ROM that stores microcode for a given microcommand. For one embodiment, the execution unit 608 includes logic to handle the packed instruction set 609. By including the packed instruction set 609 in the instruction set of the general purpose processor 602, operations associated with many multimedia applications, along with associated circuitry for executing the instructions, can be performed using the packed data in the general purpose processor 602 . Thus, many multimedia applications can be accelerated and executed more efficiently by using the full width of the data bus of the processor to perform operations on the packed data. This can eliminate the need to transfer smaller units of data over the processor ' s data bus to perform one or more operations on one data element at a time.

Alternate embodiments of the execution unit 608 may also be used in microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. The system 600 includes a memory 620. The memory 620 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM), a flash memory device, or other memory device. The memory 620 may store data and / or instructions represented by data signals that may be executed by the processor 602. [

System logic chip 616 is coupled to processor bus 610 and memory 620. In the illustrated embodiment, system logic chip 616 is a memory controller hub (MCH). The processor 602 may communicate with the MCH 616 via the processor bus 610. The MCH 616 provides a high bandwidth memory path 618 to the memory 620 for storage of instructions and data and graphics commands, data and textures. The MCH 616 directs data signals between the processor 602, the memory 620 and other components within the system 600 and is coupled to the process bus 610, the memory 620, and the system I / And bridges the data signal. In some embodiments, system logic chip 616 may provide a graphics port for coupling to graphics controller 612. The MCH 616 is coupled to the memory 620 via the memory interface 618. The graphics card 612 is coupled to the MCH 616 via an Accelerated Graphics Port (AGP)

The system 600 utilizes a dedicated hub interface bus 622 to couple the MCH 616 to the I / O controller hub (ICH) 630. ICH 630 provides direct access to some I / O devices using the local I / O bus. The local I / O bus is a high speed I / O bus for connecting peripherals to memory 620, chipset, and processor 602. Some examples include a legacy I / O controller 610, including an audio controller 636, a firmware hub (flash BIOS) 628, a wireless transceiver 626, a data storage 624, a user input and keyboard interface 642, A serial expansion port 638 such as a USB (Universal Serial Bus), and a network controller 634. The data storage device 624 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

For another embodiment of the system, an instruction according to one embodiment may be used in a system on chip. One embodiment of a system-on-chip consists of a processor and a memory. One such memory for the system is flash memory. The flash memory may be located on the same die as the process and other system components. Additionally, other logic blocks, such as a memory controller or a graphics controller, may also be located on the system on chip.

7 is a block diagram of a single core processor and a multicore processor 700 with integrated memory controller and graphics according to an embodiment of the present invention. The solid line box in Figure 7 represents a processor 700 with a single core 702A, a system agent 710, a set of one or more bus controller units 716, while the addition of an optional dashed line box, A plurality of cores 702A-N, a set of one or more integrated memory controller unit (s) 714 within system agent unit 710, and an alternative processor 700 with integrated graphics logic 708 .

The memory hierarchy may include one or more levels of cache units 704A-704N in the core, one set or one or more shared cache units 706, and an external memory (e.g., (Not shown). A set of shared cache units 706 may be implemented as a level 2 (L2), level 3 (L3), level 4 (L4), or other level cache, a last level cache (LLC), and / Level cache, such as < RTI ID = 0.0 > a < / RTI > In one embodiment, the ring-based interconnect unit 712 interconnects the integrated graphics logic 708, a set of shared cache units 706, and the system agent unit 710, Any number of known techniques for interconnecting units may be used.

In some embodiments, one or more of the cores 702A-N are multi-threadable.

System agent 710 includes components that coordinate and operate cores 702A-N. The system agent unit 710 may include, for example, a power control unit (PCU) and a display unit. The PCU may include or may include logic and components necessary to adjust the power states of cores 702A-N and integrated graphics logic 708. [ The display unit is for driving one or more externally connected displays.

The cores 702A-N may be homogeneous or heterogeneous in terms of architecture and / or instruction set. For example, some of the cores 702A-N may be sequential, while others may be unordered. As another example, two or more of the cores 702A-N may execute the same instruction set, while others may only execute a subset of the instruction set or may execute a different instruction set.

The processor may be an Intel® Core ™ i3, an Intel® Core ™ i5, an Intel® Core ™ i7, an Intel® Core ™ 2 Duo and an Intel® Core ™ 2 Quad, Intel® Xeon Itanium®, or Intel XScale® processor. Alternatively, the processor may be from another company, such as ARM Holdings, Ltd, MIPS. A processor may be, for example, a special purpose processor, such as a network or communications processor, a compression engine, a graphics processor, a co-processor, an embedded processor, The processor may be implemented on one or more chips. Processor 700 may be implemented on and / or part of one or more substrates using any of a number of process technologies, such as BiCMOS, CMOS, or NMOS, for example.

Referring now to FIG. 8, a block diagram of a second system 800 in accordance with an embodiment of the present invention is shown. 8, a multiprocessor system 800 is a point-to-point interconnect system and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850, . Each processor 870 and 880 may be a processor 700 of a predetermined version.

Although only two processors 870 and 880 are shown, it will be appreciated that the scope of the invention is not limited to this. In other embodiments, a given processor may have one or more additional processors.

Processors 870 and 880 are shown as including integrated memory controller units 872 and 882, respectively. The processor 870 also includes point-to-point interfaces 876 and 878 as part of its bus controller unit; Likewise, the second processor 880 includes P-P interfaces 886 and 888. Processors 870 and 880 may exchange information via a point-to-point (P-P) interface 850 using P-P interface circuits 878 and 888. 8, IMCs 872 and 882 couple processors to respective memories, that is, memory 832 and memory 834, which may be part of the main memory locally attached to each processor. .

Each of the processors 870 and 880 may exchange information with the chipset 890 via the respective P-P interfaces 852 and 854 using point-to-point interface circuits 876, 894, 886 and 898. The chipset 890 may also exchange information with the high performance graphics circuit 838 via the interface circuit 892 along with the high performance graphics interconnect 839.

A shared cache (not shown) may be included in either processor or external to both processors, but still be connected to the processors via the PP interconnect, so that if the processor is placed in a low power mode, Information can be stored in the shared cache.

The chipset 890 may be coupled to the first bus 816 via interface 896. In one embodiment, the first bus 816 may be a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or another third generation I / O interconnect bus, It does not.

8, various I / O devices 814 may be coupled to the first bus 816, along with a bus bridge 818 that couples the first bus 816 to the second bus 820, . In one embodiment, the second bus 820 may be a low pin count (LPC) bus. A storage unit such as a disk drive or other mass storage device that may include, for example, a keyboard and / or mouse 822, a communication device 827, and in one embodiment instructions / code and data 830 828 may be coupled to the second bus 820. Audio I / O 824 may also be coupled to second bus 820. Note that other architectures are possible. For example, instead of the point-to-point architecture of FIG. 8, the system may implement a multi-drop bus or other such architecture.

Referring now to FIG. 9, a block diagram of an SoC 900 in accordance with an embodiment of the present invention is shown. The dotted box is also an optional feature for more advanced SoCs. 9, interconnect unit (s) 902 includes: an application processor 910 including a set of one or more cores 902A-N and a shared cache unit (s) 906; A system agent unit 910; Bus controller unit (s) 916; Integrated memory controller unit (s) 914; An integrated graphics logic 908, an image processor 924 for providing still and / or video camera functionality, an audio processor 926 for providing hardware audio acceleration, and a video encoder / A set of one or more media processors 920 that may include a video processor 928; A static random access memory (SRAM) unit 930; A direct memory access (DMA) unit 932; And a display unit 940 for coupling to one or more external displays.

At least one aspect of at least one embodiment may be embodied by symbolic data stored in a machine-readable medium representing various logic within the processor and causing the machine to produce logic to perform the techniques described herein when read by the machine . These representations, known as " IP cores ", may be stored in a type of machine-readable medium (" tape ") and may be supplied to various customers or manufacturing facilities for loading into a production machine that actually creates the logic or processor. For example, IP cores such as the Cortex (TM) processor family developed by ARM Holdings, Ltd., and Loongson IP cores developed by the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences, , Qualcomm®, Apple®, or Samsung®, and can be implemented in processors manufactured by these customers or license producers.

Figures 6-8 are exemplary systems suitable for including processor 700 while Figure 9 illustrates an exemplary system on a chip (SoC), which may include one or more of cores 702. [ to be. A digital signal processor (DSP), a graphics device, a video game device, a set-top box, a microprocessor, a microprocessor, a microprocessor, Other system designs and configurations known in the art for controllers, cell phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices capable of merging the processor and / or other execution logic described herein are generally suitable.

10 illustrates a processor including a central processing unit (CPU) and a graphics processing unit (GPU), which can perform at least one instruction in accordance with one embodiment. In one embodiment, an instruction to perform an operation according to at least one embodiment may be performed by the CPU. In another embodiment, the instructions may be performed by a GPU. In yet another embodiment, the instructions may be performed through a combination of operations performed by the GPU or the CPU. For example, in one embodiment, an instruction according to one embodiment may be received and decoded for execution in the GPU. However, one or more operations in the decoded instruction may be performed by the CPU and the result may be returned to the GPU for final discard of the instruction. Conversely, in some embodiments, the CPU serves as a primary processor and the GPU may serve as a coprocessor.

In some embodiments, instructions benefiting from a highly parallel processing processor may be performed by a GPU, while instructions that benefit from the performance of processors benefiting from a deeply piped architecture may be performed by the CPU have. For example, graphics, scientific applications, financial applications, and other parallel workloads can benefit from the performance of the GPU and be executed accordingly, while more sequential applications such as the operating system kernel or application code are more suitable for CPUs can do.

10, the processor 1000 includes a CPU 1005, a GPU 1010, an image processor 1015, a video processor 1020, a USB controller 1025, a UART controller 1030, an SPI / SDIO controller 1035 A display device 1040, a memory interface controller 1045, a MIPI controller 1050, a flash memory controller 1055, a dual data rate (DDR) controller 1060, a security engine 1065, and an I2S / (1070). Other logic and circuits, including more CPUs or GPUs and other peripheral interface controllers, may be included in the processor of FIG.

At least one aspect of at least one embodiment may be embodied by symbolic data stored in a machine-readable medium representing various logic within the processor and causing the machine to produce logic to perform the techniques described herein when read by the machine . These representations, known as " IP cores ", may be stored in a type of machine-readable medium (" tape ") and may be supplied to various customers or manufacturing facilities for loading into a production machine that actually creates the logic or processor. For example, IP cores such as the Cortex (TM) processor family developed by ARM Holdings, Ltd., and Loongson IP cores developed by the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences, , Qualcomm®, Apple®, or Samsung®, and can be implemented in processors manufactured by these customers or license producers.

Referring to FIG. 11, an embodiment of a processor including a plurality of cores is shown. The processor 1100 may be a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on chip (SOC) And includes any processor or processing device. The processor 1100, in one embodiment, includes at least two core-cores 1101 and 1102, which may include an asymmetric core or a symmetric core (illustrated embodiment). However, the processor 1100 may include any number of processing elements that may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic that supports a software thread. Examples of hardware processing elements include, but are not limited to: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and / Other optional elements are included. That is, a processing element is, in one embodiment, any hardware that can be independently associated with a software thread, operating system, application, or other code. A physical processor is typically an integrated circuit potentially containing any number of other processing elements, such as a core or a hardware thread.

A core is often logic located on an integrated circuit that can maintain its independent architectural state, where each independently maintained structural state is associated with at least some dedicated execution resources. In contrast to a core, a hardware thread is typically any logic located on an integrated circuit that can maintain its independent structural state, where the independently maintained structural state shares access to execution resources. As can be seen, when a given resource is shared and other resources are dedicated to a given architectural state, the boundaries between the terms hardware thread and core are superimposed. Often, however, the core and hardware threads are recognized by the operating system as individual logical processors, where the operating system can schedule operations separately on each logical processor.

As shown in FIG. 11, the physical processor 1100 includes two cores, cores 1101 and 1102. Here, cores 1101 and 1102 are considered to be symmetric cores, i.e. cores having the same configuration, functional unit, and / or logic. In another embodiment, core 1101 includes an out-of-order processor core, while core 1102 includes a sequential processor core. However, the cores 1101 and 1102 may be implemented as a native core, a software managed core, a core adapted to execute a native ISA (Instruction Set Architecture), a core adapted to execute a translated ISA, for example, a core, a cores, a cores, a cores, a cores, a cores, a cores, a cores, a cores or a cores. However, for further discussion, the functional units shown in the core 1101 are described in more detail below, since the units in the core 1102 operate in a similar manner.

As shown, the core 1101 includes two hardware threads 1101a and 1101b, which are also referred to as hardware thread slots 1101a and 1101b. Thus, software entities, such as operating systems, in one embodiment potentially regard processor 1100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads simultaneously. As noted above, the first thread is associated with the architecture status register 1101a, the second thread is associated with the architecture status register 1101b, the third thread is associated with the architecture status register 1102a, Four threads are associated with the architecture status register 1102b. Here, each of the architecture status registers 1101a, 1101b, 1102a, and 1102b may be referred to as a processing element, a thread slot, or a thread unit, as described above. As illustrated, the architecture state register 1101a is replicated in the architecture state register 1101b, so that individual architectural states / contexts can be stored for the logical processor 1101a and the logical processor 1101b. At core 1101, other smaller resources, such as the instruction pointer and renaming logic in allocator and renamer block 1130, may also be replicated for threads 1101a and 1101b. Some resources, such as the reorder buffer, ILTB 1120, load / store buffer, and queue in reorder / destroy unit 1135, may be shared through partitioning. Such as portions of the general purpose internal register, page-table base register (s), low-level data-cache and data-TLB 1115, execution unit (s) 1140, Are potentially fully shared.

Processor 1100 often includes other resources that may be fully shared, shared through partitioning, or may be dedicated to / processing elements by processing elements. In Fig. 11, an example of a purely example processor with an example logical unit / resource of a processor is shown. It is noted that the processor may include or omit any of these functional units, as well as any other known functional units, logic, or firmware not shown. As illustrated, the core 1101 includes a simplified, exemplary, out-of-order processor core. However, sequential processors may be used in different embodiments. The OOO core includes a branch target buffer 1120 for predicting branches to be executed / taken and an instruction-to-translate buffer (I-TLB) 1120 for storing address translation entries for the instructions.

The core 1101 further includes a decode module 1125 coupled to a fetch unit 1120 to decode the fetched element. The fetch logic, in one embodiment, includes an individual sequencer associated with each thread slot 1101a, 1101b. Core 1101 is typically associated with a first ISA that defines / specifies instructions that are executable on processor 1100. Machine code instructions, which are often part of the first ISA, include a portion of an instruction (referred to as opcode) that references / specifies the instruction or operation to be performed. Decode logic 1125 includes circuitry that recognizes these instructions from their opcode and passes decoded instructions in the pipeline for processing defined by the first ISA. For example, as discussed in greater detail below, the decoder 1125 includes, in one embodiment, logic designed or adapted to recognize a particular instruction, such as a transactional instruction. As a result of recognition by the decoder 1125, the architecture or core 1101 takes a specific, predefined action to perform the task associated with the appropriate instruction. Any of the tasks, blocks, acts, and methods described herein may be performed in response to a single instruction or a plurality of instructions; It is important to note that some of these may be new or old instructions.

In one example, the allocator or identifier block 1130 includes an allocator that reserves resources, such as register files, that store the instruction processing results. However, threads 1101a and 1101b may be periodically non-sequential running, where the allocator and identifier block 1130 also reserves other resources such as a reordering buffer that tracks the result of the instruction. The unit 1130 may also include a register rename to rename the program / instruction reference register to another register within the processor 1100. The reordering / discarding unit 1135 includes components such as the reordering buffer, load buffer, and storage buffer described above to support sequential discard of non-sequential execution and subsequent nonsequential instructions.

The scheduler and execution unit (s) block 1140, in one embodiment, includes a scheduler unit for scheduling instructions / operations on the execution unit. For example, a floating-point instruction is scheduled on a port of an execution unit having an available floating-point execution unit. A register file associated with the execution unit is also included to store the information instruction processing result. An exemplary execution unit includes a floating-point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a storage execution unit, and other known execution units.

The low-level data cache and data conversion buffer (D-TLB) 1150 are coupled to the execution unit (s) The data cache is for storing recently used / computed elements, such as data operands, that are potentially maintained in a memory coherency state. The D-TLB is intended to store the recent virtual / linear-to-physical address translation. As a specific example, a processor may include a page table structure that divides physical memory into a plurality of virtual pages.

Here, cores 1101 and 1102 share access to a higher-level or further-out cache 1110 that caches recently fetched elements. It should be noted that the upper level or the potential refers to an increasing or decreasing cache level from the execution unit (s). In one embodiment, the higher level cache 1110 is the last cache in the memory hierarchy on the last level data cache-processor 1100, such as a second or third level data cache. However, the upper level cache 1110 is not limited to this, as it may be associated with or may include a command cache. Instead, a trace cache - a sort of instruction cache - can be combined after the decoder 1125 to store recently decoded traces.

In the illustrated configuration, the processor 1100 also includes a bus interface module 1105. [ Historically, a controller 1170, described in more detail below, has been included in a computing system external to the processor 1100. In this scenario, bus interface 1105 includes a system memory 1175, a chipset (which often includes an I / O controller hub that connects peripheral devices with a memory controller hub that connects to memory 1175), a memory controller hub For example, an integrated circuit, a microprocessor, a microprocessor, a microprocessor, a microprocessor, a microprocessor, a microprocessor, a microprocessor, a microprocessor, In this scenario, the bus 1105 may be implemented using any of a variety of bus architectures, including a multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherent) bus, Differential bus, GTL bus, and the like.

Memory 1175 can be dedicated to processor 1100 or shared with other devices in the system. Common examples of types of memory 1175 include DRAM, SRAM, nonvolatile memory (NV memory), and other known storage devices. The device 1180 includes a graphics accelerator, a processor or card coupled to a memory controller hub, a data storage coupled to an I / O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, It should be noted that

It should be noted, however, that in the illustrated embodiment, the controller 1170 is illustrated as part of the processor 1100. Recently, as more logic and devices are integrated on a single die such as SOC, each of these devices can be included on the processor 1100. For example, in one embodiment, the memory controller hub 1170 is on the same package and / or die as the processor 1100. Here, a portion (on-core portion) of the core includes one or more controller (s) 1170 for interfacing with other devices, such as memory 1175 or graphics device 1180. Configurations involving controllers and interconnects for interfacing with such devices are often referred to as on-core (or un-core configurations). By way of example, bus interface 1105 includes a ring interconnect with a memory controller for interfacing with memory 1175 and a graphics controller for interfacing with graphics processor 1180. However, in an SOC environment, much more devices, such as a network interface, coprocessor, memory 1175, graphics processor 1180, and any other known computer device / interface may be integrated on a single die or integrated circuit, Functionality and low power consumption.

In one embodiment, the processor 1100 may be configured to compile, transform, and / or optimize application code 1176 by executing compiler, optimizer, and / or converter code 1177 to support the devices and methods described herein You can interface with it. Compilers often include programs or sets of programs that convert source text / code to target text / code. Typically, compilation of program / application code using a compiler consists of a plurality of phases and passes to translate high level programming language code into low level machine or assembly language code. However, for simple compilation, a single pass compiler can still be used. The compiler may use any known compilation technique and perform any known compiler operations such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code conversion, and code optimization.

Larger compilers often include multiple phases, but most of these phases are included in two general phases: (1) front-end, i.e., generally syntactic, semantic, Where optimizations can be made, (2) where back-end, ie analysis, transformation, optimization, and code generalization occurs. Some compilers represent the middle of showing the opacity of the boundary between the front-end and the back-end of the compiler. As a result, references to insertion, association, generation, or other operations of the compiler may occur in any of the above-mentioned phases or passes, as well as any other known phases or passes of the compiler. By way of illustration, the compiler potentially includes operations, calls, functions in one or more phases, such as insertion of calls / operations in the front-end phase of compilation and conversion of calls / operations into lower- And so on. Note that during dynamic compilation, compiler code or dynamic optimization code not only inserts these operations / calls, but also optimizes the code for execution during runtime. As a specific example, the binary code (already compiled code) can be dynamically optimized during runtime. Here, the program code may include a dynamic optimization code, a binary code, or a combination thereof.

Similar to a compiler, a converter such as a binary converter optimizes and / or converts code by statically or dynamically converting the code. Accordingly, references to the execution of code, application code, program code, or other software environment may include: (1) compiling the program code, maintaining the software structure, performing other operations, optimizing the code, Dynamic or static execution of the compiler program (s), optimizing code optimizer, or converter for conversion; (2) execution of main program code including operations / calls, such as optimized / compiled application code; (3) execution of other program code, such as a library associated with the main program code, to maintain the software structure, perform other software-related operations, or optimize the code; Or (4) a combination thereof.

Referring now to FIG. 12A, a block diagram of an embodiment of a multicore processor is shown. As shown in the embodiment of FIG. 12A, the processor 1200 includes a plurality of domains. In particular, the core region 1230 may include a plurality of cores 1230A-1230N, the graphics region 1260 may include one or more graphics engines including a media engine 1265, Region 1210 may further be present.

In various embodiments, the system agent region 1210 processes power control events and power management, in which individual units of regions 1230 and 1260, such as the core and / or graphics engine, In a suitable power mode (including low power state or activity, and possibly a turbo mode state) in light of the current state of the system (e.g., activity). Each of the regions 1230 and 1260 can operate at different voltages and / or powers, and further, each of the individual units within the regions can operate at independent frequencies and voltages. Although only three regions are shown, it should be noted that the scope of the invention is not limited in this respect, and that additional regions may exist in other embodiments.

In general, each core 1230 may further include a lower level cache in addition to the various execution units and additional processing elements. Next, the various cores may be coupled together and coupled to a shared cache memory formed of a plurality of units or slices of a last level cache (LLC) 1240A-1240N that may include storage and cache controller functionality have. In various embodiments, the LLC 1240 may be shared between various media processing circuits as well as cores and graphics engines.

As can be seen, the ring interconnect 1250 couples the cores together, and through the plurality of ring stops 1252A-1252N at the junction between the core and the LLC slice, the core region 1230, Region 1260, and system agent circuitry 1210, as shown in FIG. As can be seen in FIG. 12A, the interconnect 1250 can be used to carry various information, including address information, data information, acknowledgment information, and snoop / invalid information.

As further seen, the system agent area 1210 can include a display engine 1212 that can provide control and associated interfaces to associated displays. The system agent area 1210 includes an integrated memory 1220 that provides an interface to system memory, such as a DRAM (e.g., comprising a plurality of DIMMs), and is coupled to the consistency logic 1222 to perform memory coherency operations And may further include a controller 1220. A plurality of interfaces may be present to enable an interconnect between the processor and other circuitry. For example, in one embodiment, at least one PCIe ™ interface 1214 may be provided as well as at least one direct media interface (DMI) 1216 interface. As can be seen, the display engine and these interfaces can be coupled to the memory via the PCIe (TM) bridge 1218. Still further, one or more other interfaces may also be provided, such as in accordance with the Intel® Quick Path Interconnect (QPI) protocol, to provide communication between other agents, such as additional processors or other circuitry.

Referring now to FIG. 12B, a block diagram of an exemplary core, such as one of the cores 1230 of FIG. 12A, is shown. In general, the structure shown in FIG. 12B generally includes instructions for fetching fetch instructions, performing various processes including decoding, and performing them on fetch data to be processed, data processing for these decoded instructions, Sequential processor that includes a front-end unit 1270 that is used to communicate to an unordered engine 1280 that may perform additional processing, including reordering the processed data.

Specifically in the embodiment of Figure 12B, the non-sequential engine 1280 receives decoded instructions, which may be in the form of one or more microinstructions or uops, from the front-end unit 1270 and assigns them to the appropriate resources, such as registers And the like. The instruction may then be provided to a reservation station 1284 that can reserve an instruction for execution on one of the plurality of execution units 1286A-1286N. For example, various types of execution units may exist, in particular, including arithmetic logic units (ALU), vector processing units (VPUs), floating point execution units, and the like. The results from these different execution units may be provided to a reordering buffer (ROB) 1288 that can take these unaligned results and return them to the correct program order.

Still referring to FIG. 12B, it is noted that the front-end unit 1270 and the non-sequential engine 1280 may be coupled to different levels of memory hierarchy. Specifically, an instruction level cache 1272 is shown, which may be then coupled to an intermediate level cache 1276, which in turn is coupled to a last level cache < RTI ID = 0.0 > Which may be coupled to an uncore unit 1295, which, in one embodiment, generally corresponds to a system agent circuit, such as the system agent region 1210 of Figure 12B, Lt; RTI ID = 0.0 > 1290 < / RTI > Next, the last level cache 1295 may communicate with higher levels of the memory hierarchy, including system memory 1299, which may be implemented via ED RAM in one embodiment. Note also that the various execution units 1286 in the non-sequential engine 1280 can communicate with the first level cache 1274, which also communicates with the intermediate level cache 1276. [ Note that additional cores 1230N-2 through 1230N may be coupled to LLC 1295. [ It should be appreciated that although this high level is shown in the embodiment of FIG. 12B, various changes and additional components may be present.

13 is a block diagram of a micro-architecture for a processor 1300 that includes logic circuitry to perform instructions in accordance with one embodiment of the present invention. In some embodiments, an instruction according to one embodiment may be computed for data elements having a data type such as a byte, word, double word, quad word, etc., as well as a single degree and double precision integer and a floating point data type Can be implemented. In one embodiment, sequential frontend 1301 is part of processor 1300 that fetches the instruction to be executed and prepares it for later use in the processor pipeline. The front end 1301 may include several units. In one embodiment, instruction prefetcher 1326 fetches instructions from memory and provides them to instruction decoder 1328, which in turn decodes or interprets them. For example, in one embodiment, the decoder decodes the received instruction into one or more operations called "micro-operations" or "micro-operations" (also referred to as micro-ops or uops) that the machine can execute. In another embodiment, the decoder parses the instructions into op-codes and corresponding data and control fields that are used by the micro-architecture to perform operations according to one embodiment. In one embodiment, the trace cache 1330 takes the decoded uops and assembles them into a program ordered sequence or trace in a uop queue 1334 for execution. When the trace cache 1330 encounters a complex instruction, the microcode ROM 1332 provides the uops necessary to complete the operation.

Some instructions are converted to a single micro op, while other instructions require several micro ops to complete the entire operation. In one embodiment, if more than four micro-ops are needed to complete an instruction, the decoder 1328 accesses the microcode ROM 1332 to execute the instruction. In one embodiment, the instruction may be decoded into a small number of micro ops for processing in instruction decoder 1328. [ In yet another embodiment, instructions may be stored in the microcode ROM 1332 if a plurality of micro ops are required to accomplish the operation. The trace cache 1330 references an entry point programmable logic array (PLA) to determine a correct microinstruction pointer for reading a microcode sequence to complete one or more instructions in accordance with one embodiment from microcode ROM 1332 do. After the microcode ROM 1332 terminates sequencing of the microops of the instruction, the machine front end 1301 resumes retrieving the microop from the trace cache 1330.

The non-sequential execution engine 1303 is where the instructions are prepared for execution. The non-sequential execution logic has a number of buffers for smoothing and reordering the instructions to optimize performance as the instructions go down the pipeline and are scheduled for execution. The allocator / register identifier 1305 includes allocator logic and register rename logic. The allocator logic allocates machine buffers and resources that each uop requires in order for execution. The register renaming logic renders the logic registers into entries in the register file. The allocator also includes two uop queues preceding the instruction schedulers: memory scheduler 1309, fast scheduler 1302, low / normal floating point scheduler 1304, and simple floating point scheduler 1306, And allocates an entry for each uop of one of the memory uop queue 1307a for operation and the integer / floating point uop queue 1307b for non-memory operation. The uop schedulers 1302, 1304, 1306, and 1309 determine when the uop is ready to execute based on the availability of their dependent input register operand sources and the availability of the execution resources that uops need to complete their operation do. The fast scheduler 1302 in one embodiment can schedule in each half of the main clock cycle while the other schedulers can schedule only once in each main processor clock cycle. Schedulers arbitrate dispatch ports to schedule uops for execution.

Register files 1308 and 1310 are placed between the schedulers 1302,1304,1306 and 1309 and the execution units 1312,1314,1316,1318,1320,1322 and 1324 in the execution block 1311. [ There are separate register files 1308 and 1310 for integer and floating point operations, respectively. Each register file 1308, 1310 of an embodiment also includes a bypass network that can only forward or bypass completed results that have not yet been written in the register file to the new dependent uops. The integer register file 1308 and the floating-point register file 1310 can also transfer data to each other. In one embodiment, the integer register file 1308 is divided into two separate register files, one register file for the lower 32 bits of data and a second register file for the upper 32 bits of data. The floating point register file 1310 in one embodiment has a 128 bit wide entry because floating point instructions typically have an operand of 64 to 128 bits wide.

Execution block 1311 includes execution units 1312, 1314, 1316, 1318, 1320, 1322, 1324, where the instructions are actually executed. This partition includes register files 1308 and 1310 that store the integer and floating point data operand values needed for the microinstruction to be executed. The processor 1300 of one embodiment includes a plurality of execution units: an address generation unit (AGU) 1312, an AGU 1314, a high speed ALU 1316, a high speed ALU 1318, a low speed ALU 1320, a floating point ALU A floating point unit 1322, and a floating point mobile unit 1324. For one embodiment, the floating-point execution blocks 1322 and 1324 perform floating point, MMX, SIMD, and SSE, or other operations. The floating-point ALU 1322 of one embodiment includes a 64-bit by 64-bit floating-point divider that performs the division, the square root, and the remainder of the micro ops. In the case of embodiments of the present invention, instructions involving floating-point values may be handled by the floating-point hardware. In one embodiment, the ALU operation goes to a fast ALU execution unit 1316, 1318. The high speed ALUs 1316 and 1318 of one embodiment can perform high speed operations with an effective latency of half of the clock cycle. In one embodiment, the slow ALU 1320 includes integer execution hardware for long latency type operations such as multiplier, shift, flag logic, and branch processing, so most complex integer operations go to the slow ALU 1320. The memory load / store operations are performed by the AGUs 1312 and 1314. For one embodiment, integer ALUs 1316, 1318, 1320 are described in the context of performing integer operations on 64-bit data operands. In an alternative embodiment, ALUs 1316, 1318, 1320 may be implemented to support various data bits, including 16, 32, 128, 256, and so on. Similarly, floating point units 1322 and 1324 may be implemented to support various operands having varying widths of bits. In one embodiment, the floating-point units 1322 and 1324 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

In one embodiment, the uop schedulers 1302, 1304, 1306, and 1309 dispatch dependent operations before the parent load ends execution. Since the uops are speculatively scheduled and executed in the processor 1300, the processor 1300 also includes logic to handle memory misses. If the data load in the data cache is inadequate, there may be dependent operations that are staying in the pipeline leaving the scheduler with temporary inaccurate data. The replay mechanism tracks and reruns commands that use inaccurate data. Only dependent operations need to be replayed and independent operations are allowed to complete. The scheduler and replay mechanism of one embodiment of the processor is also designed to capture instruction sequences for text string comparison operations.

The term " registers " may refer to an onboard processor storage location used as part of an instruction identifying an operand. That is, the registers (from the programmer's point of view) are available from outside the processor. However, the registers of the embodiments should not be limited to circuits of a particular type in meaning. Rather, the registers of an embodiment may store and provide data and may perform the functions described herein. The registers described herein may be implemented by circuitry within the processor using any number of different techniques, such as a dedicated physical register, a physical register dynamically allocated using a register name, a combination of dedicated and dynamically allocated physical registers, . In one embodiment, the integer register stores 32-bit integer data. The register file of one embodiment also includes eight SIMD registers for packed data. For the following discussion, the registers may be stored in a packed, nonvolatile memory, such as a 64 bit wide MMX register (sometimes referred to as an 'mm' register) within a MMX ™ technology enabled microprocessor from Intel Corporation of Santa Clara It is understood to be a data register designed to hold data. These MMX registers, which are available in both integer and floating point types, can operate with packed data elements that accompany SIMD and SSE instructions. Similarly, a 128 bit wide XMM register associated with the description of SSE2, SSE3, SSE4 or more (generically referred to as " SSEx ") can also be used to hold these packed data operands. In one embodiment, in storing packed and integer data, the register need not distinguish between the two data types. In one embodiment, integer and floating point numbers are included in the same register file or in different register files. Further, in one embodiment, floating point and integer data may be stored in different registers or the same register.

Figure 14 is a block diagram illustrating a sequential pipeline and register list, a nonsequential issue / execution pipeline, in accordance with at least one embodiment of the present invention. Figure 14 is a block diagram illustrating sequential architecture cores and register renaming logic, unsequenced issue / execute logic included in a processor in accordance with at least one embodiment of the present invention. In Fig. 14, solid line boxes represent sequential pipelines, while dashed boxes represent register renames, nonsequential issue / execution pipelines. Likewise, solid line boxes in FIG. 14 represent sequential architecture logic while dashed boxes represent register renaming logic and nonsequential issuing / execution logic.

In Figure 14, the processor pipeline 1400 includes an output stage 1402, a length decode stage 1404, a decode stage 1406, an assignment stage 1408, a list stage 1410, (also known as dispatch or issue) The scheduling stage 1412, the register read / memory read stage 1414, the execute stage 1416, the write back / memory write stage 1418, the exception handling stage 1422, .

In Fig. 14, the arrows indicate the combination of two or more units, and the direction of the arrows indicate the direction of the data flow between these units. 14 illustrates a processor core 1490 that includes a front end unit 1430 coupled to execution engine unit 1450 and both execution engine unit 1450 and front end unit 1430 are coupled to memory unit 1470 ).

Core 1490 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. Still another option, the core 1490 may be a special purpose core, such as, for example, a network or communications core, a compression engine, a graphics core, or the like.

Front end unit 1430 includes a branch prediction unit 1434 coupled to instruction cache unit 1434 coupled to instruction translation unit 1434 coupled to instruction fetch unit 1438 coupled to decode unit 1440, (1432). Decode units or decoders decode the instructions and generate as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from the original instruction, It reflects the original command or is derived from the original command. Decoders may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), and the like. Instruction cache unit 1434 is also coupled to a level two (L2) cache unit 1476 in memory unit 1470. Decode unit 1440 is coupled to rename / assignor unit 1452 in execution engine unit 1450.

Execution engine unit 1450 includes a renumber / allocator unit 1452 coupled to a discard unit 1454 and a set of one or more scheduler unit (s) 1456. The scheduler unit (s) 1456 may represent any number of different schedulers, including scheduler, central command window, and so on. Scheduler unit (s) 1456 are coupled to physical register file (s) unit (s) 1458. [ Each of the physical register file (s) units 1458 represents one or more physical register files, wherein the different registers are scalar, scalar floating, packed integer, packed floating point, vector integer, vector floating (E.g., a pointer to an instruction that is the address of the next instruction to be performed), and so on. The physical register file (s) unit (s) 1458 may be overlapped by the discarding unit 1454 such that the future file (s), such as the reorder buffer (s) , History buffer (s), and discard register file (s), using register maps and register pools, etc.) Register Renames and non-sequential executions can be implemented. In general, architectural registers can be viewed from outside the processor or from a programmer's perspective. These registers are not limited to any particular type of circuit known in the art. As long as data can be stored and provided as described herein, a variety of different types of registers are appropriate. Examples of suitable registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register names, and combinations of dedicated and dynamically allocated physical registers. Destroy unit 1454 and physical register file (s) unit (s) 1458 are coupled to execution cluster (s) 1460. The execution cluster (s) 1460 includes a set of one or more execution units 1462 and a set of one or more memory access units 1464. Execution unit 1462 may perform various operations (e.g., shift, add, subtract, multiply) and may include various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, Vector floating point). Some embodiments may include a plurality of execution units dedicated to a particular function or set of functions, but other embodiments may include only one execution unit, or a plurality of execution units, all of which perform all functions. The scheduler unit (s) 1456, physical register file (s) unit (s) 1458, and execution cluster (s) 1460 are shown as possibly multiple, (E.g., scalar integer pipeline, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or each of its own scheduler In the case of a memory access pipeline, a separate memory access pipeline, with a unit, physical register file (s), and / or execution clusters, only the execution cluster of this pipeline has a predetermined The embodiment can be implemented). It should also be understood that when separate pipelines are used, one or more of these pipelines may be nonsequential issue / execution and the remainder may be sequential.

A set of memory access units 1464 is coupled to a memory unit 1470 and a memory unit 1470 is coupled to a data TLB unit 1470 coupled to a data cache unit 1474 coupled to a level two (1472). In one exemplary embodiment, memory access unit 1464 may include a load unit, an address storage unit, and a data storage unit, each of which is coupled to a data TLB unit 1472 in memory unit 470. L2 cache unit 1476 is coupled to one or more other levels of cache and eventually to main memory.

By way of example, the exemplary register rename, nonsequential issue / execute core architecture may implement pipeline 400 as follows: 1) instruction fetch 1438 performs fetch and length decoding stages 1402 and 1404 ; 2) Decode unit 1440 performs decode stage 1406; 3) rename / allocator unit 1452 performs allocation stage 1408 and list stage 1410; 4) The scheduler unit (s) 1456 performs the scheduling stage 1412; 5) The physical register file (s) unit (s) 1458 and memory unit 1470 perform a register read / memory read stage 1414; Execution cluster 1460 performs execution stage 1416; 6) The memory unit 1470 and the physical register file (s) unit (s) 1458 perform a write back / memory write stage 1418; 7) Exception handling stage 1422 may involve various units; And 8) Destroy unit 1454 and physical register file (s) unit (s) 1458 perform a commit stage 1424.

Core 1490 may include one or more instruction sets (e.g., an x86 instruction set (with some extensions added to the newer version)); MIPS Technologies' MIPS instruction set from Sunnyvale, CA; CA, ARM Holdings of Sunnyvale (with optional additional extensions such as NEON).

The core can support multithreading (running more than one parallel set of operations or threads), time-divisional multithreading (for a single physical core, for each thread that the physical core can simultaneously multithread (E.g., providing logical cores), or combinations thereof (e.g., time-division fetching and decoding such as Intel® Hyperthreading technology, and concurrent multithreading thereafter). shall.

While register renames have been described in the context of nonsequential execution, it should be understood that register renames may be used in sequential architectures. Although the exemplary embodiment of the processor also includes a separate instruction and data cache units 1434/1474 and a shared L2 cache unit 1476, an alternative embodiment may include a single internal < RTI ID = 0.0 > Cache, for example, a level 1 (L1) internal cache, or may have multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache external to the core and / or processor. Alternatively, both caches may be external to the core and / or processor.

In an embodiment, the display comprises a touch screen or other touch sensitive display. The touch sensitive display (or touch screen) may include an active area and an inactive area. The active area is the area that receives the touch input and one component of the platform responds to the touch input (such as through the display). The inactive area may be the area of the touch-sensitive display (or touch screen) that does not respond to the touch input. That is, even if the touch input is provided in the inactive area, the platform may not change the display or perform any other operation. The platform may appear to be unaware of the touch input (for the inactive area) by the platform.

Embodiments may also be applicable to phoneable computing devices that may switch between a clamshell mode and a tablet mode. In a switchable computing device, the lid or display may be referred to as a tablet or tablet display (including a touch-sensitive display). However, in a switchable computing device, the tablet display (or lid) may not be detached from the base.

Embodiments may control the active area (or active display area) of the touch-sensitive display (or touch screen) based on the operating mode of the tablet or based on user input. For example, in the clamshell mode, the touch-sensitive display (or touch screen) is larger than when the touch-sensitive display (or touch screen) is on both of the tablets that can have a small active area It may have an active area (or a large display area). The size of the inactive area (or virtual bezel) of the touch-sensitive display (or touch screen) may also vary based on the changed size of the active area. This may allow for easier holding of the tablet while accidentally touching the active area. The inactive area can be referred to as a virtual bezel, which is a bezel area that decreases or increases in size by changing the active display of the display.

The user may hold the tablet with his or her hand. Thus, when using a touch-enabled tablet, a large bezel area is desirable because it does not block the display area (or active display area) when the user is holding the tablet by hand or does not cause an inadvertent touch event. However, when in the clamshell mode, it may be desirable to have a bezel as small as possible to maximize the active display area, which is no longer needed. In electronic devices (e.g., detachable tablets or switchable laptops) that operate in both tablet mode and clamshell mode, the virtual bezel can provide an optimal display area depending on how the electronic device is being used.

The virtual bezel may have an adjustable color boundary around the outer edge of the display. By increasing or decreasing the boundary around the display, the display may appear to change size. A change in pixel size may be performed by the display hardware and / or the OS driver so that the OS may not be affected by the physical translation of the display area size.

Embodiments enable effective use of the bezel by displaying content through dynamic real-time determination to render the content in a bezel region for a display with touch screen capabilities. A bezel area where content can be dynamically rendered is called a virtual bezel, and a system in which a bezel area is dynamically turned on or off to present content is called a virtual bezel-based system. The virtual bezel enables display rendering in the bezel area in addition to the primary display.

Embodiments use intelligence to determine when and how to use the bezel region to display content, where this intelligent enable of the bezel for display rendering may be through a combination of criteria. A decision vector (such as sensor, device configuration, content type, primary display activity, etc.) can be used in an intelligent manner to enable / disable the display area for rendering. Each side (left, right, top, bottom) of the bezel can be controlled independently of their enable / disable as well as the type of content being rendered. The content may be rendered on the display based on the content (primary display content) being displayed, the periphery of the display (environment, other devices), and user preferences. Smooth content movement and interaction between the primary display and the bezel region can be realized.

Embodiments can provide a computing device that includes a touch-sensitive display and display logic wherein at least a portion of the display is hardware. The display logic can control the size of the active area of the touch-sensitive display and the size of the inactive area of the touch-sensitive display based on the configuration of the device, the content to be displayed, and the like. As described herein, the display logic may perform additional operations in different embodiments.

In various embodiments, the platform may be a distributed (or distributed) system of human interface device (HID) data in a manner that enables a processor or other processor of the platform, such as a system- Pre-processing can be enabled. More specifically, the embodiment performs distributed filtering of HID information received from the user when the information is present in the inactive portion of the HID. Although the embodiments described herein relate to preprocessing dispersed in the context of a touch screen HID, the scope of the invention is not limited in this respect, but rather includes a touchpad or other touch input device, a mouse, It should be appreciated that other implementations may be used in conjunction with other HIDs.

A controller associated with the HID, such as a touch screen controller, may include logic to perform this dispersed preprocessing to filter out any touch inputs received within the inactive area. As an example described herein, these inactive zones may correspond to portions of the touch screen that overlap with inactive portions of the display, such as a virtual bezel. Other examples include an inactive area corresponding to an area outside the user input feature that is enabled by an active soft button or the like.

In some implementations, instead of controlling the secondary display area configured at the display periphery and around the primary display, a plurality of arbitrary shaped windows may be provided to enable reception of user input. For example, a movie or other video content may be displayed in the primary display area, for example, a set of active optional display areas under the display may include a movie and / or audio control button, e.g., A scene, a previous scene, a pause, a stop, a playback, an audio up / down, a view, and the like. In this example, while the movie is being played in the minimum display area (e.g., 720 pixel version) in the virtual bezel mode, the movie image corresponding to the soft button or any touch within the predetermined sub- May be delivered to the processor. Other touch events, such as the thumb around the bezel, can be filtered and not passed on the touch screen controller.

Many displays are craving low power capabilities using a variety of features. For example, an LED (light emitting diode) display can selectively illuminate pixels in the display while leaving other pixels off (this can be used to turn off most of the primary display but only to see small state images have). Likewise, electronic ink (E-ink) or bistable displays consume zero power while showing a static image to the user. And a display with panel self-refresh technology consumes power while displaying a static image to the user, but allows the rest of the platform to enter a low power state. These low power states are particularly effective when they are only displaying static images, such as when reading E-books or PDF (portable document format) documents.

By way of example, the touch contact in the invalid portion of the touch screen, such as around the outer portion of the display, can be filtered by the touch screen controller. This filtering thereby avoids the generation of an interrupt that prevents the processor / platform from transitioning to a low power state (or causing it to terminate the low power state) by keeping analyzing and discarding invalid touch data over time.

Generally, a touch screen controller is configured to analyze analog touch screen inputs and map them to a digital representation of a human interaction with the touch screen and deliver this information to the processor. In other implementations, the touch controller functionality may be integrated into the touch screen itself, or both the touch screen and the touch screen controller may be integrated into the display panel itself.

Distributed preprocessing of touch screen data can reduce platform power, where the preprocessing component analyzes the (raw) touch screen data or a subset of the touch screen data to determine its suitability within the touch screen data. In different embodiments, these preprocessing components may be implemented in hardware such as register transfer level (RTL) or microcode. The preprocessing component may be proximate to or within the touch screen. The touch screen may be proximate to a primary (or secondary) display or an external display (or display) of the platform. For example, the distributed processing may be implemented anywhere in the data path between the touch screen and the processor.

Referring now to FIG. 15A, a block diagram of a portion of a system according to an embodiment of the present invention is shown. As shown in FIG. 15A, system 1500 may be any type of platform that provides functionality for user input by touch data. By way of example, platform 1500 may be a mobile low power device, such as a smartphone, tablet computer, Ultrabook ™ computer, or other laptop or notebook device. As can be seen in FIG. 15A, the platform 1500 includes a processor 1510, which in some embodiments is a central processing unit (CPU). The processor 1510 may be a multicore processor and is coupled to a peripheral controller hub (PCH) 1520 via an interconnect 1515. In some embodiments, processor 1510 and PCH 1520 may be integrated into a single integrated circuit (IC), such as SoC, which in some embodiments may be implemented on a single semiconductor die. In other implementations, processor 1510 and PCH 1520 may be separate integrated circuits.

The platform 1500 further includes a display 1530, which in certain embodiments may be any type of display, such as a liquid crystal display (LCD), an LED display, an organic LED (OLED) As can be seen, the processor 1510 provides display information to the display 1530 via the video interface 1535. In the illustrated embodiment, the display 1530 is active in the primary display area 1534 surrounded by the inactive or virtual bezel areas 1532. [ It should be noted that the terms " virtual bezel " and " secondary display area " are used interchangeably herein to refer to areas of the display panel outside the main display area.

Above the display 1530 is a touch screen 1540 that includes input circuitry such as a grid to sense touch input from a user. In some embodiments, the touch screen controller display and the touch screen are integrated modules. By way of example, the display may be formed of a piece of glass having a printed display on one side and a laminated touch screen on the other side, and may further comprise an integrated touchscreen controller. Next, the touch screen 1540 is coupled to a touch screen controller 1550 that includes logic 1555 configured to perform the distributed preprocessing described herein. In some embodiments, the touch controller 1550 may be implemented as a microcontroller that includes microcode and / or is configured to execute touch firmware. To provide incoming touch data for processing at the processor 1510, the touch controller 1550 may include a universal serial bus (USB) interface, an inter-integrated circuit (I ² C) interface, or a universal asynchronous receiver transmitter Is coupled to the PCH 1520 via an interconnect 1545 that may be configured as a path. Although shown as being carried by the wired interconnect in FIG. 15a, the transmission is remote / external all-in-one (AIO) with a touch screen (for digital signage applications) Or wireless or wireline communications such as WiFi (TM) or Ethernet connections to the display.

To allow the processor 1510 to process valid touch data, the processor and the PCH are in an active state. When in an active state, these components can not be in a low power state, or at least these components are prevented from entering a deeper low power state. In order to enable reduced power consumption using embodiments of the present invention, the touch screen controller 1550 performs distributed preprocessing to prevent or filter out invalid touch data from being passed to the processor 1510, (And / or deeper low power state). As described herein, it is noted that invalid touch data corresponds to user touch data received in an area where no user input is expected. For example, in the context of the virtual bezel described above, if the user is holding such a virtual bezel holding a tablet computer or other computing device around its edge but the finger does not include an active display and / or does not include an active soft button When touching and holding this touch data is invalid. Likewise, when the immediate or other portions of the display include soft buttons enabling user selection, user touches outside these active soft buttons may similarly correspond to invalid touch data. Utilizing embodiments of the present invention, all such touch data received from such inactive areas is prevented from being filtered and forwarded to the processor / PCH, thereby allowing entry into and maintenance of low power and / or deeper low power states.

Note that in FIG. 15A only a single active display area 1534 and a single inactive display area 1532 are shown, but in other implementations it should be understood that a plurality of both of these different areas is possible. For example, a low power display may include a first active display area that displays content such as video content or pages of an E-book, while a second active area may receive user input Information may be displayed or other operations may be displayed by the system. In this case, the touch screen controller 1550 may be configured to prevent an invalid touch interrupt from being transmitted to the processor 1510 from outside the control panel area.

In yet another example, one or more active display areas may be enabled while other portions of the display may be powered down. In this manner, only valid touch interrupts in these active display areas are transferred from the touch screen controller 1550 to the processor 1510, while the rest of the display is not powered. As one such example, only the control panel is displayed as the active display area and the rest of the display is powered off. The platform may also be configured in a housing, such as a protective cover, that includes a physical opening with a window that allows input to allow access to the control panel while the rest of the display (and system) is in a low power state.

15A illustrates a situation in which the incoming touch data received via the touch screen 1540 is in the inactive area and must be filtered through the logic 1555 running on the touch screen controller 1550. [ In contrast, FIG. 15B shows additional operation when valid touch data is received in the case of a user touch input in the active touch region. Here, after preprocessing in logic 1555, the touch data is passed through interconnect 1545 and through PCH 1520 to appropriate processing, such as transferring user input to the appropriate OS firmware or application running on processor 1510 Lt; RTI ID = 0.0 > 1510 < / RTI > It is to be understood that although the scope of the present invention is shown at such a high level in Figs. 15A and 15B, the scope of the present invention is not limited in this respect.

Referring now to FIG. 16, a flow diagram of a method for preprocessing touch data according to an embodiment of the present invention is shown. As shown in FIG. 16, method 1600 may be performed using filter logic of a touch controller, such as logic 1555 of FIG. 15A.

As will be seen, the method 1600 begins at diamond 1610 where it is determined whether new area coordinates are received from the host. Although the scope of the invention is not limited in this respect, in some embodiments, such area coordinates may provide an indication of active and inactive touch input areas for the touch screen and may be received from the touch screen firmware running on the processor of the platform . If it is determined that such an input is received, control passes to block 1620, where valid area coordinates may be updated. More specifically, this information corresponding to the mapping information can be used to update coordinates stored in an appropriate memory accessible by the logic of the microcontroller's internal memory or microcontroller-coupled memory. In a different embodiment, this coordinate information is an aspect of the X-Y axis system, so that it can identify the valid touch input area and the invalid touch input area. Note that the touch screen firmware may define a plurality of areas within the touch screen that can generate valid touch screen data, and these areas may have different sizes and shapes.

Suitability for touch screen input can be defined as a specific area within the touch screen. In some embodiments, it may be a plurality of specific areas within the touch screen that may have similar or different sizes and shapes. These areas may be as small as a single touchscreen pixel or as large as the entire touchscreen pixel array. Also, the suitability for touch screen input may be determined by touch screen firmware or by high level firmware or software operation. This appropriateness can be changed dynamically by the same control logic. Also, the suitability for the touch screen input delivered to the preprocessing component by the touch screen firmware may include a security / privacy policy.

Still referring to FIG. 16, control is passed to diamond 1630, where it is determined whether a touch input is detected. If so, control passes to block 1640 where the touch input is analyzed to determine if the touch input is within the valid touch area or within the invalid touch area. The preprocessing may include an analysis of a group or combination of human interactions, such as pressing a combination of buttons at the same time. If the determination at diamond 1650 is that the touch input is from a valid touch region, then control passes to block 1660 where the touch input can be reported to the host. More specifically, in the embodiment of FIG. 15A, this touch data can be communicated to the processor 1510 via the PCH 1520, and on the processor 1510, the touch firmware is executed to process the touch data, Type to an appropriate agent, such as a system software or application.

In yet another embodiment, the preprocessing components can be queried by touch screen firmware, by reading registers, and the like. The touch screen controller may report the touch screen information as a HID-rated device as a touch screen device or as an extended HID-class device. Likewise, touch screen firmware or higher level firmware or software operations may be performed by a HID-rated device or an extended HID device, such as when a user is temporarily searching for a menu hierarchy with different human interaction requirements for each menu display - Dynamically load or unload an instantiation of the rating device to report touch screen information derived from a single touch screen. Here, the touch screen areas overlap (as in a Venn diagram), so that a single touch screen interaction may be interpreted as touch screen information that is simultaneously reported to a plurality of HID devices.

Note that this transfer at block 1660 occurs when the processor (and PCH) is in an active state. Alternatively, this information allows these components to enter the active state from the low power state. In contrast, if a pre-processing performed on the touch screen controller determines that the touch input is in the invalid touch area (determined as described in 1640 and thus ignores such input, for example discarded at block 1670) No propagation occurs in these upstream components. Thus, these components can be kept in a low power state or allowed to enter this low power state. That is, these components may be configured to enter a low power state when an interrupt (such as a touch data interrupt) is not received within a given time frame. It is to be understood that although the embodiment of FIG. 16 is shown at such a high level, the scope of the present invention is not limited in this respect.

By combining the area-based reporting of the touch screen input described herein with the low power display technology, the user will have the same visual experience at lower power (longer battery life). In general, the upper level software dynamically communicates graphic images to be displayed to a graphics (GFX) driver and delivers their respective windows or pixel regions. The GFX driver transmits video pixel data and control signals to the display panel to display a desired image. This higher level software also dynamically passes valid touch screen windows mapped to each graphics window to the touch screen firmware, which in turn passes this information about the valid touch screen area to the touch screen controller.

In the best case, the display / touch screen module may be powered to display the desired touch input image, while the platform power for the rest of the system (including CPU, PCH) may be shut down, And can be placed in a very low power management state.

Therefore, the touch controller prevents the invalid touch interrupt from the outside of the touch area in the E-book example and transfers the valid touch interrupt from the inside of the touch area to the host firmware. Thus, the touch controller transfers only the effective touch interrupt from the inside of the control panel touch area to the host firmware while power is not supplied to the rest of the display.

Thus, the mapping of valid touch input areas on the touch screen to the displayed areas of pixels on the display panel can be controlled by reporting this information to the GFX driver and touch screen firmware, respectively, and then the GFX driver and touch screen firmware And conveys this information to their respective displays and touchscreen controller subsystems, along with any control signals used for power management of these devices.

Many platforms include haptic feedback that allows the user to sense localized feedback in a particular area of the touch screen. By combining the reporting of the area-based touchscreen input of the virtual bezel with the haptic feedback, the user can experience a better experience. That is, the user will only receive haptic feedback when touching the display / touch screen module within the effective display / touch screen area.

In some embodiments, a combined microcontroller / ASIC (application specific integrated circuit) that performs both touch screen input preprocessing (with virtual bezel void region masking) and haptic feedback can be implemented. In this way, considerably lower power may be consumed instead of being performed in the host firmware running these functions on the CPU. In an embodiment, the haptic generator may be an eccentric cam whose movement is controlled in response to user input. This motion causes vibration to the user as feedback. Alternatively, the haptic generator may be implemented using an electric ring around the display causing the haptic feedback by controlling the static charge around the ring. In yet another embodiment, the haptic generator may be integrated into the touch screen and controlled by the touch screen controller.

Thus, the haptic feedback can be provided to the user when the user's touch screen data comes out of the effective touch screen area (if not, this haptic feedback is not delivered). In some embodiments, the haptic feedback is localized to a specific area. For example, when using a multi-touch touch screen with one or more fingers touching the touch screen, the haptic response from placing another finger on the touch screen is provided only to the newly touching finger Not provided for any other finger). Note that as the relevance to the touch screen input changes, the area that defines whether the haptic feedback will be fed back to the user also changes.

Referring now to FIG. 15C, a block diagram of a portion of a system according to another embodiment of the present invention is shown. As shown in FIG. 15C, the system 1500 is configured substantially the same as the system 1500 of FIG. 15A. Note, however, that the haptic generator 1560 is present here. In the embodiment shown in FIG. 15C, the haptic generator 1560 is implemented as a field generator such as a capacitive haptic generator that provides haptic feedback to the user. Also in this implementation, the touchscreen controller 1550 processes the valid touch data processed in logic 1555 and in response generates and provides a control signal to the haptic controller 1560 to cause an additional finger touch on the display Such as an excitation of a localized area on the display 1530, in a particular localized area of a user touch event, such as, for example, .

In some embodiments, an optical scanner may be integrated in each pixel to provide an optical scanning display that allows the screen to scan user inputs such as finger touch, business card, and other visual information placed on its surface . The soft touch screen button described herein activates an optical scanner (located within the selected pixel), either inside or outside the primary display area, with distributed preprocessing of touch screen data to trigger the display to capture the image Can be used. In this way, the power consumption of the scanner is reduced as its duty cycle becomes very low. As a different example, such a scanner can be used for security purposes, for example, to scan a two-dimensional bar code (QR code) or the like for consumer purposes, such as scanning a fingerprint or scanning a barcode. In addition, the display may illuminate only one or more selected local touch screen areas instead of the entire display, thereby further lowering the power. Thus, user input (e.g. fingerprints) is used as a security mechanism. Thus, when a user's finger is placed over a displayed area, a local scan of the fingerprint, which may include illuminating the flash for that local area, occurs.

Further, locally illuminating the selected area avoids interference to the user flashing / illuminating the entire display instead of illuminating only the local area where the finger or QR code is placed. This is especially the case if the illumination interferes with the viewing experience of video information proceeding on other parts of the display. Another exemplary use is to use a portable computing device, such as a smartphone or tablet computer, to authenticate a credit, debit, or other financial transaction using fingerprint authentication through localized illumination and scan of a selected input area of the display will be.

Also, interrupt, touch preprocessing, and optical scanning control resulting from user input may be serviced locally within the display / touch screen / scanner module assembly to avoid system level interrupt service performed by the host processor. This distributed preprocessing close to the display module assembly also occurs at a lower power consumption level than waking up the platform to service the interrupts with host firmware running on the CPU.

In one such example, the touch controller registers a touch input in the area of the valid button (corresponding to a particular navigation button), and provides a localized optical Trigger the scan. This optical scan is a local event that is co-mapped to the touch screen area of the button, so there is no visual impact (e.g., brightness, blooming, flashing) on the video in the primary display area that directs the user. Touch input elsewhere in the invalid area can be masked and ignored by the touch screen controller.

17, an example of a display 1700 that includes an active display area 1710 and a virtual bezel area 1720 that includes a plurality of soft buttons 1715 each configured to receive user input is shown in FIG. . As further shown in Fig. 17, the active display area 1710 provides instructions for the user to enter fingerprint authentication via the first soft button 1715a. If a user is activated in response to placing a finger on the appropriate button, only a scan of this local area is illuminated and an integrated scanner of the display 1700 performs a local scan of the user ' s fingerprint is performed, Allowing security / privacy policies to be implemented before allowing them to perform secure financial transactions or other transactions.

Thus, activation of the optical scanner associated with the display or with the display can be controlled to reduce platform power by scanning within the local area of the display, depending on the valid touch screen input received from the co-mapped touch screen area. The optical scanning imaging device may then report the captured image from the co-mapped region to the host processor. This captured image may have an associated security / privacy policy that may limit certain actions to be performed on the captured image, such as storage, transmission, analysis, public dissemination, etc. of the captured image. In some embodiments, the optical scanner may perform a scan based on an analysis of a group or combination of human interactions, such as simultaneously pressing a combination of buttons.

Embodiments may also intelligently determine when it is appropriate to render the content in a secondary display area, such as a bezel area. The scope of the present invention is not limited in this respect, but dynamic real-time determination for rendering content in this area may be based on one of the following criteria: device configuration (e.g., clam shell mode versus tablet mode ); Sensor information such as touch, pressure, ambient light, and / or proximity sensors, or combinations thereof, for determining one or more portions of the secondary display area to recognize the presence of a user and enable rendering; A content type such as a video mode or a gaming mode in which the full screen display uses the secondary display area; And the state of the primary display region (e.g., active, inactive, or some other such low power state).

In some embodiments, the secondary display area may include a plurality of independent areas (e.g., left, right, top, and bottom), each of which may enable rendering of content in these areas and / / RTI > and / or disabled as well as the type of content being rendered in their area.

Embodiments thus allow content to be rendered in one or more portions of the secondary display region based on one or more criteria, as described above. It should be appreciated that additional criteria may also be considered in other embodiments.

The logic to intelligently determine (and, if determined, determine the appropriate content to render) whether to enable display rendering in the secondary display region of the bezel or other, may be located at various locations in the system. As one such example, the display logic located within or executing on one or more cores of the processor may make such a determination in response to a variety of different inputs. These inputs may be received from various sensors, input devices, and information from other locations in the system, including content being rendered in the primary display area.

In some embodiments, the display logic may include other information, including device configuration, content type, and primary display area activity mode, and a registration entity that allows the logic to register events that occur on these sensors have. After this registration, this registration entity of the display logic may receive an indication of events from these sources. In response to receiving the event, a decision vector may be generated and used by the decision logic, and the decision logic may be part of the display logic or may be located in another part of the processor to determine the bezel area or other secondary display area If display rendering is enabled and enabled, a determination can be made about the appropriate content to be displayed at this location.

In some embodiments, the display logic is an operating bezel framework that operates in conjunction with a display manager that controls the management of content rendering for the primary display region, and may be implemented, at least in part, within the OS context. In another embodiment, a software development kit (SDK) may be provided to allow applications to register with this dynamic bezel framework. For example, different applications may register with this framework to indicate a request to render the content in the secondary display area. That is, various applications, such as user-level applications, may be registered with the dynamic bezel framework, e.g., via an SDK or another mechanism, so that the appropriate content associated with a given application is registered in the application's execution and primary display area And may be pushed into one or more secondary display areas as appropriate during the corresponding display of the primary content of such applications.

Referring now to Figure 18A, there is shown a graphical example of dynamic control of content rendering in different regions of a display according to various embodiments. When the clam shell-based device is used in the clam shell mode, as shown in example 1810, the primary display area 1815 is configured such that the secondary display area 1817 does not render the content, Render content while acting as a bezel.

For example, in another mode with full-screen video being rendered, this display is configured without a bezel area, where both the primary display area and the secondary display area serve as a single user interface, Screen video as shown in the display area 1825 of FIG.

In a further example 1830 shown in Figure 18C, the secondary display region 1837 may instead serve as a bezel instead of rendering the content while the primary display region 1835 displays the rendered content . This example assumes that the device is used in a tablet mode with a bezel as a touch sensor (which recognizes a user-based touch) on the sides, or in a situation where the bezel is enabled based on whether the device is in tablet mode Can occur when used. In another embodiment, the filtering may include turning off or disabling the touch sensors in the inactive area of the touch screen. In this case, the filtering may still be performed outside the peripheral controller, for example, via a touch controller.

In yet another example 1840 shown in Figure 18d, the tablet mode may occur without the bezel when the rendered content is full screen video. Thus, the primary display area and the secondary display area are combined to present a single user interface 1845. This is true even when the touch input is recognized on the periphery of the tablet.

In yet another example 1850 shown in Figure 18e, only the secondary display region may be enabled while the primary display region 1855 is controlled to be in the low power mode. Thus, in the example of example 1850, the independent secondary display areas 1856-1859 can be independently controlled to render a selectable soft button that allows content, e.g., various user input.

In order to enable controllable secondary display region rendering based on a combination of criteria, unique frame buffers may be provided for different display areas. In some embodiments, a dynamic bezel framework layer that may be implemented in the display controller may be tailored for different decision vectors (e.g., device configuration, sensor, content type, and display state) And may take appropriate actions to enable / disable the secondary display area. Also, in some instances, more than two independent display panels may be provided through a single display. For example, a primary display area and four independent secondary display areas, each corresponding to the bezel side, may be provided to independently drive content in these different areas. At the same time, with different controls, these five independent display panels can be smoothly integrated as a single primary display area to enable full-screen video or other integrated rendering.

Embodiments may further provide the ability to access content in one or more of the secondary display areas to enable appropriate related content to be rendered in the primary display area for larger viewing. For example, application shortcuts within the bezel display area may enable the corresponding application to be launched in the user interface in the primary display area when selected by the user touch. It is then possible to enable a plurality of independent user interfaces to be displayed in the primary display area in response to such user selection.

Referring now to FIG. 19, a graphical example of smooth interaction between a secondary display region and a primary display region according to an embodiment is shown. 19, the display 1900 includes a primary display region 1910 and a secondary display region 1920 that is shown to correspond to a bezel subarea in the embodiment. In this secondary display area 1920, first and second application short cut display elements 1922 and 1924, such as icons or other application identifiers, are provided. For example, when selected by the user via the touch, the corresponding application is launched and a user interface for the corresponding application is displayed on at least a portion of the primary display area 1920. Thus, as shown in FIG. 19, a first user interface 1912 for a first application is displayed alongside a second user interface 1914 for a second application in the primary display area 1920. Of course, it should be understood that only a single application user interface can be displayed in the primary display area, for example under a program or other control. Thus, by providing an enabled application shortcut in the bezel secondary display area, an application launch in the primary display area can occur.

In addition, the content rendered in the secondary display area may be based on the recognition of the content displayed in the primary display area and / or the recognition of the device context. For example, when the browse application is running in the primary display area, the secondary display area may display content showing browse content-based data. When the company email / calendar application is running in the primary display area, the secondary display area may display personal email notification. As another example, the pre-application may be displayed in the secondary display area when the E- reader application is executed in the primary display area. Alternatively, a secondary display area may be used for displaying timing, providing entertainment information, etc. while the multimedia content is displayed in the primary display area. In addition, personal settings can be used to change what content is to be displayed in the secondary display area. In some embodiments, different users may provide this display control by a controllable user login.

Embodiments can also provide a display of location aware content in a secondary display area. For example, when the system is in use at an office location, an office news ticker may be displayed in the secondary display area. Instead, when the system is at home, the secondary display area may show Facebook ™ updates, TV show timing, and so on. When in a shopping environment, e.g., another environment such as a store, the secondary display area may show transactions and / or store information.

Embodiments can also provide a display of the content in the secondary display area based on the recognition of the proximity device. For example, when the system is very close to a mobile station, such as a smart phone, incoming call information for that mobile station may be displayed in the secondary display area, for example, during conferences or other times the user can control have. Similarly, information regarding a short message service (SMS) message, missed call, etc. may also be displayed.

Embodiments can also provide a display of user-recognized content in a secondary display area. For example, personalization-based content may be displayed within the secondary display area. For example, a dad using the system may cause the system to be removed to display news, stock tickers, sports information, short cuts for office applications, etc. in the secondary display area. Instead, a mother using the system can cause fashion news, recipes, and book reviews to be displayed in the secondary display area. In the case of a child using the system, the secondary display area can be caused to show an animated character, a shot cut for the game, and the like.

Embodiments also provide for the display of content based on recognition of the device power state. For example, when the primary display is inactive in the low power mode, the secondary display area may be used to display shortcuts such as notifications of e-mail notifications, application shortcuts, etc., or provide a backlight.

Thus, embodiments allow for various contexts (e.g., location, user, primary display content, device context, etc.) to be used to determine the appropriate context for how to render certain content in the secondary display area Provide the framework. This context data may be used to generate content decisions in the content decision logic to determine the appropriate content, which may then be passed to the content engine to generate the appropriate content for rendering. Using the embodiments, the device may be personalized for certain users. In addition, the user can realize a greater battery life because the majority of the display can be turned off while enabling the display of real-time content through the secondary display area.

Embodiments can be used in many different types of systems. For example, in one embodiment, a communication device may be prepared to perform the various methods and techniques described herein. Of course, the scope of the invention is not limited to communication devices, but other embodiments may alternatively be implemented in other types of devices for processing instructions, or in one or more of the methods and techniques described herein, Readable medium including instructions for causing the computer to perform the steps of:

The following examples relate to further embodiments.

In one example, the system comprises a peripheral controller for communicating with a touch controller and communicating mapping information to the touch controller, the mapping information including a primary area of a display of the system and an identifier of a secondary area of the display; Wherein when the touch data corresponds to a user touch in the primary area, the touch data is connected to the peripheral controller, and when the touch data corresponds to a user touch in the secondary area, The touch controller comprising: The touch device coupled to the touch controller to receive the user touch and transmit the touch data to the touch controller; A display coupled to the display for displaying content on the secondary region based on at least one of a configuration of the system, information from one or more environmental sensors, a type of content to be rendered, Display logic to control; And the display coupled to the display logic, wherein the display content of the primary domain is independent of the display content of the secondary domain.

In some examples, the peripheral controller is in a low power state when the touch controller performs touch data filtering. The peripheral controller may be in a low power state when the user touch is in the secondary area.

In some examples, the processor includes at least one core and a peripheral controller. The processor is in a low power state when the touch controller performs touch data filtering. The peripheral controller receives mapping information from system software running on at least one core.

It is noted that the processor may be implemented using various means.

In some instances, the processor includes an SoC included in a user equipment touch-enabled device.

In yet another example, a system includes a display and a memory, and includes one or more processors of the above examples.

In certain examples, the display includes a touch screen including a touch device coupled to a touch controller, wherein the peripheral controller wirelessly transmits the mapping information to the touch controller, wherein the touch controller is included in the external display.

In some examples, a memory coupled to the touch controller stores mapping information, wherein the touch controller accesses mapping information in the memory to determine whether to filter the touch data.

In some examples, the peripheral controller communicates the identifier of the control panel area of the display to the touch controller, which forwards the touch data to the peripheral controller when the touch data is within the control panel area and otherwise filters the touch data. The system may wake up from a low power state in response to receiving the touch data transfer.

In some embodiments, the secondary region includes at least one soft button, and the touch controller is configured to provide the user with haptic feedback when the touch data is received within the at least one soft button while the peripheral controller is in the low power state do. The touch controller enables the optical scanner in the first scan area of the touch device in response to receipt of the touch data in the first scan area and in response to receipt of the touch data in the first scan area, Lt; / RTI > The touch controller may also enable the first scan area illumination with the optical scanner in the first scan area while the remainder of the touch device is in the low power state.

In an embodiment, the at least one sensor senses the presence of the user, the display logic receives the output of the at least one sensor and, based at least in part on the output, generates a first magnitude of the first region and a second magnitude of the second region Control the size. The display logic may control the first size and the second size based at least in part on the content to be rendered on the display. The display logic causes the display to display the user selected content for the first user in the secondary area when at least one sensor senses the presence of the first user. The display logic controls the secondary region to display at least one application shortcut, and in response to user selection of the at least one application shortcut, controls at least a portion of the primary region to display a user interface of the user selected application . The display logic may cause the display to render the second content in the secondary region based at least in part on the first content rendered in the primary region. The display logic may cause the display to render the content based on interaction with a second system in proximity to the system. The display logic may cause the display to render the call information in the secondary area when the second system, including the smart phone, receives the call. The display logic may cause the primary and secondary regions to display a single user interface when the system is in full screen video mode. The display logic may enable the secondary region when the primary region is in a low power state. The display logic may render the notification content in the secondary domain when the primary domain is in a low power state.

In some embodiments, a position sensor is coupled to the display logic, and the display logic causes the display to render the first content in the secondary region when the system is in the first position, 2 content in a secondary area, wherein the first and second positions are detected by a position sensor.

In yet another example, an apparatus includes a controller coupled to a touch input device, the controller receiving at least one of valid area information and invalid area information for a touch input device; Storing at least one of valid area information and invalid area information in a storage; And filter logic for receiving touch data from the touch input device and for filtering touch data from being passed to the host processor coupled to the controller when the touch data is in the invalid region of the touch input device.

In some examples, the filter logic reports the touch data to the host processor when the touch data is within the effective area of the touch input device. The filter logic may access the invalid area information in the storage to determine if the touch input device is within the invalid area. The effective area includes at least one soft button present on the display.

In another example, a system is a System on Chip (SoC), comprising: at least one core; a peripheral device coupled to the at least one core for controlling communication with at least one peripheral device coupled to the SoC A controller, and a power controller that allows the SoC to enter a low power state and to escape a low power state; A human interface device (HID) for receiving input from a user; And a processor coupled to the HID to receive data associated with the user input and to filter the data when the user input is within the invalid area of the HID, the SoC being held in a low power state when the user input is within the free area, And a first logic to transfer the data to the SoC when the user input is within the valid area of the HID.

In certain instances, the haptic controller provides haptic feedback to the user, wherein the HID controller causes the haptic generator to provide haptic feedback when the user input is within the effective area of the HID. The optical scanner may scan a user's second user input, wherein the HID controller enables the optical scanner in response to receiving user input within a valid region of the HID. The HID controller may cause illumination of the effective area in response to receiving user input within the valid area of the HID.

In yet another example, the system includes a touch screen that displays a user interface that includes a valid region in which user touch information is processed and an invalid region in which user touch information is discarded; And a control unit coupled to the touch screen for receiving user touch information, discarding user touch information received from the touch screen when the user touch information is within the invalid area, And a touch screen controller including logic to convey user touch information received from the screen.

The system includes a peripheral controller coupled to the touch screen controller and receiving the transmitted user touch information from the touch screen controller; And a processor coupled to the peripheral controller to receive the delivered user touch information from the peripheral controller and to process the delivered user touch information to determine an operation requested by the user, , And remains in a low power state when the user touch information is discarded by the touch screen controller.

In yet another example, the system includes a touch screen that displays a first user interface in the primary area and a second user interface in the secondary area, or does not display any user interface; And a control unit coupled to the touch screen and configured to filter the touch data received from the touch screen when the touch data corresponds to a user touch in the secondary area and, when the touch data corresponds to a user touch in the primary area, To the peripheral controller coupled to the touch screen controller.

The system includes: a plurality of sensors, each sensing environmental parameters and generating environmental information regarding the environment in which the system is operating; A sensor controller coupled to the plurality of sensors for receiving the environment information, the peripheral controller being coupled to the sensor controller and the touchscreen controller, the touchscreen controller comprising: a touchscreen controller that, when the touch data corresponds to user data in the primary area, The sensor controller receiving the touch data from a controller; And a processor, coupled to the peripheral controller, for receiving the touch data from the peripheral controller and processing the touch data to determine an operation requested by the user, wherein the processor is further configured to: And remains in a low power state when filtered by the logic.

In yet a further example, the system further comprises: a touch screen that displays a first user interface in a primary area where a user touch is processed and no user interface in a secondary area in which a user touch is ignored; And receiving and storing mapping information including an identifier of the primary domain and the secondary domain, the filter being coupled to the touch screen and storing touch data corresponding to a user touch in the secondary domain based at least in part on the mapping information When the touch data corresponds to a user touch in the primary area, based on at least partly the mapping information, the touch data is transmitted to a peripheral controller of the SoC coupled to the touch screen controller And a first logic to transmit the first logic to the touch screen controller.

The system may further comprise a ambient light sensor for detecting a level of ambient light in an environment in which the system is operating, and a sensor controller coupled to the ambient light sensor for receiving a detected level of ambient light, Controller and the touch screen controller.

In some embodiments, the SoC includes a plurality of cores, and the peripheral controller is coupled to the plurality of cores to control communication with a plurality of peripherals coupled to the SoC including the sensor controller and the touch screen controller Wherein the peripheral controller receives the detected level of ambient light from the sensor controller and communicates the detected level of ambient light to the touchscreen controller so that the touchscreen controller can control the operating parameters of the touchscreen And the peripheral controller also transmits mapping information to the touch screen controller and receives the touch data from the touch screen controller when the touch data corresponds to a user touch within the primary area.

The SoC may further include a power controller that allows the SoC to enter a low power state and to deviate from a low power state, wherein the power controller is configured to cause the touch data corresponding to a user touch in the secondary region to be transmitted to the touch screen controller The SoC can be kept in a low power state when it is filtered by the first logic and the SoC can be released from a low power state when touch data corresponding to a user touch in the primary region is delivered.

The system may further include a PMIC coupled to the SoC to control power consumption of the system.

In another example, at least one storage medium includes instructions that, when executed, cause the system to, in the display logic, display a secondary display area of the display of the system during execution of the first application, Receiving from the first application a registration message indicating the applicability of the first application to dynamic content rendering at a user interface of the first application being separated from a primary display area where the user interface of the first application is rendered; The information about the first application is included in the secondary display area list; Receive a request to display content in the secondary display area during execution of the first application; The content being rendered independent of the user interface; and the content in the secondary display area is in the second display area, And is selected using the first application information in the secondary display area list.

In yet another example, a system includes a touch device that receives a user touch input and generates touch data corresponding to a user touch input; And a touch controller, coupled to the touch device, for receiving the mapping information and identifying a primary area of the display and a secondary area of the display, wherein the touch controller is operable when the touch data corresponds to a touch input in the primary area, And first logic for delivering data to the peripheral controller and for filtering touch data received from the touch device when the touch data corresponds to a touch input in the secondary area.

In some embodiments, the touch controller: performs at least one of: receiving the mapping information from the peripheral controller and filtering the touch data when the peripheral controller is in a low power state.

In certain examples, system software running on at least one core provides mapping information to a peripheral controller.

In some examples, the display may include a control panel area, wherein the touch controller delivers touch data to the peripheral controller when the touch data corresponds to a user touch within the control panel area, Whether it is within the region or within the secondary region. The touch controller may receive an identifier of the control panel area from the peripheral controller. The system may leave the low power state when the touch controller transmits touch data to the peripheral controller and the system may be kept in a low power state when the touch controller is filtering the touch data.

In some embodiments, an optical scanner is included within a first scan area of the touch device, wherein the touch controller enables the optical scanner when the user touches the first scan area, So that the first scan area is illuminated when touched. The touch controller may enable the optical scanner and cause the first scan area to be illuminated while at least one of the peripheral controller, processor, or memory of the touch device is in the low power state.

In yet another example, the system further comprises: a HID coupled to the HID for receiving input from a user and for receiving data associated with the user input and for filtering data when the user input is within the invalid region of the HID, And an HID controller including first logic to transfer data to the SoC when in the region.

In another example, a method is provided, in a touch controller of a system, for displaying valid area information on a touch input device of the system indicating a valid area in which a user touch is processed, Receiving invalid zone information for the device; Storing the valid area information and the invalid area information in a storage coupled to the touch controller; Receiving, in the touch controller, a first touch data from the touch input device, the first touch data corresponding to a user touch in the invalid area; Determining that the user touch is in the invalid area based at least in part on the invalid area information; Filtering the first touch data from being passed to a host processor coupled to the touch controller; Receiving, at the touch controller, a second touch data from the touch input device, the second touch data corresponding to a user touch within the valid area; Determining that the user touch is in the effective area based at least in part on the valid area information; And transmitting the second touch data to the host processor.

In another example, one method includes receiving a request to display a first user interface on a touch screen of the system; Instructing the touch screen to display a first user interface; Transmitting effective area information on the touch input device of the system indicating the effective area where the user touch is processed and invalid area information on the touch input device indicating the invalid area where the user touch is ignored to the touch controller of the system ; In response to receiving the first touch data from the touch input device corresponding to a user touch in the invalid area, determining that the user touch is in the invalid area based at least in part on the invalid area information; And filtering the first touch data from being transmitted to a host processor coupled to the touch controller to allow the host processor to remain in a low power state.

In another example, a computer-readable medium containing instructions is for performing the methods of any of the above examples.

In yet another example, the apparatus includes means for performing the methods of any of the above examples.

It should be understood that various combinations of the above examples are possible.

A design can go through various stages, from creation to simulation to production. The data representing the design can represent the design in a number of ways. First, since it is useful in simulation, the hardware can be expressed using a hardware description language or another functional description language. Additionally, circuit level models using logic and / or transistor gates may be generated at certain stages of the design process. Further, most designs reach the level of data representing the physical placement of the various devices in the hardware model at a given stage. Where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be data specifying the presence or absence of various features on the different masks for the masks used to create the integrated circuit. In any representation of the design, the data may be stored in any form of machine readable medium. A magnetic or optical storage, such as a memory or disk, may be a machine-readable medium that stores information transmitted via optical or electrical waveforms that are modulated or otherwise generated to transmit such information. When copying, buffering, or retransmitting an electrical signal is performed when an electrical carrier representing a code or design is transmitted, a new copy is formed. Thus, the communication provider or network provider may store encoded information in a carrier wave that implements the techniques of embodiments of the present invention, at least temporarily, in a type of machine-readable medium.

In modern processors, a number of different execution units are used to process and execute various codes and instructions. Not all instructions are created equally because some instructions may complete faster, while others may require multiple clock cycles to complete. The faster the instruction is processed, the better the overall performance of the processor. Therefore, it would be beneficial to run as many commands as possible as soon as possible. However, there are certain instructions that are more complex and require more in terms of execution time and processor resources. For example, floating-point instructions, load / store operations, and data movement.

As more computer systems are used for Internet, text, and multimedia applications, additional processor support has been introduced over time. In one embodiment, the instruction set may be associated with one or more computer architectures, including data types, instructions, register architectures, addressing modes, memory architectures, interrupt and exception handling, external input and output (I / O)

In one embodiment, an instruction set architecture (ISA) may be implemented by one or more micro-architectures including processor logic used to implement one or more sets of instructions. Thus, processors having different microarchitectures may share at least a portion of a common instruction set. For example, processors from the Intel® Pentium 4 processor, Intel® Core ™ processor, and Advanced Micro Devices, Inc. of CA, Sunnyvale (along with some extensions added with the new version) will have the same x86 instruction set But has a different internal design. Likewise, processors designed by other processor developers, such as ARM Holdings, Ltd., MIPS, or their license producers or adopters, may share at least a portion of a common instruction set, but may include different processor designs can do. For example, the same register architecture of the ISA can be implemented using dedicated physical registers, one or more dynamically allocated physical registers (e.g., using a register alias table (RAT)) using a register rename mechanism, May be implemented in different manners in different microarchitectures, using new or known techniques, including ROB (Reorder Buffer) and retirement register files. In one embodiment, the register may include one or more registers, a register architecture, a register file, or some other set of registers that are not addressable or capable of being addressed by the software programmer.

In one embodiment, the instructions may include one or more instruction formats. In one embodiment, the instruction format may, among other things, represent various fields (number of bits, bit positions, etc.) specifying the operation to be performed and the operand (s) on which the operation is performed. Some command formats can be further subdivided as defined by the command template (or subformat). For example, a command template of a given command format may be defined to have fields of command format of different subsets and / or a given field may be defined such that a given field is interpreted differently. In one embodiment, an instruction is represented using an instruction format (and, if defined, a given one of the instruction templates in the instruction format), and specifies or indicates the operand to which the operation and operation will operate.

(E.g., 2D / 3D graphics, image processing, video compression / decompression, speech recognition algorithms and audio manipulation), and visual and multimedia applications May require that the same operation be performed on a large number of data items. In one embodiment, SIMD (Single Instruction Multiple Data) refers to a type of instruction that causes a processor to perform operations on a plurality of data elements. SIMD techniques can be used in processors that can logically separate bits in a register into a number of fixed-size or variable-size data elements (each data element representing a distinct value). For example, in one embodiment, the bits in a 64-bit register may be organized as a source operand comprising four distinct 16-bit data elements, each data element representing a separate 16-bit value. This type of data may be referred to as a "packed" data type or a "vector" data type, and operands of this data type are referred to as packed data operands or vector operands. A packed data operand or a vector operand may be a source or destination operand of a SIMD instruction (or a 'packed instruction' or a 'vector instruction'). In one embodiment, , A SIMD instruction may be a single instruction to be performed on two source vector operands to produce the same or different sized destination vector operands (also called result vector operands) having the same or different sized data elements in the same or different data element order Specifies a vector operation.

Intel® Core ™ processors, Vector Floating Point (VFP) and / or NEON instructions with instruction sets including x86, MMX ™ technology, Streaming SIMD Extensions (SSE), SSE2, SSE3, SSE4.1, and SSE4.2 instructions MIPS processors such as the ARM Cortex® processor family with a set of instructions, including the instruction set, and the Loongson processor family developed by the Institute of Computing Technology (ICT) of the Chinese Academy of Sciences, (Core ™ and MMX ™ are registered trademarks or trademarks of Intel Corporation of Santa Clara, Calif.).

In one embodiment, the destination and source register / data are generic terms that represent the source and destination of the corresponding data or operation. In some embodiments, these may be implemented by a register, memory, or other storage area having a name or function different from that described. For example, in one embodiment, "DEST1" may be a temporary storage register or other storage area, while "SRC1" and "SRC2" may be first and second source storage registers or other storage areas. In another embodiment, two or more of the SRC and DEST storage areas may correspond to different data storage elements in the same storage area (e.g., a SIMD register). In one embodiment, one of the source registers, for example, rewrites the result of an operation performed on the first and second source data to one of two source registers serving as a destination register, You can act.

A module as used herein refers to any combination of hardware, software, and / or firmware. By way of example, a module includes hardware, such as a microcontroller, associated with a non-volatile medium that stores code adapted to be executed by the microcontroller. Thus, reference to a module refers, in one embodiment, to a hardware specifically configured to recognize and / or execute code maintained on a non-transient medium. Also, in yet another embodiment, the use of a module refers to a non-volatile medium comprising code specially adapted to be executed by a microcontroller to perform a predetermined operation. As can also be deduced, the term module (in this example) may refer to a combination of a microcontroller and a non-transitory medium. Module boundaries, often illustrated as distinct, typically vary and can potentially overlap. For example, the first and second modules may share hardware, software, firmware, or a combination thereof while potentially maintaining some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

The use of the phrase " configured to " refers to arranging, assembling, manufacturing, or providing, importing, and / or designing devices, hardware, logic or elements to perform specified or determined logic in one embodiment. In this example, a device or element that is not in operation is " configured " to still perform a designated task if it is designed, coupled, and / or interconnected to perform the specified task. As a pure example, a logic gate may provide a 0 or 1 during operation. However, a 'configured' logic gate to provide an enable signal to the clock does not include all potential logic gates that may provide a 1 or a 0. Instead, the logic gates are coupled in a manner such that 1 or 0 enables the clock during operation. The use of the term " configured to " once more does not require an action, but instead focuses on the potential state of the device, hardware, and / or element, and the device, hardware, and / It is noted that the device, hardware, and / or elements are designed to perform certain tasks when operating.

In addition, use of the phrase " operable to " or " operable to " means that the device, logic, hardware Refers to some device, logic, hardware, and / or element designed in a manner that allows for the use of, and / or the use of, elements. Refers to the potential state of a device, logic, hardware, and / or element in one embodiment, wherein the device, logic, hardware, and / or elements are operable in a manner that enables the use of the function without modification It is not designed but designed.

When used herein, a value includes any known expression of a number, a state, a logic state, or a binary logic state. Often, the use of logic levels, logic values, or logic values also refers to ones and zeros representing binary logic states. For example, 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage cell, such as a transistor or a flash cell, may hold a single logical value or a plurality of logical values. However, other representations of values have been used in computer systems. For example, a decimal number 10 may be represented as a binary value 1010 and represented as a hexadecimal value A. Thus, the value includes any representation of information that may be held in a computer system.

In addition, the state can be represented by values or by some of the values. By way of example, a first value such as logical 1 may represent a default or initial state, while a second value such as logical 0 may represent a non-default state. In addition, the term resets and sets, in one embodiment, refer to default and updated values or states, respectively. For example, the default value potentially contains a high logic value, i. E. Reset, while the update value potentially contains a low logic value, i. It is noted that any combination of values may be used to indicate any number of states.

Embodiments of the disclosed method, hardware, software, firmware, or code set may include instructions or code executable by a processing unit and stored on a machine-accessible, machine-readable, computer-accessible, or computer- Lt; / RTI > Non-transitory machine-accessible / readable media includes any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transient machine-accessible medium may include random-access memory (RAM), such as SRAM (static RAM) or DRAM (dynamic RAM); ROM; Magnetic or optical storage media; A flash memory device; Electrical storage; Optical storage; Acoustic storage; And other types of storage devices for retaining information received from transient (propagated) signals (e.g., carrier waves, infrared signals, digital signals) that are distinct from non-transitory media capable of receiving information do.

The instructions used to program the logic to perform embodiments of the present invention may be stored in memory in a system such as DRAM, cache, flash memory, or other storage. In addition, the instructions may be distributed over a network by other computer readable media. Thus, the machine-readable medium may be a floppy diskette, an optical disk, a compact disk, a read-only memory (CD-ROM), a magneto-optical disk, a read-only memory (ROM), a random access memory (EEPROM), a magnetic or optical card, a flash memory, or an electrically, optically, acoustically, or other form of propagated signal (e. G. (E.g., a computer) that includes, but is not limited to, machine-readable storage of the type used for the transmission of information over the Internet using a carrier wave, an infrared signal, a digital signal, Lt; RTI ID = 0.0 > information. ≪ / RTI > Thus, the computer-readable medium includes any type of machine-readable medium for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

The word " one embodiment " or " an embodiment " throughout this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Accordingly, the appearances of the phrase " in one embodiment " or " in an embodiment " in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in any suitable manner in one or more embodiments.

While the invention has been described with respect to a limited number of embodiments, those skilled in the art will recognize numerous modifications and variations therefrom. The appended claims are intended to cover all such modifications and variations as fall within the true spirit and scope of the invention.

Claims (15)

As a system,
A host processor comprising at least one core and a peripheral controller, wherein the peripheral controller is coupled to the host processor, the peripheral controller interfaces with a touch controller, receives mapping information from the host processor, Wherein the mapping information is configured to identify the secondary region of the display including the primary region of the display of the system and the inactive touch input region including the active touch input region, - including coordinate information for the object;
A memory coupled to the touch controller and configured to store the mapping information, wherein the touch controller is coupled to the peripheral controller and the touch controller is configured to receive the touch data from the touch screen when the touch data corresponds to a user touch within the secondary area Using the mapping information in the memory to filter the touch data from transferring to the peripheral controller and to transfer the touch data to the peripheral controller when the touch data corresponds to the user touch in the primary area, Wherein the first logic further communicates the touch data to the peripheral controller when the touch data is within the control panel area of the display and otherwise filters the touch data, Lt; / RTI > Wherein the host processor is in a low power state when the touch controller performs touch data filtering and the host processor is inactive in the low power state and the touch screen connected to the touch controller receives the user touch And transmit the touch data to the touch controller; And
Display logic associated with the processor, to display content in the secondary area based on one or more configurations of the system, information from one or more environmental sensors, type of content being displayed, and mode of the primary area The display configured to control the display, the content in the primary area being independent of the content in the secondary area,
/ RTI > 2. The system of claim 1, wherein the peripheral controller is in a low power state when the touch controller performs the touch data filtering and the peripheral controller is inactive in the low power state. 2. The system of claim 1, wherein the peripheral controller is in a low power state when the user touch is in the secondary region and the peripheral controller is inactive in the low power state. 2. The system of claim 1, wherein the peripheral controller is configured to receive the mapping information from system software running on the at least one core. The system of claim 1, wherein the peripheral controller is configured to communicate an identification of the control panel region of the display to the touch controller, the system being configured to wake up from the low power state in response to receipt of touch data transfer , system. The touch screen of claim 1, wherein the secondary area includes at least one soft button, and wherein the touch controller is configured to allow the at least one soft button when the touch data is received in the at least one soft button while the peripheral controller is in a low- Thereby providing the user with haptic feedback. The touchscreen of claim 1, wherein the touch controller enables an optical scanner in a first scan region of the touch screen in response to receipt of the touch data in the first scan region, To enable illumination of the first scan area in response to receipt of the touch data and enable the optical scanner and the first scan area illumination in the first scan area while the remainder of the touch screen is in a low power state , system. The method according to claim 1,
At least one sensor for sensing the presence of a user; And
A display logic for receiving an output of the at least one sensor and for controlling a first size of the primary region and a second size of the secondary region based at least in part on the output,
≪ / RTI > 9. The system of claim 8, wherein the display logic causes the display to display user selected content for the first user in the secondary area when the at least one sensor senses the presence of the first user. . 2. The apparatus of claim 1, wherein the display logic controls the secondary region to display at least one application shortcut, and in response to user selection of the at least one application shortcut, at least a portion of the primary region is controlled To display a user interface of the user selected application. 2. The system of claim 1, wherein the display logic causes the display to render content based on interaction with a second system proximate the system, and when the second system receives a call, And rendering the call information in a car area, wherein the second system comprises a smart phone. The display logic of claim 1, wherein the display logic is configured to enable the secondary region when the primary region is in a low power state, render the notification content in the secondary region when the primary region is in the low power state, System. 2. The apparatus of claim 1, further comprising a position sensor coupled to the display logic, wherein the display logic causes the display to render the first content in the secondary region when the system is in the first position, And cause the display to render the second content in the secondary area when the system is in the second position, wherein the first position and the second position are detected by the position sensor. As a system,
A touch screen configured to display a user interface including a valid area in which user touch information is processed and an invalid area in which the user touch information is ignored;
A touch screen controller coupled to the touch screen and configured to receive the user touch information from the touch screen, wherein the touch screen controller is configured to receive the user touch information received from the touch screen when the user touch information is within the invalid area, And logic for communicating the user touch information received from the touch screen when the user touch information is within the valid area, wherein the logic is further operable when the user touch information is within the control panel area of the touch screen To transmit the user touch information when the user touch information is received and otherwise to filter the user touch information;
A peripheral controller coupled to the touch screen controller and configured to receive the transmitted user touch information from the touch screen controller; And
A processor coupled to the peripheral controller and configured to receive the delivered user touch information from the peripheral controller and to process the delivered user touch information to determine an action requested by the user, Wherein the processor is held in an inactive low power state when ignored by the touch screen controller, the processor comprising the peripheral controller and at least one core,
. As a system,
A touch screen that displays a first user interface in the primary area and a second user interface in the secondary area or does not display any user interface;
A touch screen controller coupled to the touch screen, the touch screen controller filtering touch data received from the touch screen when the touch data corresponds to a user touch in the secondary area, And a first logic for transferring the touch data to a peripheral controller coupled to the touch screen controller when the touch data corresponds to a user touch, the first logic being configured to transmit the touch data when the touch data is within the control panel area of the touch screen Wherein the touch screen controller is further configured to receive and store mapping information from a processor, wherein the mapping information is configured to identify the primary area and the secondary area - including coordinate information for the object;
A plurality of sensors configured to sense environmental parameters and to generate environmental information while the system is operating;
A sensor controller coupled to the plurality of sensors and configured to receive the environment information, the peripheral controller being adapted to receive the touch data delivered from the touch screen controller when the touch data corresponds to a user touch within the primary area Wherein the peripheral controller does not receive the filtered touch data; And
A processor coupled to the peripheral controller and configured to receive the touch data from the peripheral controller and to process the touch data to determine an operation requested by the user, the processor being configured to cause the touch data to be received by the first logic Wherein the processor is maintained in a low power state when filtered, the processor comprising the peripheral controller and at least one core,
.

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