KR101936450B1 - 메모리 크기에 매칭하여 직렬 데이터 전송을 하는 방법 및 장치 - Google Patents

메모리 크기에 매칭하여 직렬 데이터 전송을 하는 방법 및 장치 Download PDF

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KR101936450B1
KR101936450B1 KR1020137031201A KR20137031201A KR101936450B1 KR 101936450 B1 KR101936450 B1 KR 101936450B1 KR 1020137031201 A KR1020137031201 A KR 1020137031201A KR 20137031201 A KR20137031201 A KR 20137031201A KR 101936450 B1 KR101936450 B1 KR 101936450B1
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KR20140030214A (ko
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플로리안 하르트비치
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로베르트 보쉬 게엠베하
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Priority claimed from DE102011078266A external-priority patent/DE102011078266A1/de
Priority claimed from DE102011080476A external-priority patent/DE102011080476A1/de
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40013—Details regarding a bus controller
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
    • H04L12/4135—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD] using bit-wise arbitration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40215—Controller Area Network CAN

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
KR1020137031201A 2011-04-26 2012-04-26 메모리 크기에 매칭하여 직렬 데이터 전송을 하는 방법 및 장치 Active KR101936450B1 (ko)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
DE102011017539A DE102011017539A1 (de) 2011-04-26 2011-04-26 Verfahren und Vorrichtung zur an Speichergrößen angepassten seriellen Datenübertragung
DE102011017539.3 2011-04-26
DE102011078266A DE102011078266A1 (de) 2011-06-29 2011-06-29 Verfahren und Vorrichtung zur seriellen Datenübertragung mit flexibler Nachrichtengröße und variabler Bitlänge
DE102011078266.4 2011-06-29
DE102011080476.5 2011-08-05
DE102011080476A DE102011080476A1 (de) 2011-08-05 2011-08-05 Verfahren und Vorrichtung zur Verbesserung der Datenübertragungssicherheit in einer seriellen Datenübertragung mit flexibler Nachrichtengröße
PCT/EP2012/057623 WO2012146649A1 (de) 2011-04-26 2012-04-26 Verfahren und vorrichtung zur an speichergrössen angepassten seriellen datenübertragung

Publications (2)

Publication Number Publication Date
KR20140030214A KR20140030214A (ko) 2014-03-11
KR101936450B1 true KR101936450B1 (ko) 2019-01-08

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KR1020137031201A Active KR101936450B1 (ko) 2011-04-26 2012-04-26 메모리 크기에 매칭하여 직렬 데이터 전송을 하는 방법 및 장치
KR1020137031199A Active KR101956940B1 (ko) 2011-04-26 2012-04-26 메모리 크기에 매칭하여 직렬 데이터 전송을 하는 방법 및 장치

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US (2) US9825852B2 (enExample)
EP (2) EP2702497B1 (enExample)
JP (2) JP5702505B2 (enExample)
KR (2) KR101936450B1 (enExample)
CN (2) CN103649933B (enExample)
ES (1) ES2549640T3 (enExample)
RU (2) RU2597502C2 (enExample)
WO (2) WO2012146649A1 (enExample)

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JP5702505B2 (ja) 2015-04-15
WO2012146631A1 (de) 2012-11-01
CN103649934B (zh) 2016-07-06
KR20140030213A (ko) 2014-03-11
EP2702497B1 (de) 2016-01-20
RU2013152206A (ru) 2015-06-10
EP2702495A1 (de) 2014-03-05
JP2014522140A (ja) 2014-08-28
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EP2702495B1 (de) 2015-09-09
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CN103649933A (zh) 2014-03-19
US9432289B2 (en) 2016-08-30
JP5723062B2 (ja) 2015-05-27
US20140177651A1 (en) 2014-06-26
US9825852B2 (en) 2017-11-21
WO2012146649A1 (de) 2012-11-01
CN103649934A (zh) 2014-03-19
US20140156887A1 (en) 2014-06-05
KR101956940B1 (ko) 2019-03-11
EP2702497A1 (de) 2014-03-05

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