KR101907733B1 - Bridge interconnection with layered interconnect structures - Google Patents

Bridge interconnection with layered interconnect structures Download PDF

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Publication number
KR101907733B1
KR101907733B1 KR1020160006273A KR20160006273A KR101907733B1 KR 101907733 B1 KR101907733 B1 KR 101907733B1 KR 1020160006273 A KR1020160006273 A KR 1020160006273A KR 20160006273 A KR20160006273 A KR 20160006273A KR 101907733 B1 KR101907733 B1 KR 101907733B1
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South Korea
Prior art keywords
bridge
conductive
substrate
die
layer
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KR1020160006273A
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Korean (ko)
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KR20160015340A (en
Inventor
유에리 리우
칭레이 장
아만다 이. 슈크맨
루이 장
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인텔 코포레이션
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Priority to US13/903,828 priority Critical patent/US9147663B2/en
Priority to US13/903,828 priority
Application filed by 인텔 코포레이션 filed Critical 인텔 코포레이션
Publication of KR20160015340A publication Critical patent/KR20160015340A/en
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Publication of KR101907733B1 publication Critical patent/KR101907733B1/en

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Abstract

Embodiments of the present invention are directed to a technique and configuration for a stacked interconnect structure for a bridge interconnect of an integrated circuit assembly. In one embodiment, the apparatus can include a substrate, and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between the two dies. The interconnection structure electrically connected to the bridge includes a via structure comprising a first conductive material, a barrier layer comprising a second conductive material disposed on the via structure, and a third conductive material disposed on the barrier layer, . ≪ / RTI > The first conductive material, the second conductive material, and the third conductive material may have different chemical compositions. Other embodiments may be described and / or claimed.

Description

[0001] BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES [0002]

Embodiments of the present invention generally relate to the field of integrated circuits, and more particularly, to techniques and configurations for bridge interconnects with integrated interconnect structures in integrated circuit assemblies.

An embedded bridge interconnect can provide faster communication between the processor and the memory chip. The various die may need to be attached to the substrate at the first level interconnection (FLI) to enable high performance computing (HPC). As the die continues to shrink to smaller dimensions, finer pitches are generally required between interconnect structures at the FLI level.

Providing finer pitches to future computing devices may be difficult when using current technology. For example, mixed bump pitches between the processor die and the memory die can present packaging and assembly difficulties at the present time, resulting in poor yield performance. FLI joint structures using a solder paste printing (SPP) process can result in yield failure due to restrictions on the solder bump height and / or solder volume on the die, and in particular the smaller pitch areas of the FLI Resulting in non-contact openings and bump cracks. In addition, the risk of electromigration can be increased due to copper diffusion (Cu) and the organic solder preservative (OSP) surface finish used on the substrate side of the FLI joint.

The embodiments will be readily understood by the following detailed description together with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings.
1 schematically illustrates a cross-sectional view of an exemplary integrated circuit (IC) assembly configured to use embedded bridge interconnects with stacked interconnect structures on a substrate, in accordance with some embodiments.
2 schematically illustrates a flow diagram of a package substrate fabrication process for forming a substrate with a bridge interconnect using a stacked interconnect structure, in accordance with some embodiments.
FIG. 3 schematically illustrates a cross-sectional view of some selected processes prior to embedding a bridge in a substrate, in connection with the package substrate manufacturing process illustrated in FIG. 2, in accordance with some embodiments.
Figure 4 schematically illustrates a cross-sectional view of some other selected processes prior to embedding the bridge in a substrate, in connection with the package substrate manufacturing process illustrated in Figure 2, in accordance with some embodiments.
Figure 5 schematically illustrates a cross-sectional view of some selected processes for embedding bridges in a substrate, in connection with the package substrate manufacturing process illustrated in Figure 2, in accordance with some embodiments.
Figure 6 schematically illustrates a cross-sectional view of some selected processes for forming a stacked interconnect structure in connection with the package substrate fabrication process illustrated in Figure 2, in accordance with some embodiments.
Figure 7 schematically illustrates a cross-sectional view of some other selected processes for forming a stacked interconnect structure, in connection with the package substrate fabrication process illustrated in Figure 2, in accordance with some embodiments.
FIG. 8 schematically illustrates a cross-sectional view of some selected processes for completing a laminated interconnect structure, in connection with the package substrate fabrication process illustrated in FIG. 2, in accordance with some embodiments.
9 schematically illustrates a flow diagram of an assembly process using a package substrate with embedded bridge interconnects, in accordance with some embodiments.
10 schematically illustrates a computing device including embedded bridge interconnects with stacked interconnect structures on a substrate, as described in this application, in accordance with some embodiments.

Embodiments of the present invention describe techniques and configurations for bridge interconnects with stacked interconnect structures in an integrated circuit assembly. In the following description, various aspects of an exemplary implementation will be described using terms commonly used by those skilled in the art to convey the work of one of ordinary skill in the art to others skilled in the art. It will be apparent, however, to one skilled in the art that the embodiments of the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth to provide a thorough understanding of the exemplary implementations. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without specific details. In other instances, known features may be omitted or simplified in order not to obscure the exemplary implementation.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, in which like numerals represent like parts throughout, and are shown as exemplary embodiments in which the subject matter of the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

For purposes of the present invention, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of the present invention, the phrases "A, B, and / or C" refer to a combination of A, B, C, A and B, A and C, B and C, , B and C).

Explanations can use perspective-based descriptions such as top / bottom, inside / outside, top / bottom, and so on. Such description is used merely to facilitate discussion and is not intended to limit the application of the embodiments described in this application to any particular direction.

The description can use the phrase "in an embodiment "," in embodiments ", or "in some embodiments ", each of which may refer to one or more of the same or different embodiments. Furthermore, the terms " comprising, "" having ", " having ", and the like used in the embodiments of the present invention are synonymous.

The term " associated with "can be used in the present application in conjunction with its derivatives. "Linked" can mean one or more of the following. "Linked" may mean that two or more elements are in direct physical or electrical contact. However, "connected" also means that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and that one or more other elements are connected or connected between elements You may. The term "directly connected" may mean that two or more elements are in direct contact.

In various embodiments, the phrase "first feature formed, deposited, or otherwise disposed on the second feature" means that the first feature is formed, deposited, or placed on the second feature, (E. G., Physically and / or electrically in direct contact) or indirect contact (e. G., At least one other feature between the first feature and the second feature, And the like).

The term "module" as used herein refers to an application specific integrated circuit (ASIC), an electronic circuit, a system-on-chip (SoC), a processor (shared, dedicated, or group) And / or memory (shared, dedicated or grouped), combinational logic circuitry, and / or other suitable components that provide the described functionality.

1 schematically illustrates a cross-sectional view of an exemplary IC assembly 100 configured to utilize embedded bridge interconnects with laminated interconnect structures on a substrate, in accordance with some embodiments. In an embodiment, the IC assembly 100 can include one or more dies, such as die 110 and die 120, electrically and / or physically connected to the package substrate 150, as can be seen . The package substrate 150 may further be electrically connected to the circuit board 190, as can be seen. As used in this application, a first level interconnect (FLI) may refer to an interconnect between a die and a package substrate, while a second level interconnect (SLI) may refer to an interconnect between a package and a circuit board have.

The die 110 or 120 may represent a separate unit made of a semiconductor material using semiconductor fabrication techniques such as thin film deposition, lithography, etch, and the like. In some embodiments, the die 110 or 120 may comprise or be part of a processor, memory, SoC, or ASIC. The dies 110 and 120 may be attached to the package substrate 150 in accordance with various suitable configurations, including flip-chip configurations as depicted, or other configurations, such as, for example, embedded in the package substrate 150 . In a flip-chip configuration, die 110 or 120 may be used to electrically and / or mechanically connect dies 110 and 120 to package substrate 150 and to route electrical signals between one or more dies 110 and 120 and other electrical components (E.g., the S1 side) of the package substrate 150 using an FLI structure, such as an interconnect structure 130, 135, In some embodiments, the electrical signal may include an input / output (I / O) signal and / or power / ground associated with driving the die 110,120.

The interconnect structure 130 may be electrically connected to the bridge 140 to route electrical signals between the dies 110 and 120 using the bridge 140. The interconnect structure 130 can substantially reduce diffusion and mitigate the risk of electromigration, as discussed further below, and provide higher and more conforming FLI joints and stand-off heights ), Which can improve assembly performance, reduce assembly yield loss, and increase FLI reliability.

The interconnect structure 135 includes a die (e.g., a die 110) and a package substrate 150 that extends from the first side S1 to the second side S2 opposite the first side S1 The electrical path between the electrical path 133 and the electrical path 133, as shown in FIG. For example, the interconnect structure 135 may be configured to route electrical signals of the die 110 between the first side S1 and the second side S2 of the package substrate 150, for example, a trench, (E.g., interconnect structure 137), such as via, via, traces, or conductive layers, and the like. The interconnect structure 135 may be part of the electrical path 133 in some embodiments.

The interconnect structure 137 is merely an example structure for discussion and may represent any suitable interconnect structure and / or layer. Similarly configured interconnect structures 130 and 135 may connect die 120 or other die (not shown) to package substrate 150. The package substrate 150 may include more or fewer interconnect structures or layers than those depicted. In some embodiments, an electrically insulating material, such as, for example, a molding compound or an underfill material (not shown) may partially encapsulate the die 110 or 120 and / or a portion of the interconnect structures 130 and 135.

In some embodiments, the bridge 140 may be configured to electrically connect the dies 110 and 120 to one another. In some embodiments, the bridge 140 may include interconnect structures (e.g., interconnect structure 130) that function as an electrical routing feature between the dies 110 and 120. In some embodiments, the bridge may be disposed between some dies on the package substrate 150 and not between other dies. In some embodiments, the bridge may not be visible in the top view. The bridge 140 may be embedded in the cavity of the package substrate 150 in some embodiments. The bridge 140 may be a dense routing structure that provides a path for electrical signals. Bridge 140 may be formed of a glass or semiconductor material such as high resistivity silicon (Si) formed over the electrical routing interconnect feature to provide chip-to-chip connection between dies 110 and 120 And may comprise a configured bridge substrate. The bridge 140 may be constructed of other suitable materials in other embodiments. In some embodiments, the package substrate 150 may include a plurality of built-in bridges to route electrical signals between the plurality of dies.

In some embodiments, the package substrate 150 is an epoxy-based laminate substrate having a core and / or build-up layer, such as, for example, an Ajinomoto Build-up Film (ABF) substrate. The package substrate 150 may, in other embodiments, include other suitable types of substrates, including, for example, a substrate formed of glass, ceramic, or semiconductor material.

The circuit board 190 may be a printed circuit board (PCB) composed of an electrically insulating material such as an epoxy laminate. For example, the circuit board 190 may be formed from a phenolic cotton paper material such as polytetrafluoroethylene, FR-4 (Flame Retardant 4), FR-1, CEM-1 or CEM- Such as a woven glass material that is laminated together using the same cotton and epoxy material, or epoxy resin prepreg material. Trenches, trenches, vias, etc., through the electrical insulation layer may be formed to route the electrical signals of the die 110 or 120 through the circuit board 190. The circuit board 190 may be constructed of other suitable materials in other embodiments. In some embodiments, circuit board 190 is a motherboard (e.g., motherboard 1002 of FIG. 10).

Level interconnections, such as solder balls 170 or land-grid array (LGA) structures, to one or more lands (hereinafter "land 160") and circuit board 190 on package substrate 150, To form a corresponding solder joint that is configured to further route the electrical signal between the package substrate 150 and the circuit board 190. In one embodiment, The lands 160 and / or the pads 180 may be formed of any suitable material, such as, for example, metals including nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper Of a suitable electrically conductive material. Other suitable techniques for physically and / or electrically connecting the package substrate 150 to the circuit board 190 may be used in other embodiments.

Figure 2 illustrates a substrate (e.g., a package substrate of Figure 1 (see Figure 1) with embedded bridge interconnects using stacked interconnect structures (e.g., interconnect structure 130 of Figure 1) 150 (hereinafter referred to as "process 200"). The process 200 may operate in conjunction with the embodiments described in connection with Figs. 3-8, in accordance with various embodiments.

At step 210, the process 200 may include forming a bridge (e.g., bridge 140 of FIG. 1) on the substrate. In embodiments, the bridge may comprise a glass or semiconductor material (e.g., Si) and may include an electrical routing feature that routes electrical signals between the dies. In some embodiments, the bridge may be disposed on or in a plane formed by one or more build-up layers of the substrate. For example, as can be seen in the embodiment depicted in connection with FIG. 1, the bridge 140 is embedded in the build-up layer of the substrate 150. In some embodiments, the bridge may be disposed in a plane formed by the build-up layer, but may be formed separately from the build-up layer.

In some embodiments, the step of forming a bridge (e.g., bridge 140 in FIG. 1) disposed in the build-up layer plane may be performed in accordance with any suitable technique, Up layer by embedding the bridge in the build-up layer, or by forming the cavity in the build-up layer and placing the bridge in the cavity after forming the build-up layer. The bridge may be embedded in the substrate during manufacture as described in connection with Figs. 3-5, in accordance with various embodiments.

In step 220, the process 200 may include forming a joint comprising a first conductive material connected to the bridge to route the electrical signal over the surface of the substrate. In embodiments, the joint may be part of an interconnect structure (e.g., interconnect structure 130 of FIG. 1) that is capable of electrically connecting the bridge to the die. The joint may comprise a first electrically conductive material. In one embodiment, the first electrically conductive material may comprise Cu. In other embodiments, the first electrically conductive material may comprise other chemical compositions or combinations thereof. In embodiments, the joint may include, for example, a trace, which provides a corresponding electrical path for the electrical signal of the die through the package substrate to the embedded bridge, and then to another die electrically connected to the bridge, for example. Trenches, vias, lands, pads, or other structures. In one embodiment, the joint may include a via structure. In an embodiment, the joint may further include a pad structure coupled to the via structure. The joint may be formed during manufacture as described in connection with Fig. 6, according to various embodiments.

In step 230, the process 200 may include forming a barrier layer comprising a second conductive material directly over the joint. In embodiments, the barrier layer may comprise a second electrically conductive material, such as a barrier metal, and may be applied to cover the joint. The barrier layer can reduce or prevent diffusion of the first conductive material used in the joint to the surrounding material while maintaining electrical connection between the joint and the die. The second conductive material may have a different chemical composition than the first conductive material. The second electrically conductive material includes, for example, nickel (Ni), tantalum (Ta), hafnium (Hf), niobium (Nb), zirconium (Zr), vanadium (V), tungsten . In some embodiments, the second electrically conductive material can comprise a conductive ceramic such as tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride.

In embodiments, the barrier layer may reduce the risk of electromigration. The risk of electromigration may increase with higher DC density when the structure size in an electronic device such as an integrated circuit (IC) decreases. Electromigration can cause diffusion processes such as grain boundary diffusion, bulk diffusion, or surface diffusion. In embodiments, when the first conductive material comprises copper, the surface diffusion induced by electromigration can predominate in the copper interconnect. The barrier layer can prevent copper diffusion between adjacent copper and / or copper alloy lines. In one embodiment, electrolytic plating may be used to form the barrier layer. The barrier layer may be formed during manufacture as described in connection with Fig. 7, according to various embodiments.

In step 240, the process 200 may include forming a solder layer comprising a third conductive material directly over the barrier layer, and the barrier layer and the solder layer being configured to route the electrical signals. In embodiments, the solder layer may comprise a third electrically conductive material, such as a soluble metal alloy, applied over the barrier layer. A solder layer may be used to bond the sub-structure, including the barrier layer and the joint, with the die through its connection points, while maintaining electrical connection between the sub-structure and the die. In embodiments, the joint, the barrier layer, and the solder layer collectively form an interconnect structure to route electrical signals between the bridge and the die.

In embodiments, the third conductive material may have a different chemical composition than the first and second conductive materials. The third electrically conductive material may comprise, for example, tin (Sn), silver (Ag), nickel (Ni), zinc (Zn) The solder layer may be formed during manufacture as described in connection with FIG. 7, in accordance with various embodiments. In other embodiments, the solder layer may be formed by electrolytic plating, paste printing, ball bumping, or other compatible process.

The various processes are described in turn as a plurality of separate processes in a manner that is most useful for understanding the claimed subject matter. However, the order of description should not be interpreted as suggesting that these processes are order-dependent. The processes of process 200 may be performed in a suitable order other than those depicted. In some embodiments, the process 200 may include the measures described in connection with Figs. 3-8, and vice versa.

FIG. 3 schematically illustrates a cross-sectional view of some selected processes prior to embedded bridges, in connection with the package substrate fabrication process 200 illustrated in FIG. 2, in accordance with some embodiments. In step 392, the substrate after the step of forming the dielectric layer 320 on the patterned metal layer 310 is depicted, as can be seen. In embodiments, the patterned metal layer and any number of layers below the patterned metal layer can be part of the substrate and can be formed in any manner known in the art. For example, the patterned metal layer may be an upper or outermost conductive layer of a build-up layer formed of a semi-additive process (SAP).

In embodiments, dielectric layer 320 is, for example, epoxy-based laminate material, a silicon oxide (e.g., SiO 2), for silicon carbide (SiC), silicon carbonitrile nitride (SiCN) or silicon nitride (e.g. , SiN, Si 3 N 4, and the like). Other suitable dielectric materials may also be used including, for example, a low-k dielectric material having a dielectric constant (k) that is less than the dielectric constant k of silicon dioxide. The dielectric layer 320 may be deposited by depositing a dielectric material using any suitable technique including, for example, atomic layer deposition (ALD), physical vapor deposition (PVD) or chemical vapor deposition . In embodiments, the dielectric layer 320 may comprise a polymer (epoxy-based resin) having a silica filler to provide appropriate mechanical properties to meet the reliability requirements of the package. In embodiments, dielectric layer 320 may be formed as a polymeric film, for example, by ABF lamination. The dielectric layer 320 may have an appropriate ablation rate to enable laser patterning as described elsewhere in the present application.

In process 394, the substrate after depicting cavity 332 on dielectric layer 320 is depicted, as can be seen. In embodiments, the cavity 332 may be a via hole that can be laser drilled into the dielectric layer 320 to expose a portion of the patterned metal layer 310. Any conventional technique, such as using a CO 2 laser, may be used to form the cavity 332. In embodiments, to remove smeared dielectric material, such as an epoxy-resin, from the surface of the patterned metal layer 310 to prevent smear residues from forming another dielectric layer A desmear process may be applied later.

In embodiments, a metallic seed layer 330 is then deposited on top of the N-2 layer with any suitable technique. In some embodiments, electroless plating may be used to form the metallic seed layer 330. For example, a catalyst such as palladium (Pd) may be deposited followed by an electroless copper (Cu) plating process. In some embodiments, physical vapor deposition (i.e., sputtering) techniques may be used to deposit the metallic seed layer 330. In process 396, the substrate is depicted after formation of a photosensitive layer, such as, for example, a DFR (dry film resist) layer 336, as can be seen. In embodiments, the DFR layer 336 may be laminated and patterned using any technique known in the art. The openings 328 of the DFR layer 336 may have a greater lateral dimension than the cavity 332. In other embodiments,

Figure 4 schematically illustrates a cross-sectional view of some other selected processes prior to embedding the bridge, in connection with the package substrate manufacturing process illustrated in Figure 2, in accordance with some embodiments. In step 492, as can be seen, the substrate after depression of the conductive material in cavity 332 and opening 328 is depicted. In embodiments, the conductive material may be a metal such as, for example, a metal containing nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper And may include a first electrically conductive material. In embodiments, cavity 332 and opening 328 may be filled with, for example, an electroplating process. In embodiments, an electrolytic copper plating process may be performed to fill the cavity 332 and the opening 328. In embodiments, the interconnect structure 410 formed in process 492 may protrude above the surface of the N-2 layer.

In step 494, as can be seen, the substrate after the DFR is stripped is depicted. In embodiments, the DFR may be removed using any conventional strip process. In step 496, as can be seen, the substrate after etching the metallic seed layer 330 is depicted. In embodiments, the interconnect structure 410 may be further depicted by DFR stripping and may expose the lower dielectric layer 320.

Figure 5 schematically illustrates a cross-sectional view of some selected processes for embedding bridges, in connection with the package substrate manufacturing process illustrated in Figure 2, in accordance with some embodiments. In step 592, as can be seen, the substrate after forming the bridge cavity 502 is depicted. In embodiments, bridge cavity 502 may be provided for placement of the bridge. In embodiments, at least a portion of the dielectric layer 320 may be removed by exposure to heat or chemicals to form the bridge cavity 502. In embodiments, the bridge cavity 502 may be laser drilled into the dielectric layer 320 to expose a portion of the patterned metal layer 310. In other embodiments, the bridge cavity 502 may remain open during fabrication of the previously discussed build-up layer. In yet other embodiments, the patterning process may be used to form the bridge cavity 502 through the build-up layer discussed previously. For example, the dielectric layer 320 may be comprised of a photosensitive material that is well tolerated by masking, patterning, and etching processes.

In step 594, as can be seen, the substrate after loading the bridge 530 (only a portion of the bridge is shown) is depicted. In embodiments, the bridge 530 includes a bridge substrate comprised of a glass or semiconductor material such as high resistivity silicon (Si) formed over the electrical routing interconnect feature to provide chip-to-chip connection between the dies can do. In embodiments, the bridge 530 may be mounted on the patterned metal layer 310 using an adhesive layer 520. The adhesive layer 520 material may comprise any suitable adhesive configured to withstand the process associated with the manufacture of the substrate. In embodiments, a chemical treatment such as a copper roughing technique may be applied to improve adhesion between the bridge 530 and its surrounding surface. The bridge 530 may have a routing feature 540 such as a pad that protrudes over the bridge substrate surface and is configured as an attachment point to route electrical signals to and from the bridge 530 .

In step 596, as will be seen, the substrate after the dielectric layer 550 is formed on the bridge 530 to substantially form the N-1 layer on the N-2 layer is depicted. In embodiments, dielectric layer 550 may be comprised of any of a wide variety of suitable dielectric materials. In embodiments, dielectric layer 550 may be formed by depositing a dielectric material using any suitable technique, including, for example, ALD, PVD or CVD techniques. In embodiments, dielectric layer 320 may comprise a polymer (e.g., epoxy resin) and may include a filler (e.g., silica) to provide appropriate mechanical properties to meet the reliability requirements of the package. May be further included. In embodiments, dielectric layer 320 may be formed as a polymeric film, for example, by ABF lamination. Dielectric layer 550 may have an appropriate ablation rate to enable laser patterning as described elsewhere in the present application.

6 is a cross-sectional view of some selected processes for forming a stacked interconnect structure (e.g., interconnect structure 130 of FIG. 1) in connection with the package substrate fabrication process illustrated in FIG. 2, in accordance with some embodiments. As shown in FIG.

In step 692, as can be seen, the substrate after depicting the cavity 604 on the dielectric layer 550 is depicted. In embodiments, the cavity may be a via hole that can be laser drilled into the dielectric layer 550 to expose a portion of the lower routing feature 540. Any conventional technique, such as using a CO 2 laser, may be used to form the cavity 604. In embodiments, a desmear process may be subsequently applied to remove the smeared dielectric material, such as epoxy resin, from the bottom surface of the cavity 604 to prevent the smear residue from forming another dielectric layer. In embodiments, a metal seed layer 610 is then deposited on top of the N-1 layer by any suitable technique. In some embodiments, electroless plating may be used to form the metallic seed layer 610. For example, a catalyst such as palladium (Pd) may be deposited followed by an electroless copper (Cu) plating process. In some embodiments, physical vapor deposition (i.e., sputtering) techniques may be used to deposit the metallic seed layer 330.

In process 694, as will be seen, a substrate is depicted after forming a photosensitive layer such as, for example, a DFR layer 612 to substantially form the N layer on the N-1 layer. In embodiments, the DFR layer 612 is laminated and patterned using any technique known in the art. In embodiments, the opening 614 of the DFR layer 612 may have a greater lateral dimension than the cavity 604. [ In embodiments, process 694 may be performed on both the top and bottom sides of the substrate (e.g., the S1 and S2 sides of FIG. 1).

In step 696, as can be seen, the substrate after depression of the conductive material in cavity 604 and opening 614 is depicted. In embodiments, the conductive material may comprise a metal including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu) And may include the same first electrically conductive material. In embodiments, the cavity 604 and the opening 614 may be filled, for example, with an electroplating process. In embodiments, the joint 620 may be formed by performing an electrolytic copper plating process to fill the cavity 604 and the opening 614. At step 696, the joint 620 may be planarized by removing the over-plated fill metal by one or more of etching, buff grinding, chemical-mechanical polishing, and the like . For example, chemical mechanical polishing (CMP) or buff grinding may be used first to planarize the joint 620, and then etching may be used to remove any residual fill metal from the top surface of the DFR layer 612 . In embodiments, the interconnect structure or joint 620 formed in process 696 may be projected onto the surface of the N-1 layer (e.g., in the formation of the pad structure) and configured to connect the bridge 530 to the die .

In embodiments, other stacked FLI interconnection structures (e.g., interconnect structure 135 of FIG. 1) may be partially formed by processes 692, 694, and 696.

Figure 7 schematically illustrates a cross-sectional view of some other selected processes for forming a stacked interconnect structure, in connection with the package substrate fabrication process illustrated in Figure 2, in accordance with some embodiments. In step 792, as can be seen, the substrate after forming the barrier layer 710 directly above the joint is depicted. In embodiments, the barrier layer 710 may comprise a second electrically conductive material, such as a barrier metal, and may be applied to cover the joint. The barrier layer 710 may be configured to suppress diffusion of the first conductive material used in the joint while maintaining electrical connection between the joint and the die. The second conductive material may be different from the first conductive material. The second electrically conductive material may be selected from the group consisting of Ni, tantalum, tantalum nitride, titanium nitride, tungsten titanium, hafnium, niobium, zirconium, Zr), vanadium (V), or tungsten (W) and combinations thereof. In some embodiments, the second electrically conductive material can comprise a conductive ceramic such as tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride. The barrier layer 710 may be composed of a plurality of layers of different materials in some embodiments. In embodiments, process 792 can include applying a protective film on the backside of the substrate.

The barrier layer 710 may be deposited using any suitable deposition technique. In some embodiments, one or more barrier materials of the barrier layer 710 may be deposited using PVD techniques. The barrier layer 710 may be formed using other suitable deposition techniques in other embodiments.

In step 794, as can be seen, the substrate after depicting the solder layer 720 just above the barrier layer is depicted. In embodiments, the solder layer 720 may comprise a third electrically conductive material, such as a soluble metal alloy, and may be applied over the barrier layer 710. In embodiments, the third conductive material may be different from the first and second conductive materials. The third electrically conductive material may comprise, for example, tin (Sn), silver (Ag), nickel (Ni), zinc (Zn) and combinations thereof. In embodiments, a solder layer 720 may be used to bond the sub-structure with the die and to maintain electrical connection between the sub-structure and the die. In embodiments, the joint 620, the barrier layer 710 and the solder layer 720 form a generally interconnect structure to form a bridge 530 and at least one of the dies 110 and 120, The electrical signals between the dies can be routed.

In step 796, as can be seen, the substrate after stripping the DFR layer 612 is depicted. In embodiments, the DFR layer 612 may be removed using any conventional strip process. In embodiments, a portion of the metallic seed layer 610 may be removed, for example by etching, to further illustrate the interconnect structure. In some embodiments, the etch process may include wet etching of the metallic seed layer 610. Other suitable etching techniques or chemical reactions may be used in other embodiments. In embodiments, the protective film on the back side of the substrate may also be removed.

In embodiments, other stacked FLI interconnection structures (e.g., interconnect structure 135 of FIG. 1) may be partially formed by processes 792, 794, and 796.

Figure 8 schematically illustrates a cross-sectional view of some selected processes for completing a stacked interconnect structure, in connection with the package substrate manufacturing process illustrated in Figure 2, in accordance with some embodiments. In step 892, the substrate after the bump region is exposed on the top side (e.g., the S1 side in FIG. 1) is depicted. In embodiments, a solder resist (SR) layer may be deposited on the dielectric layer 550. In embodiments, the SR layer may be patterned in the non-bump region to cover traces or other electrical routing features and also to form a fiducial pad, e.g., pad 802, for assembly. Thereafter, the bump region SR layer on the upper side of the substrate (for example, the S1 side in Fig. 1) can be removed with a technique such as SR exposure or SR development. In other embodiments, the SR layer may be removed from the bump region using any suitable technique, including, for example, patterning techniques such as etching and / or lithography. In embodiments, process 892 may further include SR lamination and formation (not shown) of SRO (solder resist openings) on the bottom of the substrate (e.g., the S2 side of FIG. 1).

In step 894, as can be seen, the substrate after forming the protective film 804 is depicted. The protective film 804 may protect the component on the top of the substrate (e.g., the S1 side in FIG. 1) during machining on the back side (e.g., S2 side in FIG. 1) of the substrate. In embodiments, the protective film 804 may be formed by any suitable technique, such as a thin film deposition technique. In embodiments, a nickel-palladium-gold (NiPdAu) lead surface finish (SF) may be applied (not shown) on the backside of the substrate while the protective film 804 is applied to the top of the substrate.

In step 896, as can be seen, the substrate after the round bump top is formed on the interconnect structure is depicted. In embodiments, the protective film 804 may be removed first, and then the solder layer 720 may be reflowed into a round shape using a thermal process that raises the temperature of the solder layer beyond the reflow temperature of the solder material .

In embodiments, other stacked FLI interconnection structures (e.g., interconnect structure 135 of FIG. 1) may be partially formed by processes 892, 894, and 896.

9 schematically illustrates a flow diagram of an assembly process 900 using a package substrate with embedded bridge interconnects, in accordance with some embodiments. Such a package substrate can be manufactured through the exemplary process described above with reference to FIGS. 2-8.

The assembly process 900 begins with a process 910 of preparing a package substrate having a built-in bridge with a stacked interconnect structure (e.g., interconnect structure 130 of FIG. 1). The package substrate depicted in FIG. 8 may be used in the assembly process 900.

In process 920, an IC chip having a chip I / O connection point (e.g., a pad, bump or pillar) may be received. The IC chip may generally be of any conventional type, but in some embodiments the IC chip may be a processor, such as a microprocessor, with a large I / O count. In some embodiments, the IC chip may be a large memory die with an I / O count. In some embodiments, solder may be applied to the chip I / O junction.

In process 930, the IC chip may be aligned with the package substrate such that the soldered chip I / O connection points are aligned with the stacked interconnect structures. The solderable material and / or solder on the chip I / O junctions of the stacked interconnect structures are then reflowed in process 940 to attach the IC chip to the stacked interconnect structures. Additional processing may be performed to complete the packaging in process 950. For example, in some embodiments, an electrically insulating material may be deposited and / or the package substrate may be further connected to the circuit board to encapsulate or partially encapsulate the IC chip.

Embodiments of the present invention may be implemented in a system using any suitable hardware and / or software to configure as desired. 10 schematically illustrates a computing device including embedded bridge interconnects with stacked interconnect structures on a substrate, as described in this application, in accordance with some embodiments. The computing device 1000 may receive a substrate, such as a motherboard 1002. The motherboard 1002 may include a number of components including, but not limited to, a processor 1004 and at least one communication chip 1006. [ The processor 1004 may be physically and electrically connected to the motherboard 1002. In some implementations, the at least one communications chip 1006 may also be physically and electrically connected to the motherboard 1002. In further implementations, the communications chip 1006 may be part of the processor 1004.

Depending on the application, the computing device 1000 may include other components that may or may not be physically and electrically connected to the motherboard 1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, , A touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a GPS device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera and a mass storage device , DVD, etc.).

The communication chip 1006 may enable wireless communication to transfer data to and from the computing device 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., capable of communicating data by using modulated electromagnetic radiation through non-solid media. The term does not imply that the associated device does not include any wires, although this may not be the case in some embodiments. The communication chip 1006 may include, but is not limited to, an IEEE standard (IEEE 802.11 group) including Wi-Fi, an IEEE 802.16 standard (e.g., IEEE 802.16-2005 Amendment) Including any LTE project (e.g., an advanced LTE project, an ultra mobile broadband (UMB) project (also referred to as "3GPP2 "), etc.) Can be implemented. An IEEE 802.16 compatible BWA network is generally referred to as a WiMAX network, which stands for "Worldwide Interoperability for Microwave Access," which is a certification mark for products that have passed the IEEE 802.16 standard conformance and interoperability testing. The communication chip 1006 may be connected to a Global System for Mobile Communications (GSM), a General Packet Radio Service (GPRS), a Universal Mobile Telecommunications System (UMTS), a High Speed Packet Access (HSPA), an Evolved HSPA Can be driven. The communication chip 1006 may be driven according to EDGE (Enhanced Data for GSM Evolution), GERAN (GSM EDGE Radio Access Network), UTRAN (Universal Terrestrial Radio Access Network), or E-UTRAN (Evolved UTRAN). The communication chip 1006 may be any one of 3G, 4G, 5G, and 10G as well as Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution- And may be driven according to any other wireless protocol specified further. The communication chip 1006 may be driven in accordance with other wireless protocols in other embodiments.

The computing device 1000 may include a plurality of communication chips 1006. For example, the first communication chip 1006 may be dedicated for short range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 1006 may be a GPS, EDGE, GPRS, CDMA, WiMAX, Lt; RTI ID = 0.0 > LTE, < / RTI > Ev-DO and others.

The processor 1004 of the computing device 1000 may include an IC assembly (not shown) including a substrate (e.g., the package substrate 150 of Figure 1) having a built-in bridge with a stacked interconnect structure as described in this application (E.g., the IC assembly 100 of FIG. 1). For example, the circuit board 190 of FIG. 1 may be a motherboard 1002 and the processor 1004 may include a die 110 connected to the package substrate 150 using the interconnect structure 130 of FIG. Lt; / RTI > Package substrate 150 and motherboard 1002 may be connected together using package level interconnections. The term "processor" may refer to any device or portion of a device that processes electronic data from a register and / or memory and transforms the electronic data into a register and / or other electronic data that may be stored in memory.

The communications chip 1006 may also include an IC assembly (e.g., a package substrate 150) including a substrate (e.g., the package substrate 150 of FIG. 1) having a built-in bridge with a stacked interconnect structure as described in the present application (E.g., the die 120 of FIG. 1) that can be packaged in a package (e.g., IC assembly 100 of FIG. 1). In further implementations, other components (e.g., memory devices or other integrated circuit devices) received within the computing device 1000 may include a substrate having a built-in bridge having a stacked interconnection structure as described herein (E.g., die 110 of FIG. 1) that can be packaged in an IC assembly (e.g., IC assembly 100 of FIG. 1) that includes a substrate (e.g., package substrate 150 of FIG. 1) . ≪ / RTI > In accordance with some embodiments, a multiprocessor chip and / or memory chip may be located on the same package substrate, and a built-in bridge with a stacked interconnect structure may be used to electrically couple signals between any two of the processors or memory chips Lt; / RTI > In some embodiments, a single processor chip may be coupled to another processor chip using a first embedded bridge, and may be coupled to the memory chip using a second embedded bridge.

In various implementations, the computing device 1000 may be a laptop, a netbook, a notebook, an Ultrabook , a smartphone, a tablet, a PDA, an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, , An entertainment controller, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 1000 may be any other electronic device that processes data.

<Examples>

According to various embodiments, the present invention provides a lithographic apparatus comprising: a substrate; a bridge embedded in the substrate configured to route electrical signals between the first die and the second die; And a device or an integrated circuit assembly that may include an interconnect structure electrically connected to the bridge. The interconnect structure includes a via structure including a first conductive material disposed to route electrical signals through at least a portion of the substrate, a barrier layer comprising a second conductive material disposed on the via structure, and a barrier layer disposed on the barrier layer, 3 &lt; / RTI &gt; conductive material. The first conductive material, the second conductive material, and the third conductive material may have different chemical compositions.

In embodiments, the bridge may further comprise a pad. The first conductive material may be in direct contact with the pad.

In embodiments, the via structure may protrude beyond the surface of the outermost build-up layer of the substrate.

In embodiments, the barrier layer may cover the surface of the via structure to inhibit diffusion of the first conductive material through the barrier layer.

In embodiments, the first die may comprise a processor, and the second die may comprise a memory die or other processor.

In embodiments, the electrical signal may be an input / output (I / O) signal.

In embodiments, the bridge may comprise a semiconductor material comprising silicon (Si), and the substrate may comprise an epoxy based dielectric material.

In embodiments, the bridge may be embedded in the substrate using ABF lamination.

In embodiments, the first conductive material may comprise copper (Cu); The second conductive material may comprise nickel (Ni); The third conductive material may include tin (Sn).

In accordance with various embodiments, the present invention describes the fabrication of a packaging substrate of an integrated circuit assembly. In some embodiments, the method includes the steps of embedding a bridge in a substrate, forming a joint comprising a first conductive material connected to a bridge that routes an electrical signal over the surface of the substrate; Forming a barrier layer comprising a second conductive material directly over the joint; And forming a solder layer comprising a third conductive material directly over the barrier layer. The barrier layer and the solder layer may be configured to route electrical signals.

In embodiments, embedding the bridge in the substrate may further comprise forming a bridge cavity, placing the bridge in the bridge cavity, and laminating the dielectric material over the bridge.

In embodiments, forming the joint may include forming a via cavity in the substrate, forming an opening in the photosensitive material over the via cavity, and depositing a first conductive material in the via cavity and the opening using a plating process May be further included.

In embodiments, forming the barrier layer may include depositing a second conductive material on the joint.

In embodiments, forming the solder layer may include depositing a third conductive material on the barrier layer.

In embodiments, the method may further include reflowing the solder layer to form a round bump.

In embodiments, the first conductive material may comprise copper (Cu); The second conductive material may comprise nickel (Ni); The third conductive material may include tin (Sn).

In accordance with various embodiments, the present invention describes a storage medium having multiple instructions configured to cause a device to perform any of the above-described methods in response to execution of a command by a device.

In accordance with various embodiments, the present invention describes an apparatus for a bridge interconnect having means for implementing any of the aforementioned methods.

In accordance with various embodiments, the present invention describes an article made by any of the aforementioned methods.

According to various embodiments, the present invention provides a method of manufacturing a semiconductor device comprising a first die and a second die; And a substrate having a built-in bridge and interconnect structure. The bridge and interconnect structure may be configured to route electrical signals between the first die and the second die.

The interconnect structure may include a via structure including a first conductive material disposed to route an electrical signal through at least a portion of the substrate, a barrier layer comprising a second conductive material disposed on the via structure, And a solderable material comprising a third conductive material. The first conductive material, the second conductive material, and the third conductive material may have different chemical compositions.

In embodiments, the first conductive material may comprise copper (Cu); The second conductive material may comprise nickel (Ni); The third conductive material may include tin (Sn).

In embodiments, the bridge may comprise a semiconductor material comprising silicon (Si). The substrate may comprise a dielectric material.

In embodiments, the first die may comprise a processor, and the second die may comprise a memory die or other processor.

In embodiments, the first die may comprise a memory die, and the second die may comprise another memory die or processor.

In some embodiments, the system or computing device may further include a circuit board. The circuit board may include an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a GPS device, a compass, a Geiger counter, an accelerator, a gyroscope, Lt; RTI ID = 0.0 &gt; and / or &lt; / RTI &gt; In some embodiments, the system or computing device may be a wearable computer, a smartphone, a tablet, a PDA, a mobile phone, an ultra mobile PC, an Ultrabook , a netbook, a laptop, a laptop computer, a server, , A monitor, a set-top box, an entertainment controller, a digital camera, a portable music player, or a digital video recorder.

The various embodiments may include any suitable combination of the above-described embodiments, including embodiments of the embodiments described above, in other embodiments, and / or in connection form (and, for example, And "may be" and / or "). In addition, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer readable media) in which instructions that, when executed, result in the execution of any of the above-described embodiments are stored. In addition, some embodiments may include an apparatus or system having any suitable means for implementing the various processes of the above-described embodiments.

The above description of the illustrated implementations, including those described in the Summary, is not intended to be exhaustive or to limit the embodiments of the invention to the precise forms disclosed. Although specific implementations and embodiments are described for illustrative purposes in the present application, various equivalent variations are possible within the scope of the present invention, as will be appreciated by those skilled in the art.

These modifications can be made to the embodiments of the present invention in light of the above detailed description. The terms used in the following claims should not be construed as limiting the various embodiments of the invention to the specific implementations set forth in the specification and claims. Rather, the scope should be determined entirely by the following claims that are to be construed in accordance with established principles of claim interpretation.

Claims (21)

  1. As an apparatus,
    A substrate comprising a patterned metal layer, and a dielectric layer formed over and around the patterned metal layer;
    A bridge constructed from a glass substrate and mounted on the patterned metal layer by an adhesive layer inside the substrate;
    A first die electrically connected to the bridge; And
    A second die electrically connected to the bridge,
    Wherein the bridge includes at least one electrical routing feature disposed therein for routing electrical signals between the first die and the second die, the electrical routing features being located on the glass substrate surface of the bridge And one or more pads protruding above the glass substrate surface and disposed within the dielectric layer of the substrate.
  2. 2. The apparatus of claim 1, wherein the bridge comprises a glass bridge substrate.
  3. delete
  4. 2. The apparatus of claim 1, wherein the one or more electrical routing features comprise one or more interconnect structures.
  5. 5. The apparatus of claim 4, wherein the first die or the second die is electrically connected to the bridge by one of the one or more interconnect structures.
  6. 5. The method of claim 4, wherein the interconnect structure among the one or more interconnect structures comprises:
    A via structure comprising a first conductive material, the via structure routing the electrical signals through at least a portion of the substrate;
    A barrier layer comprising a second conductive material disposed on the via structure; And
    A solderable material comprising a third conductive material disposed on the barrier layer;
    Wherein the first conductive material, the second conductive material, and the third conductive material have different chemical compositions from each other.
  7. 7. The apparatus of claim 6, wherein the barrier layer covers a surface of the via structure to prevent diffusion of the first conductive material.
  8. 7. The apparatus of claim 6, wherein the first conductive material comprises copper (Cu), the second conductive material comprises nickel (Ni), and the third conductive material comprises tin (Sn).
  9. 9. The apparatus of any one of claims 1, 2, and 4 to 8 wherein the first die comprises a processor and the second die comprises a memory die or another processor.
  10. 9. The apparatus of any one of claims 1, 2, and 4 to 8, wherein the electrical signals are input / output (I / O) signals.
  11. 9. The apparatus of any one of claims 1, 2, and 4 to 8, wherein the first die or the second die is also physically connected to a surface of the substrate.
  12. delete
  13. 9. The apparatus of any one of claims 1, 2, and 4 to 8, wherein the bridge is an element located in a bridge cavity of the substrate.
  14. As a system,
    Printed circuit board (PCB); And
    A package connected to the PCB
    The package comprising:
    A patterned metal layer, and a dielectric layer formed over and around the patterned metal layer;
    A bridge constructed from a glass substrate and mounted on the patterned metal layer by an adhesive layer inside the substrate;
    A first die electrically connected to the bridge; And
    A second die electrically connected to the bridge;
    Wherein the bridge includes at least one electrical routing feature disposed therein for routing electrical signals between the first die and the second die, the electrical routing features being located on the glass substrate surface of the bridge And one or more pads disposed within the dielectric layer of the substrate and projecting over the glass substrate surface,
    Wherein the bridge glass substrate comprises a glass material that is different from the material of the substrate.
  15. delete
  16. delete
  17. 15. The system of claim 14, wherein the one or more electrical routing features comprise one or more interconnect structures.
  18. 18. The system of claim 17, wherein the first die or the second die is electrically connected to the bridge by one of the one or more interconnect structures.
  19. 18. The method of claim 17, wherein the interconnect structure among the one or more interconnect structures comprises:
    A via structure comprising a first conductive material, the via structure routing the electrical signals through at least a portion of the substrate;
    A barrier layer comprising a second conductive material disposed on the via structure; And
    And a third conductive material disposed on the barrier layer,
    Lt; / RTI &gt;
    Wherein the first conductive material, the second conductive material, and the third conductive material have different chemical compositions from each other.
  20. 20. The system of any one of claims 14 and 17 to 19, wherein the first die or the second die is also physically connected to a surface of the substrate.
  21. delete
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9200973B2 (en) * 2012-06-28 2015-12-01 Intel Corporation Semiconductor package with air pressure sensor
US9429427B2 (en) 2012-12-19 2016-08-30 Intel Corporation Inductive inertial sensor architecture and fabrication in packaging build-up layers
US9147663B2 (en) * 2013-05-28 2015-09-29 Intel Corporation Bridge interconnection with layered interconnect structures
JP2014236187A (en) * 2013-06-05 2014-12-15 イビデン株式会社 Wiring board and manufacturing method therefor
JP2014236188A (en) * 2013-06-05 2014-12-15 イビデン株式会社 Wiring board and manufacturing method therefor
US20150255411A1 (en) * 2014-03-05 2015-09-10 Omkar G. Karhade Die-to-die bonding and associated package configurations
US9583426B2 (en) 2014-11-05 2017-02-28 Invensas Corporation Multi-layer substrates suitable for interconnection between circuit modules
US9418966B1 (en) * 2015-03-23 2016-08-16 Xilinx, Inc. Semiconductor assembly having bridge module for die-to-die interconnection
US9443824B1 (en) 2015-03-30 2016-09-13 Qualcomm Incorporated Cavity bridge connection for die split architecture
US9595494B2 (en) * 2015-05-04 2017-03-14 Qualcomm Incorporated Semiconductor package with high density die to die connection and method of making the same
US10283492B2 (en) 2015-06-23 2019-05-07 Invensas Corporation Laminated interposers and packages with embedded trace interconnects
WO2017052660A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Antennas for platform level wireless interconnects
US10438881B2 (en) * 2015-10-29 2019-10-08 Marvell World Trade Ltd. Packaging arrangements including high density interconnect bridge
US9852994B2 (en) 2015-12-14 2017-12-26 Invensas Corporation Embedded vialess bridges
WO2017105520A1 (en) * 2015-12-18 2017-06-22 Intel Corporation Transmissive composite film for application to the backside of a microelectronic device
US20180366438A1 (en) * 2015-12-22 2018-12-20 Intel Corporation Projecting contacts and method for making the same
US10276403B2 (en) * 2016-06-15 2019-04-30 Avago Technologies International Sales Pe. Limited High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer
US20180005944A1 (en) * 2016-07-02 2018-01-04 Intel Corporation Substrate with sub-interconnect layer
KR20180016124A (en) 2016-08-05 2018-02-14 삼성전자주식회사 Semiconductor Package
KR20190032615A (en) * 2016-08-16 2019-03-27 인텔 코포레이션 Rounded metal trace edges for reduced stress
US9837341B1 (en) * 2016-09-15 2017-12-05 Intel Corporation Tin-zinc microbump structures
US20180182707A1 (en) * 2016-12-22 2018-06-28 Intel Corporation Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same
US10468374B2 (en) 2017-03-31 2019-11-05 Intel Corporation Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
US10692830B2 (en) 2017-10-05 2020-06-23 Texas Instruments Incorporated Multilayers of nickel alloys as diffusion barrier layers
US10651126B2 (en) * 2017-12-08 2020-05-12 Applied Materials, Inc. Methods and apparatus for wafer-level die bridge
US10217708B1 (en) 2017-12-18 2019-02-26 Apple Inc. High bandwidth routing for die to die interposer and on-chip applications
US10163798B1 (en) * 2017-12-22 2018-12-25 Intel Corporation Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same
KR20190094952A (en) 2018-02-06 2019-08-14 삼성전자주식회사 Semiconductor packages

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110233764A1 (en) * 2010-03-29 2011-09-29 Hsiao-Chuan Chang Semiconductor device package and method of fabricating the same
KR101131230B1 (en) * 2009-05-06 2012-03-28 삼성전기주식회사 A printed circuit board comprising a bump supporiting part and a method of manufacturing the same

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI286372B (en) * 2003-08-13 2007-09-01 Phoenix Prec Technology Corp Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same
US6984583B2 (en) * 2003-09-16 2006-01-10 Micron Technology, Inc. Stereolithographic method for forming insulative coatings for via holes in semiconductor devices
WO2005081064A1 (en) * 2004-02-20 2005-09-01 Jsr Corporation Bilayer laminated film for bump formation and method of bump formation
JP4581768B2 (en) * 2005-03-16 2010-11-17 ソニー株式会社 Manufacturing method of semiconductor device
JP4535002B2 (en) 2005-09-28 2010-09-01 Tdk株式会社 Semiconductor IC-embedded substrate and manufacturing method thereof
US7569422B2 (en) * 2006-08-11 2009-08-04 Megica Corporation Chip package and method for fabricating the same
JP2008091638A (en) * 2006-10-02 2008-04-17 Nec Electronics Corp Electronic equipment, and manufacturing method thereof
US20080157316A1 (en) 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
US8102663B2 (en) * 2007-09-28 2012-01-24 Oracle America, Inc. Proximity communication package for processor, cache and memory
US8721901B2 (en) * 2007-10-05 2014-05-13 Micron Technology, Inc. Methods of processing substrates and methods of forming conductive connections to substrates
US7892885B2 (en) * 2007-10-30 2011-02-22 International Business Machines Corporation Techniques for modular chip fabrication
JP5150518B2 (en) * 2008-03-25 2013-02-20 パナソニック株式会社 Semiconductor device, multilayer wiring board, and manufacturing method thereof
US8253230B2 (en) * 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
JP5330065B2 (en) * 2009-04-13 2013-10-30 新光電気工業株式会社 Electronic device and manufacturing method thereof
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8569894B2 (en) * 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
JP5715334B2 (en) * 2009-10-15 2015-05-07 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2011142256A (en) * 2010-01-08 2011-07-21 Elpida Memory Inc Semiconductor device and method of manufacturing the same
US8507966B2 (en) * 2010-03-02 2013-08-13 Micron Technology, Inc. Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same
KR101139699B1 (en) * 2010-04-26 2012-05-02 한국과학기술원 passive component-stacked semiconductor chip, 3-dimensional multi-chip and 3-dimensional multi-chip package having the same
KR20120019091A (en) * 2010-08-25 2012-03-06 삼성전자주식회사 Multi-chip package and method of manufacturing the same
US8736065B2 (en) * 2010-12-22 2014-05-27 Intel Corporation Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
US8610285B2 (en) * 2011-05-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC packaging structures and methods with a metal pillar
US8581400B2 (en) * 2011-10-13 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure
US9059179B2 (en) * 2011-12-28 2015-06-16 Broadcom Corporation Semiconductor package with a bridge interposer
US8704364B2 (en) * 2012-02-08 2014-04-22 Xilinx, Inc. Reducing stress in multi-die integrated circuit structures
US8836587B2 (en) * 2012-03-30 2014-09-16 Apple Inc. Antenna having flexible feed structure with components
US9054030B2 (en) * 2012-06-19 2015-06-09 Micron Technology, Inc. Memory cells, semiconductor device structures, memory systems, and methods of fabrication
US10192804B2 (en) * 2012-07-09 2019-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace packaging structure and method for forming the same
US9006908B2 (en) * 2012-08-01 2015-04-14 Marvell Israel (M.I.S.L) Ltd. Integrated circuit interposer and method of manufacturing the same
US8872349B2 (en) * 2012-09-11 2014-10-28 Intel Corporation Bridge interconnect with air gap in package assembly
US8946900B2 (en) * 2012-10-31 2015-02-03 Intel Corporation X-line routing for dense multi-chip-package interconnects
US9236366B2 (en) * 2012-12-20 2016-01-12 Intel Corporation High density organic bridge device and method
US8901748B2 (en) * 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US10269619B2 (en) * 2013-03-15 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale packaging intermediate structure apparatus and method
US8916981B2 (en) * 2013-05-10 2014-12-23 Intel Corporation Epoxy-amine underfill materials for semiconductor packages
US9147663B2 (en) * 2013-05-28 2015-09-29 Intel Corporation Bridge interconnection with layered interconnect structures
KR102094924B1 (en) * 2013-06-27 2020-03-30 삼성전자주식회사 Semiconductor packages having through electrodes and methods for fabricating the same
US10192810B2 (en) * 2013-06-28 2019-01-29 Intel Corporation Underfill material flow control for reduced die-to-die spacing in semiconductor packages
US9147638B2 (en) * 2013-07-25 2015-09-29 Intel Corporation Interconnect structures for embedded bridge
US8987915B1 (en) * 2013-08-29 2015-03-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9642259B2 (en) * 2013-10-30 2017-05-02 Qualcomm Incorporated Embedded bridge structure in a substrate
US9971089B2 (en) * 2015-12-09 2018-05-15 Intel Corporation Chip-to-chip interconnect with embedded electro-optical bridge structures
US9852994B2 (en) * 2015-12-14 2017-12-26 Invensas Corporation Embedded vialess bridges

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101131230B1 (en) * 2009-05-06 2012-03-28 삼성전기주식회사 A printed circuit board comprising a bump supporiting part and a method of manufacturing the same
US20110233764A1 (en) * 2010-03-29 2011-09-29 Hsiao-Chuan Chang Semiconductor device package and method of fabricating the same

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US9640485B2 (en) 2017-05-02
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KR20140139974A (en) 2014-12-08
US10475745B2 (en) 2019-11-12
US20170207168A1 (en) 2017-07-20
CN108364926A (en) 2018-08-03
CN104218024B (en) 2018-03-30
US20150364423A1 (en) 2015-12-17
KR101588312B1 (en) 2016-01-26
DE102014107514A1 (en) 2015-03-26
CN104218024A (en) 2014-12-17
US20190013271A1 (en) 2019-01-10
US20140353827A1 (en) 2014-12-04
US10103103B2 (en) 2018-10-16

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