DE112015007283B3 - SEMICONDUCTOR PACKAGE WITH THROUGH BRIDGES-THE-CONNECTIONS - Google Patents

Abstract

A semiconductor package (200, 320) comprising: a first build-up layer (102, 204) having a top surface and a bottom surface opposite said top surface, said first build-up layer (102, 204) having a power contact (108; 206; 304) on the top surface of the first structural layer (102, 204);a second structural layer (110, 210) overlying the first structural layer (102, 204), the second structural layer (110, 210) defining a cavity overlying the power contact (108; 206); a bridge die (118, 212, 324) disposed within the cavity of the second structural layer (110, 210), the bridge die (118, 212, 324) being a bridge - having a die back and a bridge die top, said bridge die top having a plurality of bridge die top contacts, said bridge die back being electrically coupled to said power contact (108, 206); anda third build-up layer (130, 220) overlying the top of the bridge die (118, 212, 324) and disposed over the second build-up layer (110, 210), the third build-up layer (112, 220) having an interconnection trace (132; 224), wherein the interconnection trace is electrically coupled to a first bridge die top contact (230) of the plurality of bridge die top contacts, the bridge die including a bulk portion (120; 214) electrically coupled to a backside metal provided on the bridge die backside, and wherein at least one of the plurality of bridge die top contacts is electrically coupled to the bulk portion to transmit power through the bulk portion of the bridge die the at least one of the plurality of bridge die top contacts and to one or more dies electrically connected to the at least one of the plurality of bridge die top contacts.

Description

FIELD OF TECHNOLOGY

This disclosure relates generally to semiconductor packages having a bridge die, and more particularly to electrical through bridge die connections.

BACKGROUND

An integrated circuit or integrated circuits and other electronic devices can be housed on a semiconductor package. The semiconductor package may be integrated on an electronic system, such as a consumer electronics system. The integrated circuit(s) and/or electronic devices provided on the semiconductor package may have relatively fine pitch input/output requirements, as well as relatively stringent power delivery or ground plane requirements. patent document 1, DE 10 2014 107 514 A1 refers to layered interconnect structures in integrated circuit assemblies. Patent document 2, WO 2015/130264 A1 relates to a microelectronic structure.

character list

• 1A-1G stellen vereinfachte schematische Querschnittsdiagramme eines beispielhaften Halbleiter-Packages mit Durchgangsbrücken-Die-Verbindungen und einen Fertigungsprozess dafür gemäß beispielhaften Ausführungsformen der Offenbarung dar.
• 2 stellt ein vereinfachtes schematisches Querschnittsdiagramm dar, das ein Halbleiter-Package mit mehreren darin bereitgestellten Dies mit Durchgangsbrücken-Die-Verbindungen gemäß beispielhaften Ausführungsformen der Offenbarung veranschaulicht.
• 3A und 3B stellen vereinfachte schematische Querschnittsdiagramme dar, die Leistungsabgabepfade in einem Multi-Die-Halbleiter-Package ohne und mit Durchgangs-Die-Verbindungen gemäß beispielhaften Ausführungsformen der Offenbarung veranschaulichen.
• 4 stellt ein Flussdiagramm dar, das ein beispielhaftes Verfahren zum Fertigen von Halbleiter-Packages mit den Durchgangsbrücken-Die-Verbindungen aus 1-3 gemäß beispielhaften Ausführungsformen der Offenbarung veranschaulicht.
• 5A-5F stellen vereinfachte schematische Querschnittsdiagramme eines beispielhaften Brücken-Dies mit Durchgangs-Die-Verbindungen und einen Fertigungsprozess dafür gemäß beispielhaften Ausführungsformen der Offenbarung dar.
• 6 stellt ein Flussdiagramm dar, das ein beispielhaftes Verfahren zum Fertigen des Brücken-Dies mit den Durchgangs-Die-Verbindungen aus 5A-5F gemäß beispielhaften Ausführungsformen der Offenbarung veranschaulicht.

Reference is now made to the accompanying drawings, which are not necessarily to scale, and in which:

• 1A-1G 12 illustrate simplified cross-sectional schematic diagrams of an example semiconductor package with through bridge die connections and a manufacturing process therefor according to example embodiments of the disclosure.
• 2 12 is a simplified schematic cross-sectional diagram illustrating a semiconductor package having multiple dies provided therein with through-bridge die connections according to example embodiments of the disclosure.
• 3A and 3B 12 are simplified cross-sectional schematic diagrams illustrating power delivery paths in a multi-die semiconductor package with and without through-die interconnects, according to example embodiments of the disclosure.
• 4 FIG. 12 depicts a flow chart depicting an exemplary method for fabricating semiconductor packages with the via bridge die interconnects 1-3 according to exemplary embodiments of the disclosure.
• 5A-5F 12 illustrate simplified cross-sectional schematic diagrams of an example bridge die with through-die connections and a manufacturing process thereof, according to example embodiments of the disclosure.
• 6 FIG. 12 depicts a flowchart outlining an example method for fabricating the bridge die with the through die connections 5A-5F according to exemplary embodiments of the disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE DISCLOSURE

Embodiments of the disclosure are described in more detail below with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. However, this disclosure may be embodied in many different forms. Like numbers refer to like, but not necessarily the same or identical, elements throughout.

The following embodiments are described in sufficient detail to enable at least those skilled in the art to understand and use the disclosure. It is understood that other embodiments will be apparent based on the present disclosure and that process, mechanical, material, dimensional, process tooling, and parametric changes may be made.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments of the disclosure. However, it will be apparent that the disclosure may be practiced without these specific details. To avoid obscuring the present disclosure, some well-known system configurations and process steps may not be fully disclosed. Similarly, the drawings depicting embodiments of the disclosure are semi-diagrammatic and not to scale, and in particular some of the dimensions are for clarity of illustration and may be exaggerated in the drawings. Additionally, when multiple embodiments are disclosed and described as having some common features, similar and like features are commonly described with like reference numbers for clarity and ease of illustration, description and understanding thereof, even if the features are not identical.

The term "horizontal" as used herein can be defined as a direction parallel to a plane or surface (e.g. surface of a substrate) regardless of its orientation. The term "vertical" as used herein may refer to a direction orthogonal to the horizontal direction as just described. Terms such as "on", "above", "below", "bottom", "top", "side-" (as in "sidewall"), "higher", "lower", "upper", "above" and "below" can be referenced in relation to the horizontal plane. The term "processing" as used herein includes depositing material or photoresist, patterning, exposing, developing, etching, cleaning, ablating, polishing and/or removing the material or photoresist as necessary to form a described structure is required.

In example embodiments, semiconductor package structures may include a package substrate. In some cases, the package substrate can be an organic structure. In other cases, the package substrate can be inorganic (e.g. ceramic, glass, etc.). The package substrate, in example embodiments, may include a core layer with one or more interconnect layers built up on one or both sides of the core layer. The build-up layers as built up on the core may have interconnects formed therein. The interconnects can be electrical paths for signals between electronic components (e.g., integrated circuits, passive devices, etc.), input/output (I/O) connections on the semiconductor package, signal fan-out from/to the electronic components, signal connections between two or more electrical components, power delivery to electrical component(s), ground connections to electrical component(s), clock signal delivery to the electrical component(s), combinations thereof, or the like. The build-up layers can be fabricated on one or both sides of the package core. In some cases, there may be the same number of build-up layers on both sides of the package core. In other cases, the build-up layers formed on both sides of the package core may be asymmetrical. Furthermore, the core of the semiconductor package may have a plurality of vias to make electrical connections from one side of the core to the other side of the core. Thus, vias in the core may enable electrical connections between one or more build-up layers on top of the semiconductor package to one or more build-up layers on the bottom of the semiconductor package.

One or more electronic components, including at least one integrated circuit die, may be electrically and mechanically attached via any suitable mechanism, such as metal posts (e.g., copper posts), flip-chip bumps, solder bumps, any type of low-lead or lead-free solder bumps, tin-copper bumps, wire bonds, wedge bonds, controlled collapse chip connect (C4), anisotropic conductive film (ACF), nonconductive film (NCF), combinations thereof, or the like, be coupled to the package substrate. In some example embodiments, the build-up layers on the underside of the core may include one or more input/output (I/O) connections between the semiconductor package and a circuit board. Semiconductor package-to-board level interconnects may be provided on one or both sides of the package substrate. In exemplary embodiments, the semiconductor package-to-board level interconnects may be ball grid array (BGA) interconnects, other area interconnects, peripheral interconnects, or the like.

Embodiments of the disclosure may provide a semiconductor package and a method of manufacturing the semiconductor package. In exemplary embodiments, the semiconductor package may include one or more bridge dies, such as one or more embedded dies within a semiconductor package based on an embedded multi-die interconnect bridge (EMIB). as described herein. These semiconductor packages with the embedded bridge die can be fabricated using the methods disclosed herein. The bridge die may be provided within the package substrate, such as in a cavity formed within build-up layers of the package substrate. to enable relatively finer (e.g., high density) interconnections between electrical components (e.g., integrated circuits) provided on the semiconductor package. The bridge die may provide a relatively more rigid substrate than the semiconductor package substrate embedded within a portion of the semiconductor package substrate. Due to the relatively greater stiffness of the embedded bridge die, it may be possible to fabricate finer pitch interconnects between dies disposed on the surface of the semiconductor package.

In some cases, the embedded bridge die may be fabricated at a semiconductor fabrication facility (e.g., fab) while the semiconductor package substrate may be fabricated at a semiconductor packaging facility direction can be manufactured. Typically, a fab may have equipment and facilities to fabricate smaller sized features on the bridge die than could be fabricated at a packaging facility. Alternatively, silicon fabrication type tools can be provided in a packaging facility to fabricate the bridge die with relatively fine pitch structures.

In example embodiments, dies attached to the semiconductor package substrate may have portions overlying the bridge die and other portions not overlying the bridge die. In some example embodiments, the dies (e.g., integrated circuits) that are in the semiconductor package in a package as described herein may have input/output (I/O) connections for different sizes. For example, a particular die may have finer pitch I/O connections to another die that is on the semiconductor package in a package, via the bridge die, and may have other I/O connections, the looser pitch connections are where the signals do not propagate through the bridge die.

The semiconductor package may include a power layer (e.g., a metal interconnect layer of the semiconductor package at a supply voltage of one or more integrated circuits or other components of the semiconductor package) provided within the semiconductor package. Additionally, the semiconductor package may include a ground plane formed in a layer located within the package substrate, such as on the package core and/or a build-up layer. According to example embodiments, the bridge die may be configured such that a power and/or ground connection may be provided through the bridge die, for example through the bulk of the bridge die.

According to exemplary embodiments of the disclosure, the bulk portions of the bridge die may be doped with a relatively high doping level (e.g., N _A or N _D ~10 ¹⁹ -10 ²⁰ cm ^-3 etc.) to provide a relatively low bulk Provide resistivity (5 mΩ•cm etc.) of the silicon bulk of the bridge die. As a result, not only can back-end-of-line (BEOL) interconnect layers on the bridge die be used to provide signal paths across the bridge die, but the bulk of the bridge die can also be used to provide power. In exemplary embodiments, the bridge die with vias may be placed in a cavity formed in the build-up layers of the semiconductor package. In example embodiments, the bulk of the bridge die may be electrically connected to either power or ground. The bridge die may also have one or more build-up layers disposed thereon. In other words, the bridge die may have a built-up layer underneath and on top. The bridge die may provide a vertical path for power or ground from the underlying build-up layer to the overlying build-up layer in these example embodiments. It is understood that without routing through the bridge die, the power or ground in the package substrate would be routed around the bridge die. Such routing may be less direct through various interconnects (e.g., vias and/or traces), resulting in a more resistive and/or inductive path to certain end nodes (e.g., I/Os of ICs in packages) relative to the routing through the bridge die as disclosed herein.

In exemplary embodiments, the bulk of the bridge die may include impurities (e.g., acceptor or donor atoms) to provide a relatively low resistivity path for conducting power or ground. The bridge die may also include an ohmic contact on the backside of the bridge die. In exemplary embodiments, this may be a metallic (e.g., a refractory metal, etc.) contact to the backside of the bridge die. In some example embodiments, the metallic backside contact to degeneratively doped silicon may be on the backside surface (e.g., the bottom surface of the bridge die). The bridge die may also have one or more levels of interconnects (e.g., metal layers) formed thereon. Metal traces in the interconnect level(s) may provide paths for signals and/or to provide contact to the bulk of the bridge die. Contacts (e.g., vias and/or contacts to the bulk of the bridge die) may provide a path for conducting power or ground through the bulk of the bridge die. Thus, the metal traces of the interconnect layers on the bridge die can be used for routing through the bulk silicon of the bridge die as well as for signaling and I/O of the integrated circuits placed in the semiconductor package with through bridge die connections , may be used, according to exemplary embodiments of the disclosure.

In example embodiments, power may be distributed to dies that are in a package on the semiconductor package with through-bridge die interconnects. In this case, the bulk of the bridge dies can be electrically powered with a Leis device level of the semiconductor package and can provide a vertical route for power through the bridge die to the top of the bridge die. In exemplary embodiments, the bridge die may have a backside ohmic contact with the power plane. The power plane may have one or more contacts with the backside of the bridge die using a conductive paste or other adhesive provided between the bridge die and the power plane buildup layer. The bridge die may be placed in a cavity formed within the semiconductor substrate, such as by removing portions of one or more build-up layers. The bulk of the bridge die may be at the power supply voltage and the current flowing through the bridge die may depend on the power consumption as well as the other power supply connections of the integrated circuits used in the semiconductor package with through bridge die connections are in a package. It will be appreciated that by providing power through the bridge die rather than having to route power paths around the bridge die, a more direct (e.g., relatively more vertical) power path for the I/Os of the integrated circuits used in the semiconductor Package are in a package can be deployed. In exemplary embodiments, providing power in a more direct path as disclosed herein may result in a generally higher quality of power delivery, such as with reduced resistive and dynamic drop from the source power voltage or with reduced variation of power delivery across different dies and/or different Parts of a die that are in a package in the semiconductor package.

In example embodiments, ground connections may be provided to dies that are on the semiconductor package with via bridge die connections in a package. In this case, the bulk of the bridge die may be electrically connected to a ground plane of the semiconductor package and may provide a vertical route for ground through the bridge die to the top of the bridge die. In exemplary embodiments, the bridge die may have a backside ohmic contact with the ground plane. The ground plane may have one or more contacts to the backside of the bridge die using a conductive paste or other adhesive provided between the bridge die and the build-up layer of the ground plane. The bridge die may be placed in a cavity formed within the semiconductor substrate, such as by removing portions of one or more build-up layers. The bulk of the bridge dies may be at the reference/ground voltage (e.g., 0 volts) and the return current flowing through the bridge die from the integrated circuits in a package may depend on power consumption and the others Connections to ground depend on the integrated circuits that are in the semiconductor package with through-bridge die connections in a package. It will be appreciated that by providing ground connections through the bridge die, rather than having to route ground paths around the bridge die, a more direct (e.g., relatively more vertical) ground path for the I/Os of the integrated circuits used in the semiconductor Package are in a package can be deployed. In exemplary embodiments, providing ground connections in a more direct path as disclosed herein may result in a generally higher ground connection quality, such as with reduced resistive drop and relatively closer alignment to the reference voltage or with reduced ground voltage variation across different dies and/or different parts a die that are in the semiconductor package in a package.

1A-1G 12 illustrate simplified cross-sectional schematic diagrams of an example semiconductor package with via bridge die connections and a manufacturing process therefor according to example embodiments of the disclosure. Although FIG 1A-1G While FIG. 1 depicts a particular process flow and resulting semiconductor package with through bridge die interconnects, it is understood that variations in the processes and structures are contemplated and encompassed by the disclosure provided herein. For example, it should be understood that some processes may be performed out of the order presented herein. As another example, it should be understood that some processes may have appropriate substitutes that may be implemented without departing from embodiments of the disclosure.

The processes as illustrated herein can be implemented to fabricate a plurality of semiconductor packages with through bridge die interconnects simultaneously or nearly simultaneously. Although a particular fabrication sequence is shown herein as fabricating various structures and/or features, both final and/or temporary, any variations for fabricating similar features may be implemented in accordance with exemplary embodiments of the disclosure. Furthermore, additional and/or fewer features than the features disclosed herein may be present for fabricating the semiconductor package according to example embodiments of the disclosure. Although the Where cross-sections as illustrated herein show a specific number of semiconductor packages (e.g., a single semiconductor package) being fabricated concurrently on a package substrate sheet, it is understood that any number of semiconductor packages may be present can be manufactured simultaneously or almost simultaneously on a specific package substrate board. In addition, while an exemplary embodiment of the sequence of processes for fabricating a semiconductor package having through-bridge die interconnects is illustrated on a single package substrate board, it should be understood that there may be any number of package substrate boards that may be simultaneously and/or or processed nearly simultaneously by any of the processes outlined herein. For example, some processes may be batch processes, where a particular entity may be processed along with another of that entity. In other cases, unit processes on work in progress (WIP, work-in-progress) can be performed sequentially.

1A 12 illustrates a simplified cross-sectional schematic diagram of an example semiconductor package core 100 upon which build-up layers may be fabricated, according to example embodiments of the disclosure. At this point, the package core 100 may have a size larger than the size of the package substrate is. In other words, the package substrate and the core can be singulated into separate semiconductor packages after other batch manufacturing processes are completed with other package substrates on the same board. The package core 100 may have any suitable size and/or shape. For example, in example embodiments, the package core 100 may be a rectangular plate. In exemplary embodiments, the package core 100 may be made of any suitable material, including polymeric material, ceramic material, plastics, composite materials, glass, epoxy laminates of fiberglass panels, FR-4 materials, FR-5 materials, combinations thereof, or the like. Although not shown here, it is understood that the package core 100 may have vias formed therein. Vias can be used to propagate electrical signals from the top of the package core 100 to the bottom of the package core 100 and vice versa.

1B FIG. 12 shows a simplified cross-sectional schematic diagram of a build-up layer 102 formed on the package core 100. FIG 1 is fabricated with a power plane contact 108, according to example embodiments of the disclosure. The build-up layer 102 may have dielectric materials 106 and electrical connections 104, 108 (e.g., vias, pads, traces, etc.) thereon. The power plane contact 108 may have a relatively large contact area compared to other electrical connections 104 in example embodiments. In some example embodiments, the power plane contact 108 may be fabricated to have as large a surface area as permitted by appropriate packaging design rules. In some example embodiments, the power plane contact 108 may be slotted or have various other formation patterns to avoid having a relatively large continuous metal surface within the dielectric material 106 . By separating the face of the power plane contact 108, a relatively more robust design with a relatively greater tolerance for temperature cycling, relatively reduced failure rates, etc. can be realized in example embodiments.

The build-up layer 102 or the interconnection layer may be formed by a variety of suitable processes. Dielectric material 106 may be laminated to semiconductor package core 100 . In exemplary embodiments, the dielectric laminate may be any suitable material, including polymeric material, ceramic material, plastics, composite materials, liquid crystal polymer (LCP), epoxy laminates of fiberglass panels, FR-4 materials, FR-5 materials, combinations thereof, or the like. In some example embodiments, the package core 100 and the build-up dielectric material 106 may be the same type of material. In other exemplary embodiments, the package core 100 and the build-up dielectric material 106 may not be constructed of the same type of material. Vias and/or trenches may be patterned in build-up layer 102 using any suitable mechanism, including photolithography, plasma etching, laser ablation, wet etching, combinations thereof, or the like. The vias and trenches may be defined by vertical and horizontal metal lines within build-up layer 102, respectively. The vias and trenches can then be filled with metal, such as by electroless metal plating, electrolytic metal plating, physical vapor deposition, combinations thereof, or the like. Excess metal may be removed by any suitable mechanism, such as etching, cleaning, polishing, and/or chemical mechanical polishing (CMP), combinations thereof, or the like.

1C 12 illustrates a simplified cross-sectional schematic diagram of a plurality of build-up layers 102, 110, 112 formed on the package core 100. FIG 1A is manufactured, according to exemplary embodiments of the disclosure. In exemplary embodiments, subsequent build-up layers 110, 112 may be fabricated in a manner similar to the fabrication of the first build-up layer 102. FIG. It should also be understood that although the build-up layers 102, 110, 112 are shown on the top of the package core 100, in example embodiments of the disclosure the build-up layers are on the bottom of the package core 100 and/or on both sides of the package core. Kerns 100 can be manufactured. Indeed, in some exemplary embodiments, the build-up layers on both sides of the core may be fabricated at or near the same time. For example, the dielectric material 106 and/or the metal may be laminated to both sides of the package core 100 in these example embodiments. Furthermore, in these exemplary embodiments, other processes such as plating and/or cleaning processes may be performed for a build-up layer fabricated on both sides of the package core 100 .

As discussed above, the build-up layers 110, 112, as shown in FIG 1C illustrated, can be made of any suitable material, including but not limited to polymeric material, ceramic material, plastics, composite materials, LCP, epoxy laminates of fiberglass board, FR-4 materials, FR-5 materials, combinations thereof, or the like. As previously mentioned, the package core 100 and the overall dielectric build-up material 106 may be the same material type in some example embodiments. In other example embodiments, the package core 100 and at least one or more of the dielectric build-up materials 106 may not be constructed of the same type of material. Vias and/or trenches may be patterned in the build-up layer using any suitable mechanism, including photolithography, plasma etching, laser ablation, wet etching, combinations thereof, or the like. The vias and trenches may be defined by vertical and horizontal metal lines within the build-up layer, respectively. The vias and trenches can then be filled with metal, such as by electroless metal plating, electrolytic metal plating, physical vapor deposition, combinations thereof, or the like. Excess metal may be removed by any suitable mechanism, such as etching, cleaning, polishing, and/or chemical mechanical polishing (CMP), combinations thereof, or the like.

In example embodiments, the portions of build-up layers 110, 112 overlying power-plane contact 108 of build-up layer 102 may not include metal traces and/or metal pads. Indeed, design rules may prevent the provision of metal traces embedded within the dielectric build material 106 in portions of the build layers 110, 112 overlying the power plane contact 108 in example embodiments. Such an exclusion zone may be larger than the actual size of the power plane contact 108 in exemplary embodiments to allow for inaccuracies in bridge die placement and/or inaccuracies in cavity formation in subsequent processes.

1D 12 illustrates a simplified schematic cross-sectional diagram of a cavity 114 formed in the build-up layers 110, 112 shown in FIG 1C are shown with conductive adhesive 116 disposed on top of power plane contact 108, according to example embodiments of the disclosure. The cavity 114 may be formed by any suitable mechanism including, for example, laser ablation, dry etching, wet etching, combinations thereof, or the like. It is understood that for processes such as wet etching and/or dry etching, a patterning (e.g., photolithographic) process may be performed to define the areas where the build-up dielectric material 106 is to be removed. It is also understood that the formation of the cavity 114 can be performed using multiple processes. For example, a laser ablation process can be followed by an unmasked wet etch/clean process. In exemplary embodiments, the dimensions of cavity 114 may be relatively larger than the corresponding dimensions of the bridge die to be seated within cavity 114 . The difference in dimensions between the cavity 114 and the corresponding dimensions of the bridge die may depend, at least in part, on the alignment and/or placement accuracy of pick and place tools or other mechanisms used to place the bridge die within the cavity 114 is to be arranged.

Conductive adhesive 116 such as conductive ink and/or conductive paste may be applied to the surface of power plane contact 108 . The conductive adhesive 116 can be deposited on the surface of the power plane contact 108 by spin deposition, spray deposition, screen printing, doctor blade process and/or a any other suitable deposition process may be arranged. In exemplary embodiments, the conductive adhesive 116 may wet the metal of the power plate contact 108 and therefore spread over the surface of the power plate contact 108 through van der Waals forces and/or surface wetting action. In the same or other exemplary embodiments, the conductive adhesive 116 may be pressed into the cavity 114 by mechanical force, such as a doctor blade process. In still other example embodiments, conductive adhesive 116 may preferably be deposited using a screen printing process, such as by aligning a patterned screen on top of the surface of power plate contact 108 and conductive adhesive 116. In some example embodiments, the amount of conductive adhesive 116 , which is deposited in the cavity 114, can be a predetermined amount. In some cases, the predetermined amount may be approximately the expected difference between the volume of the cavity 114 and the volume of the bridge die to be embedded within the cavity 114 in subsequent processes. In this case, the conductive adhesive 116 can be sandwiched between the sidewalls of the embedded bridge die and the sidewalls of the cavity 114 . In this way, a relatively planar surface can be achieved after embedding the bridge die by filling the gap, which can be designed to account for misalignment errors in embedding the bridge die in subsequent processes.

The conductive adhesive 116 may be an epoxy material with metal nanoparticles or microparticles suspended therein. In exemplary embodiments, the conductive adhesive 116 may have silver (Ag) nanoparticles suspended therein. In other exemplary embodiments, the conductive ink may have nanoparticles of copper (Cu), tin (Sn), iron (Fe), gold (Au), combinations thereof, or the like suspended therein. In some embodiments, the conductive adhesive 116 may have non-metallic, electrically conductive particles suspended therein. In addition to having conductive materials present in conductive adhesive 116 , other chemical means may also be present to tune the physical, electrical, and/or processing properties of conductive adhesive 116 . In exemplary embodiments, the conductive adhesive 116 may include solvents that allow the conductive adhesive 116 to have a viscosity that may be relatively favorable for gap filling, while allowing for a relatively rapid increase in viscosity and/or tack for delivery into the cavity 114 is achieved. In the same or different example embodiments, the conductive adhesive 116 may include reducing agents to prevent or reduce the oxidation of metal particles that may be suspended in the conductive ink. Furthermore, the conductive adhesive 116 may contain filler particles (e.g., carbon fibers, silica particles, ceramics, etc.) in proportions that provide the conductive adhesive 116 with desirable properties, such as a preferred range of viscosity, a preferred range of tack, a preferred range of hydrophobicity (eg, surface wetting), preferred range of particle suspension properties, preferred range of curing temperatures, combinations thereof, or the like. In example embodiments, the conductive adhesive 116 may be a B-level epoxy, where the conductive adhesive 116 may be provided on top of the power board contact 108 and then cured (e.g., crosslinked, cured, etc.) after the bridge die is embedded became. In exemplary embodiments, the conductive adhesive 116 may be cured during subsequent processing, such as while the subsequent layer(s) of dielectric build-up material 106 is/are being laminated on top of the bridge die.

1F FIG. 12 illustrates a simplified schematic cross-sectional diagram of the example semiconductor package with bridge die 118 within cavity 114. FIG 1D is embedded, according to exemplary embodiments of the disclosure. Although the bridge die 118 is shown as fitting snugly within the cavity 114 , it is understood that there may be some gap between the edges of the bridge die 118 and the sidewalls of the cavity 114 . In exemplary embodiments, such a gap may be at least partially filled with an epoxy, such as conductive adhesive 116 or other non-conductive materials. The backside of bridge die 118 may rest on and make electrical contact with conductive adhesive 116 and thus be electrically coupled to power plate contact 108 . The bridge die 118 may include a bulk 120 and one or more metal interconnect layers 122 fabricated on top of the bulk 120 . The bulk portion 120 may make electrical contact with the power plate contact 108 via the conductive adhesive 116 . Metal interconnect layer(s) 122 may include dielectric materials 124 with metal vias/contacts 128 and metal lines 126 . In some example embodiments, one or more of the vias/contacts 128 may make contact with the bulk portion 120 of the bridge die 118 to conduct power from the power plane contact 108 through the conductive adhesive 116 and the bulk portion 120 and to one or more metal lines 126 or pads. These fed metal lines 126 may be electrically connected, such as via another build-up layer overlying the bridge die, to one or more dies intended to be in the semiconductor package with via bridge die contacts in a package. The metal lines 126, such as metal traces and/or contact pads, may be used for the purpose of routing the signaling I/O between the dies mounted on the semiconductor package with via bridge die contacts.

1F 12 illustrates a simplified schematic cross-sectional diagram of the bridge die embedded semiconductor package 118 with a build-up layer 130 on top and encapsulating the bridge die 118, according to example embodiments of the disclosure. The buildup layer 130 may be fabricated in a manner similar to the buildup layers 102,110,112. The build-up layer 130, like the other build-up layers 102,110,112, may include a dielectric material 106 separating the metal lines and/or pads 104,132. In exemplary embodiments, the metal lines 104, 132 to which the I/Os may be connected may be of a different size. For example, there may be smaller sized contacts 132 and larger sized contacts 104, as shown. In exemplary embodiments, the smaller gauge contacts 132 may be fabricated to metal lines 126 of the bridge die 118, and the larger gauge contacts 104 may be fabricated for contacts fabricated with underlying top layer contacts. In some exemplary embodiments, the smaller gauge contacts may be further connected to relatively fine gauge I/O contacts of one or more dies. In these example embodiments, the rigidity provided to the packaging in selected areas (e.g., areas overlying or relatively close to bridge die 118) may permit the use of relatively smaller I/O contacts Allow for sizing of dies in packages, smaller sizing pads 132 at the top layer of package build layers 130 and/or higher density routing across bridge dies 118 .

1G 12 depicts a simplified schematic cross-sectional diagram of the inventive semiconductor package with embedded bridge die 118. FIG 1F 12 with two dies 134, 136 mounted thereon, according to exemplary embodiments of the disclosure. The dies 134, 136 can be attached by any suitable mechanism. Die 134, 136 may be any suitable electronic component, including, but not on, integrated circuits, surface mount devices, active devices, passive devices, diodes, transistors, connectors, resistors, inductors, capacitors, microelectromechanical systems (MEMSs), combinations thereof, or the like limited. The dies 134, 136 may be electrically and mechanically connected via any suitable contact 138, such as metal posts (e.g., copper posts), flip chip bumps, solder bumps, any type of low-lead or lead-free solder bumps, tin-copper - Bumps, Wire Bonds, Wedge Bonds, Controlled Collapse Chip Connect (C4), Anisotropic Conductive Film (ACF), Nonconductive Film (NCF), combinations thereof, or the like, with the package core 100 be coupled. In some example embodiments, the type of contact 138 may be different for the different dies 134,136. For example, one die 134, 136 may have copper pillar contacts 138 and the other die 134, 136 may have solder bump 138 contacts. In other exemplary embodiments, the different dies 134, 136 may have the same type of contacts 138 (e.g., both dies 134, 136 have copper pillar contacts 138), but may have different dimensions of those contacts 138. In other words, one die 134, 136 can have a smaller or larger contact size than the other die 134, 136, and the build-up layer 130 on the top side can be designed to accommodate the difference in size. Furthermore, in exemplary embodiments, each of the dies 134, 136 may have different types and/or different sizes of contacts 138 to the top build layer 130 and the contacts 132, 104 thereon. For example, die-level contacts 138 may have relatively smaller dimensions when making contact with package-level contacts 132 rather than package-level contacts 104 . Indeed, in exemplary embodiments, the use of the bridge die 118 and the rigidity thereby provided may allow the use of finer die-level contacts 138 and/or package-level contacts 132 to provide I/O and/or signaling with allow higher density.

Although the sequence of processes involved in 1A-1G 1 illustrates a package (e.g., system-in-package (SiP)) having two dies 134, 136, it is understood that any suitable number of dies may be present in the SiP structure. It is further understood that the die can be any suitable type of die (e.g. elec ronical components) can be. As a non-limiting example, a microprocessor die, a non-volatile memory die, a volatile memory die, and a graphics controller die may reside on a single SiP as a semiconductor package with pass-through bridge die connections. The various dies on this SiP can be powered by contacts made via a bridge die to a power plane contact. Additionally, contacts between dies (e.g., microprocessor to non-volatile memory contact, processor to volatile memory contact, graphics controller to non-volatile memory contact, etc.) may also be made via interconnects provided on the bridge die. As another non-limiting example, a SiP with bridge dies may include a digital signal processor (DSP) die, a baseband die, a memory die, and a power amplifier die. Again in this example, one or more of the dies may be fed at least in part via via bridge die contacts to a powered contact of the SiP. Additionally, one or more of the dies may be communicatively coupled to one another, at least in part, via interconnect structures fabricated on top of the bridge die.

2 12 is a simplified cross-sectional schematic diagram illustrating a semiconductor package 200 having a plurality of dies 226, 228 provided therein with through-bridge die connections according to example embodiments of the disclosure, according to the present invention. As discussed above, a core 202 may be present with at least one build-up layer 204 provided over the core 202 and having a power plane contact 206 therein. Although a single build-up layer 204 is shown between the core 202 and the bridge die 212, it is understood that any suitable number of build-up layers between the core 202 and the bridge die 212 may be present. There may be any suitable number of build-up layer(s) 210 over the power plane build-up layer 204 . After the build-up layer(s) 210 are fabricated, a cavity overlying the power-plane contact 206 in the power-plane build-up layer 204 may be formed within the build-up layers 210 to accommodate the bridge die 212 . In example embodiments, the bridge die 212 may be disposed with vias within the cavity and over at least a portion of the power plane contact 206 . A layer of conductive adhesive 208 may be provided between the power plane contact 206 and the back side of the bulk 214 of the bridge die 212 .

It is understood that the thickness of the bridge die 212 in exemplary embodiments of the disclosure may be such that it is approximately the thickness of an integer number of build-up layers. This may be so that the processing surface remains relatively planar after embedding the bridge die 212 in the cavity formed in the build-up layers 210 . The surface planarity at these intermittent manufacturing points may provide a relatively more robust manufacturing process and resulting semiconductor package 200 . For example, providing a relatively flat intermittent surface may result in relatively improved adhesion of subsequent layers, which may overlie the bridge die 212 and the build-up layer 210 surface.

One or more overlying build-up layers 220 may be formed on top of bridge die 212 . The overlying build-up layer 220 may include metal contacts 222, 224 that may align and contact metal lines and/or vias 218 formed in one or more back-end-of-line (BEOL) interconnect layers 216 of the bridge die 212 . If the overlying build layer 220 is also the top build layer, as illustrated here, then the dies 226, 228 can be mounted thereon. In other exemplary embodiments, the build-up layer 220 overlying the bridge die 212 may not be the top build-up layer. In these cases, one or more build-up layers may be present over the build-up layer, overlying and contacting the bridge die 212, and the dies 226, 228 may be mounted on these one or more build-up layers.

The dies 226, 228 may be mounted on the semiconductor package 200 with through-bridge die interconnects in exemplary embodiments using die-to-package interconnects 230, 232, 234, 236 of various types and/or dimensions. In some example embodiments, the die-to-package interconnects 230, 234, which may be over or relatively close to the bridge die 212, may be narrower (e.g., smaller size, reduced pitch and/or higher spatial density, etc .) as the die-to-package interconnects 232, 236 not overlying the bridge die 212 and/or not in relative proximity to the bridge die 212. In some exemplary embodiments, the die-to-package interconnects 230, 232, 234, 236 may be connected to one or more power delivery metal contacts 224 of the build-up layer 220, which may be connected to power delivery metal lines and/or vias 218 of the interconnect layer(s) 216 of the bridge die 212 that can be connected again rum may be connected to the bulk 214 of the bridge die 212 , which may further in turn be connected to the power plane contact 206 of the buildup layer 204 . Thus, through the aforesaid path, power may be supplied to one or more of the dies 226, 228 through the bulk 214 of the bridge die 212 according to example embodiments of the disclosure.

First die 226 and second die 228 may be electrically and mechanically attached to package build-up layer 220 by any suitable mechanism, including metal (e.g., copper) posts, flip-chip bumps, solder bumps, any type but not limited to low-lead or lead-free solder bumps, tin-copper bumps, wire bonds, wedge bonds, C4, ACF, NCF, combinations thereof, or the like. For example, pick and place tools and processes can be used to align and attach dies 226, 228 to the package. In exemplary embodiments, copper pillars may be used to attach the die. The copper columns can be of any suitable size. For example, the copper columns may range approximately from about 10 microns to about 150 microns in width. Die 226, 228 may be aligned and attached to the semiconductor substrate by any suitable mechanism. For example, a thermosonic process can be used to fuse the copper pillars to corresponding pads on the package substrate using gold/nickel, tin/lead, or any suitable metallurgy. As another exemplary embodiment, a wave soldering process may be used to attach the dies 226, 228 to the package build-up layer 220. FIG.

In example embodiments, the underfill material 238 , 240 may be provided around the die-to-package contacts 230 , 232 , 234 , 236 between the dies 226 , 228 and the buildup layer 220 . Representative epoxy materials in underfill material 238, 240 may include an amine epoxy, imidizole epoxy, a phenolic epoxy, or an anhydride epoxy. Other examples of underfill material include polyimide, benzocyclobutene (BCB), bismaleimide-type underfill, polybenzoxazine (PBO) underfill, or polynorbornene underfill. Additionally, the underfill material 238, 240 may include a filler material such as silica. The underfill material 238, 240 may be applied by spin coating, extrusion coating, or spray coating techniques. In another embodiment, the underfill material 238, 240 includes a standard manufacturing passivation material, such as an inorganic passivation material (e.g., silicon nitride, silicon oxynitride) or organic passivation material (e.g., polyimide).

Molding 242 may be disposed on the top surface of build layer 220 and encapsulate dies 226,228. The molding material can be any suitable molding material. For example, the molding material can be a liquid dispersed thermosetting epoxy resin molding compound. The molding compound may be deposited onto the surface of the build layer 220 using any suitable mechanism, including but not limited to liquid spreading, spin coating, spray coating, doctor blade, screen printing, combinations thereof, or the like.

The molding compound, after being spread on the top surface of build layer 220, can be cured while pressure is applied thereto by a chase surface. In exemplary embodiments, the chase (e.g., a relatively flat surface that is pressed onto the top of the liquid molding material disposed on top of the build layer 220) itself can be heated. After curing (e.g., crosslinking), the deposited molding compound may solidify and form a molding 242 to adhere to the build layer 220 and encapsulate the dies 226,228. In exemplary embodiments, the molded part 242 may have fillers and/or other materials therein to preferentially control the coefficient of thermal expansion (CTE), reduce stress, impart flame retardant properties, promote adhesion and/or moisture absorption in the Molding 242 to reduce. Molding 242 may have any suitable thickness in exemplary embodiments.

As disclosed above, the semiconductor package 200 may have through-holes 244 formed in the core 202 with through-bridge die interconnects. These through-holes 244 can provide electrical connectivity of the dies 226, 228 to one or more build-up layers 246 on the underside. Similar to the top construction layers 204 , 210 , the bottom construction layer(s) 246 may also include a dielectric material 248 , such as a dielectric laminate material, and metal contacts 250 . Although a single build-up layer is shown on the bottom of the semiconductor package 200, it is understood that there may be any suitable number of build-up layers on the bottom of the semiconductor package 200. FIG. It should be understood that in some exemplary processing schemes, a plurality of construction layers on the underside of the semiconductor package 200 may be present. Indeed, in some example embodiments, there may be an equal number of build-up layers on the bottom as on the top of the semiconductor package 200 . In some cases, the processes for forming build-up layers may be amenable to forming build-up layers on both sides of the core 202 almost simultaneously and in a relatively cost-effective manner. For example, a dielectric material for a build-up layer may be laminated to both sides of the core 202 at the same time.

In example embodiments, contacts 252 for package-level I/O may be provided on bottom build-up layer(s) 246 . Contacts 252 may be any suitable semiconductor package-to-board interconnect contacts, such as ball grid array (BGA) or other area array contacts.

3A and 3B 12 are simplified cross-sectional schematic diagrams illustrating power delivery paths 316, 330 in a multi-die semiconductor package without through-die interconnects 300 and a multi-die semiconductor package with through-die interconnects 320 according to example embodiments of the disclosure.

3A 12 is a simplified cross-sectional schematic diagram illustrating a semiconductor package 300 having a bridge die 306 embedded therein, where the bridge die 306 does not provide through bridge die connections and is therefore not in accordance with the claims. In other words, the bridge die 306 can be off 3A are not used to provide a power or ground connection from the power contacts 302 and/or a power plane trace/contact 304 to the dies 312, 314 via the contacts 310. The adhesive 308 may not be a conductive material and/or the bridge die 306 may not provide a relatively electrically conductive path from the bottom to the top of the bridge die 306 . Additionally, the bridge die 306 can be fabricated such that the contacts 310 cannot be electrically connected to the bulk of the bridge die 306 . In this case, the path for providing power to different areas of the dies 312, 314 can be a curved path 316, where the power current flow can be around the embedded bridge die 306. FIG. It is understood that such a circuitous path 316 for providing power to the dies 312, 314 may result in degradation of the quality of the power supplied. For example, an indirect path to power delivery may result in relatively larger voltage drops caused by larger resistances and inductances, relatively larger noise (shot noise, EMI noise, crosstalk noise, etc.), relatively larger power delivery-induced timing jitter, and/or result in a relatively larger offset across spatially distributed power delivery points. In embodiments where the bridge die 306 is used for ground plane connections, similar types of vulnerabilities can result from a relatively circuitous path 316 .

3B 12 is a simplified cross-sectional schematic diagram illustrating a semiconductor package 320 having a bridge die 324 embedded therein, wherein the bridge die 324 is configured for through bridge die connections according to exemplary embodiments of the disclosure, according to the present invention. In other words, the bridge die 324 may be used to provide power or ground connections from the power contacts 328 and/or a power plane trace/contact 304 to the dies 312, 314 via the contacts 326. The adhesive 322 may be a conductive adhesive and the bridge die 324 may provide a relatively conductive electrical path from the bottom to the top of the bridge die 324 . In this case, the bridge die 324 can be fabricated such that the contacts 326 can be electrically connected to the bulk of the bridge die 324 . In this case, the path for providing power to different portions of the dies 312, 314 can be a relatively straight, vertical path 330, where at least some power current flow can be through the embedded bridge die 324. It will be appreciated that such a direct path 330 for providing power to the dies 312, 314 results in relative improvements in the quality of the power supplied as compared to the circuitous path 316 3A can lead. For example, a direct route to power delivery may result in relatively reduced voltage drops due to lower resistances and inductances, relatively lower noise (shot noise, EMI noise, crosstalk noise, etc.), relatively reduced power delivery-induced timing jitter, and/or relatively reduced lead offset over spatially distributed power delivery points. In embodiments where the bridge die 324 is used for ground plane connections, similar types of improvements can be realized from a relatively direct path 330 .

4 FIG. 12 depicts a flow chart depicting an example method for fabricating semiconductor packages with the pass bridge die ver ties off 1-3 according to exemplary embodiments of the disclosure.

At block 402, a power plane interconnect may be formed on a package substrate. It is understood that the package substrate at this time can be in the form of a board and can be processed with a plurality of other semiconductor packages fabricated on the same package substrate board. At a later time, the package substrate can be singulated (eg, by laser ablation, sawing, etc.) to form individual package substrates. The power plane interconnect may be a build-up layer with built-up dielectric and metal lines and/or pads disposed therein. The power plane interconnect may have a power plane contact disposed on its surface. In some example embodiments, the power plane interconnect may be directly over the core of the semiconductor package, and in other cases the power plane interconnect may be over another build-up layer(s) disposed on top of the core. In some alternative exemplary embodiments, it is understood that a core may not be present when the semiconductor package is fabricated. In these coreless designs, there may still be a performance layer that can be formed, for example, by building on top of other build layers (e.g., underlying build layers).

At block 404, one or more interconnect layers may be formed on top of the power plane. Like the power plane interconnect, the one or more interconnect layers may be build-up layers with metal lines and/or pads of a dielectric build-up material. In example embodiments, the build-up layers may not have traces and/or pads overlying the power plane contact in the power plane layer. In other words, there may be a metal feature exclusion zone in the build-up layers where the cavity for the bridge die is to be formed.

At block 406, a cavity may be formed in the one or more interconnect layers and conductive material may be deposited within the cavity and in contact with the power plane contact. The cavity may be formed by any suitable mechanism, including but not limited to patterned wet etch, patterned dry etch, laser ablation, wet cleaning, combinations thereof, or the like. In some cases, the metal contact may be surface treated prior to forming the build-up layers at block 404 such that the dielectric material of the overlying build-up layers releases relatively cleanly from the surface of the power plane contact. After the power plane contact is exposed at the bottom of the cavity, the conductive adhesive can be placed on top.

At block 408, the bridge die may be inserted into the cavity such that the backside of the bridge die contacts the conductive paste. In exemplary embodiments, the bridge die can be aligned over the cavity and inserted into the cavity. In exemplary embodiments, this process may be performed using pick and place tools to align and place the bridge die within the cavity. In example embodiments, the bridge die may have a height such that the top surface (e.g., the top surface of the bridge die and the top surface of the previously fabricated top build-up layer) of the previously formed semiconductor package after insertion into the cavity is relatively planar. The underside of the bridge die can be arranged to make ohmic contact with the power plane contact. The top surface of the bridge die can be positioned relative to the rest of the semiconductor package so that contact can be made to one or more electrical pads on the surface of the bridge die.

At block 410, at least one additional package interconnect layer may be formed on top of the bridge die, wherein the at least one additional package interconnect layer may include interconnects contacting metal lines of the bridge die. The at least one additional package interconnect layer in the form of one or more build-up layers may be configured to make electrical contact with one or more pads on the surface of the bridge die. In exemplary embodiments, the build-up layer formed immediately on top of the bridge die may have electrical contacts with the underlying bridge die and/or other build-up layers surrounding the bridge die.

At block 412, one or more integrated circuit dies may be mounted on top of the at least one additional package interconnect layer. The die can be any suitable electronic device, such as a semiconductor-based one electronic device. In example embodiments, the die may be an integrated circuit (IC) with at least one active device (e.g., transistor, diodes, etc.) and/or passive device (e.g., resistors, inductors, capacitors, etc.). .

It should be noted that the method 400 can be modified in various ways according to certain embodiments of the disclosure. For example, one or more operations of method 400 may be eliminated or performed in a different order in other embodiments of the disclosure. Additionally, other operations may be added to method 400 according to other embodiments of the disclosure.

5A-5F 12 illustrate simplified cross-sectional schematic diagrams of an example bridge die with through-die connections and a manufacturing process thereof, according to example embodiments of the disclosure. Although FIG 5A-5F Illustrating a particular process flow and resulting bridge dies, it is understood that variations in the processes and structures are contemplated and encompassed by the disclosure provided herein. For example, it should be understood that some processes may be performed out of the order presented herein. As another example, it should be understood that some processes may have appropriate substitutes that may be implemented without departing from embodiments of the disclosure. It is further understood that while manufacturing processes described herein may be processes that may typically be performed in a semiconductor manufacturing facility/clean room (Fab), the processes may be performed in any suitable processing facility using any suitable processing tool.

5A 12 illustrates a simplified schematic cross-sectional diagram of a bulk silicon wafer 500 that is doped 502 and on which the bridge die is to be fabricated, according to exemplary embodiments of the disclosure. The wafer 500 may have any suitable size, thickness, crystal type, grade, and flat/groove/laser scribe orientation. In exemplary embodiments, the wafer 500 may be any 300 mm (12 inch), 200 mm (8 inch), 150 mm (6 inch), 100 mm (4 inch), 50 mm (2 inch), and/or sized wafer any other suitable size. In example embodiments, the wafer 500 may have a thickness in an approximate range of about 400 μm to about 1.5 mm. In some example embodiments, the thickness of the wafer 500 may be approximately in the range of about 720 μm to about 775 μm. In some other example embodiments, the thickness of the wafer 500 may be approximately in the range of about 950 μm to about 1.1 mm. In exemplary embodiments, the wafer crystal orientation of wafer 500 may be any of <100>, <110>, <111>, or any other suitable crystal orientation. In some example embodiments, a p-type wafer may be used, and in other example embodiments, an n-type wafer may be used. In some example embodiments, the wafer 500 may be a device quality wafer with or without an ultra-clean epitaxial layer. In other example embodiments, the wafer 500 may be a test grade wafer. In other exemplary embodiments, non-circular silicon substrates may be used. In still other alternative embodiments, non-crystalline silicon wafers, such as polysilicon wafers, may be used. In still other exemplary embodiments, semiconductor wafers other than silicon (e.g., germanium wafers) may be used for subsequent processes.

The wafer 500 can be cleaned before doping. The doping process may include any of an ion implantation process and/or a diffusion process. Dopant material can be introduced by ion implantation. In exemplary embodiments where ion implantation is used for doping, a relatively thin layer of oxide (e.g., SiO ₂ , tetraethyl orthosilicate deposited oxide (TEOS), etc.) may be grown and/or deposited prior to the ion implantation process. In some example embodiments, the thin oxide layer may be sacrificed and stripped prior to subsequent processing. In other exemplary embodiments, the thin oxide layer may remain on the surface and not interfere with subsequent processing of the wafer 500. The ion implantation can be performed with any suitable energy, dose and/or current. After the ion implantation process, a heat/anneal process may be performed to activate and/or drive the dopant 502 (e.g., diffused dopant material). In exemplary embodiments, donor dopants (N _D ) (e.g., phosphorous, arsenic, bismuth, antimony, etc.) may be used to form an n-type wafer 500 . In other exemplary embodiments, acceptor (N _A ) dopants (e.g., boron, etc.) may be used to form a p-type wafer 500 . In other exemplary embodiments, the doping process may be performed by thermal diffusion, using dopants ( _ND or NA) 502 be introduced on the surface and/or in the gas phase on the surface of the wafer 500. The thermal process may drive the dopants 502 into the wafer 500, such as by Fickian diffusion (e.g., according to Fick's second law of diffusion), in example embodiments.

In example embodiments, the wafer 500 may be doped at least relatively proximal to the top surface to about a range of about 10 ¹⁸ cm ^-3 to about 10 ²⁰ cm ^-3 . In example embodiments, the doping density of the donor dopant 502 may be approximately 10 ²⁰ cm ^-3 . In example embodiments, the wafer 500 may be degenerately doped. The resistivity after doping the wafer 500 may range approximately from about 10 ^-5 Ω•cm to about 10 ^-3 Ω•cm in example embodiments.

5B FIG. 5 depicts a simplified schematic cross-sectional diagram of bulk silicon wafer 500. FIG 5A 10 with a contact layer 504 having a dielectric 506 and bulk silicon contacts 508 according to example embodiments of the disclosure. The dielectric 506 may be grown and/or deposited. For example, the dielectric can be grown in a dry (O ₂ ) thermal process or a wet (H ₂ O) thermal process. The thermal process can consume some of the bulk silicon by forming the dielectric (SiO ₂ ) on it. In other example embodiments, the dielectric 506 may be deposited on the surface of the doped wafer 500, such as by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atmospheric pressure CVD (APCVD), etc. , combinations thereof or the like. The above processes can use any variety of chemistries and feed gases such as TEOS, silane/oxygen (SiH ₄ /O ₂ ), trimethylsilane (3MS), dimethylsilane (2MS), diluent gases (Ar, He, Xe, Ne), combinations of it or something like that. As discussed above, prior to the ion implantation process 5A a thin oxide layer may have been deposited on top of the bulk silicon wafer 500 in some cases. In exemplary embodiments, the thin oxide layer deposited for ion implantation purposes may remain on the surface of the bulk silicon wafer 500, on top of which the remainder of the dielectric 506 may be grown and/or deposited.

After forming (e.g., growing or depositing) the dielectric 506, a number of processes may be performed to form contacts 508 to the bulk silicon wafer 500. FIG. These processes may include a patterning process, such as a photolithography process, where a light-sensitive photoresist may be deposited on top of the dielectric 506 and patterned by shining a light of the appropriate frequency through a mask (e.g., a patterned stencil) onto it is directed and the photoresist is developed. Although a photolithographic patterning process is discussed, it should be understood that any suitable patterning process (e.g., e-beam, x-ray, stencil embossing, screen printing, etc.) may be used for the purpose of defining the bulk contact 508 locations. After forming a photoresist mask, the contact holes in the dielectric 506 can be etched. Etching the dielectric may involve any suitable mechanism, including but not limited to wet etching and/or dry etching. In some exemplary embodiments, a plasma etch, such as a Magnetically Enhanced Reactive Ion Etch (MERIE) may be performed to form the vias for the doped bulk wafer 500 . In exemplary embodiments, the photoresist may be stripped/ashed after the via is formed. After the vias are formed, the vias may be filled with metal or any other suitable conductor to form contacts 508. The vias may be filled using any suitable metal deposition process, including but not limited to CVD, physical vapor deposition (PVD), and/or plating. In example embodiments, the vias may be filled with tungsten (W) or another refractory metal using a CVD process. In these or other example embodiments, the tungsten may be deposited over the surface of the dielectric 506 while being deposited in the vias. A chemical mechanical polishing (CMP) process may be performed to remove the tungsten from the surface of the dielectric 506 . In some alternative embodiments, the contacts 508 may be lined with other refractory metals and/or their nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) prior to being filled with tungsten.

5C FIG. 5 depicts a simplified schematic cross-sectional diagram of silicon wafer 500. FIG 5B with one or more layers 510, 520 of metal interconnects that fabricated thereon, according to exemplary embodiments of the disclosure. The metal interconnect layers may be formed by any suitable process, such as patterned metal processes (e.g., aluminum subtraction processes) and/or inlaid processes (e.g., copper damascene, copper dual damascene, etc.). In example embodiments, the trenches 514 may be formed within the dielectric 512 in a single inlaid process on top of the contacts 508, and then the vias 516 and trenches 518 may be formed in a dual inlaid manner, with the metallization of vias 516 and trenches 518 can be performed simultaneously or nearly simultaneously. Similarly, vias 524 and trenches 526 of metal layer 520 may be formed within dielectric 522 in a dual-inlaid manner. Alternatively, the metal interconnect layers 510, 520 can be fabricated in a single-inlaid fashion, either via-first or trench-first. In still other alternative embodiments, the metal interconnect layers 510, 520 may be formed in a subtractive metallization scheme, wherein trenches may be defined by etching blanket deposited metal (e.g., aluminum).

In example embodiments, the processes involved in forming the trenches 518, 526 and the vias 516, 524 in the metal interconnect layers 510, 520 may be any suitable process for depositing dielectric, patterning vias, etching vias, patterning trenches , etching trenches and filling vias and trenches with metal and polishing back excess metal. In some exemplary embodiments, a first photolithography process (e.g., spin-on resist, exposure, development, etc.) may be performed to define the vias 516, 524 of the metal interconnect layers 510, 520 with the photoresist. After the vias 516, 524 are defined, the via holes may be etched, such as by using a MERIE process with any suitable chemistry (e.g., CF ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F chemistries ₆ , C ₄ F ₈ etc.) and the photoresist can be stripped. A second photolithography process may be performed to define the trenches 518,526 in the metal interconnect layers 510,520. The trenches 518, 526 can then be etched to a desired depth within the dielectric 512, 522 and then the photoresist can be stripped. After forming the via and trench well, a metal liner and/or barrier metal layer (e.g., TaN, TiN, etc.) may be deposited in a continuous manner over the walls of the via holes and trench cavities, as well as the surface of the wafer dielectric 512, 522 . The barrier metal layer can be deposited by any suitable mechanism such as CVD. After depositing the barrier metal layer, a seed layer of copper may be deposited on top of the barrier metal layer by any suitable mechanism such as PVD. The seed may be a continuous (e.g., electrically continuous) layer to allow for subsequent electroplating. After depositing the Cu seed layer, Cu electroplating can be performed using any suitable process parameters and chemistries, such as a cupric solution with surfactants and inhibitors to improve bottom-up via filling. The Cu electroplating process can fill the vias and trenches as well as deposit Cu on the surface of the dielectric. After Cu electroplating, a CMP process may be performed to remove the Cu plating, Cu seed, and barrier metal from the dielectric 512, 522 surface.

5D Figure 12 presents a simplified schematic cross-sectional diagram of the silicon wafer 5C with back thinning of the bulk silicon wafer 500 according to example embodiments of the disclosure. The thinning process may include a back grind followed by a back polish of a predetermined depth 528 followed by a cleaning process in example embodiments. In example embodiments, backside thinning may include first mounting the bridge die wafer onto a second substrate, such as a handle wafer or dicing tape. In these embodiments, the front side (e.g., the side on which the interconnect metal layers were fabricated) may be attached (e.g., in a face-down manner) to the second substrate. The grinding and/or polishing process may involve any suitable tribology and/or process parameters including any suitable type and/or size of polishing cloth and/or grit and/or slurry. The wafer 500 can be thinned to an appropriate bulk wafer 530 thickness to fit into a cavity formed in the semiconductor package in which it is to be placed. For example, if a build-up layer of the semiconductor package is 30 µm thick, then the bridge die can be thinned to a thickness of about 30 µm to fit in a cavity having a build-up layer thickness. As another example, if the build-up layer is 30 µm thick and the cavity for inserting the bridge die is three build-up layers thick, the bridge die can be thinned to a thickness of about 90 µm to fit into the cavity. In some exemplary embodiments, the bridge die wafer may be thinned to approximately the range of about 25 μm to about 400 μm; approximately to the range of about 25 µm to about 60 µm in the same or other exemplary embodiments; and in still other exemplary embodiments to about the range of about 150 µm to about 250 µm.

5E FIG. 5 depicts a simplified schematic cross-sectional diagram of the thinned silicon wafer 530. FIG 5D with backside metal 532 according to example embodiments of the disclosure. After thinning, if tape and/or handle substrates were attached for the thinning process, the tape or handle substrates may be removed or they may remain attached for subsequent processing. The wafer 530 may have an ohmic contact formed on the backside with the backside metal 532 . In some example embodiments, another doping process (diffusion, ion implantation, etc.) can optionally be performed on the ground and/or polished back side of the wafer 530 to provide a highly doped surface for relatively good ohmic contact. Next, metal 532 may be deposited on the back side of wafer 530 using any suitable process such as CVD, PVD, or the like. In some cases, tungsten can be deposited on the backside. In other cases, Ni/Au contacts can be formed on the backside of the wafer 530. FIG. In fact, any suitable metallurgy to form backside metal 532 may be used.

5F Figure 12 presents a simplified schematic cross-sectional diagram of the silicon wafer 5E , which is singulated and ready to be embedded in the semiconductor package 1D 1, according to example embodiments of the disclosure. After forming the backside ohmic contact, the wafer may be cleaned and singulated (e.g., diced into individual chips). The cleaning process may include any suitable cleaning process (e.g., sonic cleaning (SC1), SC2, piranha cleaning, etc.). The dicing process may include attaching the wafer to the dicing tape in a face-up configuration (e.g., interconnect metal layers facing up) and performing a sawing process or a laser process to singulate each of the bridge dies that are on the Wafer 530 through the in 5A-5F processes shown were formed.

6 FIG. 6 illustrates a flow chart depicting an example method 600 for fabricating the bridge die with the through die connections 5A-5F according to exemplary embodiments of the disclosure.

At block 602, a top surface of bulk silicon may be doped. As discussed above, the doping may be performed by any suitable mechanism, including but not limited to diffusion, ion implantation, combinations thereof, or the like. At block 604, dielectric and bulk silicon contacts may be formed. The dielectric can be any suitable grown dielectric (e.g., SiO 2 ) and/or deposited dielectric (e.g., TEOS deposited dielectric, 3MS deposited dielectric, 2MS deposited dielectric, low-k dielectric, etc.). Contacts may be formed using any suitable process, such as patterning, etching, photoresist stripping, barrier metal deposition, CMP, etc. At block 606, one or more metal interconnect layers may be formed. The one or more metal interconnect layers may be formed by any suitable process including via first trench last, trench first via last, single inlaid, dual inlaid, Cu interconnects, subtractive metal, Al interconnects, combinations thereof or the like, but not limited thereto. It should be understood that some of the interconnects fabricated on the bridge wafer may be used with through bridge die interconnects for purposes of routing signals between two or more dies that are in a package in the semiconductor package, as disclosed herein .

At block 608, back thinning of the bulk wafer may be performed. The thinning process can use any suitable sequence of grinding, polishing, and/or cleaning. The thinning process can be monitored in situ to achieve a target thickness. In some example embodiments, the target thickness may be an integer multiple of the thickness of the build-up layers formed on the surface of the semiconductor package, as described herein. At block 610, backside metal may be deposited on the wafer. In some cases, a backside doping may be performed before depositing the backside metal. For example, the backside can be degenerately doped to form a good ohmic contact to the backside metal. The back metal can be deposited by any suitable mechanism such as CVD, PVD and/or plating. At block 612, cleaning and singulation may be performed. Separation can be done using dicing tape are carried out. After dicing, the bridge die can be held on dicing tape such that the bridge die can be picked up using pick and place tools for placement in the cavity formed in the semiconductor packages , as described herein.

It should be noted that the method 600 can be modified in various ways according to certain embodiments of the disclosure. For example, one or more operations of method 600 may be eliminated or performed in a different order in other embodiments of the disclosure. Additionally, other operations may be added to method 600 according to other embodiments of the disclosure.

It is understood that the device described herein may be any suitable type of microelectronics packaging and configurations thereof including, for example, system-in-package (SiP), system-on-package (SoP), package-on-package (PoP), interposer package, 3D stacked package, etc. In fact, any suitable type of microelectronic components can be provided in the semiconductor packages with through bridge die interconnects as described herein. For example, microcontrollers, microprocessors, baseband processors, digital signal processors, memory dies, field gate arrays, logic gate dies, passive component dies, MEMSs, surface mount devices, application specific integrated circuits, baseband processors, amplifiers, filters, combinations thereof, or the like in the semiconductor packages with through bridge die connections in a package as disclosed herein. The semiconductor packages with through-bridge die interconnects as disclosed herein may be provided in any variety of electronic devices including consumer, industrial, military, communications, infrastructure, and/or other electronic devices.

The semiconductor package with bridge die connections as described herein can be used to house one or more processors. The one or more processors may include, without limitation, a central processing unit (CPU), a digital signal processor (DSP), a reduced instruction set computer (RISC), a complex instruction set (CISC) computer instruction set computer), a microprocessor, a microcontroller, a field programmable gate array (FPGA), or any combination thereof. The processors may also include one or more Application Specific Integrated Circuits (ASICs) or Application Specific Standard Products (ASSPs) for handling specific data processing functions or tasks. In certain embodiments, the processors may be based on an Intel® architecture system, and the one or more processors and each chipset included in an electronic device may be from a family of Intel® processors and chipsets, such as the Intel® Atom ® processor family or Intel 64 processors (e.g. Sandy Bridge®, Ivy Bridge®, Haswell®, Broadwell®, Skylake®, etc.).

Additionally or alternatively, the semiconductor package with via bridge die connections as described herein may be used to house one or more memory chips. The memory may include one or more volatile and/or non-volatile memory devices, including magnetic memory devices, read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), static RAM ( SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM (DDR-SDRAM), RAM-BUS DRAM (RDRAM), flash memory devices, Electrically Erasable Programmable Read Only Memory (EEPROM). -Only Memory), Non-Volatile RAM (NVRAM), USB (Universal Serial Bus) removable memory, or combinations thereof, but not limited to.

In example embodiments, the electronic device in which the semiconductor package is provided with through bridge die connections may be a computing device. Such a computing device may house one or more circuit boards on which the semiconductor package may be placed with bridge die connections. The circuit board may include a number of components including, but not limited to, a processor and/or at least one communications chip. The processor may be physically and electrically connected to the board, such as by electrically connecting the semiconductor package to an EMI shield. The computing device may further include a plurality of communication chips. For example, a first communication chip may be dedicated to shorter-range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO and others, be dedicated. In various exemplary embodiments, the computing device may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer , a scanner, a monitor, a set-top box, an entertainment controller, a digital camera, a portable music player, a digital video recorder, combinations thereof, or the like. In other exemplary embodiments, the computing device may be any other electronic device that processes data.

Various features, aspects and embodiments have been described herein. The features, aspects, and embodiments are capable of combination with one another, as well as variations and modifications, as will be understood by those skilled in the art. The present disclosure should therefore be considered to encompass such combinations, variations and modifications.

The terms and expressions used herein are for the purpose of description rather than limitation, and there is no intention in the use of such terms and expressions to exclude any equivalents of the features (or portions thereof) shown and described. Accordingly, the claims are intended to cover all such equivalents.

While the disclosure includes various embodiments, including at least a best mode, it is understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. are to be interpreted in an illustrative and non-limiting sense.

This written description uses examples to disclose specific embodiments of the disclosure, including the best mode, and also to enable any person skilled in the art to practice specific embodiments of the disclosure, including making and using any device, device, or system and performing any integrated procedures and processes.

According to example embodiments of the disclosure, there may be a semiconductor package comprising: a first build-up layer having a top surface and a bottom surface opposite the top surface, the first build-up layer having a power contact on the top surface of the first build-up layer; a second build-up layer overlying the first build-up layer and having a cavity overlying the power contact; a bridge die disposed within the cavity of the second build-up layer, the bridge die having a bridge die back and a bridge die top, the bridge die top having a plurality of bridge die top contacts wherein the bridge die back is electrically coupled to the power contact; and a third build-up layer overlying the top of the bridge die and disposed over the second build-up layer, the third build-up layer having an interconnection trace, the interconnection trace electrically connected to a first bridge-die top-side contact of the plurality of bridge-die top-side contacts is coupled. In example embodiments, a conductive adhesive may be placed between the power contact and the bridge die backside. In further exemplary embodiments, the bridge die backside comprises a bridge die backside metal layer and wherein the conductive adhesive contacts the bridge die backside metal. In still further example embodiments, the semiconductor package further includes a die disposed on the third build-up layer and electrically connected to the interconnection trace.

According to example embodiments, the die is a first die, and further comprising a second die disposed on the third build-up layer, wherein the first die is electrically coupled to the second die via the interconnection trace. In further exemplary embodiments, the interconnection trace is a first interconnection trace, the die being electrically connected to the first interconnection trace via a first die-to-package connection, and the die being further electrically connected to a second via a second die-to-package connection interconnection trace of the third build-up layer, and wherein the second die-to-package connection has a larger size than the first die-to-package connection. In still other exemplary embodiments, the first bridge die top contact is electrically coupled to the bridge die backside through a bridge die via a bridge die bulk. In still further exemplary embodiments, the cavity is a first cavity, and further comprising a fourth build-up layer disposed above the second build-up layer and below the third build-up layer, the fourth build-up layer having a second cavity overlying the power contact, and wherein the first cavity and the second cavity define a cavity in which the bridge die is arranged. In some example embodiments, the bridge die includes a bulk portion that is electrically coupled to a backside metal provided on the bridge die backside, and at least one of the plurality of bridge die top side contacts is electrically connected to the bulk portion is coupled to provide power through the bulk portion of the bridge die to the at least one of the plurality of bridge die top contacts and to one or more dies electrically connected to the at least one of the plurality of bridge die top contacts , to direct. In example embodiments, the semiconductor package may further include a fourth build-up layer. Furthermore, the semiconductor package may have a package core, the package core having an upper package core surface and a lower package core surface; a fourth build-up layer formed on the lower package core surface; and one or more package-to-board contacts electrically coupled to the fourth build-up layer.

According to example embodiments, there may be a method comprising: forming a first build-up layer, the first build-up layer having a power contact; forming one or more second build layers overlying the first build layer; removing portions of the one or more second build-up layers to form a cavity in the one or more second build-up layers; providing a bridge die within the cavity, a backside of the bridge die being electrically connected to the power contact; forming one or more third build-up layers overlying the bridge die and the one or more second build-up layers; and attaching a first die and a second die to interconnects provided on the one or more third build-up layers. In example embodiments, the method may include cutting through the first build-up layer, the one or more second build-up layers, and the one or more third build-up layers to singulate a semiconductor package with the bridge die. In further example embodiments, forming the first build-up layer includes forming the first build-up layer on a top surface of a package core. In still other example embodiments, the method includes forming one or more fourth build-up layers on the bottom side of the package core; and forming one or more package-to-board connections on the one or more fourth layers of construction. In still other example embodiments, removing the portions of the one or more second build-up layers further comprises laser ablating the portions of the one or more second build-up layers to expose the power contact underlying the one or more second build-up layers.

According to some exemplary embodiments of the disclosure, the method includes depositing a conductive adhesive within the cavity. In exemplary embodiments, providing the bridge die within the cavity further includes aligning the bridge die over the cavity and then placing the bridge die within the cavity, wherein a volume of the cavity is greater than a volume of the bridge die. In other exemplary embodiments, providing the bridge die within the cavity further includes: doping a wafer; forming one or more bulk contacts on a top surface of the wafer; forming one or more metal interconnect layers over the one or more bulk contacts; thinning the wafer on a bottom side of the wafer; depositing backside metal on the underside of the wafer; and dicing the wafer to form the bridge die. In still other example embodiments, thinning the wafer includes thinning the wafer to a thickness substantially equal to the thickness of the one or more second build-up layers. In still further example embodiments, attaching a first die includes: connecting a first contact of the first die to a first pad on the one or more third build-up layers; and connecting a second contact of the first die to a second pad on the one or more third build-up layers, wherein the first pad has a smaller area than the second pad, and wherein the first pad overlies the bridge die and the second pad does not over the bridge die lies.

Claims (10)

A semiconductor package (200, 320) comprising: a first build-up layer (102, 204) having a top surface and a bottom surface opposite the top surface, the first build-up layer (102, 204) having a power contact (108; 206; 304) on the top surface of the first build-up layer (102, 204); a second build-up layer (110, 210) overlying the first build-up layer (102, 204), the second build-up layer (110, 210) defining a cavity overlying the power contact (108; 206); a bridge die (118, 212, 324) disposed within the cavity of the second build-up layer (110, 210), the bridge die (118, 212, 324) having a bridge die backside and a bridge die -upper side, with the bridge- the top side has a plurality of bridge die top side contacts, the bridge die back side being electrically coupled to the power contact (108, 206); and a third build-up layer (130, 220) overlying the top of the bridge die (118, 212, 324) and disposed over the second build-up layer (110, 210), the third build-up layer (112, 220) comprising an interconnection trace (132; 224), wherein the interconnection trace is electrically coupled to a first bridge die top contact (230) of the plurality of bridge die top contacts, the bridge die including a bulk portion (120; 214) that is electrically coupled to a backside metal provided on the bridge die backside, and wherein at least one of the plurality of bridge die top side contacts is electrically coupled to the bulk portion to transmit power through the bulk portion of the bridge die to the at least one of the plurality of bridge die top contacts and to one or more dies electrically connected to the at least one of the plurality of bridge die top contacts. semiconductor package claim 1 , further comprising a conductive adhesive (116; 208; 322) disposed between the power contact and the bridge die backside. semiconductor package claim 2 wherein the bridge die backside comprises a bridge die backside metal, and wherein the conductive adhesive contacts the bridge die backside metal. A semiconductor package according to any one of the preceding claims, further comprising a die (134; 226; 312) disposed on the third build-up layer and electrically connected to the interconnection trace (132; 224). semiconductor package claim 4 , wherein the die is a first die (134; 226; 312), and further comprising a second die (136; 228; 314) disposed on the third build-up layer, the first die being connected via the interconnection trace (132; 224) electrically coupled to the second die. semiconductor package claim 4 wherein the interconnection trace (132; 224) is a first interconnection trace, the die (134; 226; 312) being electrically connected to the first interconnection trace via a first die-to-package connection (230), the die further via a second die-to-package connection (138; 232) electrically connected to a second interconnection trace (104; 222) of the third build-up layer, and wherein the second die-to-package connection is larger in size than the first die-to -Package connection. The semiconductor package of any preceding claim, wherein the first bridge die top contact is electrically coupled to the bridge die backside through a bridge die bulk of the bridge die (118, 212, 324). A semiconductor package according to any one of the preceding claims, wherein the cavity is a first cavity, and further comprising a fourth build-up layer (112; 210) disposed above the second build-up layer (110; 210) and below the third build-up layer (130; 220). wherein the fourth build-up layer has a second cavity (122; 216) overlying the power contact, and wherein the first cavity and the second cavity define a cavity (114) in which the bridge die is disposed. A semiconductor package according to any one of the preceding claims, further comprising a fourth build-up layer (112; 210). A semiconductor package according to any one of the preceding claims, further comprising: a package core (100; 202), the package core having an upper package core surface and a lower package core surface, wherein the first build-up layer (102; 204) is formed on the upper package core surface; a fifth build-up layer (246) formed on the bottom package core surface, and one or more package-to-board contacts (250; 252) electrically coupled to the fifth build-up layer.

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