KR101903773B1 - Gate Driving Circuit and Display Device using the same - Google Patents

Abstract

Embodiments of the present invention may include: shift register blocks; And a signal separator located between the gate voltage output terminals of the shift register blocks and the start voltage input terminals and controlling a dependent connection relationship between the shift register blocks.

Description

[0001] The present invention relates to a gate driving circuit and a display device using the same,

An embodiment of the present invention relates to a gate driving circuit and a display using the same.

Some of the display devices can display an image corresponding to the gate voltage and the data signal supplied to the subpixels arranged in a matrix form.

The gate driver for supplying the gate voltage to the subpixels is formed on the substrate in the form of IC (Integrated Circuit) or formed in the form of a gate in panel (GIP) on the substrate in the process of forming the thin film transistor included in the subpixels do.

Some of the display devices ages a thin film transistor (hereinafter referred to as a TFT) by utilizing a gate drive circuit constituting a GIP type gate driver. When aging the TFT, the TFT formed in the sub-pixel must be placed under a specific condition (VGS> 0, VDS <0). At this time, the TFT must be supplied with a sufficient aging voltage condition (VGS >> 0, VDS << 0) so that the subpixel reaches the off current level for obtaining a normal image. Therefore, a high driving voltage is required when supplying the aging voltage condition using the GIP type gate driver.

However, in the conventional GIP type gate driver, when a high driving voltage is applied, the bias voltage between the Q-QB nodes outputting the gate voltage may rise further, and insulation breakdown may occur at a thinner portion of the gate insulating film. In addition, in the conventional GIP type gate driver, it is not possible to uniformly perform TFT aging over all subpixels, and TFT aging for a specific subpixel is not easy within a limited time (one horizontal period).

In order to solve the problems of the background art described above, an embodiment of the present invention is to provide a method of driving a plasma display panel in which, when a voltage required for aging of a transistor included in a subpixel is supplied, And a display device using the same.

According to an embodiment of the present invention, there is provided a semiconductor memory device including shift register blocks; And a signal separator located between the gate voltage output terminals of the shift register blocks and the start voltage input terminals and controlling a dependent connection relationship between the shift register blocks.

The signal separator maintains a dependent connection relationship between the shift register blocks when the shift register blocks sequentially output the first gate voltage and when the shift register blocks output the second gate voltage all at the same time, The connection relationship can be separated.

The signal separator may include N (N is an integer equal to or greater than 1) switching transistors connected to the first signal line with all of the gate electrodes.

The signal separator includes two switching transistors, and the shift register blocks may be turned on when supplying the first gate voltage and may be turned off when supplying the second gate voltage.

The shift register blocks may each include a Q-node control unit that includes M (M is an integer equal to or greater than 1) switching transistors located between the Q-node and the QB node and the gate electrodes are all connected to one second signal line .

The Q-node control unit includes two switching transistors, and when the shift register blocks supply the first gate voltage, the Q-node control unit is turned off, and when the second gate voltage is supplied, the Q-node control unit can be turned on.

In another aspect, an embodiment of the present invention provides a display device including: a display panel including subpixels; A data driver for supplying a data signal to the display panel; And a gate driver for supplying a gate voltage to the display panel, wherein the gate driver is located between the gate voltage output terminals of the shift register blocks and the start voltage input terminals, and the signal for controlling a dependent connection relationship between the shift register blocks And a gate driver circuit including a separator.

When the shift register blocks successively output the first gate voltage for driving the transistors included in the subpixels, the signal separator maintains a dependent connection relationship between the shift register blocks, and the shift register blocks maintain the sub- When the second gate voltages for aging the transistors are all output in the same manner, the dependent connection relationship between the shift register blocks can be separated.

The signal separator may include N (N is an integer equal to or greater than 1) switching transistors connected to the first signal line with all of the gate electrodes.

The signal separator includes two switching transistors, and the shift register blocks may be turned on when supplying the first gate voltage and may be turned off when supplying the second gate voltage.

The shift register blocks may each include a Q-node control unit that includes M (M is an integer equal to or greater than 1) switching transistors located between the Q-node and the QB node and the gate electrodes are all connected to one second signal line .

The Q-node control unit includes two switching transistors, and when the shift register blocks supply the first gate voltage, the Q-node control unit is turned off, and when the second gate voltage is supplied, the Q-node control unit can be turned on.

An embodiment of the present invention is a gate driver circuit which can prevent a circuit failure problem due to insulation breakdown of an insulating film constituting transistors of a gate driver by a high voltage difference when a voltage required for aging of a transistor included in a sub- And a display device using the same. In addition, since the embodiments of the present invention do not sequentially drive during the aging operation, it is possible to equalize aging to the transistors included in all subpixels. In addition, since the time for charging a specific node to a desired voltage (one horizontal time) is not required, the degree of freedom in timing adjustment can be increased and an off margin can be secured in driving at a high temperature. The embodiment of the present invention also provides a gate driving circuit in which subpixels can reach an off current level for obtaining a normal image because the transistors included in the subpixel are aged with sufficient aging voltage conditions, .

1 is a schematic block diagram of a display device according to an embodiment of the present invention;
FIG. 2 is a circuit example of a subpixel included in the display panel of FIG. 1; FIG.
FIG. 3 is a diagram illustrating a driving waveform of a subpixel shown in FIG. 2. FIG.
FIG. 4 is a view for explaining an aging condition of a transistor included in the sub-pixel shown in FIG. 2. FIG.
5 is a schematic block diagram of a gate driver according to an embodiment of the present invention;
6 is a detailed circuit configuration example of the signal separation unit shown in FIG.
FIG. 7 is a diagram for explaining a drive mode for each power supply signal supplied to the signal separation unit shown in FIG. 6; FIG.
8 and 9 are output waveform diagrams of gate voltages of the power supply signals supplied to the signal separation unit.
10 is an exemplary circuit configuration of the Nth shift register block shown in FIG. 5;
11 is a view for explaining an operation in which the Nth shift register block shown in FIG. 10 outputs the second gate voltage.
12 is a waveform diagram of each section of the Nth shift register block shown in FIG.
13 is a waveform diagram for explaining a maximum bias voltage generated at each node when outputting a second gate voltage;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a display device according to an embodiment of the present invention.

As shown in FIG. 1, a display device according to an exemplary embodiment of the present invention includes a timing driver TCN, a gate driver SDRV, a data driver DDRV, and a display panel PNL.

The timing driver TCN receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK and a data signal RGB from the outside. The timing driver TCN supplies data signals to the data driver DDRV and the data driver DDRV using timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. And controls the operation timing of the driving unit SDRV. The timing driver TCN can count the data enable signal DE in one horizontal period to determine the frame period so that the externally supplied vertical sync signal Vsync and horizontal sync signal Hsync can be omitted. The control signals generated by the timing driver TCN include a gate timing control signal GDC for controlling the operation timing of the gate driver SDRV and a data timing control signal DDC for controlling the operation timing of the data driver DDRV. ) And the like.

The gate driver SDRV is formed on the periphery of the substrate in the form of a GIP (Gate In Panel) together with a process of forming a thin film transistor (hereinafter abbreviated as a transistor) included in the subpixels SP. The gate driver SDRV is a gate driver for driving the transistors of the subpixels SP included in the display panel PNL in response to a gate timing control signal GDC supplied from the timing driver TCN, The gate voltage is sequentially generated while shifting the level of the signal. The gate driver SDRV supplies a gate voltage generated through the scan lines SL1 to SLm to subpixels SP included in the display panel PNL.

The data driver DDRV is formed on a display panel (PNL) or a circuit board in the form of an integrated circuit (IC). The data driver DDRV samples and latches the digital data signal RGB supplied from the timing driver TCN in response to the data timing control signal DDC supplied from the timing driver TCN, . The data driver DDRV converts a digital data signal RGB into a gamma reference voltage and converts the digital data signal into an analog data signal. The data driver DDRV supplies the data signals converted through the data lines DL1 to DLn to the sub-pixels SP included in the display panel PNL.

The display panel PNL includes sub-pixels SP arranged in a matrix form. The subpixels SP may be formed by a top emission method, a bottom emission method, or a dual emission method depending on the structure. The subpixels SP may be configured to include a switching transistor, a sensing transistor, a driving transistor, a capacitor, and an organic light emitting diode, or may have a structure in which a compensation transistor and a compensation capacitor are further added.

The display device according to the embodiment of the present invention is applicable to all structures in which the sensing transistor ST2 for sensing the threshold voltage of the driving transistor TD is used for the subpixel constituting the display panel. Also, the display device according to an embodiment of the present invention is applicable to a transistor and a gate driver formed on a polysilicon (P-Si) basis.

Hereinafter, the circuit configuration, the driving waveform, and the aging conditions of the sub-pixel in which the sensing transistor ST2 for sensing the threshold voltage of the driving transistor TD are used will be described.

FIG. 2 is a diagram illustrating a circuit configuration of a subpixel included in the display panel of FIG. 1, FIG. 3 is an exemplary driving waveform of the subpixel shown in FIG. 2, Fig. 8 is a view for explaining the aging condition of a transistor.

As shown in FIGS. 2 and 3, the subpixels include first through fifth transistors ST1 through ST5, a driving transistor TD, a capacitor Cst, and an organic light emitting diode OLED.

The first transistor ST1 is a switching transistor that is turned on by the gate voltage SL1a supplied through the first A gate line SL1A to transfer a data signal supplied through the first data line DL1.

The second transistor ST2 is a sensing transistor that is turned on by the gate voltage SL1a supplied through the first A gate line SL1A to sense the threshold voltage of the driving transistor TD.

The third transistor ST3 is a switching transistor that is turned on by the gate voltage SL1b supplied through the first B gate line SL1B and serves to transfer a reference voltage supplied through the reference line Vref.

The fourth transistor ST4 is a switching transistor that is turned on by the gate voltage SL1b supplied through the first B gate line SL1B to transfer the driving current to the organic light emitting diode OLED.

The fifth transistor ST5 is a switching transistor that is turned on by the gate voltage SL1c supplied through the first C gate line SL1C and serves to initialize the organic light emitting diode OLED.

The driving transistor TD is a driving transistor which serves to generate a driving current corresponding to the data voltage stored in the capacitor Cst.

The capacitor Cst serves to store the data signal supplied through the first data line DL1 as a data voltage based on the threshold voltage and the first power supply voltage VDD and the organic light emitting diode OLED, And emits light based on the driving current generated by the driving transistor TD.

The above-described subpixel operates as follows by the driving waveform shown in FIG. In the (a) period, initialization of the transistors included in the subpixel proceeds. In the period (b), programming is performed so that the data voltage is stored in the capacitor in addition to the threshold voltage sensing for the driving transistor included in the subpixel. In the period (c), the voltage programmed in the capacitor is maintained and stabilized. In the period (d), the organic light emitting diode is driven to emit light based on the driving current generated by the driving transistor.

The transistors T1 to T5 and TD included in the above-described sub-pixel are all formed on the basis of polysilicon (P-Si). The transistor of the display panel formed on the basis of polysilicon is required to have an aging step for lowering the off current level through aging due to the characteristics of the transistor. At this time, the aging step may be performed during the period (c) and (d).

In the aging step, as shown in FIG. 4, it is necessary to set the transistor to a specific condition (VGS> 0, VDS <0) so that the off current level can be reduced. At this time, the transistor must be supplied with a sufficient aging voltage condition (VGS >> 0, VDS << 0) so that the subpixel reaches the off current level for obtaining a normal image. Accordingly, a high driving voltage is required when supplying the aging voltage condition using the polysilicon-based GIP type gate driver.

On the other hand, the aging voltage used in the aging step must make the transistor included in the sub-pixel a high voltage difference between a gate high voltage of a high potential and a gate low voltage (VGH-VGL) of a low potential, Is required. Therefore, when the above-described aging voltage condition is supplied using the GIP type gate driver, dielectric breakdown may occur at a specific node of the gate drive circuit due to a high voltage difference.

To solve this problem, the gate driver of the GIP type should be designed as follows.

FIG. 5 is a schematic block diagram of a gate driver according to an embodiment of the present invention, FIG. 6 is a detailed circuit configuration diagram of the signal separator shown in FIG. 5, and FIG. FIGS. 8 and 9 are output waveform diagrams of gate voltages of the power supply signals supplied to the signal separation unit. FIG.

5, the gate driver according to an embodiment of the present invention includes shift register blocks STG [N-3] to STG [N] and shift register blocks STG [N-3] N-3] to STG [N], which are located between the gate voltage output terminals OUT [N-3] to OUT [N] and the start voltage input terminals of the shift register blocks [ (ISOP [N-3] to ISOP [N-1]) for controlling the dependent connection relationship between the signal separation units ISOP [N-3] to ISOP [N-1].

The shift register blocks STG [N-3] to STG [N] are connected to the first power supply line GVDD, the second power supply line GVSS, the first to fourth clock lines CLK1 to CLK4, (VST), the first signal line (ISO) and the second signal line (QH). Here, since the second clock line CLK2 is irrelevant to the description, it is omitted.

When the shift register blocks STG [N-3] to STG [N] successively output the first gate voltage, the signal separation units ISOP [N-3] to ISOP [N- (STG [N-3] to STG [N]). Alternatively, the signal separation units ISOP [N-3] to ISOP [N-1] may be configured so that the shift register blocks STG [N-3] to STG [N] And separates the dependent connection relationship between the shift register blocks STG [N-3] to STG [N].

N (N is an integer equal to or greater than 1) switching transistors connected to one first signal line (ISO) and all gate electrodes are included in the signal separation units ISOP [N-3] to ISOP [N-1]. For example, the signal separation units ISOP [N-3] to ISOP [N-1] include two switching transistors M1 and M2 as shown in FIG.

The two switching transistors M1 and M2 are turned on when the shift register blocks STG [N-3] to STG [N] supply the first gate voltage and are turned off when the second gate voltage is supplied. .

One of the first signal lines ISO connected to the two switching transistors M1 and M2 is selectively supplied with a logic low signal and a logic high signal as shown in FIG. When a logic low signal is supplied to one first signal line ISO, the two switching transistors M1 and M2 included in all the signal separators ISOP [N-3] to ISOP [N-1] When the logic high signal is supplied, the two switching transistors M1 and M2 included in all the signal separators ISOP [N-3] to ISOP [N-1] are turned off.

When the two switching transistors M1 and M2 are turned on, the gate driver is driven in a normal mode. When the gate driver is driven in the normal mode, each of the shift register blocks STG [N-3] to STG [N] sequentially outputs the first gate voltage for driving the transistor. As a result, the output terminals OUT [N-3] to OUT [N] of the shift register blocks STG [N-3] to STG [N] (VGL) are sequentially output with a predetermined time difference. Here, in the case of the gate low voltage (VGL), it may have a negative potential which is equal to or lower than the ground voltage according to the transistor included in the subpixel.

On the other hand, when the two switching transistors M1 and M2 are turned off, the gate driver is driven in the aging mode. When the gate driver is driven in an aging mode, each of the shift register blocks STG [N-3] to STG [N] outputs the same second gate voltage for aging the transistor. As a result, the output terminals OUT [N-3] to OUT [N] of the shift register blocks STG [N-3] to STG [N] (VGH) may all be output at the same time or may be output at different times in the same order as in Fig.

The gate driver according to an embodiment of the present invention may shift the shift register blocks STG [N-1] in a normal mode (Aging Mode) by using signal separators ISOP [N-3] N-3] to STG [N]). In addition, the gate driver according to an embodiment of the present invention uses a power supply and a signal supplied to the shift register blocks STG [N-3] to STG [N] to generate a gate high voltage and a gate low voltage VGH- VGL) are formed with a high voltage difference, which will be described below.

10 is a circuit diagram of the Nth shift register block shown in FIG.

As shown in FIG. 10, the Nth shift register block STG [N] includes first through twelfth transistors T1 through T12, a capacitor C and a Q node controller QHC. The configuration of the elements included in the Nth shift register block STG [N] is described as the first circuit portion BL [1], the second circuit portion BL [2], and the third Circuit section BL [3], and the configuration and connection relationship therebetween will be described as follows.

The first circuit portion BL [1] uses the voltages and signals supplied through the first power supply line GVDD, the start voltage line VST, the third clock line CLK3 and the fourth clock line CLK4 And controls the Q node and the QB node.

More specifically, the first circuit portion BL [1] responds to the voltage and signal supplied through the start voltage line VST, the third clock line CLK3 and the fourth clock line CLK4, And forms a QB node to a voltage supplied through the second power line GVSS and the first power line GVDD. Here, the start voltage line VST of the first circuit portion BL [1] is connected to the gate of the N-1th shift register block STG [N] through the gate voltage OUT [N-1] The first gate voltage is supplied as the start voltage.

The first circuit portion BL [1] includes a first transistor T1, a second transistor T2, a seventh transistor T7, and an eighth transistor T8. The connection relation of the transistors included in the first circuit part BL [1] will be described below.

The first transistor T1 has a gate electrode and a first electrode connected to a start voltage line VST and a second electrode connected to a first electrode of the second transistor T2. The second transistor T2 has a gate electrode connected to the fourth clock line CLK4, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the Q node.

The seventh transistor T7 has a gate electrode connected to the third clock line CLK3 and a first electrode connected to the first power supply line GVDD and a second electrode connected to the first electrode of the eighth transistor T8. do. The eighth transistor T8 has a gate electrode connected to the third clock line CLK3, a first electrode connected to the second electrode of the seventh transistor T7, and a second electrode connected to the QB node.

The second circuit BL [2] serves to control the Q node and the QB node using the voltages and signals supplied through one second signal line QH and the second power line GVSS.

In more detail, the second circuit portion BL [2] responds to the voltage and signal supplied via the start voltage line VST, the QB node voltage and the one second signal line QH, To the voltage supplied through the second power supply line GVSS and the first power supply line GVDD.

The third transistor T3, the fourth transistor T4 and the fifth transistor T6 are connected to the second circuit part BL [2], and the thirteenth transistor T13 and the fourteenth transistor T13 constituting the Q node control part QHC, The transistor T14 is included. The connection relationship of the transistors included in the second circuit portion BL [2] will be described below.

The third transistor T3 has a gate electrode connected to the QB node, a first electrode connected to the second electrode of the fourth transistor T4, and a second electrode connected to the second power line GVSS. The fourth transistor T4 has a gate electrode connected to the QB node, a second electrode connected to the first electrode of the third transistor T3, and a first electrode coupled to the second electrode of the fourteenth transistor T14.

The fifth transistor T5 has a gate electrode connected to the start voltage line VST, a first electrode connected to the second electrode of the sixth transistor T6, and a second electrode connected to the second power line GVSS . The sixth transistor T6 has a gate electrode connected to the start voltage line VST, a second electrode connected to the first electrode of the fifth transistor T5, and a first electrode connected to the QB node.

The thirteenth transistor T13 has a gate electrode connected to one second signal line QH, a first electrode connected to the Q node, and a second electrode connected to the first electrode of the fourteenth transistor T14. The fourteenth transistor T14 has a gate electrode connected to one second signal line QH and a first electrode connected to the second electrode of the thirteenth transistor T13 and connected to the first electrode of the fourth transistor T4 And the second electrode is connected.

The third circuit BL [3] uses the voltage and signal supplied through the first clock line CLK1, the Q-node voltage, the QB node voltage and the second power supply line GVSS to output the output OUT [N] And controls the voltage output through the output terminal.

More specifically, the third circuit BL [3] serves to form a voltage output through the output terminal OUT [N] in response to the first clock line CLK1, the Q node voltage, and the QB node voltage do.

The ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 are included in the second circuit portion BL [3]. The connection relation between the transistors included in the third circuit part BL [3] and the capacitor will be described below.

The ninth transistor T9 has a gate electrode connected to the Q node, a first electrode connected to the second electrode of the tenth transistor T10, and a second electrode connected to the second power supply line GVSS. The tenth transistor T10 has a gate electrode connected to the Q node, a first electrode connected to the first electrode of the ninth transistor T9, and a first electrode connected to the QB node.

The eleventh transistor T11 has a gate electrode connected to the Q node, a first electrode connected to the first clock line CLK1, and a second electrode connected to the output terminal OUT [N]. One end of the capacitor C is connected to the Q node and the other end is connected to the output terminal OUT [N]. The second transistor T12 has a gate electrode connected to the QB node, a first electrode connected to the output terminal OUT [N], and a second electrode connected to the second power supply line GVSS.

The configuration and connection relationship of the first to third circuit portions BL [1] to BL [3] included in the Nth shift register block STG [N] have been mainly described. However, not only the Nth shift register block (STG [N]) but also other shift register blocks have the same configuration and connection relationship as shown in FIG. Then, they form a dependent connection relation as shown in FIG. In addition, the first and second electrodes of the transistors may be defined as source and drain electrodes, or drain and source electrodes, For convenience, the top is defined as the first electrode and the bottom is defined as the second electrode.

As can be seen from the above description, in the shift register blocks according to an embodiment of the present invention, M (M (N)) transistors, which are located between a Q node and a QB node and each have a gate electrode connected to one second signal line And a Q-node control unit (QHC) including switching transistors of at least one integer. Here, the Q-node control unit QHC includes two switching transistors T13 and T14.

On the other hand, the Q-node control unit QHC controls the Q-node voltage to reduce the voltage bias Bias between the Q-node and the QB node to prevent the insulation breakdown of the insulating film constituting the fourth and fifth transistors T4 and T5 . The Q-node controller QHC included in all the shift register blocks is controlled by one second signal line QH. As a signal supplied to one second signal line (QH), an AC voltage supplied in accordance with the aging section of the transistor can be selected.

The Q-node controller QHC is turned off when the shift register blocks supply the first gate voltage corresponding to the gate voltage, and turns on when supplying the second gate voltage corresponding to the aging voltage. That is, the Q-node controller QHC also selectively drives the gate driver according to the driving mode (Normal Mode, Aging Mode) of the signal separator ISOP [N-3] to ISOP [N-1].

The gate driver according to an embodiment of the present invention generates a first gate voltage for driving a transistor included in a subpixel and a second gate voltage for aging a transistor. The following will be described.

FIG. 11 is a view for explaining an operation of outputting the second gate voltage by the Nth shift register block shown in FIG. 10, and FIG. 12 is a waveform diagram for each section of the Nth shift register block shown in FIG.

First, a signal corresponding to the gate high voltage VGH is supplied to the first signal line ISO as shown in FIG. Then, all the signal separators ISOP [N-3] to ISOP [N-1] are turned off and the dependent connection relationship between all the shift register blocks included in the gate driver is separated. Thus, the start voltage between the output terminals of each stage and the start voltage line (VST) is separated.

Next, the gate line voltage VGL (DC) is supplied to the first power supply line GVDD along with all of the clock lines CLK1 to CLK4 as in the first period. At this time, the start voltage VST corresponding to the gate high voltage VGH (DC) is supplied to the first shift register block included in the gate driver for driving the circuit. Accordingly, the QB node is formed with the gate-low voltage VGL supplied through the first power supply line GVDD.

And the gate line voltage VGL is supplied to the second signal line QH. Then, all the Q-node control units QHC are turned on and the Q-node is formed with the gate high voltage VGH supplied through the second power supply line GVSS. When the waveform of the second gate voltage corresponding to the aging voltage is controlled through the QB node and the second power supply line (GVSS) by operating the Q-node controller QHC as described above, the unnecessary voltage is prevented from flowing into the output do.

At this time, the first power supply line GVDD continuously supplies the gate low voltage VGL to the QB node, and each shift register block outputs the gate high voltage VGH supplied through the second power supply line GVSS do.

Next, the voltage supplied through the second power supply line GVSS is switched from the gate high voltage VGH to the gate low voltage VGL as in the second period. Accordingly, the QB node is formed at a voltage lower than the gate low voltage (VGL) by the parasitic capacitance of the transistor, and each shift register block outputs the gate low voltage (VGL) supplied through the second power supply line (GVSS) .

The first power supply line GVDD continuously supplies the gate low voltage VGL to the QB node and each shift register block supplies the gate high voltage VBL supplied through the second power supply line GVSS VGH).

The voltage supplied through the second power supply line (GVSS) is supplied in the form of alternating current (AC), which is a gate high voltage (VGH) and a gate low voltage (VGL), and is supplied On the other hand, the first power supply line GVDD is continuously supplied with the gate-low voltage VGL.

On the other hand, in the period (2), the Q node and the QB node generate a voltage fluctuation (kickback) together with a voltage change of the second power supply line (GVSS) due to the capacitance between the node and the second power supply line (GVSS) node. However, as can be seen from the voltages of the first net (Net 1) and the fourth net (Net 4), the maximum bias voltage (Max Bias Voltage) generated between them corresponds to the bias voltage level at the time of normal operation. A more detailed description will be given in more detail with reference to FIG. 13 and Table 1. FIG.

13 is a waveform diagram for explaining the maximum bias voltage generated at each node when outputting the second gate voltage. Table 1 below shows the Q-node, QB node, first, third and fourth Is the maximum bias voltage of the net (Net 1, Net 3, Net 4).

division Q node
~
QH Q node
~
Net 4 Net 4
~
QH Net 1
~
Net 4 Net 1
~
QH Net 1
~
QB node Net 1
~
Net 3 Net 3
~
QB node
normal
Driving Max
Bias
(V)
31
18
31
31
31
31
0
31
31

13 and Table 1, when a gate driver according to an embodiment of the present invention performs an operation for aging a transistor, the Q node and the QB node are connected to the capacitance with the second power supply line (GVSS) node A voltage variation (kickback) occurs with the voltage change of the second power supply line GVSS.

However, the maximum bias voltage generated between the QB nodes - Net 1, Net 1 - QH, QH - Net 2, and QH - Q nodes corresponds to the bias voltage level during normal operation. Therefore, when the second gate voltage required for aging the transistor included in the subpixel is supplied, the gate driver according to the embodiment of the present invention can prevent the breakdown of the insulating film constituting the transistors of the gate driver by the high voltage difference, Bad problems are prevented.

In addition, since the gate driver according to the embodiment of the present invention does not sequentially drive during the aging operation, the transistors included in all the subpixels can be equally aged. In addition, since the time for charging a specific node to a desired voltage (one horizontal time) is not affected, the degree of freedom of timing adjustment can be increased, and it is possible to secure an off margin when driving at a high temperature. In addition, since the transistors included in the subpixel are aged to a sufficient aging voltage condition (VGS &quot; 0, VDS &quot; 0), the subpixel can reach an off current level for obtaining a normal image. Further, even when the transistor included in the subpixel is aged, the voltage bias VGS, VDS can be formed equal to the voltage bias level for driving the normal transistor.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

TCN: timing driver SDRV: gate driver
DDRV: Data driver PNL: Display panel
ISOP [N-3] to ISOP [N-1]: signal separator M1, M2: two switching transistors
QHC: Q node control unit T13: thirteenth transistor
T14: Fourteenth transistor
STG [N-3] to STG [N]: Shift register blocks

Claims (13)

Shift register blocks; And
And a signal separator located between the gate voltage output terminals of the shift register blocks and the start voltage input terminals and controlling a dependent connection relationship between the shift register blocks,
The signal separation unit
Wherein when the shift register blocks sequentially output a gate low voltage, a dependent connection relationship between the shift register blocks is maintained,
And separates the dependent connection relationship between the shift register blocks when the shift register blocks simultaneously output the gate high voltage. delete The method according to claim 1,
The signal separation unit
And N (N is an integer equal to or greater than one) switching transistors whose gate electrodes are all connected to one first signal line. The method of claim 3,
The signal separation unit
Wherein the gate driving circuit includes two switching transistors and turns on when the shift register blocks supply the gate low voltage and turns off when supplying the gate high voltage. The method according to claim 1,
The shift register blocks
And a Q-node controller including M (M is an integer equal to or greater than 1) switching transistors located between the Q-node and the QB node and having gate electrodes all connected to one second signal line. 6. The method of claim 5,
The Q node control unit
Wherein the gate driving circuit includes two switching transistors and turns off when the shift register blocks supply the gate low voltage and turns on when supplying the gate high voltage. A display panel including subpixels;
A data driver for supplying a data signal to the display panel; And
And a gate driver for supplying a gate voltage to the display panel,
Wherein the gate driver includes a signal separator which is located between the gate voltage output terminals of the shift register blocks and the start voltage input terminals and controls the dependent connection relationship between the shift register blocks,
The signal separation unit
Wherein when the shift register blocks sequentially output the first gate voltage for driving the transistors included in the subpixels, a dependent connection relationship between the shift register blocks is maintained,
And separates the dependent connection relationship between the shift register blocks when the shift register blocks simultaneously output all the second gate voltages for aging the transistors included in the subpixels. delete 8. The method of claim 7,
The signal separation unit
And N (N is an integer equal to or larger than 1) switching transistors whose gate electrodes are all connected to one first signal line. 10. The method of claim 9,
The signal separation unit
Wherein the switching transistor includes two switching transistors and turns on when the shift register blocks supply the first gate voltage and turns off when supplying the second gate voltage. 8. The method of claim 7,
The shift register blocks
And a Q-node controller including M (M is an integer equal to or greater than 1) switching transistors located between the Q-node and the QB node and having gate electrodes all connected to one second signal line. 12. The method of claim 11,
The Q node control unit
Wherein the display device includes two switching transistors, and the shift register blocks are turned off when supplying the first gate voltage, and turned on when supplying the second gate voltage. 8. The method of claim 7,
The first gate voltage is a gate low voltage,
And the second gate voltage is a gate high voltage.

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