KR20130052896A - Gate driving circuit and display device using the same - Google Patents

Abstract

PURPOSE: A gate driving circuit and a display device using the same are provided to uniformly age a transistor included in all sub pixels by preventing a successive driving operation in an aging process. CONSTITUTION: A gate driving circuit includes shift register blocks and signal separating units. The signal separating units are located between start voltage input terminals and gate voltage output terminals of the shift register blocks. The signal separating unit maintains a subordinated connection between the shift register blocks when the shift register blocks successively output a first gate voltage, and separates the subordinated connection between the shift register blocks when the shift register blocks equally output a second gate voltage.

Description

Gate driving circuit and display device using the same

Embodiments of the present invention relate to a gate driving circuit and a display device using the same.

Some of the display devices may display an image in response to the gate voltage and the data signal supplied to the subpixels arranged in the matrix form.

The gate driver for supplying the gate voltage to the subpixels is formed on the substrate in the form of an integrated circuit (IC) or formed on the outside of the substrate in the form of a gate in panel (GIP) together with a process of forming a thin film transistor included in the subpixels. do.

Some of the display devices use thin film transistors (hereinafter referred to as TFTs) by utilizing a gate driver circuit that constitutes a GIP gate driver. When aging a TFT, it is necessary to allow the TFT formed in the subpixel to be placed under specific conditions (VGS> 0, VDS <0). At this time, the TFT needs to be supplied with sufficient aging voltage conditions (VGS >> 0, VDS < < 0) to reach the off current level for the subpixel to obtain a normal image. Therefore, when supplying the above aging voltage conditions using the GIP type gate driver, a high driving voltage is required.

However, when a high driving voltage is applied to the conventional GIP type gate driver, insulation breakdown may occur in a thin portion of the gate insulating layer due to an additional increase in the bias voltage between the Q-QB nodes that output the gate voltage. In addition, the conventional GIP gate driver is not only capable of aging TFT evenly over all sub pixels, but also needs to be improved because TFT aging for a specific sub pixel is not easy within a limited time (one horizontal period).

The embodiment of the present invention for solving the above-described problems of the background art is caused by the dielectric breakdown of the insulating film constituting the transistors of the gate driver due to a high voltage difference when a voltage required for aging of the transistor included in the subpixel is supplied. To provide a gate driving circuit and a display device using the same that can prevent a circuit failure problem.

Embodiment of the present invention by the above-described problem solving means, the shift register blocks; And a signal separation unit disposed between the gate voltage output terminals of the shift register blocks and the start voltage input terminals to control a dependent connection relationship between the shift register blocks.

The signal separator maintains the dependent connection relationship between the shift register blocks when the shift register blocks sequentially output the first gate voltage, and depends on the shift register blocks when the shift register blocks output all of the second gate voltages identically. The connection relationship can be separated.

The signal separator may include N switching transistors in which all of the gate electrodes are connected to one first signal line.

The signal separator may include two switching transistors and may be turned on when the shift register blocks supply the first gate voltage, and may be turned off when the second gate voltage is supplied.

The shift register blocks may include a Q node control unit including M switching transistors (M is an integer of 1 or more), each of which is positioned between the Q node and the QB node, and all of the gate electrodes are connected to one second signal line. .

The Q node controller may include two switching transistors and may be turned off when the shift register blocks supply the first gate voltage, and may be turned on when the second gate voltage is supplied.

In another aspect, an embodiment of the present invention, a display panel including sub-pixels; A data driver supplying a data signal to the display panel; And a gate driver configured to supply a gate voltage to the display panel, wherein the gate driver is positioned between the gate voltage output terminals of the shift register blocks and the start voltage input terminals and controls a dependent connection relationship between the shift register blocks. A display device including a gate driving circuit including a separator is provided.

When the shift register blocks sequentially output a first gate voltage for driving a transistor included in the subpixels, the signal separator maintains a dependent connection relationship between the shift register blocks, and the shift register blocks are included in the subpixels. When the second gate voltages for aging the transistors are all output identically, the dependent connection relationship between the shift register blocks may be separated.

The signal separator may include N switching transistors in which all of the gate electrodes are connected to one first signal line.

The signal separator may include two switching transistors and may be turned on when the shift register blocks supply the first gate voltage, and may be turned off when the second gate voltage is supplied.

The shift register blocks may include a Q node control unit including M switching transistors (M is an integer of 1 or more), each of which is positioned between the Q node and the QB node, and all of the gate electrodes are connected to one second signal line. .

The Q node controller may include two switching transistors and may be turned off when the shift register blocks supply the first gate voltage, and may be turned on when the second gate voltage is supplied.

According to an embodiment of the present invention, when a voltage required for aging of a transistor included in a subpixel is supplied, a gate driving circuit capable of preventing a circuit failure problem due to dielectric breakdown of an insulating film constituting the transistors of the gate driver due to a high voltage difference. It is effective to provide a furnace and a display device using the same. In addition, since the embodiment of the present invention does not sequentially drive during the aging operation, it is possible to equalize the transistors included in all sub-pixels. In addition, since timing is not limited to a time (1 horizontal time) for charging a specific node to a desired voltage, timing adjustment can increase the degree of freedom and additionally secure off margin during high temperature driving. In addition, according to an embodiment of the present invention, since the transistor included in the subpixel is aged under a sufficient aging voltage condition, the gate driving circuit and the display apparatus using the same may reach the off current level for obtaining a normal image. Has the effect of providing.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.
2 is a diagram illustrating a circuit configuration of a subpixel included in the display panel of FIG. 1.
3 is an exemplary driving waveform diagram of a sub-pixel illustrated in FIG. 2;
4 is a diagram for describing an aging condition of a transistor included in a subpixel illustrated in FIG. 2.
5 is a schematic block diagram of a gate driver according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating a detailed circuit configuration of the signal separator of FIG. 5. FIG.
FIG. 7 is a view for explaining a driving mode for each power signal supplied to the signal separation unit illustrated in FIG. 6.
8 and 9 are output waveform diagrams of the gate voltage for each power signal supplied to the signal separation unit.
FIG. 10 is an exemplary circuit diagram of an Nth shift register block shown in FIG. 5; FIG.
FIG. 11 is a view for explaining an operation of outputting a second gate voltage by the Nth shift register block shown in FIG. 10; FIG.
12 is a waveform diagram for each section of the Nth shift register block illustrated in FIG. 11.
FIG. 13 is a waveform diagram illustrating a maximum bias voltage generated at each node when a second gate voltage is output. FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a display device according to an exemplary embodiment includes a timing driver TCN, a gate driver SDRV, a data driver DDRV, and a display panel PNL.

The timing driver TCN receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable, DE, a clock signal CLK, and a data signal RGB from the outside. The timing driver TCN uses the timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal Data Enable, and the clock signal CLK, and the gate of the data driver DDRN and the gate. The operation timing of the driver SDRV is controlled. Since the timing driver TCN may determine the frame period by counting the data enable signal DE of one horizontal period, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync supplied from the outside may be omitted. The control signals generated by the timing driver TCN include a gate timing control signal GDC for controlling the operation timing of the gate driver SDRV and a data timing control signal DDC for controlling the operation timing of the data driver DDR. ), And the like.

The gate driver SDRV is formed on the outside of the substrate in the form of a gate in panel (GIP) together with a process of forming a thin film transistor (hereinafter, abbreviated as a transistor) included in the subpixels SP. The gate driver SDRV is a swing width of the gate driving voltage at which the transistors of the subpixels SP included in the display panel PNL can operate in response to the gate timing control signal GDC supplied from the timing driver TCN. The gate voltage is sequentially generated while shifting the signal level. The gate driver SDRV supplies gate voltages generated through the scan lines SL1 to SLm to the subpixels SP included in the display panel PNL.

The data driver DDRV is formed in the display panel PNL or the circuit board in the form of an integrated circuit IC. The data driver DDRV samples and latches the digital data signal RGB supplied from the timing driver TCN in response to the data timing control signal DDC supplied from the timing driver TCN. Convert to The data driver DVV converts the digital data signal RGB into a gamma reference voltage and converts the data into an analog data signal. The data driver DDRV supplies the data signal converted through the data lines DL1 to DLn to the subpixels SP included in the display panel PNL.

The display panel PNL includes subpixels SP arranged in a matrix. The subpixels SP may be formed in a top-emission method, a bottom-emission method, or a dual-emission method according to a structure. The subpixels SP may be configured to include a switching transistor, a sensing transistor, a driving transistor, a capacitor, and an organic light emitting diode, or may have a structure in which a compensation transistor and a compensation capacitor are further added.

The display device according to an exemplary embodiment of the present invention can be applied to any structure in which the sub-pixel constituting the display panel uses the sensing transistor ST2 for sensing the threshold voltage of the driving transistor TD. In addition, the display device according to the exemplary embodiment may be applied to a transistor and a gate driver formed on the basis of polysilicon (P-Si).

Hereinafter, a circuit configuration, a driving waveform, and an aging condition of a subpixel in which the sensing transistor ST2 for sensing the threshold voltage of the driving transistor TD is used will be described.

2 is a diagram illustrating a circuit configuration of a subpixel included in the display panel of FIG. 1, FIG. 3 is a diagram illustrating driving waveforms of a subpixel illustrated in FIG. 2, and FIG. 4 is included in a subpixel illustrated in FIG. 2. It is a figure for demonstrating the aging condition of a transistor.

As illustrated in FIGS. 2 and 3, the subpixel includes first to fifth transistors ST1 to ST5, a driving transistor TD, a capacitor Cst, and an organic light emitting diode OLED.

The first transistor ST1 is a switching transistor that is turned on by the gate voltage SL1a supplied through the first A gate line SL1A and transfers a data signal supplied through the first data line DL1.

The second transistor ST2 is a sensing transistor that is turned on by the gate voltage SL1a supplied through the first A gate line SL1A and senses a threshold voltage of the driving transistor TD.

The third transistor ST3 is a switching transistor that is turned on by the gate voltage SL1b supplied through the first B gate line SL1B and transfers the reference voltage supplied through the reference line Vref.

The fourth transistor ST4 is a switching transistor that is turned on by the gate voltage SL1b supplied through the first B gate line SL1B and transfers a driving current to the organic light emitting diode OLED.

The fifth transistor ST5 is a switching transistor that is turned on by the gate voltage SL1c supplied through the first C gate line SL1C to initialize the organic light emitting diode OLED.

The driving transistor TD is a driving transistor that generates a driving current in response to the data voltage stored in the capacitor Cst.

The capacitor Cst stores the data signal supplied through the first data line DL1 as a data voltage based on the threshold voltage and the first power supply voltage VDD, and the organic light emitting diode OLED is a driving transistor. It emits light based on the driving current generated by (TD).

The aforementioned subpixel is operated as follows by the driving waveform as shown in FIG. 3. In section (a), initialization of the transistors included in the subpixel is performed. In the section (b), programming is performed in which a data voltage is stored in a capacitor along with sensing a threshold voltage of a driving transistor included in a subpixel. In the section (c), maintenance and stabilization of the voltage programmed in the capacitor are performed. In the period (d), the organic light emitting diode emits light based on a driving current generated by the driving transistor.

The transistors T1 to T5 and TD included in the above-described subpixel are all formed on the basis of polysilicon (P-Si). An transistor of a display panel formed based on polysilicon needs an aging step of lowering an off current level through aging due to the characteristics of the transistor. At this time, the aging step may be performed in the interval (c) and (d).

In the aging step, as shown in FIG. 4, the transistor must be placed under specific conditions (VGS> 0 and VDS <0) to reduce the off current level. At this time, the transistor must be supplied with sufficient aging voltage conditions (VGS >> 0, VDS < < 0) to reach the off current level for the subpixel to obtain a normal image. Accordingly, a high driving voltage is required to supply the aging voltage condition using the polysilicon-based GIP type gate driver.

On the other hand, the aging voltage used in the aging step should make the transistor included in the sub-pixel a high voltage difference between the gate high voltage of the high potential and the gate low voltage of the low potential (VGH-VGL), for example, a high driving voltage. Required. Therefore, when the aging voltage condition is supplied using the GIP type gate driver, insulation breakdown may occur at a specific node of the gate driver circuit due to a high voltage difference.

To solve this problem, the GIP gate driver should be designed as follows.

FIG. 5 is a schematic block diagram of a gate driver according to an exemplary embodiment of the present invention, FIG. 6 is an exemplary circuit configuration of the signal separator of FIG. 5, and FIG. 7 is a signal separator of FIG. 6. 8 is a view illustrating a driving mode for each power signal supplied, and FIGS. 8 and 9 are output waveform diagrams of gate voltages for power signals supplied to a signal separator.

As shown in FIG. 5, the shift driver blocks STG [N-3] to STG [N] and the shift register blocks STG [N-3] to STG include a gate driver in accordance with an embodiment of the present invention. Shift register blocks STG [N-3] to STG [N] located between the gate voltage output terminals OUT [N-3] to OUT [N] of the [N]) and the start voltage input terminals. Signal separation units ISOP [N-3] to ISOP [N-1] for controlling the dependent connection relationship therebetween are included.

The shift register blocks STG [N-3] to STG [N] include the first power line GVDD, the second power line GVSS, the first to fourth clock lines CLK1 to CLK4, and the start voltage line. (VST), the first signal line (ISO) and the second signal line (QH). Here, the second clock line CLK2 is omitted because it is irrelevant to the description.

The signal separators ISOP [N-3] to ISOP [N-1] may shift the shift register block when the shift register blocks STG [N-3] to STG [N] sequentially output the first gate voltage. Maintains a subordinate connection between them (STG [N-3] to STG [N]). In contrast, the signal separators ISOP [N-3] to ISOP [N-1] may output the second gate voltages identically to the shift register blocks STG [N-3] to STG [N]. In this case, the dependent connection relationship between the shift register blocks STG [N-3] to STG [N] is separated.

The signal separators ISOP [N-3] to ISOP [N-1] include N switching transistors (N is an integer of 1 or more) in which all of the gate electrodes are connected to one first signal line ISO. For example, the signal separators ISOP [N-3] to ISOP [N-1] include two switching transistors M1 and M2 as shown in FIG. 6.

The two switching transistors M1 and M2 are turned on when the shift register blocks STG [N-3] to STG [N] supply the first gate voltage, and are turned off when the second gate voltage is supplied. Becomes

As shown in FIG. 7, a logic low signal and a logic high signal are selectively supplied to one first signal line ISO connected to two switching transistors M1 and M2. When the logic low signal is supplied to one first signal line ISO, the two switching transistors M1 and M2 included in all signal separation units ISOP [N-3] to ISOP [N-1] are turned on. When the logic high signal is supplied, the two switching transistors M1 and M2 included in all the signal separation units ISOP [N-3] to ISOP [N-1] are turned off.

When the two switching transistors M1 and M2 are turned on, the gate driving unit is driven in a normal mode. When the gate driver is driven in the normal mode, the shift register blocks STG [N-3] to STG [N] sequentially output the first gate voltage for driving the transistor. Accordingly, the gate low voltage corresponding to the first gate voltage is applied to the output terminals OUT [N-3] to OUT [N] of the shift register blocks STG [N-3] to STG [N] as shown in FIG. 8. (VGL) is sequentially output with a certain time difference. In the case of the gate low voltage VGL, the gate low voltage VGL may have a negative potential that is less than or equal to the ground voltage depending on the transistor included in the subpixel.

On the contrary, when the two switching transistors M1 and M2 are turned off, the gate driver drives the aging mode. When the gate driver is driven in an aging mode, each of the shift register blocks STG [N-3] to STG [N] outputs the same second gate voltage for aging the transistor. Accordingly, the gate high voltage corresponding to the second gate voltage at the output terminals OUT [N-3] to OUT [N] of the shift register blocks STG [N-3] to STG [N] as shown in FIG. 9. The VGHs may all be output at the same time or may be output at different times in the same order as in FIG. 8.

The gate driver according to the exemplary embodiment of the present invention uses the signal separators ISOP [N-3] to ISOP [N-1] to shift the shift register blocks STG [by the driving mode (Normal Mode, Aging Mode). N-3] to STG [N]) maintain or separate the dependency. In addition, the gate driver according to an embodiment of the present invention uses the power and the signals supplied to the shift register blocks STG [N-3] to STG [N], and the gate high voltage and the gate low voltage VGH−. VGL) is formed with a high voltage difference, which will be described below.

FIG. 10 is an exemplary circuit diagram of an Nth shift register block illustrated in FIG. 5.

As illustrated in FIG. 10, the Nth shift register block STG [N] includes first to twelfth transistors T1 to T12, a capacitor C, and a Q node controller QHC. According to an embodiment of the present invention, the configuration of the elements included in the Nth shift register block STG [N] is illustrated in the first circuit portion BL [1], the second circuit portion BL [2], and the third for convenience of description. The circuit section BL [3] will be divided, and their configuration and connection relationship will be described as follows.

The first circuit unit BL [1] uses a voltage and a signal supplied through the first power line GVDD, the start voltage line VST, the third clock line CLK3, and the fourth clock line CLK4. It controls Q node and QB node.

In more detail, the first circuit portion BL [1] may be connected to the Q node in response to the voltage and the signal supplied through the start voltage line VST, the third clock line CLK3, and the fourth clock line CLK4. The QB node forms a voltage supplied through the second power line GVSS and the first power line GVDD. Here, the start voltage line VST of the first circuit portion BL [1] is output through the gate voltage OUT [N-1] of the N-1 shift register block STG [N] positioned at the front end. The first gate voltage is supplied as the start voltage.

The first circuit portion BL [1] includes a first transistor T1, a second transistor T2, a seventh transistor T7, and an eighth transistor T8. A connection relationship between transistors included in the first circuit unit BL [1] will be described below.

In the first transistor T1, the gate electrode and the first electrode are connected to the start voltage line VST, and the second electrode is connected to the first electrode of the second transistor T2. In the second transistor T2, the gate electrode is connected to the fourth clock line CLK4, the first electrode is connected to the second electrode of the first transistor T1, and the second electrode is connected to the Q node.

In the seventh transistor T7, a gate electrode is connected to the third clock line CLK3, a first electrode is connected to the first power line GVDD, and a second electrode is connected to the first electrode of the eighth transistor T8. do. In the eighth transistor T8, a gate electrode is connected to the third clock line CLK3, a first electrode is connected to the second electrode of the seventh transistor T7, and a second electrode is connected to the QB node.

The second circuit unit BL [2] controls the Q node and the QB node by using a voltage and a signal supplied through one second signal line QH and second power line GVSS.

In more detail, the second circuit unit BL [2] may include the Q node and the QB node in response to the voltage and the signal supplied through the start voltage line VST, the QB node voltage, and one second signal line QH. To form a voltage supplied through the second power line GVSS and the first power line GVDD.

The second circuit part BL [2] has a third transistor T3, a fourth transistor T4, and a fifth transistor T6 together with a thirteenth transistor T13 and a fourteenth element constituting the Q node control unit QHC. Transistor T14 is included. The connection relationship between the transistors included in the second circuit unit BL [2] is as follows.

In the third transistor T3, a gate electrode is connected to the QB node, a first electrode is connected to the second electrode of the fourth transistor T4, and a second electrode is connected to the second power line GVSS. In the fourth transistor T4, a gate electrode is connected to the QB node, a second electrode is connected to the first electrode of the third transistor T3, and a first electrode is connected to the second electrode of the 14th transistor T14.

In the fifth transistor T5, a gate electrode is connected to the start voltage line VST, a first electrode is connected to the second electrode of the sixth transistor T6, and a second electrode is connected to the second power line GVSS. . In the sixth transistor T6, a gate electrode is connected to the start voltage line VST, a second electrode is connected to the first electrode of the fifth transistor T5, and a first electrode is connected to the QB node.

In the thirteenth transistor T13, a gate electrode is connected to one second signal line QH, a first electrode is connected to the Q node, and a second electrode is connected to the first electrode of the fourteenth transistor T14. The fourteenth transistor T14 has a gate electrode connected to one second signal line QH, a first electrode connected to a second electrode of the thirteenth transistor T13, and a first electrode of the fourth transistor T4. The second electrode is connected.

The third circuit unit BL [3] uses the first clock line CLK1, the Q node voltage, the QB node voltage, and the voltage and the signal supplied through the second power line GVSS to output the output terminal OUT [N]. It controls the output voltage.

In more detail, the third circuit BL [3] forms a voltage output through the output terminal OUT [N] in response to the first clock line CLK1, the Q node voltage, and the QB node voltage. do.

The second circuit portion BL [3] includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The connection relationship between the transistors and the capacitors included in the third circuit unit BL [3] is as follows.

In the ninth transistor T9, a gate electrode is connected to the Q node, a first electrode is connected to the second electrode of the tenth transistor T10, and a second electrode is connected to the second power line GVSS. In the tenth transistor T10, a gate electrode is connected to the Q node, a second electrode is connected to the first electrode of the ninth transistor T9, and a first electrode is connected to the QB node.

In the eleventh transistor T11, a gate electrode is connected to the Q node, a first electrode is connected to the first clock line CLK1, and a second electrode is connected to the output terminal OUT [N]. One end of the capacitor C is connected to the Q node and the other end thereof is connected to the output terminal OUT [N]. In the second transistor T12, a gate electrode is connected to the QB node, a first electrode is connected to the output terminal OUT [N], and a second electrode is connected to the second power line GVSS.

In the above description, the configuration and connection relationship of the first to third circuit units BL [1] to BL [3] included in the Nth shift register block STG [N] are described. However, not only the Nth shift register block STG [N] but also the configuration and connection relationship of other shift register blocks may be formed as shown in FIG. 10. And they form a dependent connection relationship in the form as shown in FIG. In addition, the first and second electrodes of the transistors may be defined as a source electrode and a drain electrode or a drain electrode and a source electrode. For convenience, the upper end is defined as a first electrode and the lower end is defined as a second electrode.

As can be seen from the above description, the shift register blocks according to an embodiment of the present invention are located between the Q node and the QB node and have M gate electrodes connected to all one second signal line QH. Is a Q-node control unit QHC each including a switching transistor of an integer of 1 or more. Here, the Q node control unit QHC includes two switching transistors T13 and T14.

On the other hand, the Q node control unit QHC controls the Q node voltage to reduce the voltage bias between the Q node and the QB node, thereby preventing dielectric breakdown of the insulating films forming the fourth and fifth transistors T4 and T5. Prevents. The Q node control unit QHC included in all shift register blocks is controlled by one second signal line QH. As the signal supplied to one second signal line QH, an AC voltage supplied according to the aging period of the transistor may be selected.

The Q node control unit QHC is turned off when the shift register blocks supply the first gate voltage corresponding to the gate voltage, and is turned on when the second gate voltage corresponding to the aging voltage is supplied. That is, the Q node control unit QHC also selectively drives the driving mode (Normal Mode, Aging Mode) of the gate driving unit like the signal separation units ISOP [N-3] to ISOP [N-1].

The gate driver according to the exemplary embodiment of the present invention described above generates a second gate voltage for aging the transistor together with a first gate voltage for driving the transistor included in the sub-pixel. The description is as follows.

FIG. 11 is a diagram for describing an operation of outputting a second gate voltage by the Nth shift register block illustrated in FIG. 10, and FIG. 12 is a waveform diagram for each section of the Nth shift register block illustrated in FIG. 11.

First, a signal corresponding to the gate high voltage VGH is supplied to the first signal line ISO as shown in FIG. 7. Then, all signal separation units ISOP [N-3] to ISOP [N-1] are turned off and the dependent connection relationships between all shift register blocks included in the gate driver are separated. Accordingly, the start voltages between the output terminals of each stage and the start voltage line VST are separated.

Next, the gate low voltage VGL (DC) is supplied to the first power line GVDD together with all the clock lines CLK1 to CLK4 as in section ①. At this time, the first shift register block included in the gate driver is supplied with a start voltage VST corresponding to the gate high voltage VGH to drive the circuit. Accordingly, the QB node is formed of the gate low voltage VGL supplied through the first power line GVDD.

The gate low voltage VGL is supplied to the second signal line QH. Then, all the Q node controllers QHC are turned on and are formed with the gate high voltage VGH supplied to the Q node through the second power line GVSS. As the Q node controller QHC operates as described above, when the waveform of the second gate voltage corresponding to the aging voltage is controlled through the QB node and the second power line GVSS, unnecessary flow of voltage to the output is blocked. do.

At this time, the first power line GVDD continuously supplies the gate low voltage VGL to the QB node, and each shift register block outputs the gate high voltage VGH supplied through the second power line GVSS. do.

Next, as in section ②, the voltage supplied through the second power line GVSS is switched from the gate high voltage VGH to the gate low voltage VGL. Accordingly, the QB node is formed at a voltage lower than the gate low voltage VGL by the parasitic capacitance of the transistor, and each shift register block outputs the gate low voltage VGL supplied through the second power line GVSS. .

Next, as in section ③, the first power line GVDD continuously supplies the gate low voltage VGL to the QB node, and each shift register block is provided with the gate high voltage (VVSS) supplied through the second power line GVSS. VGH) will be displayed.

As can be seen in section ② of the above process, the voltage supplied through the second power line (GVSS) is supplied by switching in the form of alternating current (AC), the gate high voltage (VGH) and the gate low voltage (VGL). On the other hand, the first power line GVDD is continuously supplied with the gate low voltage VGL.

On the other hand, in the section ②, the Q node and the QB node generate a voltage change (kickback) together with the voltage change of the second power line GVSS due to the capacitance with the second power line GVSS node. However, as can be seen from the voltage of the first net (Net 1) and the fourth net (Net 4), the maximum bias voltage generated between them corresponds to the bias voltage level during normal driving. The detailed description will be described in more detail with reference to FIG. 13 and Table 1. FIG.

FIG. 13 is a waveform diagram illustrating a maximum bias voltage generated at each node when the second gate voltage is output. Table 1 below shows the Q node, QB node, first, third and fourth nodes shown in FIG. 11. The maximum bias voltage for the nets (Net 1, Net 3, Net 4).

division Q node
~
QH Q node
~
Net 4 Net 4
~
QH Net 1
~
Net 4 Net 1
~
QH Net 1
~
QB node Net 1
~
Net 3 Net 3
~
QB node
normal
Driving Max
Bias
(V)
31
18
31
31
31
31
0
31
31

As shown in FIG. 13 and Table 1, when the gate driver according to an embodiment of the present invention performs an operation for aging the transistor, the Q node and the QB node are connected to the capacitance with the second power line (GVSS) node. As a result, a voltage change (kickback) occurs together with the voltage change of the second power line GVSS.

However, the maximum bias voltage generated between the QB nodes-Net 1, Net 1-QH, QH-Net 2, and QH-Q nodes corresponds to the bias voltage level in normal driving. Therefore, the gate driver according to an embodiment of the present invention is a circuit due to the dielectric breakdown of the insulating film constituting the transistors of the gate driver by a high voltage difference when the second gate voltage required for aging of the transistor included in the sub-pixel is supplied. Defective problems are avoided.

In addition, the gate driver according to the exemplary embodiment of the present invention does not perform sequential driving during the aging operation, so that aging can be equally applied to the transistors included in all the sub-pixels. In addition, the timing adjustment can increase the degree of freedom since it is not limited to a time (1 horizontal time) for charging a specific node to a desired voltage, and additional off margin can be secured when driving at a high temperature. In addition, since the transistors included in the subpixel are aged under sufficient aging voltage conditions (VGS >> 0, VDS << 0), the subpixel may reach an off current level for obtaining a normal image. In addition, even when the transistor included in the subpixel is aged, the voltage biases VGS and VDS can be formed to be equal to the voltage bias level for driving the conventional transistor.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

TCN: timing driver SDRV: gate driver
DDRV: Data driver PNL: Display panel
ISOP [N-3] to ISOP [N-1]: Signal Separators M1, M2: Two Switching Transistors
QHC: Q node control unit T13: 13th transistor
T14: 14th transistor
STG [N-3]-STG [N]: Shift Register Blocks

Claims (12)

Shift register blocks; And
And a signal separator disposed between the gate voltage output terminals and the start voltage input terminals of the shift register blocks and controlling a dependent connection relationship between the shift register blocks. The method of claim 1,
The signal separation unit
When the shift register blocks sequentially output the first gate voltage, the dependent connection relationship between the shift register blocks is maintained.
And when the shift register blocks output the same second gate voltage, the dependent connection relationship between the shift register blocks. The method of claim 2,
The signal separation unit
A gate driving circuit comprising N switching transistors (N is an integer of 1 or more) in which all of the gate electrodes are connected to one first signal line. The method of claim 3,
The signal separation unit
And two switching transistors, wherein the shift register blocks are turned on when the first gate voltage is supplied, and are turned off when the second gate voltage is supplied. The method of claim 2,
The shift register blocks
A gate driving circuit, each of which includes a Q node control unit positioned between a Q node and a QB node, and including M switching transistors (M is an integer of 1 or more) in which all of the gate electrodes are connected to one second signal line. The method of claim 5,
The Q node control unit
And two switching transistors, wherein the shift register blocks are turned off when the first gate voltage is supplied, and are turned on when the second gate voltage is supplied. A display panel including subpixels;
A data driver supplying a data signal to the display panel; And
A gate driver configured to supply a gate voltage to the display panel,
And a gate driver circuit disposed between the gate voltage output terminals of the shift register blocks and the start voltage input terminals and including a signal separator for controlling a dependent connection relationship between the shift register blocks. The method of claim 7, wherein
The signal separation unit
When the shift register blocks sequentially output the first gate voltage for driving the transistors included in the subpixels, the dependent connection relationship between the shift register blocks is maintained.
And when the shift register blocks output the same second gate voltage for aging the transistors included in the subpixels, the dependent connection relationship between the shift register blocks is separated. 9. The method of claim 8,
The signal separation unit
A display device including N switching transistors in which all of the gate electrodes are connected to one first signal line (N is an integer of 1 or more). 10. The method of claim 9,
The signal separation unit
And two switching transistors, wherein the shift register blocks are turned on when the first gate voltage is supplied, and are turned off when the second gate voltage is supplied. The method of claim 7, wherein
The shift register blocks
And a Q node controller, each of which includes M switching transistors (M is an integer of 1 or more), which are positioned between the Q node and the QB node, and all of the gate electrodes are connected to one second signal line. The method of claim 11,
The Q node control unit
And two switching transistors, wherein the shift register blocks are turned off when the first gate voltage is supplied, and are turned on when the second gate voltage is supplied.

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