KR101870187B1

KR101870187B1 - In Plane Switching Type Liquid Crystal Display Having Ultra High Transmittance Rate

Info

Publication number: KR101870187B1
Application number: KR1020150151421A
Authority: KR
Inventors: 문선지; 조재형; 고성곤; 조정옥
Original assignee: 엘지디스플레이 주식회사
Priority date: 2015-10-29
Filing date: 2015-10-29
Publication date: 2018-06-25
Also published as: KR20170051627A

Abstract

Field of the Invention [0002] The present invention relates to a horizontal electric field type liquid crystal display device having an ultra high transmittance. The pixel electrodes and the common electrodes of the horizontal electric field type liquid crystal display device are arranged alternately with line shapes within the pixel region. The block regions include an electrode region and a spacing region. The electrode region corresponds to any one of the pixel electrode and the common electrode which are arranged continuously in the pixel region. The interval region corresponds to between two neighboring electrodes. The interval area width of the outermost block area in the pixel area is larger than 1.0 times and not larger than 1.6 times the interval area width of the inner block area.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a horizontal electric field liquid crystal display device having an ultra high transmittance,

Field of the Invention [0002] The present invention relates to a horizontal electric field type liquid crystal display device having an ultra high transmittance. In particular, the present invention relates to a horizontal electric field type liquid crystal display device in which a common electrode and a pixel electrode are arranged on the same plane, and a horizontal electric field is applied also to an upper portion of the electrode to have an ultra high transmittance.

A liquid crystal display displays an image by adjusting the light transmittance of a liquid crystal using an electric field. Such a liquid crystal display device is divided into a vertical electric field system and a horizontal electric field system in accordance with the direction of the electric field for driving the liquid crystal.

In a vertical electric field type liquid crystal display device, a common electrode formed on an upper substrate and a pixel electrode formed on a lower substrate are opposed to each other to drive a liquid crystal of a TN (twisted nematic) mode by a vertical electric field formed therebetween. The vertical electric field type liquid crystal display device has a disadvantage that the aperture ratio is large, but the viewing angle is narrow to about 90 degrees.

In a horizontal electric field type liquid crystal display device, there is a method of driving a liquid crystal in an in-plane switching (IPS) mode by a horizontal electric field between a pixel electrode and a common electrode arranged in parallel on a lower substrate. The liquid crystal display device of the horizontal electric field type has an advantage that the viewing angle is about 160 degrees, which is larger than the vertical electric field type, and the driving speed is fast. Therefore, a demand for a horizontal electric field type liquid crystal display device that provides a better display quality is increasing day by day.

Hereinafter, the IPS mode horizontal electric field type liquid crystal display device will be described in detail. The IPS mode horizontal electric field type liquid crystal display panel according to the related art includes a thin film transistor (TFT) array substrate, a color filter array substrate, and a liquid crystal layer interposed between the two substrates. 1 is a plan view showing a thin film transistor array substrate of a conventional IPS mode horizontal electric field liquid crystal display panel. FIG. 2 is a cross-sectional view showing the structure of a thin film transistor substrate for an IPS mode horizontal electric field liquid crystal display panel cut by a perforated line I-I 'in FIG.

In the IPS mode horizontal electric field type liquid crystal display device having the thin film transistor substrate shown in Figs. 1 and 2, the pixel electrode and the common electrode are arranged at a certain distance from each other on the same plane, Layer is driven to display image data. 1 and 2, the thin film transistor array substrate of the IPS mode horizontal electric field liquid crystal display panel according to the related art includes a gate wiring GL and a data wiring DL formed so as to intersect on a lower substrate SUB, A pixel electrode PXL and a common electrode COM formed so as to form a horizontal electric field in a pixel region provided in the cross structure and a gate electrode GL connected to the common electrode COM, And a common wiring line CL extending in parallel with the common wiring line CL.

The gate wiring GL supplies a gate signal to the gate electrode G of the thin film transistor T. [ The data line DL supplies a pixel signal to the pixel electrode PXL through the drain electrode D of the thin film transistor T. [ The gate line GL and the data line DL are formed in an intersecting structure to define a pixel region. The common line CL is arranged in parallel with the gate line GL on one side in the pixel region and supplies a reference voltage for driving the liquid crystal to the common electrode COM.

The thin film transistor T responds to the gate signal of the gate line GL so that the pixel signal of the data line DL is charged and held in the pixel electrode PXL. To this end, the thin film transistor T includes a gate electrode G connected to the gate wiring GL, a source electrode S connected to the data wiring DL, and a drain electrode connected to the pixel electrode PXL D). The thin film transistor T includes an active channel layer A forming a channel between the source electrode S and the drain electrode D and an active layer A forming an ohmic contact with the source electrode S and the drain electrode D. [ And a contact layer (not shown).

The pixel electrode PXL is formed in the pixel region by being connected to the drain electrode D of the thin film transistor T through the protective film PAS and the drain contact hole DH penetrating the planarization film PAC. Particularly, the pixel electrode PXL includes a horizontal pixel electrode PXLh connected to the drain electrode D and formed in parallel with the adjacent gate line GL, and a vertical pixel electrode PXLh branched from the horizontal pixel electrode PXLh in the vertical direction And a plurality of vertical pixel electrodes PXLv.

The common electrode COM is connected to the common wiring CL through the common contact hole CH through the gate insulating film GI, the protective film PAS and the planarization film PAC. And a portion that runs parallel to the gate wiring GL has a wider width and forms a horizontal common electrode COMh. And a plurality of vertical common electrodes COMv formed in the vertical direction in the pixel region are formed by branching from the horizontal common electrode COMh. In particular, the vertical common electrode COMv is arranged to be spaced apart from the vertical pixel electrode PXLv by a certain distance in the pixel region.

A horizontal electric field is formed between the vertical pixel electrode PXLv to which the pixel signal is supplied through the thin film transistor T and the vertical common electrode COMv to which the reference voltage is supplied through the common wiring CL. This horizontal electric field causes liquid crystal molecules arranged in the horizontal direction to rotate due to dielectric anisotropy between the thin film transistor array substrate and the color filter array substrate. The light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing an image.

(Vertical) pixel electrode PXL and a (vertical) common electrode COM are spaced apart from each other by a predetermined distance on the same plane, in order to secure the charging capacity for driving the liquid crystal in the pixel region, The common electrode COMh and the extended portion of the drain electrode D are overlapped to form the storage capacitor STG. Alternatively, the auxiliary capacitance may be formed by overlapping the horizontal common electrode COMh and a portion extending from the horizontal pixel electrode PXLh. 2 shows the case where the storage capacitor STG is formed in the space formed by the gate insulating film GI and the channel layer A interposed between the overlapped horizontal common electrode COMh and the extended drain electrode D.

A planarizing film PAC is further formed on the passivation film PAS covering the thin film transistor T so that the vertical pixel electrode PXLv and the vertical common electrode COMv are spaced apart from each other by a predetermined distance on the same plane. In this case, it is difficult to form the auxiliary capacitance in the space between the horizontal pixel electrode PXLh and the horizontal common electrode COMh. In this case, the planarization layer PAC is formed of organic material such as polyacrylate. 2, the drain electrode D connected to the horizontal pixel electrode PXLh is extended to be overlapped with the horizontal common electrode COMh to form the storage capacitor STG .

However, between the horizontal common electrode COMh and the drain electrode D, a gate insulating film GI having a thickness of 4,000 ANGSTROM or more and a channel layer A having a thickness of 2,000 ANGSTROM or more are interposed. Therefore, the storage capacitor STG is formed in a space having a thickness of 6,000 ANGSTROM or more. , The distance between the two electrodes (the horizontal common electrode COMh and the drain electrode D) is still far away in order to form a sufficient storage capacitance STG. As a result, the area in which the horizontal common electrode COMh and the drain electrode D overlap with each other must be widened in order to secure a sufficient storage capacitance STG. For example, as shown in Fig. 1, it is preferable to form the pixel electrodes so as to have a long length that is almost full in the space between the data line DL and the data line DL and a width wider than the common line CL.

The storage capacitor STG is a region that does not allow light to pass through the pixel region. That is, although the storage capacitor STG is a necessary component in driving the liquid crystal display panel, it is a main cause of decreasing the aperture ratio of the pixel.

The horizontal electric field for driving the liquid crystal layer in the IPS mode horizontal electric field type liquid crystal display device as described above will be described in detail as follows. FIG. 3 is an enlarged cross-sectional view cut along a perforated line II-II ', which is a part of the pixel region in FIG. 1, and is a schematic view showing driving states of horizontal electric fields and liquid crystal molecules formed between the pixel electrode and the common electrode of the IPS mode horizontal electric field type liquid crystal display device.

Referring to FIG. 3, the vertical pixel electrode PXLv and the vertical common electrode COMv are formed on the same plane in a horizontal direction. When a DC voltage difference occurs between the vertical pixel electrode PXLv and the vertical common electrode COMv, an electric field is formed as shown in the curve of FIG.

3, the IPS mode horizontal electric field type liquid crystal display device which is currently being produced as a mainstream has a bar shape having a line width of about 2.5 占 퐉 in the vertical pixel electrode PXLv and the vertical common electrode COMv . The vertical pixel electrode PXLv and the vertical common electrode COMv are arranged to have an interval of about 12 to 20 mu m corresponding to 5 to 8 times the line width. On the vertical pixel electrode PXLv and the vertical common electrode COMv, an alignment layer ALG for determining the initial alignment state of the liquid crystal molecules LCM constituting the liquid crystal layer is formed.

When an electric field is formed between the vertical pixel electrode PXLv and the vertical common electrode COMv, the liquid crystal molecules LCM are rearranged under the influence of the electric field. In this state, when a horizontal electric field is applied between the vertical pixel electrode PXLv and the vertical common electrode COMv, the horizontal electric field is generated between the vertical pixel electrode PXLv and the vertical common electrode COMv, . On the other hand, in the space directly above the vertical pixel electrode PXLv and the vertical common electrode COMv, a horizontal electric field is not formed and a weak electric field is generated only in a substantially vertical direction.

In this state, most of the liquid crystal molecules (LCM) lying on the vertical pixel electrode (PXLv) and the vertical common electrode (COMv) are not rearranged because they can not be influenced by the horizontal electric field, . In other words, the liquid crystal molecules LCM between the vertical pixel electrode PXLv and the vertical common electrode COMv are driven by the horizontal electric field to exhibit a display function. However, since the liquid crystal molecules LCM are arranged directly above the vertical pixel electrode PXLv and the vertical common electrode COMv The liquid crystal molecules (LCM) deposited are not driven by a horizontal electric field, and display functions are not exhibited. Therefore, the portion occupied by the vertical pixel electrode PXLv and the vertical common electrode COMv becomes the non-opening region NDA, and only the space between the vertical pixel electrode PXLv and the vertical common electrode COMv becomes the opening region DA, .

Thus, in the IPS mode horizontal electric field type, the area occupied by the vertical pixel electrode PXLv and the vertical common electrode COMv in the pixel region is an area which does not contribute to the aperture ratio and the luminance. As described above, even when the pixel electrode PXL and the common electrode COM are made of a transparent conductive material in the horizontal electric field type liquid crystal display device, the aperture ratio and the luminance are deteriorated.

In addition, when the vertical pixel electrode PXLv and the vertical common electrode COMv are transparent electrodes, the liquid crystal disposed on the vertical electrodes PXLv and the common electrode COMv is not driven, which causes light leakage. For example, in a liquid crystal display device of a normally black mode, a black gradation is shown in a state in which no electric field is applied, and a white gradation is shown in an electric field applied state. However, when an electrode is used as a transparent electrode in an IPS mode liquid crystal display, the liquid crystal molecules in the upper portion of the electrode are in a black gradation state, which is an initial state, even when an electric field is applied. Thus, it becomes a hindrance to realize full white. On the contrary, when the liquid crystal display device of the normally white mode is intended to realize full black, the liquid crystals on the electrodes maintain the white gradation state, which hinders realization of the full black.

Therefore, in the IPS mode horizontal electric field type, it is preferable that the vertical pixel electrode PXLv and the vertical common electrode COMv are formed of an opaque metal material. That is, in the IPS mode liquid crystal display device, since the upper region of the electrode where the liquid crystal is not driven causes a light leakage, this portion should be made a non-transmissive region. As a result, it is not preferable to use a transparent conductive material for the electrodes in the IPS mode.

The IPS mode horizontal electric field type liquid crystal display device has an advantage of being able to drive a liquid crystal at a high speed, but the electrode region becomes a non-transmissive region, which has a limitation in improving the transmittance. It is necessary to develop a horizontal electric field type liquid crystal display device which has a high-speed driving characteristic and is advantageous for moving picture display and can secure a very high transmittance.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a horizontal electric field type liquid crystal display device having an ultra high transmittance by overcoming the problems occurring in a horizontal electric field type liquid crystal display panel by an IPS mode. It is another object of the present invention to provide a horizontal electric field type liquid crystal display device having a structure in which a pixel electrode and a common electrode are adjacent to each other on the same plane and has a thin film transistor substrate having high driving characteristics. It is still another object of the present invention to provide a horizontal electric field type liquid crystal display device having an ultra high transmittance by applying a horizontal electric field to an upper portion of an electrode portion so that an electrode region becomes an opening region and almost all of the pixel region is used as an opening region.

In order to achieve the object of the present invention, a horizontal electric field type liquid crystal display device according to the present invention includes a lower substrate, pixel regions, a pixel electrode, a common electrode, and a plurality of block regions. The pixel regions are arranged in a matrix manner on the lower substrate. The pixel electrode and the common electrode are alternately arranged in a line shape within the pixel region. The block regions include an electrode region and a spacing region. The electrode region corresponds to any one of the pixel electrode and the common electrode which are arranged continuously in the pixel region. The interval region corresponds to between two neighboring electrodes. The width of the interval area of the outermost block area in the pixel area is larger than 1.0 times and not larger than 1.6 times the width of the interval area of the inner block area.

For example, when the width of the pixel region is 20 to 65 占 퐉, the width ratio of the block region to the pixel region is 10% or less. When the width of the pixel region is 65 to 125 占 퐉, the width ratio of the block region to the pixel region is 6% or less. When the width of the pixel region is 125 to 210 占 퐉, the width ratio of the block region to the pixel region is 4% or less.

In one example, the pixel electrode and the common electrode include a transparent conductive material such as indium-tin oxide and indium-zinc oxide.

For example, the pixel electrode and the common electrode have a line width of 1.0 mu m and an interval therebetween is 1.0 mu m to 5.0 mu m.

For example, the pixel electrode and the common electrode have a bending angle of not less than 25 degrees and not more than 40 degrees with respect to the vertical line of the pixel region.

For example, the horizontal electric field type liquid crystal display device according to the present invention further includes an upper substrate and a liquid crystal layer. The upper substrate is adhered to the lower substrate at a distance from the lower substrate. The liquid crystal layer is interposed between the lower substrate and the upper substrate.

For example, the liquid crystal layer includes a liquid crystal material having a difference between a short axis permittivity and a long axis permittivity of from -5 to 5.

For example, the liquid crystal layer includes a negative type liquid crystal material having a difference between a short axis permittivity and a long axis permittivity greater than -5.
In one example, the width of the inner block region among the block regions may be 2.0 탆 to 6.0 탆.

The present invention provides a liquid crystal display device of the U-IPS (ltra high transmissive In Plane Switching) horizontal electric field type which can utilize the upper space of the common electrode and the pixel electrode as a transmissive region. More particularly, the present invention relates to a horizontal electric field type liquid crystal display device having an optimized electrode width value capable of minimizing a non-electric field region in an electrode region, an interval between the electrodes optimized to secure a maximum transmittance, to provide. As a result, in the horizontal electric field type liquid crystal display device according to the present invention, a horizontal electric field can be formed also in the upper layer region of the common electrode and the pixel electrode. Further, the spacing distance between the common electrode and the pixel electrode is sufficiently close to increase the liquid crystal capacitance, and the total capacitance required for driving the liquid crystal has such a large value as not to require the auxiliary capacitance. Therefore, it is not necessary to form the auxiliary capacitance which is the non-aperture region in the pixel region. The horizontal electric field type liquid crystal display device according to the present invention provides a thin film transistor substrate for a horizontal electric field type liquid crystal display having a high aperture ratio and a high luminance which can utilize almost all portions of a pixel region as an opening region.

1 is a plan view showing a structure of a thin film transistor substrate for IPS (In Plane Switching) mode liquid crystal display according to the related art.
FIG. 2 is a cross-sectional view showing the structure of a thin film transistor substrate for an IPS mode liquid crystal display cut along a perforated line I-I 'in FIG. 1; FIG.
FIG. 3 is an enlarged cross-sectional view cut along a perforated line II-II ', which is a part of the pixel region in FIG. 1, illustrating a driving state of a horizontal electric field and liquid crystal molecules formed between a pixel electrode and a common electrode of an IPS mode liquid crystal display device.
4 is a plan view showing a structure of a thin film transistor substrate for a horizontal electric field (U-IPS mode) liquid crystal display device having an ultra-high transmittance according to the present invention.
FIG. 5 is an enlarged cross-sectional view cut along a perforated line II-II ', which is a part of a pixel region in FIG. 4, showing the arrangement structure of a pixel electrode and a common electrode.
6 is a comparative diagram showing the shape of an electric field formed between a pixel electrode and a common electrode in a horizontal electric field type liquid crystal display device to which the concept of the present invention is applied to the prior art.
7 is a sectional view showing the shape of an electric field formed in the arrangement structure of the pixel electrode and the common electrode of the U-IPS mode liquid crystal display device according to the present invention.
8 is a graph showing the transmittance according to the electrode array pitch of the U-IPS mode liquid crystal display device according to the present invention.
9 is a cross-sectional view showing the structure of a pixel electrode and a common electrode constituting one pixel in an IPS mode liquid crystal display device according to a related art.
10 is a sectional view showing the structure of a pixel electrode and a common electrode constituting one pixel in a U-IPS mode liquid crystal display device according to the present invention.
11 is a sectional view showing a structure of a U-IPS mode liquid crystal display device according to an application example of the present invention.
12 is a plan enlarged view showing an electrode structure of a U-IPS mode liquid crystal display device according to an application example of the present invention.
13 is a graph showing a change in the transmittance of light according to a change in the angle of bending of an electrode in a U-IPS mode liquid crystal display according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured.

The horizontal electric field type liquid crystal display device according to the present invention includes a lower substrate and an upper substrate bonded to each other with a predetermined distance and facing each other, and a liquid crystal layer interposed therebetween. Since the thin film transistors are disposed on the lower substrate, they are also referred to as thin film transistor substrates. The lower substrate has a structure in which line-shaped pixel electrodes and line-shaped common electrodes are alternately arranged on the same plane. In particular, the interval between the pixel electrode and the common electrode is narrowed to form a horizontal electric field by the fringe field in the upper space of the electrode. Therefore, in the liquid crystal display device of the horizontal electric field system according to the present invention, ultra-high transmissivity can be ensured by using the electrode region as the transmissive region, which is also called a U-IPS mode liquid crystal display device.

Hereinafter, this will be described in detail with reference to Figs. 4 is a plan view showing a structure of a thin film transistor substrate for a horizontal electric field (U-IPS mode) liquid crystal display device having an ultra-high transmittance according to the present invention. FIG. 5 is an enlarged cross-sectional view cut along a perforated line II-II ', which is a part of the pixel region in FIG. 4, showing the arrangement structure of the pixel electrode and the common electrode.

Referring to FIG. 4, the thin film transistor substrate of the U-IPS mode liquid crystal display panel according to the present invention includes a gate line GL and a data line DL formed so as to intersect on a lower substrate SUB, And a thin film transistor (T). In addition, a pixel electrode (PXL) and a common electrode (COM) formed so as to form a horizontal electric field in a pixel region provided with the cross structure are provided. Although not shown in the figure, common wiring for applying a common voltage to the common electrode COM can be further arranged. Here, there is a structure in which the outermost common electrode COMo overlapping the data line DL functions as a common wiring connecting the common electrodes COM of each pixel, without a separate common wiring.

The thin film transistor T responds to the gate signal of the gate line GL so that the pixel signal of the data line DL is charged and held in the pixel electrode PXL. To this end, the thin film transistor T includes a gate electrode G connected to the gate wiring GL, a source electrode S connected to the data wiring DL, and a drain electrode connected to the pixel electrode PXL D). The thin film transistor T has an active channel layer (not shown) that forms a channel between the source electrode S and the drain electrode D and an ohmic contact with the source electrode S and the drain electrode D And an ohmic contact layer (not shown).

The pixel electrode PXL is formed in the pixel region by being connected to the drain electrode D of the thin film transistor T through the drain contact hole DH that penetrates the protective film and / or the planarization film. Particularly, the pixel electrode PXL includes a horizontal pixel electrode PXLh connected to the drain electrode D and formed in parallel with the adjacent gate line GL, and a vertical pixel electrode PXLh branched from the horizontal pixel electrode PXLh in the vertical direction And a plurality of vertical pixel electrodes PXLv.

The common electrode COM may include an outermost common electrode COMo, a horizontal common electrode COMh, and a vertical common electrode COMv. The outermost common electrode COMo has a structure in which the data line DL is completely covered with the gate insulating film GI, the protective film PAS and the planarizing film PAC interposed therebetween, and the common electrode COM ) Are electrically connected to each other. The horizontal common electrode COMh is connected to the outermost common electrode COMo and has a rod shape disposed across the pixel. The vertical common electrode COMv has a plurality of line segments branched from the horizontal common electrode COMh and arranged in the vertical direction within the pixel region.

In particular, the vertical common electrode COMv is arranged in parallel with the vertical pixel electrode PXLv in the pixel region. In addition, the first or last vertical pixel electrode PXLv is disposed immediately beside the outermost common electrode COMo.

A horizontal electric field is formed between the vertical pixel electrode PXLv supplied with the pixel signal through the thin film transistor T and the vertical common electrode COMv supplied with the reference voltage through the outermost common electrode COMo. This horizontal electric field causes liquid crystal molecules arranged in the horizontal direction to rotate due to dielectric anisotropy between the thin film transistor array substrate and the color filter array substrate. The light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing an image.

4 showing the structure of the U-IPS mode liquid crystal display device according to the present invention and FIG. 1 showing the structure of the IPS mode liquid crystal display device according to the related art, most of the components are similar. If there is a difference, the auxiliary capacitance electrode is not included in Fig. Another important difference is in the arrangement structure of the vertical pixel electrode PXLv and the vertical common electrode COMv. However, there is no difference in the arrangement structure of the electrodes on the drawing. Hereinafter, the structure of the U-IPS mode liquid crystal display device according to the present invention will be described in detail with reference to FIG.

Referring to FIG. 5, the vertical pixel electrode PXLv and the vertical common electrode COMv are formed in a horizontal direction on the same plane. A planarization layer, a protection layer, and a gate insulation layer may be formed under the vertical pixel electrode PXLv and the vertical common electrode COMv. Here, the arrangement structure of the electrodes will be mainly described.

The vertical pixel electrode PXLv and the vertical common electrode COMv are arranged alternately. The vertical pixel electrode PXLv and the vertical common electrode COMv have the same line width CD. The vertical pixel electrode PXLv and the vertical common electrode COMv are arranged in parallel with a predetermined gap GAP.

For example, the line width CD of the vertical pixel electrode PXLv and the vertical common electrode COMv has a value of 0.5 mu m to 2.0 mu m. In addition, the arrangement pitch of the vertical pixel electrode PXLv and the vertical common electrode COMv has a value of 2.0 mu m to 6.0 mu m. Accordingly, the gap GAP between the vertical pixel electrode PXLv and the vertical common electrode COMv may have a value of 1.5 mu m to 4.0 mu m. Most preferably, the line width CD of the vertical pixel electrode PXLv and the vertical common electrode COMv is 1.0 탆. Considering the electrode pitch under this condition, it is preferable that the gap GAP between the vertical pixel electrode PXLv and the vertical common electrode COMv has a value of 1.0 mu m to 5.0 mu m.

The line width CD and the pitch values of the vertical pixel electrode PXLv and the vertical common electrode COMv are not arbitrarily determined by any change of the designer. In the present invention, the above values are determined through various experiments and simulations in order to design a U-IPS mode liquid crystal display device capable of ensuring ultra-high transmittance.

First, in order to form a horizontal electric field in the upper space of the vertical pixel electrode PXLv and the vertical common electrode COMv, the electrode gap GAP is designed to be narrow. That is, if the electrode gap GAP is designed to be narrow, a horizontal electric field can be formed not only between the electrodes but also on the upper surface of the electrode by the fringe field.

However, even if a horizontal electric field is formed on the upper surface of the electrode by narrowing the electrode interval, the electrode region can not always be used as the transmissive region. In the IPS mode liquid crystal display device according to the related art, even if the interval between the electrodes is reduced to be close to the width of the electrodes, the upper region of the electrode can not be used as the transmissive region.

The reason will be described with reference to Fig. 6 is a comparative diagram showing the shape of an electric field formed between a pixel electrode and a common electrode in a horizontal electric field type liquid crystal display device to which the concept of the present invention is applied to the prior art. Fig. 6 shows the horizontal electric field shape in a state in which the interval of the electrodes in the IPS mode liquid crystal display device according to the prior art is narrowed corresponding to the case of the present invention.

For example, when the width CD of the electrodes is 2.3 mu m or more, if the electrode interval GAP is narrowed to about 3.0 mu m, not only between the vertical pixel electrode PXLv and the vertical common electrode COMv, A horizontal electric field can be formed. The semicircular solid line shown above the electrodes PXLv, COM represents the horizontal electric field formed between the electrodes. The graph curve shown above shows the overall profile of the horizontal electric field applied to the liquid crystal cell.

Referring to FIG. 6, a maximum electric field is formed between the vertical pixel electrode PXLv and the vertical common electrode COMv. Also, in the upper space of the electrodes, a certain electric field is formed. However, in a certain region of the center of the electrode, a dead zone occurs in which the electric field value is rapidly lowered. When the width CD of the electrodes is 2.3 mu m or more, the region of the dead zone occupies at least 1.0 mu m or more. Therefore, as shown in FIG. 6, the horizontal electric field has a shape that abruptly drops in the middle region of the upper layer of the electrodes, and this portion still remains as a non-transparent region.

However, as in the present invention, when the width CD of the electrodes is designed to be 0.5 to 2.0 탆, the dead zone of the electric field can be minimized. Will be described with reference to FIG. 7 is a cross-sectional view showing the shape of an electric field formed in the arrangement structure of the pixel electrode and the common electrode of the U-IPS mode liquid crystal display device according to the present invention.

In Fig. 7, a semicircular solid line indicated on the upper side of the electrodes PXLv, COM represents a horizontal electric field formed between the electrodes. And the graph curve shown above shows the overall profile of the horizontal electric field applied to the liquid crystal cell. As shown in Fig. 7, when the line width CD of the electrode is 2.0 m or less, the dead zone of the horizontal electric field formed in the upper layer of the electrode can be reduced to a region of 0.5 m or less. Further, since the width of the electrodes is relatively narrow, a freeze field is also formed at the center of the electrodes. Therefore, in order to achieve the target ultra high transmittance in the present invention, it is preferable that the line width CD of the vertical pixel electrode PXLv and the vertical common electrode COMv is 2.0 탆 or less. It is not difficult to form an electrode having a line width smaller than 2.0 mu m by the current photolithography process. The electrode with a much narrower line width can be manufactured sufficiently. However, forming wirings with narrower linewidths can result in an exponential increase in manufacturing time and manufacturing costs.

As described above, in the horizontal electric field type liquid crystal display device according to the present invention, considering the production conditions of the liquid crystal display devices of various sizes and the ultra high transmittance capable of providing high quality, the vertical pixel electrode PXLv and the vertical common electrode It is preferable that the linewidth (CD) of the laser beam (COMv) has a value of 0.5 mu m to 2.0 mu m. In particular, it is most preferable that the line width CD of the vertical pixel electrode PXLv and the vertical common electrode COMv has a value of 1.0 mu m.

Second, the pitch of the electrodes was determined with the line width (CD) of the electrodes determined. The pitch of the electrodes may be closely related to the transmittance. Therefore, the change of the transmittance according to the arrangement pitch of the electrodes was measured to determine the most preferable pitch of the electrode arrangement.

For example, the vertical pixel electrode PXLv and the vertical common electrode COMv are designed so as to have a value of 1.0 탆 which is the most preferable electrode line width CD, and the arrangement pitch of the electrodes is changed from 12.0 탆 to 0.5 탆 While narrowing down, the transmittance is measured. If the pitch of the electrode arrangement is narrowed, since the number of electrodes can be increased, it can be sufficiently predicted that the transmittance is reduced to some extent. And it was an experiment to find out to what extent the electrode pitch can be narrowed.

However, as shown in FIG. 8, the experimental result has an unexpected result. 8 is a graph showing the transmittance according to the electrode array pitch of the U-IPS mode liquid crystal display device according to the present invention.

In the IPS mode according to the prior art, the pitch of the electrode array is 12.5 [micro] m at the minimum value. Therefore, the transmittance was measured while decreasing the electrode array pitch starting from 12.0 μm. The transmittance of light gradually decreased as the electrode array pitch was decreased. At about 8.5 μm, the minimum transmittance value of 0.380 (au) was acceptable for the product. From the results up to this point, it is desirable to design the electrode pitch at 8.5 mu m as the lowest value. In Fig. 8, only the transmittance when the electrode pitch is 8.5 탆 or less is shown for convenience. The transmittance increases almost linearly in the range of 8.5 μm or more.

However, we continued the experiment by further narrowing the electrode arrangement pitch (Pich). As a result, the pitch of the electrode arrangement showed a minimum value at 7.0 탆 and then gradually increased. Even the smallest permissible transmittance value of 0.380 (au) with the product at 6.0 μm reappears, and since then the transmittance has continued to increase.

Considering that the electrode width (CD) set in the foregoing is 1.0 탆, the experiment was conducted by narrowing the electrode array pitch to 2.0 탆. As a result, the transmittance showed an increasing tendency. Of course, it is also possible to make the electrode arrangement pitch as small as 2.0 占 퐉 or less. However, in the horizontal electric field type liquid crystal display according to the present invention, considering the production conditions of the liquid crystal display devices of various sizes and the ultra high transmittance capable of providing high quality, the vertical pixel electrode PXLv and the vertical common electrode COMv The arrangement pitch is preferably 2.0 占 퐉 to 6.0 占 퐉. In this case, the gap GAP between the electrodes is 1.0 탆 to 5.0 탆.

In the horizontal electric field type liquid crystal display device having the ultra high transmittance according to the present invention, the line width CD of the vertical pixel electrode PXLv and the vertical common electrode COMv is 1.0 탆 and the arrangement pitch Pitch) is most preferably 3.0 탆. In this case, the gap GAP between the electrodes becomes 2.0 mu m. When manufacturing the actual U-IPS mode liquid crystal display device based on the above simulation and the experimental results, considering the current production equipment and process conditions, the line widths of the vertical pixel electrode (PXLv) and the vertical common electrode (COMv) (CD) of 1.9 mu m and an arrangement pitch of 5.6 mu m. In this case, the gap GAP between the electrodes is 3.7 mu m.

When the electrodes are designed in this way, the upper electrode region can be utilized as the transmission region. Therefore, even if both the pixel electrode PXL and the common electrode COM are formed of a transparent conductive material, no light spots are generated and an ultra high transmittance can be ensured. Here, the transparent conductive material includes an oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

Finally, when the intervals between the electrodes are narrow, the horizontal electric field formed between the vertical pixel electrode PXLv and the vertical common electrode COMv may have characteristics different from those in the IPS mode according to the related art. That is, in the horizontal electric field type liquid crystal display device according to the present invention, it is preferable to use a liquid crystal material having properties different from those of the prior art.

The electrode structure proposed in the present invention was applied to various liquid crystal materials. As a result, the liquid crystal material having a dielectric constant difference Δ∈ within the range of -5 to 5 showed the maximum transmittance. Permittivity difference between the liquid crystal means a difference in dielectric constant speed of the liquid crystal molecules (ε _⊥) and longitudinal dielectric constant (ε _∥). For example, if the permittivity difference is a positive number, it is divided into a positive type liquid crystal and if it is negative, it is divided into a negative type liquid crystal. In the present invention, the difference in dielectric constant is preferably 5 or less irrespective of the type of liquid crystal. Further, a negative type liquid crystal having a difference in dielectric constant of 5 or less is more preferable. That is, a negative type liquid crystal having a difference in permittivity greater than -5 is preferable.

Up to now, structural characteristics have been described in terms of a horizontal electric field for driving a liquid crystal layer in a horizontal electric field liquid crystal display device having ultra high transmittance according to the present invention. Hereinafter, with reference to FIGS. 9 and 10, the features of the pixel structure for realizing the ultra-high transmittance in the application example of the U-IPS mode liquid crystal display device according to the present invention will be described. To explain effectively, a comparison with the prior art will be given.

&Lt; Case of Prior Art >

First, with reference to Figs. 1 to 3 and Fig. 9, the characteristics of the pixel configuration of the IPS mode liquid crystal display device according to the related art will be described first. 9 is a cross-sectional view showing the structure of a pixel electrode and a common electrode constituting one pixel in an IPS mode liquid crystal display device according to a related art.

Referring to FIGS. 1 to 3 and 9, in the IPS mode liquid crystal display according to the related art, a plurality of unit pixels are arranged in a matrix manner. Here, the unit pixel means a pixel that displays a unit point constituting the whole image. In the case of a color display device, a unit pixel is made up of smaller sub-pixels. For example, one unit pixel may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Or a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel. The 'pixel' described in the present invention means a 'sub-pixel' unless otherwise specified.

One pixel is defined by gate lines (GL) and data lines (DL) that are perpendicular to each other on a substrate. Various components are arranged in one pixel region. Elements necessary for driving such as the thin film transistor T, the storage capacitor STG and / or the lines GL, DL and CL and the pixel electrodes PXL and the common electrodes COM are arranged.

The region where the vertical pixel electrode PXLv and the vertical common electrode COMv are arranged among these constituent elements can be defined as the pixel region EPA. In the pixel region EPA, each of the vertical pixel electrode PXLv and the vertical common electrode COMv has a line segment shape having a width of approximately 3 mu m and is arranged in parallel at an interval of approximately 15 mu m. A basic unit in which the electrodes PXLv and COMv are alternately arranged is defined as a block, and an area occupied by the block is defined as a block area BA. Further, a space between the electrodes PXLv and COMv is defined as a gap region GA. FIG. 9 shows a case where four block regions B1, B2, B3 and B4 are arranged in one pixel.

In the IPS mode liquid crystal display device according to the related art, since the horizontal electric field is not formed in the area occupied by the electrodes PXLv and COMv, the light transmittance can not be controlled by the liquid crystal. Therefore, in order to prevent light leakage, the electrodes PXLv and COMv are formed of an opaque metal so as to be in an impermeable region. Therefore, in the unit block area BA constituting the pixel area EPA, only the spacing area GA is a transmissive area. For example, in Fig. 9, the aperture ratio in the pixel area EPA is defined as {(sum of four interval areas GA) / (pixel area EPA)}. That is, in the IPS display device according to the prior art, the aperture ratio always has a value smaller than 1.

Further, it has a structure in which the width of the interval region GA is larger than the width of the electrodes PXLv, COMv by at least about five times. Therefore, the ratio occupied by the unit block area BA in the pixel area EPA also has a considerably large value. In particular, the higher the resolution, the smaller the pixel size. Even if the pixel size is small, since there is a limit to narrow the width of the wiring, a method of reducing the number of blocks is used in order to make the pixel small. That is, in the case of having the same screen size, the high resolution liquid crystal display device has pixels smaller in size than the low resolution liquid crystal display device, and the number of blocks is smaller in one pixel.

For example, in a liquid crystal display having a pixel structure as shown in FIG. 9, the most efficient method for increasing the resolution is to reduce the number of blocks from four to three or two. In particular, in order to always arrange the vertical common electrode COMv in the pixel area EPA at the outermost periphery, it is preferable to reduce the number of blocks to two. That is, if the third block B3 and the fourth block B4 are deleted, the resolution can be doubled.

More specifically, in the IPS mode liquid crystal display device according to the related art, the size of the pixel region differs depending on the resolution and the size of the liquid crystal display panel. In the case of a typical liquid crystal display panel currently produced, the area ratio of the unit block area BA to the pixel area EPA is calculated as shown in the following table.

The definition of the resolution is based on what is currently in common use. For example, Full HD (FHD) is expressed as 2K in 1920 × 1080 (number of pixels in the horizontal unit × number of pixels in the vertical unit), 4K in the QHD of 3840 × 2160 or 4096 × 2160, and 7680 × 4320 in the UHD 8K. Here, K means 1,000. The number of unit pixels represented by the ideal resolution is a color basic pixel, and one unit pixel includes three (red-green-blue) or four (red-green-blue-white) sub-pixels. Therefore, in terms of the number of sub-pixels, the number of horizontal sub-pixels is at least three times the number of pixels per horizontal unit.

mode resolution
(Number of pixels) Panel diagonal size
(Inch) Sub pixel size (width: 탆) BA / EPA area ratio (%)

IPS mode
FHD (2K) 55 210 6.20 49 186.42 7.11 43 161.1 8.41 QHD (4K) 65 124 14.38 55 105 14.31 UHD (8K) 98 93.7 14.28 QHD (4K) 49 93.21 14.39 43 81.7 13.70 UHD (8K) 65 62 21.79 55 52.5 45.34

Table 1 is a table summarized according to the panel size and resolution which are mainly produced in the IPS mode liquid crystal display device. Here, the area ratio of the unit block area BA to the pixel area EPA is shown in the order of the size of the sub-pixels. (Sub) pixel size, it can be divided into three groups as follows.

First, when the width of the pixel region is 210 to 130 占 퐉, the area ratio is 6% or more. Secondly, when the width of the pixel region is 125 to 80 占 퐉, the area ratio is 13% or more. Thirdly, when the width of the pixel region is 65 to 20 占 퐉, the area ratio is 20% or more.

In a liquid crystal display panel having the same diagonal size, the larger the resolution, the smaller the area of the pixel. At this time, when the pixel region has a rectangular shape with a lengthwise and longitudinal length of 1: 3, the block regions BA are elongated in the longitudinal direction and are arranged in the lateral direction. In this state, in order to increase the resolution, the number of block areas BA arranged in the horizontal direction is reduced. Thus, the size of the shrinking pixel is more dependent on the width than the length.

Table 2 shows the width ratio of the unit block area BA to the width of the pixel area EPA in the case of a representative liquid crystal display panel currently being produced.

mode resolution
(Number of pixels) Panel diagonal size
(Inch) Sub pixel size (width: 탆) BA / EPA width ratio (%)

IPS mode FHD (2K) 55 210 5.6 49 186.42 6.4 43 161.1 7.6 QHD (4K) 65 124 8.9 55 105 11.8 UHD (8K) 98 93.7 10.5 QHD (4K) 49 93.21 11.7 43 81.7 11.1 UHD (8K) 65 62 14.6 55 52.5 24.5

Likewise, by the size of the pixel, it can be divided into three groups as follows. First, when the width of the pixel region is 210 to 130 占 퐉, the width ratio is 5% or more. Secondly, when the width of the pixel region is 125 to 80 占 퐉, the width ratio is 8% or more. Thirdly, when the width of the pixel region is 65 to 20 占 퐉, the width ratio is 14% or more.

In the case of the present invention,

Next, with reference to Figs. 4, 5, and 10, the characteristics of the pixel configuration of a liquid crystal display device of a U-IPS (Ultra High Transmittive In-Plane Switching) method according to the present invention will be described first. FIG. 10 is a cross-sectional view illustrating the structure of a pixel electrode and a common electrode of a pixel in a U-IPS mode liquid crystal display device according to the present invention.

Referring to FIGS. 4, 5 and 10, in the U-IPS mode liquid crystal display according to the present invention, a plurality of pixels are arranged in a matrix manner. The pixels are defined by gate lines GL and data lines DL that are orthogonal to each other on the substrate. Various components are arranged in one pixel region. Elements necessary for driving such as the thin film transistor T and / or the lines GL and DL and the pixel electrode PXL and the common electrodes COM are disposed.

The region where the vertical pixel electrode PXLv and the vertical common electrode COMv are arranged among these constituent elements can be defined as the pixel region EPA. In the pixel region EPA, each of the vertical pixel electrode PXLv and the vertical common electrode COMv has a line segment shape having a width of approximately 0.5 to 2.0 mu m, and is arranged in parallel at an interval of approximately 1.5 to 4.0 mu m. Most preferably, they have a line segment shape having a width of approximately 1.0 mu m and are arranged side by side at intervals of approximately 3.0 mu m. A basic unit in which the electrodes PXLv and COMv are alternately arranged is defined as a block, and an area occupied by the block is defined as a block area BA. Further, the space between the electrodes PXLv and COMv is defined as an interval, and the region occupied by the interval is defined as a gap region GA. FIG. 10 shows a case where there are 10 block areas (B1 to B10) in one pixel.

In the U-IPS mode liquid crystal display device according to the present invention, since the horizontal electric field is formed also in the area occupied by the electrodes PXLv and COMv, the light transmittance can be controlled by the liquid crystal. Therefore, in order to maximize the transmittance, the electrodes PXLv and COMv are formed of a transparent conductive material to form a transmissive region. Therefore, the entire unit block area BA constituting the pixel area EPA becomes the transmissive area. For example, in Fig. 10, the aperture ratio in the pixel area EPA is defined as {(sum of ten block areas BA) / (pixel area EPA)}. That is, in the U-IPS mode liquid crystal display device according to the present invention, the aperture ratio has substantially the same value as one.

In addition, the width of the interval area GA with respect to the width of the electrodes PXLv, COMv has a value of three times or less. Therefore, the ratio of the unit block area BA occupying in the pixel area EPA is considerably smaller than that of the IPS mode liquid crystal display of the related art. Therefore, even if the number of blocks is reduced in order to increase the resolution, the number of blocks is considerably larger in one pixel than in the prior art.

For example, in a liquid crystal display having the pixel structure shown in FIG. 10, the most efficient method for increasing the resolution is to reduce the number of blocks from ten to eight, six, or four. For example, if the seventh block B7 to the tenth block B10 are deleted, the resolution can be doubled.

More specifically, in the U-IPS mode liquid crystal display device according to the present invention, the size of the pixel region varies depending on the resolution and the size of the liquid crystal display panel. In the case of developing a typical IPS liquid crystal display panel which is currently being produced with a U-IPS liquid crystal display panel, the area ratio of the unit block area BA to the pixel area EPA is calculated as shown in Table 3 below.

mode resolution
(Number of pixels) Panel diagonal size
(Inch) Sub pixel size (width: 탆) BA / EPA area ratio (%)

U-IPS mode FHD (2K) 55 210 1.65 49 186.42 1.99 43 161.1 2.28 QHD (4K) 65 124 4.63 55 105 3.54 UHD (8K) 98 93.7 4.66 QHD (4K) 49 93.21 4.71 43 81.7 5.53 UHD (8K) 65 62 8.63 55 52.5 11.86

Table 3 is a table summarized according to the panel size and resolution for implementing the U-IPS mode liquid crystal display device. Here, the area ratio of the unit block area BA to the pixel area EPA is shown in the order of the size of the pixel area. By the size of the pixel, it can be divided into three groups as follows.

First, when the width of the pixel region is 210 to 130 占 퐉, the area ratio is 3% or less. Secondly, when the width of the pixel region is 125 to 80 占 퐉, the area ratio is 8% or less. Thirdly, when the width of the pixel region is 65 to 20 占 퐉, the area ratio is 15% or less.

In Table 4, the width ratio of the unit block area BA to the width of the pixel area EPA is calculated in a case where the U-IPS mode is to be implemented in the standard of a representative liquid crystal display panel currently produced.

mode resolution
(Number of pixels) Panel diagonal size
(Inch) Sub pixel size (width: 탆) BA / EPA width ratio (%)

U-IPS mode FHD (2K) 55 210 1.5 49 186.42 1.7 43 161.1 1.9 QHD (4K) 65 124 2.5 55 105 3.0 UHD (8K) 98 93.7 3.3 QHD (4K) 49 93.21 3.3 43 81.7 3.8 UHD (8K) 65 62 5.0 55 52.5 5.9

Likewise, by the size of the pixel, it can be divided into three groups as follows. First, when the width of the pixel region is 210 to 130 占 퐉, the width ratio is 4% or less. Secondly, when the width of the pixel region is 125 to 80 占 퐉, the width ratio is 6% or less. Thirdly, when the width of the pixel region is 65 to 20 占 퐉, the width ratio is 10% or less.

In the comparative example of the structural characteristics of the conventional IPS mode liquid crystal display device and the U-IPS mode liquid crystal display device according to the present invention described above, the shape of a pixel is a rectangular shape with a ratio of 1: 3 . However, in the case where the pixel region has a rectangular shape with a length ratio of 3: 1 in the longitudinal direction to the width in the lateral direction and the line segments extending in the horizontal direction of the pixel electrode and the common electrode are arranged in the vertical direction, &Lt; / RTI > In this case, the length can be calculated as a ratio of the length of the unit block to the length, which is substantially the same as the value described above.

The basic structural features of the horizontal electric field type liquid crystal display device according to the present invention have been described above. Hereinafter, an application example of an actual horizontal electric field type liquid crystal display device to which all the features of the present invention are applied will be described with reference to FIGS. First, with reference to FIG. 11, optimization conditions for the interval region between the electrodes will be described. 11 is a cross-sectional view illustrating a structure of a U-IPS mode liquid crystal display device according to an embodiment of the present invention.

11, a U-IPS mode liquid crystal display according to an embodiment of the present invention includes a lower substrate SUB, a plurality of pixel regions arranged in a matrix manner on the lower substrate SUB, And a pixel electrode PXLv and a common electrode COMv alternately arranged in a line shape on a plane. In particular, the pixel electrode PXLv and the common electrode COMv are arranged alternately with a constant pitch value. As shown in FIGS. 5 and 10, the pitch of the pixel electrode PXL and the common electrode COM is the same as the interval between the electrode region CD corresponding to one of the pixel electrode PXL and the common electrode COM, And a block area BA having a low-resolution area GA. Particularly, the width of one of the block areas BA is characterized by being 2.0 mu m to 6.0 mu m.

Further, in the application example of the present invention, the following structural features are further provided in order to maximize the light transmittance. First, in the application of the present invention, there are two kinds of gap regions (GA) between the electrodes. For example, one is the outermost gap (G _OT ) arranged at the outermost positions on both sides in the pixel area (EPA). And the other is the inner gap G _IN disposed inside except for the outer gap G _OT . In particular, the outermost gap G _OT and the inner gap G _IN may be the same, or the outermost gap G _OT may have a greater width than the inner gap G _IN . Specifically, it is preferable that the ratio of the innermost gap (G _OT ) to the inner gap (G _IN ) has a ratio value of 1.0: 1.0 to 1.6: 1.0.

As described in the foregoing comparative example, in the IPS mode liquid crystal display device according to the prior art, the interval area GA is at least 12 mu m or more, and the ratio of the interval area GA to the pixel area is considerably large. Therefore, when the outermost gap G _OT is made larger than the inner gap G _IN , luminance unevenness may occur in one pixel because the electric field formed at wide intervals is smaller than the electric field formed at narrow intervals.

However, in the U-IPS mode liquid crystal display device, the gap area GA is less than 6.0 mu m, and the proportion occupying the pixel area is relatively small. Thus, the outermost wacheuk gap (G _OT) to the inner gap (G _IN), even larger than the pixel area than the outermost distance (G _OT) For this reason, there is little occupying ratio without the transmission loss does not occur, luminance variations in the pixel area, Do not occur.

In particular, the outermost distance (G _OT) than the inner distance (G _IN) ratio of 1.0: 1.0 to 1.6: 1.0 in between it is possible to ensure the transmittance of light at least 94%. Further, when the transmittance is changed, the value after the fluctuation is also ensured by a value of 99% or more, so that the transmittance variation is hardly recognized.

12 and 13, characteristics of the pixel electrode PXL and the common electrode COM in terms of the bending angle in the U-IPS mode liquid crystal display device according to the present invention will be described. 12 is an enlarged plan view showing an electrode structure of a U-IPS mode liquid crystal display device according to an application example of the present invention. FIG. 13 is a graph showing a change in transmittance of light according to a change in the angle of bending of an electrode in a U-IPS mode liquid crystal display according to an application example of the present invention.

Referring to FIG. 12, the vertical pixel electrode PXLv and the vertical common electrode COMv have a bending angle,?, With respect to the vertical line Lv. In the U-IPS mode liquid crystal display according to the application of the present invention, the angle? Is preferably 5 degrees or more and 45 degrees or less. Most preferably, the angle? Is not less than 25 degrees and not more than 40 degrees.

The vertical pixel electrode PXLv and the vertical common electrode COMv may have a bending angle in the IPS mode liquid crystal display according to the prior art shown in FIG. However, in the prior art, the angle is determined in consideration of the orientation angle of the orientation film, which is different from the bending angle proposed in the present invention.

The main purpose of the U-IPS mode liquid crystal display device according to the present invention is to maximize the light transmittance. Therefore, even when the angle of break is determined, it is characterized by setting the direction for maximizing the transmittance.

Specifically, the transmissivity is measured while varying the tilt θ from 0 degrees to 90 degrees with respect to the vertical line Lv of the vertical pixel electrodes PXLv and vertical common electrodes COMv. As a result, the results shown in Fig. 13 were obtained. Here, as a condition that the transmittance can be ensured at 95% or more, it is most preferable that? Is 25 degrees or more and 40 degrees or less.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

GL: gate wiring DL: data wiring
CL: common wiring T: thin film transistor
G: gate electrode S: source electrode
D: drain electrode A: semiconductor channel layer
GI: gate insulating film SUB: substrate
Cst, STG: auxiliary capacity PAS: protective film
PXL: pixel electrode COM: common electrode
PXLh: Horizontal pixel electrode PXLv: Vertical pixel electrode
COMh: horizontal common electrode COMv: vertical common electrode
DH: drain contact hole CH: common contact hole
G _OT : outermost gap G _IN : inner gap

Claims

A lower substrate;
A plurality of pixel regions arranged on the lower substrate in a matrix manner;
A pixel electrode and a common electrode alternately arranged on the same plane in the pixel region; And
A plurality of block regions successively arranged in the pixel region,
Wherein the block region has an electrode region and a spacing region, the electrode region corresponds to one of the pixel electrode and the common electrode, the spacing region corresponds to a region between two neighboring electrodes,
Wherein a width of the interval area of the outermost block area in the pixel area is larger than 1.0 times and not larger than 1.6 times the width of the interval area of the inner block area.

The method according to claim 1,
Wherein the width ratio of the inner block region to the pixel region is 10% or less when the width of the pixel region is 20 to 65 占 퐉.

The method according to claim 1,
Wherein a width ratio of the inner block region to the pixel region is 6% or less when the width of the pixel region is 65 to 125 占 퐉.

The method according to claim 1,
Wherein a width ratio of the inner block region to the pixel region is 4% or less when the width of the pixel region is 125 to 210 占 퐉.

The method according to claim 1,
Wherein the pixel electrode and the common electrode are connected to each other,
A transparent conductive material such as indium-tin oxide and indium-zinc oxide.

The method according to claim 1,
The line width of the pixel electrode and the common electrode is 1.0 mu m,
And the width of the interval region of the inner block region is 1.0 탆 to 5.0 탆.

The method according to claim 1,
Wherein the pixel electrode and the common electrode have a bending angle of not less than 25 degrees and not more than 40 degrees with respect to a vertical line of the pixel region.

The method according to claim 1,
An upper substrate bonded to the lower substrate at a distance from the upper substrate; And
And a liquid crystal layer interposed between the lower substrate and the upper substrate.

9. The method of claim 8,
Wherein the liquid crystal layer comprises a liquid crystal material having a difference between a short axis permittivity and a long axis permittivity of from -5 to 5.

9. The method of claim 8,
Wherein the liquid crystal layer comprises a negative type liquid crystal material having a difference between a short axis permittivity and a long axis permittivity greater than -5.

The method according to claim 1,
And the width of the inner block region is 2.0 占 퐉 to 6.0 占 퐉.