KR101859239B1 - 캐쉬 메모리 관리의 최적화 방법 및 대응하는 장치 - Google Patents

캐쉬 메모리 관리의 최적화 방법 및 대응하는 장치 Download PDF

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KR101859239B1
KR101859239B1 KR1020127030138A KR20127030138A KR101859239B1 KR 101859239 B1 KR101859239 B1 KR 101859239B1 KR 1020127030138 A KR1020127030138 A KR 1020127030138A KR 20127030138 A KR20127030138 A KR 20127030138A KR 101859239 B1 KR101859239 B1 KR 101859239B1
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cache memory
data
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KR20130093506A (ko
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띠리 께르
르노 리갈
플로렁 프레나예
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톰슨 라이센싱
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Information Transfer Between Computers (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Circuits Of Receivers In General (AREA)
KR1020127030138A 2010-05-17 2011-05-16 캐쉬 메모리 관리의 최적화 방법 및 대응하는 장치 Active KR101859239B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP10305518A EP2388704A1 (en) 2010-05-17 2010-05-17 Method of optimization of cache memory management and corresponding apparatus
EP10305518.2 2010-05-17
PCT/EP2011/057899 WO2011144576A1 (en) 2010-05-17 2011-05-16 Method of optimization of cache memory management and corresponding apparatus

Publications (2)

Publication Number Publication Date
KR20130093506A KR20130093506A (ko) 2013-08-22
KR101859239B1 true KR101859239B1 (ko) 2018-05-18

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KR1020127030138A Active KR101859239B1 (ko) 2010-05-17 2011-05-16 캐쉬 메모리 관리의 최적화 방법 및 대응하는 장치

Country Status (11)

Country Link
US (1) US10691598B2 (https=)
EP (2) EP2388704A1 (https=)
JP (1) JP5680188B2 (https=)
KR (1) KR101859239B1 (https=)
CN (1) CN102906715B (https=)
CA (1) CA2797435C (https=)
MX (1) MX2012013168A (https=)
MY (1) MY156708A (https=)
PT (1) PT2572284E (https=)
RU (1) RU2599537C2 (https=)
WO (1) WO2011144576A1 (https=)

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JP6327959B2 (ja) * 2014-06-04 2018-05-23 キヤノン株式会社 情報処理端末、キャッシュ制御方法及びウェブシステム
KR102017284B1 (ko) 2015-05-26 2019-09-02 삼성전자주식회사 부팅 디바이스 및 그 동작 방법
CN106997351B (zh) * 2016-01-22 2021-03-02 斑马智行网络(香港)有限公司 一种资源缓存管理方法及系统和装置
US10129360B2 (en) * 2016-03-28 2018-11-13 The Boeing Company Unified data networking across heterogeneous networks
US10031834B2 (en) 2016-08-31 2018-07-24 Microsoft Technology Licensing, Llc Cache-based tracing for time travel debugging and analysis
US11907091B2 (en) 2018-02-16 2024-02-20 Microsoft Technology Licensing, Llc Trace recording by logging influxes to an upper-layer shared cache, plus cache coherence protocol transitions among lower-layer caches
CN115061654B (zh) * 2022-08-11 2022-11-22 歌尔股份有限公司 穿戴产品消息显示方法、装置、设备及可读存储介质

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US20080151817A1 (en) * 2006-12-20 2008-06-26 Jeffrey William Fitchett Method and system for reducing service interruptions to mobile communication devices

Also Published As

Publication number Publication date
PT2572284E (pt) 2015-03-04
JP5680188B2 (ja) 2015-03-04
US10691598B2 (en) 2020-06-23
US20130198314A1 (en) 2013-08-01
MY156708A (en) 2016-03-15
KR20130093506A (ko) 2013-08-22
EP2572284A1 (en) 2013-03-27
CA2797435C (en) 2018-06-05
EP2388704A1 (en) 2011-11-23
RU2012154297A (ru) 2014-06-27
CN102906715A (zh) 2013-01-30
WO2011144576A1 (en) 2011-11-24
CA2797435A1 (en) 2011-11-24
RU2599537C2 (ru) 2016-10-10
CN102906715B (zh) 2016-05-25
EP2572284B1 (en) 2015-01-28
MX2012013168A (es) 2013-01-17
JP2013526743A (ja) 2013-06-24

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