KR101841930B1 - Method of spreading a plurality of interrupts, interrupt spreader, and system on-chip having the same - Google Patents

Abstract

The interrupt spread method includes receiving a plurality of interrupt request signals, determining whether each time interval between interrupt request signals is less than a predetermined interval, and if the time interval is smaller than the predetermined interval, And output the interrupt request signals to the plurality of processors, respectively. Thus, the interrupt spread method can prevent processors from suddenly waking up due to interrupts generated continuously in a short time.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt spread method, an interrupt spread device, and a system on-chip having the interrupt spread device,

The present invention relates to a multiprocessor system (or multicore system), and more particularly, to an interrupt spread method for a plurality of interrupts generated in a plurality of interrupt sources, an interrupt spread device, and a system on- .

Generally, an electronic device has an interrupt controller for interrupt processing, and when the interrupt sources generate a plurality of interrupts, the interrupts can be prioritized and output to the processor. In recent years, system on-chip (SOC) has been widely used in accordance with the trend of downsizing and lightening of electronic devices, and a plurality of Intellectual Property (IP) (Or a processor having a plurality of cores) can be mounted.

On the other hand, a plurality of processors mounted on the system on-chip frequently enter the low-power mode to reduce power consumption, and when interrupts are generated from the interrupt sources and an interrupt request signal is input, . In this case, when a plurality of processors mounted on the system-on-chip are simultaneously escaping in the low power mode, an in-rush current is generated in the processors due to sudden wake-up Lt; / RTI >

It is an object of the present invention to provide a system and method for a plurality of processors (or processors) in an inactive state (e.g., a power down state, a power off state, etc.) by a plurality of interrupts consecutively generated in a short time in a plurality of interrupt sources (I.e., a sudden wake-up) in a short period of time (for example, a plurality of cores of a multi-core processor), an active state .

It is another object of the present invention to provide a system and method for a plurality of processors (or processors) in an inactive state (e.g., a power down state, a power off state, etc.) by a plurality of interrupts consecutively generated in a short time in a plurality of interrupt sources , An interrupt spread device capable of preventing continuous change (i.e., abrupt wake-up) of an active state (e.g., a plurality of cores of a multicore processor) in an active state .

It is still another object of the present invention to provide a system on-chip having the interrupt spread device.

It is to be understood, however, that the present invention is not limited to the above-described embodiments and various modifications may be made without departing from the spirit and scope of the invention.

According to an aspect of the present invention, there is provided an interrupt spread method including receiving a plurality of interrupt request signals, determining whether each of the interrupt request signals is less than a predetermined interval Adjusting the time interval to a predetermined interval when the time interval is smaller than the preset interval, and outputting the interrupt request signals to the plurality of processors, respectively .

According to one embodiment, the interrupt request signals are generated based on a plurality of interrupts output from a plurality of interrupt sources, and each of the interrupt request signals may be respectively assigned to the processors.

According to one embodiment, the predetermined interval may be determined within a range in which an inrush current is not generated in the processors when the processors are changed from an inactive state to an active state.

According to an embodiment of the present invention, the step of adjusting at the predetermined interval may include: when kth time interval between the k-th (k is an integer equal to or greater than 1) interrupt request signal and the (k + And delaying the output of the (k + 1) -th interrupt request signal until the k-th time interval becomes the predetermined interval.

According to an embodiment of the present invention, the adjusting step may further include changing an output order of the interrupt request signals according to a predetermined priority.

According to an embodiment of the present invention, when the k-th time interval is 0, the controlling of the k-th interrupt request signal and the (k + 1) And delaying the output by the predetermined interval.

According to an aspect of the present invention, there is provided an interrupt spread method comprising: receiving a plurality of interrupt request signals; The method of claim 1, further comprising the steps of: classifying the interrupt request signals into processors that are inactive with the processors and non-target interrupt request signals to be output to the active processors among the interrupt request signals, Determining whether a time interval between target interrupt request signals to be output to the inactive processors among the interrupt request signals is less than a predetermined interval, When the interval is smaller than the preset interval, And outputting the target interrupt request signals to the processors in the inactive state, respectively.

According to an embodiment of the present invention, the step of adjusting at the predetermined interval may include a step of setting a k-th time interval between the k-th target interrupt request signal and the k-th target interrupt request signal of the k-th contiguous k And if the kth time interval is greater than the predetermined time, delaying the output of the (k + 1) th target interrupt request signal until the kth time interval becomes the predetermined interval.

According to an embodiment of the present invention, the adjusting step may further include changing an output order of the target interrupt request signals according to a predetermined priority.

According to an embodiment of the present invention, when the k-th time interval is 0, the controlling of the k-th target interrupt request signal and the (k + 1) th target interrupt request signal And delaying one output by the predetermined interval.

According to another aspect of the present invention, there is provided an interrupt spreading apparatus for receiving first to m-th (m is an integer of 2 or more) interrupt request signals, First to m-th interrupt holders for outputting request signals to the first to m-th processors while leaving request signals at least over a predetermined interval, and first to m-th interrupt holders for outputting the interrupt request signals among adjacent interrupt request signals And an interrupt arbiter for adjusting the time interval to a predetermined interval when the time interval is smaller than the predetermined interval.

According to an embodiment, the first to m-th interrupt request signals are generated based on a plurality of interrupts output from a plurality of interrupt sources, and the first to m-th interrupt request signals are generated by the first to m- Interrupt holders, respectively.

According to an embodiment, the first through the m-th interrupt holders are connected to the first through m-th processors, respectively, and the first through m-th interrupt request signals are connected to the first through m- Lt; RTI ID = 0.0 > m processors. ≪ / RTI >

According to an embodiment of the present invention, the predetermined interval is set to a value within a range in which an inrush current is not generated in the first to mth processors when the first to mth processors are changed from an inactive state to an active state Can be determined.

According to an embodiment, when the first to m-th interrupt holders receive the first to m-th interrupt request signals, they transmit an output request signal to the interrupt arbiter, and when they receive the output enable signal from the interrupt arbitrator And output the first to m-th interrupt request signals to the first to m-th processors, respectively.

According to an embodiment, each of the first through m-th interrupt holders may wait for the output permission signal from the interrupt arbiter in an idle state indicating that the first through the m-th interrupt request signals are not received, And an assert state indicating that the first to the m-th interrupt request signals are output to the first to m-th processors, respectively, and a state machine Can be implemented.

According to an embodiment, the interrupt arbiter sequentially outputs the output permission signal to the first through m-th interrupt holders when receiving the output request signal from the first through m-th interrupt holders, And to control the first through m-th interrupt request signals to be output to the first through m-th processors at least over the predetermined interval.

According to an embodiment, the interrupt arbiter includes an idle state indicating that any one of the first through m-th interrupt request signals is not output to the first through m-th processors, And a weight state indicating that at least one of the signals is being output to the first to m-th processors.

According to an embodiment, the interrupt arbiter may change the output order of the first to m-th interrupt request signals according to a predetermined priority.

According to one embodiment, the interrupt arbiter classifies the first through m-th processors into a first group composed of processors in an active state and a second group composed of processors in an inactive state, and the first through m- The interrupt request signals allocated to the first group among the interrupt request signals are not adjusted at the predetermined intervals and the interrupt request signals allocated to the second group among the first to the m- Can be adjusted at the predetermined interval.

According to still another aspect of the present invention, there is provided a system on-chip comprising a plurality of interrupt sources for generating a plurality of interrupts, first to m-th m is an integer greater than or equal to 2) interrupt request signals; an interrupt spread device for adjusting a time interval between adjacent interrupt request signals among the first to the m-th interrupt request signals to at least a predetermined interval; And first to m-th processors for performing interrupt processing for the interrupt sources in response to the first to m-th interrupt request signals, respectively.

According to an embodiment, the interrupt spread device receives the first through m-th interrupt request signals and transmits the first through m-th interrupt request signals to the first through m- And outputting the interrupt request signals to the first to mth interrupt holders when the time interval between the adjacent interrupt request signals is less than the preset interval, And an interrupt arbiter for adjusting the interrupt interval at a predetermined interval.

According to an embodiment, the first to the m-th interrupt request signals are received in the first to m-th interrupt holders, respectively, and the first to m-th interrupt holders are connected to the first to m- .

According to an embodiment, the interrupt arbiter may change the output order of the first to m-th interrupt request signals according to a predetermined priority.

According to one embodiment, the interrupt arbiter classifies the first through m-th processors into a first group composed of processors in an active state and a second group composed of processors in an inactive state, and the first through m- The interrupt request signals allocated to the first group among the interrupt request signals are not adjusted at the predetermined intervals and the interrupt request signals allocated to the second group among the first to the m- Can be adjusted at the predetermined interval.

According to one embodiment, the system on-chip may be provided in a mobile device such as a mobile phone, a smart phone, a smart pad, and the like.

According to another aspect of the present invention, there is provided an interrupt processing method, wherein in a state where a part of a plurality of processors is in an active state and another part is in an inactive state, When a plurality of interrupt sources generate a plurality of interrupts, the processors can process the interrupts. Specifically, the interrupt processing method may include causing the interrupt controller to receive the interrupts from the interrupt sources, to allocate the interrupts to each of the processors according to a predetermined method to output a plurality of interrupt request signals, For receiving the interrupt request signals from the interrupt controller and outputting the interrupt request signals to non-target interrupt request signals to be output to the active processors and target interrupt request signals to be output to the inactive processors And causes the interrupt spreader to output the non-target interrupt request signals directly to the processors in the active state, and the interrupt spreader may cause the interrupt spreader to output the non- Determines whether the time interval is smaller than a predetermined interval, and adjusts the time interval to the predetermined interval when the time interval is smaller than the preset interval, and the interrupt spreader sets the target interrupt request signals And sequentially output the information to processors in the inactive state.

An interrupt spreading method according to embodiments of the present invention is a method for interrupting a plurality of interrupt sources in a short time when successively outputting a plurality of interrupts in a short time, (Or a plurality of cores of a multicore processor) in an inactive state (e.g., a power down state, a power off state, etc.) can be activated It is possible to prevent a continuous change (i.e., abrupt wake-up) to a state (e.g., power-on state, etc.). Accordingly, an inrush current can be prevented from being generated in the processors.

An interrupt spread device according to embodiments of the present invention includes a plurality of interrupt sources for generating a plurality of interrupts in succession when a plurality of interrupt sources continuously output a plurality of interrupts in a short time, (E.g., a plurality of cores of a multicore processor) in an inactive state (e.g., power-down state, power-off state, etc.) (I.e., sudden wake-up) in an active state (e.g., a power-on state, etc.) Accordingly, an inrush current can be prevented from being generated in the processors.

The system on-chip according to embodiments of the present invention may be provided with the interrupt spread device so that a plurality of processors in an inactive state (for example, a power-down state, a power-off state, (I.e., a plurality of cores of the core processor) are continuously changed in an active state (for example, a power-on state, etc.) within a short time (that is, sudden wake-up) have.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be variously expanded without departing from the spirit and scope of the present invention.

1 is a flowchart illustrating an interrupt spread method according to an embodiment of the present invention.
FIGS. 2A and 2B are diagrams illustrating an example in which the interrupt spread method of FIG. 1 is performed.
FIGS. 3A and 3B are diagrams showing another example in which the interrupt spread method of FIG. 1 is performed. FIG.
4A and 4B are diagrams showing still another example in which the interrupt spread method of FIG. 1 is performed.
5 is a flowchart illustrating an interrupt spread method according to another embodiment of the present invention.
6A and 6B are diagrams illustrating an example in which the interrupt spread method of FIG. 5 is performed.
7 is a flowchart showing an interrupt spread method according to another embodiment of the present invention.
8A and 8B are diagrams illustrating an example in which the interrupt spread method of FIG. 7 is performed.
9 is a flowchart showing an interrupt spread method according to another embodiment of the present invention.
10 is a diagram for explaining the interrupt spread method of FIG.
11 is a block diagram showing an interrupt spread device according to an embodiment of the present invention.
12 is a diagram showing a state machine of an interrupt holder provided in the interrupt spread device of FIG.
13 is a diagram showing a state machine of an interrupt arbiter provided in the interrupt spread device of FIG.
14 is a timing chart showing an example of the operation of the interrupt spread device of FIG.
15 is a block diagram illustrating a system on-chip according to one embodiment of the present invention.
16 is a diagram showing an example in which the interrupt spread device operates in the system on-chip of FIG.
17 is a diagram showing another example of the operation of the interrupt spread device in the system on-chip of FIG.
FIG. 18 is a diagram showing another example in which the interrupt spread device operates in the system on-chip of FIG.
19 is a flowchart showing an example of a method for verifying whether or not any system on-chip has an interrupt spread device.
FIG. 20 is a diagram for explaining an example of a method for verifying whether or not an arbitrary system on-chip has an interrupt spread device.
Fig. 21 is a flowchart showing another example of a method for verifying whether or not any system on-chip has an interrupt spread device.
22 is a block diagram illustrating a multicore system in accordance with an embodiment of the present invention.
23 is a diagram showing an example in which the multicore system of FIG. 22 is implemented as a smartphone.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a flowchart illustrating an interrupt spread method according to an embodiment of the present invention.

Referring to FIG. 1, the interrupt spread method of FIG. 1 receives a plurality of interrupt request signals (Step S120) and determines whether each time interval between interrupt request signals is smaller than a preset interval (Step S140) can do. In this case, if each time interval between the interrupt request signals is smaller than the predetermined interval, the interrupt spread method of FIG. 1 can adjust each time interval between the interrupt request signals at a predetermined interval (Step S160) have. On the other hand, if each time interval between the interrupt request signals is larger than the predetermined interval, the interrupt spread method of FIG. 1 can maintain the respective time intervals between the interrupt request signals (Step S165). Then, the interrupt spread method of FIG. 1 may output the interrupt request signals to the plurality of processors, respectively (Step S180). On the other hand, each of the plurality of processors may correspond to independent processors and may correspond to a plurality of cores of a multicore processor (e.g., a dual core processor, a quad core processor, etc.). Although the active state is divided into an active state and an inactive state in this specification, the inactive state is a power-down state, a power-off state, Such as < RTI ID = 0.0 > a < / RTI > low power mode. Hereinafter, the interrupt spread method of FIG. 1 will be described in detail.

The interrupt spread method of FIG. 1 may sequentially receive interrupt request signals (Step S120). In one embodiment, interrupt request signals may be generated based on interrupts output from interrupt sources, and interrupt request signals may be assigned to processors, respectively. Each of the interrupt sources is an Intellectual Property (IP) that performs a predetermined operation in a multicore system (or a multiprocessor system), and includes various components constituting a system on-chip (SOC) For example, it may correspond to certain modules such as a video module, a sound module, a display module, a memory module, a communication module, a camera module, and the like. Generally, the interrupt sources can be implemented in a single system on-chip, in the order of tens to hundreds. When these interrupt sources generate interrupts, interrupt request signals generated based on the interrupts can be input to the processors, respectively, and the processors perform interrupt processing for the interrupt sources in response to the interrupt request signals, respectively can do. In recent years, system-on-chips where a plurality of IPs and a plurality of processors are mounted on a single chip have been widely used in order to miniaturize and lighten electronic devices. In order to reduce power consumption, Mode, so that when a plurality of processors simultaneously escape (i.e., abruptly wake up) in a low power mode based on interrupts generated from the interrupt sources, an inrush current an in-rush current may be generated, which may cause malfunction due to the inrush current. Particularly, as the size of the system on-chip becomes smaller, the generation of the inrush current due to the change of the dynamic current becomes a serious problem in the operation stability of the system on-chip.

In the interrupt spread method of FIG. 1, when the interrupt request signals are received, it is determined whether each time interval between the interrupt request signals is smaller than a predetermined interval (Step S140). In one embodiment, the predetermined interval may be determined within a range in which an inrush current is not generated within the processors when a plurality of processors are changed from an inactive state to an active state. In this case, if each time interval between the interrupt request signals is smaller than the predetermined interval, the interrupt spread method of FIG. 1 can adjust each time interval between the interrupt request signals at a predetermined interval (Step S160) have. On the other hand, if each time interval between the interrupt request signals is larger than the predetermined interval, the interrupt spread method of FIG. 1 can maintain the respective time intervals between the interrupt request signals (Step S165). In other words, in the case of the interrupt spread method of FIG. 1, only when each time interval between interrupt request signals is smaller than a predetermined interval, the time interval is adjusted to a predetermined interval and output to each of the processors, Can be output to the processors without adjusting the time interval, respectively. As a result, the interrupt request signals can be input to the processors with a predetermined interval or more.

Specifically, in the interrupt spread method of FIG. 1, each time interval between interrupt request signals is adjusted at a predetermined interval (Step S160). In step S160, K interrupt request signal until the k-th time interval becomes a predetermined interval when the k-th time interval between the interrupt request signal and the (k + 1) -th interrupt request signal is greater than zero have. That is, even though the k-th time interval between the k-th interrupt request signal and the k-th interrupt request signal that are sequentially input and adjacent to each other is smaller than a preset interval, the k-th interrupt request signal and the (k + 1) Is directly output to the two processors, an inrush current can be generated in the processors because the two processors are caused to suddenly wake up in a short time. Therefore, the interrupt spread method of FIG. 1 delays the output of the (k + 1) -th interrupt request signal so that the k-th time interval between the k-th interrupt request signal and the (k + 1) -th interrupt request signal becomes a predetermined interval. 1, when the k-th time interval between the k-th interrupt request signal and the (k + 1) -th interrupt request signal is 0 (i.e., simultaneously input), the interrupt spread method It is possible to delay one output from the interrupt request signal and the (k + 1) -th interrupt request signal by a predetermined interval. As a result, even though the k-th interrupt request signal and the (k + 1) -th interrupt request signal are input simultaneously, the k-th time interval between the k-th interrupt request signal and the (k + An in-rush current is not generated inside.

In addition, the interrupt spread method of FIG. 1 may change the output order of the interrupt request signals according to a predetermined priority in adjusting the time interval between the interrupt request signals at predetermined intervals (Step S160). For example, the k-th interrupt request signal, the k + 1-th interrupt request signal, and the (k + 2) -th interrupt request signal are sequentially input, And the (k + 1) -th time interval between the k + 1-th interrupt request signal and the (k + 2) -th interrupt request signal are all less than a predetermined interval, the interrupt spread method of FIG. 1 interrupt request signal to delay the output of the (k + 1) -th interrupt request signal so that the (k + 1) -th time interval becomes a predetermined interval. However, the interrupt spread method of FIG. 1 may delay the outputs of the k-th interrupt request signal, the (k + 1) -th interrupt request signal, and the (k + 2) -th interrupt request signal in a non- . For example, the k-th interrupt request signal, the k + 1-th interrupt request signal, and the (k + 2) -th interrupt request signal are sequentially input, And the (k + 1) -th time interval between the k + 1-th interrupt request signal and the (k + 2) -th interrupt request signal are all less than a predetermined interval, If the priority of the request signal is the lowest, the interrupt spread method of FIG. 1 may output the k-th interrupt request signal, the (k + 2) -th interrupt request signal, and the (k + 1) -th interrupt request signal.

Generally, when an interrupt request signal is received, the processor changes from an inactive state to an active state, and then performs an interrupt processing (i.e., an interrupt service). At this time, the inrush current is generated while the plurality of transistors constituting the inside of the processor suddenly start operating. Particularly, in the case of a low-power processor, since most clocks are not toggled in the inactive state because a plurality of clock gating circuits are provided to reduce power consumption in an inactive state, Is changed from the inactive state to the active state, most of the clocks start the toggle at the same time, so that the inrush current can be largely generated. At this time, if a plurality of processors suddenly wake up within a short time, an inrush current generated by a plurality of processors is added, and the power supply of the peripheral circuit becomes unstable, so that malfunction may occur. The interrupt spread method of FIG. 1 is characterized in that when a plurality of interrupt sources successively output a plurality of interrupts in a short time, a time interval between a plurality of interrupt request signals generated based on the interrupts is set to at least a predetermined interval , It is possible to prevent a plurality of processors (e.g., multicore processors, etc.) in an inactive state from being continuously changed to an active state in a short time (i.e., sudden wake-up) . As a result, an inrush current due to a sudden wake-up in a plurality of processors (or a plurality of cores of a multicore processor) is prevented from being generated in the system on-chip, The electronic device can secure high operation stability. 1, the interrupt spread method of FIG. 1 is applied to the interrupt request signals input to all processors irrespective of whether the plurality of processors are in an active state or an active state. However, The interrupt spread method of FIG. 1 may be applied only to the interrupt request signals input to the processors.

FIGS. 2A and 2B are diagrams illustrating an example in which the interrupt spread method of FIG. 1 is performed.

Referring to FIGS. 2A and 2B, FIG. 2A shows that the first to fourth interrupt request signals nIRQ_1,..., NIRQ_4 are sequentially input. FIG. The first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4 are sequentially output to the first to fourth processors.

Specifically, the interrupt spread method of FIG. 1 can sequentially receive the first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4. 2A, the first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is smaller than the predetermined interval PS and the second interrupt request signal nIRQ_2 is smaller than the predetermined interval PS, the second time interval S2 between the third interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 is also smaller than the predetermined interval PS and the second time interval S2 between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 The third time interval S3 is also smaller than the predetermined interval PS. 1, the first interrupt interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is set to a predetermined interval PS, And the second interval S2 between the second interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 delays the output of the second interrupt request signal nIRQ_2 to a predetermined interval PS The output of the third interrupt request signal nIRQ_3 is delayed so that the third time interval S3 between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 becomes a predetermined interval PS It is possible to delay the output of the fourth interrupt request signal nIRQ_4. 1, the first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4 may be sequentially output to the first to fourth processors with a predetermined interval PS have.

FIGS. 3A and 3B are diagrams showing another example in which the interrupt spread method of FIG. 1 is performed. FIG.

3A and 3B, FIG. 3A shows that first through fourth interrupt request signals nIRQ_1 through nIRQ_4 are sequentially input. FIG. 3B illustrates an interrupt spreading method of FIG. The first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4 are sequentially output to the first to fourth processors.

Specifically, the interrupt spread method of FIG. 1 can sequentially receive the first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4. 3A, a first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is greater than a predetermined interval PS, and a second interrupt request signal the second time interval S2 between the third interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 is smaller than the predetermined interval PS and the third interrupt request signal nIRQ_2 is between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4. The third time interval S3 is less than the predetermined interval PS. As shown in FIG. 3B, the interrupt spread method of FIG. 1 maintains the first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 as it is, The output of the third interrupt request signal nIRQ_3 is delayed so that the second time interval S2 between the interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 becomes the predetermined interval PS, The output of the fourth interrupt request signal nIRQ_4 may be delayed such that the third time interval S3 between the request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 becomes the predetermined interval PS. In this way, the interrupt spread method of FIG. 1 sequentially outputs the first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4 to the first to fourth processors with a predetermined interval (PS) or more .

4A and 4B are diagrams showing still another example in which the interrupt spread method of FIG. 1 is performed.

Referring to FIGS. 4A and 4B, FIG. 4A shows sequentially inputting first through fourth interrupt request signals nIRQ_1,..., NIRQ_4, FIG. 4B illustrates an interrupt spread method The first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4 are sequentially output to the first to fourth processors.

Specifically, the interrupt spread method of FIG. 1 can sequentially receive the first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4. 4A, the first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is smaller than the predetermined interval PS and the second interrupt request signal nIRQ_2 is smaller than the predetermined interval PS, the second time interval S2 between the third interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 is smaller than the predetermined interval PS and the third interrupt request signal nIRQ_2 is between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4. The third time interval S3 is also smaller than the predetermined interval PS. However, depending on the performance of the system on-chip, even if two processors continuously wake up in a short time, an inrush current may not be generated within the two processors, and three processors may be continuously The inrush current may not be generated in the three processors. 4A and 4B, it is assumed that the two processors allow continuous wake-up in a short time, but do not allow the three processors to successively wake up in a short time. For example, as shown in FIG. 4B, the interrupt spread method of FIG. 1 allows a predetermined number (i.e., two) of processors to continuously wake up in a short time, The first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 are set to the same value even if the first time interval S1 between the signal nIRQ_1 and the second interrupt request signal nIRQ_2 is smaller than the predetermined interval PS, The first time interval S1 can be maintained as it is. However, since the interrupt spread method of FIG. 1 does not allow the three processors to continuously wake up in a short time, a second time between the second interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 The output of the third interrupt request signal nIRQ_3 may be delayed so that the second time interval S2 becomes the predetermined interval PS since the interval S2 is smaller than the predetermined interval PS. Since the interrupt spread method of Fig. 1 allows the two processors to continuously wake up in a short time, a third time between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 The third time interval S3 between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 can be maintained as it is even if the interval S3 is smaller than the predetermined interval PS.

5 is a flowchart illustrating an interrupt spread method according to another embodiment of the present invention.

5, the interrupt spread method receives a k-th interrupt request signal (Step S210), receives a (k + 1) -th interrupt request signal (Step S220) It can be determined whether the time interval between the +1 interrupt request signals is greater than 0 (Step S230). At this time, if the time interval between the k-th interrupt request signal and the k + 1-th interrupt request signal is greater than 0, the output of the k-th interrupt request signal is delayed (Step S240) K interrupt request signal and the (k + 1) -th interrupt request signal at a predetermined interval according to a predetermined priority when the time interval between the k-th interrupt request signal and the k + (Step S250). In FIG. 5, it is assumed that the time interval between the k-th interrupt request signal and the (k + 1) -th interrupt request signal is smaller than a predetermined interval.

The interrupt spread method of FIG. 5 sequentially receives the k-th interrupt request signal and the (k + 1) -th interrupt request signal, and determines whether the time interval between the k-th interrupt request signal and the (k + 1) -th interrupt request signal is less than It is determined whether the time interval between the k-th interrupt request signal and the (k + 1) -th interrupt request signal is greater than zero. In other words, when the k-th interrupt request signal and the (k + 1) -th interrupt request signal are sequentially input, the time interval between the k-th interrupt request signal and the (k + Therefore, the time interval between the k-th interrupt request signal and the (k + 1) -th interrupt request signal is greater than 0 because the k-th interrupt request signal and the k + 1-th interrupt request signal may be input substantially simultaneously. It is judged whether it is big or not. If the time interval between the k < th > interrupt request signal and the (k + 1) -th interrupt request signal is greater than 0, the interrupt spread method of FIG. And if the time interval between the k < th > interrupt request signal and the (k + 1) -th interrupt request signal is 0, the interrupt spread method of FIG. 5 may delay the output of the k & The output of the +1 interrupt request signal may be delayed by a predetermined interval. As a result, even if the k-th interrupt request signal and the (k + 1) -th interrupt request signal are inputted at the same time, the k-th interrupt request signal and the (k + 1) The interrupt spread method of FIG. 5 can prevent a plurality of processors from changing from an inactive state to an active state (i. E., Sudden wake-up) in a short time on a system on-chip.

6A and 6B are diagrams illustrating an example in which the interrupt spread method of FIG. 5 is performed.

Referring to FIGS. 6A and 6B, FIG. 6A shows that the first to fourth interrupt request signals nIRQ_1,..., NIRQ_4 are sequentially input. FIG. 6B shows an interrupt spread method The first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4 are sequentially output to the first to fourth processors.

5 may sequentially receive the first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4. The first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4 may be sequentially received. ., nIRQ_4) can be input at substantially the same time. 6A, the first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is smaller than the predetermined interval PS, The second time interval S2 between the interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 is also smaller than the predetermined interval PS and the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_3, lt; RTI ID = 0.0 > nIRQ_4 < / RTI > Accordingly, assuming that the priority of the fourth interrupt request signal nIRQ_4 is higher than that of the third interrupt request signal nIRQ_3, as shown in FIG. 6B, the interrupt spread method of FIG. the output of the second interrupt request signal nIRQ_2 is delayed so that the first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 becomes the predetermined interval PS, the output of the fourth interrupt request signal nIRQ_4 is delayed so that the second time interval S2 between the fourth interrupt request signal nIRQ_2 and the fourth interrupt request signal nIRQ_4 becomes the predetermined interval PS, And the fourth interrupt request signal nIRQ_4 may delay the output of the third interrupt request signal nIRQ_3 to a predetermined interval PS. At this time, since the priority of the fourth interrupt request signal nIRQ_4 is higher than that of the third interrupt request signal nIRQ_3, the fourth interrupt request signal nIRQ_4 is outputted first than the third interrupt request signal nIRQ_3 . 5, even if adjacent interrupt request signals among the first to fourth interrupt request signals nIRQ_I1, ..., nIRQ_I4 are input substantially simultaneously, the interrupt spread method of FIG. (NIRQ_1, ..., nIRQ_4) sequentially to the first to fourth processors by placing the first to fourth interrupt request signals (PS).

7 is a flowchart showing an interrupt spread method according to another embodiment of the present invention.

Referring to FIG. 7, the interrupt spread method of FIG. 7 receives a kth interrupt request signal (Step S310), receives a k + 1 interrupt request signal (Step S320) It can be determined whether the priority is higher than that of the +1 interrupt request signal (Step S330). In this case, if the priority of the k-th interrupt request signal is higher than that of the (k + 1) -th interrupt request signal, the interrupt spread method of FIG. 7 can delay the k + If the priority of the k-th interrupt request signal is lower than the priority of the (k + 1) -th interrupt request signal, the k-th interrupt request signal may be delayed (Step S345). However, it is assumed in FIG. 7 that the time interval between the k-th interrupt request signal and the (k + 1) -th interrupt request signal is smaller than a predetermined interval.

The interrupt spread method of FIG. 7 sequentially receives the k-th interrupt request signal and the (k + 1) -th interrupt request signal and determines whether the time interval between the k-th interrupt request signal and the (k + 1) -th interrupt request signal is less than It is possible to determine whether the k < th > interrupt request signal has a higher priority than the (k + 1) -th interrupt request signal. 7, the output order of the k-th interrupt request signal and the k + 1-th interrupt request signal can be determined independently of the input order of the k-th interrupt request signal and the (k + 1) -th interrupt request signal . 7 can delay the (k + 1) -th interrupt request signal if the priority of the k-th interrupt request signal is higher than that of the (k + 1) -th interrupt request signal, K interrupt request signal if the priority of the (k + 1) -th interrupt request signal is lower than the priority of the (k + 1) -th interrupt request signal. As a result, even when the k-th interrupt request signal and the (k + 1) -th interrupt request signal are sequentially input, the k-th interrupt request signal and the (k + 1) -th interrupt request signal are output in a non- Since the (k + 1) -th interrupt request signal and the k-th interrupt request signal are output to the k-th processor and (k + 1) -th processor at predetermined intervals, respectively, the interrupt spread method of FIG. It is possible to prevent a plurality of processors from changing from an inactive state to an active state (i.e., sudden wake-up).

8A and 8B are diagrams illustrating an example in which the interrupt spread method of FIG. 7 is performed.

8A and 8B show that the first through fourth interrupt request signals nIRQ_1 through nIRQ_4 are sequentially input. FIG. 8B illustrates an interrupt spreading method of FIG. The first through fourth interrupt request signals nIRQ_1 through nIRQ_4 are output to the first through fourth processors, respectively, according to a predetermined priority.

Specifically, the interrupt spread method of FIG. 7 can sequentially receive the first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4. 8A, a first time interval S1 between the first interrupt request signal nIRQ_1 and the second interrupt request signal nIRQ_2 is smaller than a predetermined interval PS and a second interrupt request signal the second time interval S2 between the third interrupt request signal nIRQ_2 and the third interrupt request signal nIRQ_3 is also smaller than the predetermined interval PS and the second time interval S2 between the third interrupt request signal nIRQ_3 and the fourth interrupt request signal nIRQ_4 The third time interval S3 is also smaller than the predetermined interval PS. At this time, when the first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4 are respectively output to the first to fourth processors, the first to fourth interrupt request signals the output order of the first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4 may need to be changed, unlike the input order of the nIRQ_1, ..., nIRQ_4. Accordingly, the interrupt spread method of FIG. 7 changes the output order of the first to fourth interrupt request signals nIRQ_1, ..., nIRQ_4 according to a predetermined priority, thereby outputting the first to fourth interrupt request signals up sequence of the first to fourth processors for performing the interrupt processing in response to the nIRQ_1, nIRQ_1, ..., nIRQ_4. For example, as shown in FIG. 8B, the interrupt spread method of FIG. 7 includes first to fourth interrupt request signals nIRQ_1 to nIRQ_4 as a first interrupt request signal nIRQ_1, The request signal nIRQ_3, the fourth interrupt request signal nIRQ_4, and the second interrupt request signal nIRQ_2. Similarly, each time interval between the first interrupt request signal nIRQ_1, the third interrupt request signal nIRQ_3, the fourth interrupt request signal nIRQ_4, and the second interrupt request signal nIRQ_2 is a predetermined interval PS, . 7, the output order of the first to fourth interrupt request signals nIRQ_I1, ..., nIRQ_I4 is determined according to a predetermined priority, and the output order is output to the first to fourth processors can do.

FIG. 9 is a flowchart illustrating an interrupt spread method according to another embodiment of the present invention, and FIG. 10 is a diagram for explaining an interrupt spread method of FIG.

9 and 10, the interrupt spread method of FIG. 9 sequentially receives interrupt request signals (Step S410) and sequentially transmits the interrupt request signals to target interrupt request signals and non- Interrupt request signals (step S420). Specifically, the target interrupt request signals are interrupt request signals to be output to the inactive processors TP_1, ..., TP_4, and the non-target interrupt request signals are transmitted to the active processors NTP_1 and NTP_2 Interrupt request signals to be output. Thereafter, the interrupt spread method of FIG. 9 may output the non-target interrupt request signals to the active processors NTP_1 and NTP_2, respectively (step S430). 9, it is determined whether each time interval between the target interrupt request signals is smaller than a preset interval (step S440). If it is determined that the respective time intervals between the target interrupt request signals have been set If the time interval between the target interrupt request signals is greater than the predetermined interval, the time interval is maintained (Step S460) ). 9, the target interrupt request signals may be output to the inactive processors TP_1, ..., TP_4, respectively (step S470). Generally, since the in-rush current is generated when a plurality of processors are continuously changed (i.e., abruptly woken up) from the inactive state to the active state in a short time, the interrupt spread method of FIG. 9 requires a wake- The non-target interrupt request signals output to the non-active processors NTP_1 and NTP_2 are not adjusted at predetermined intervals. As a result, since the interrupt spread method of FIG. 9 adjusts the time interval of the target interrupt request signals output to the inactive processors TP_1, ..., TP_4 at predetermined intervals, The interrupt request signals can be relatively reduced (i.e., relatively reduced in load) to operate at high speed.

11 is a block diagram showing an interrupt spread device according to an embodiment of the present invention.

11, the interrupt spread device 100 may include first to m-th (where m is an integer greater than or equal to 2) interrupt holders 120_1 to 120_m and an interrupt arbiter 140 .

The first to mth interrupt holders 120_1 to 120_m receive first to mth interrupt request signals nIRQ_I1 to nIRQ_Im respectively and output first to mth interrupt request signals (nIRQ_O1, ..., nIRQ_Om) to the first to mth processors (not shown) with a predetermined interval or more. 11, the first through the m-th interrupt request signals nIRQ_I1, ..., nIRQ_Im are generated based on a plurality of interrupts output from a plurality of interrupt sources (not shown) 1 to m-th interrupt request signals nIRQ_I1, ..., nIRQ_Im may be received in the first to mth interrupt holders 120_1, ..., and 120_m, respectively. The first through m-th interrupt holders 120_1 through 120_m are connected to the first through m-th processors, respectively. The first through m-th interrupt request signals nIRQ_O1 through nIRQ_Om, To the first to the m-th processors, respectively, at a predetermined interval or more. Each of the first through m-th interrupt holders 120_1 through 120_m receives the first through the m-th interrupt request signals nIRQ_I1 through to nIRQ_Im to the interrupt arbiter 140 ..., ASm from the interrupt arbiter 140 and outputs the first through the m-th interrupt request signals nIRQ_O1, ..., ..., nIRQ_Om) to the first to m processors, respectively. To this end, each of the first through m-th interrupt holders 120_1, ..., and 120_m is connected to a state machine (not shown) having an idle state, a wait state and an assert state. ), Which will be described later with reference to FIG.

If the time interval between adjacent interrupt request signals among the first to mth interrupt request signals nIRQ_I1, ..., nIRQ_Im is smaller than a preset interval, the interrupt arbiter 140 sets the time interval to a predetermined interval . At this time, the predetermined interval may be determined within a range in which an inrush current is not generated in the first to m-th processors when the first to m-th processors are changed from the inactive state to the active state. Specifically, when the interrupt arbiter 140 receives the output request signals RS1 through RSm from the first through m-th interrupt holders 120_1 through 120m, The first to the m-th interrupt request signals nIRQ_O1, ..., nIRQ_Om are outputted to the holders 120_1, ..., and 120_m sequentially by outputting the output enable signals AS1, And may be output to the first to m-th processors at a predetermined interval or more. For this purpose, the interrupt arbiter 140 may be implemented as a state machine composed of an idle state and a wait state, which will be described later with reference to FIG. In one embodiment, the interrupt arbiter 140 may change the output order of the first through the m-th interrupt request signals nIRQ_O1, ..., nIRQ_Om according to a predetermined priority. As a result, the input order of the first to m-th interrupt request signals nIRQ_I1, ..., nIRQ_Im input to the first to mth interrupt holders 120_1 to 120_m and the first to mth interrupt request signals The output order of the first to mth interrupt request signals nIRQ_O1, ..., nIRQ_Om output from the interrupt holders 120_1, ..., and 120_m may be different from each other.

Meanwhile, the interrupt arbiter 140 classifies the first through m-th processors into a first group consisting of processors in an active state and a second group composed of processors in an inactive state, , nIRQ_Im among the first to the m-th interrupt request signals (nIRQ_I1, ..., nIRQ_Im) without adjusting the interrupt request signals allocated to the first group among the nIRQ_I1, Only the interrupt request signals assigned to the second group can be adjusted at predetermined intervals. However, since this has been described above, a duplicate description thereof will be omitted. As described above, when the plurality of interrupt sources successively output a plurality of interrupts in a short time, the interrupt spread device 100 divides a time interval between a plurality of interrupt request signals generated based on the interrupts into a predetermined interval (Or a plurality of cores of a multicore processor) in an inactive state can be prevented from continuously changing (i. E., Abruptly waking up) to an active state within a short time have. As a result, generation of an inrush current due to sudden wake-up in a plurality of processors in the system on-chip is prevented, and the system on chip and the electronic apparatus including the system on-chip can secure high operation stability .

12 is a diagram showing a state machine of an interrupt holder provided in the interrupt spread device of FIG.

12, the state machine 200 of each of the first through m-th interrupt holders 120_1 through to 120_m receives first through mth interrupt request signals nIRQ_I1 through nIRQ_Im A wait state 240 indicating that the output enable signals AS1 through ASm are waiting for the interrupt arbiter 140 and a first wait state 240 indicating that the first through mth interrupt request signals (nIRQ_O1, ..., nIRQ_Om) are being output to the first to mth processors. At this time, the idle state 220 may correspond to a default state of each of the first through m-th interrupt holders 120_1, ..., and 120_m. Accordingly, the idle state 220 indicates an initial state in which an interrupt has not occurred, the wait state 240 indicates a state in which an inrush current due to another interrupt is waited for, and the assert state 260 indicates a state The interrupt request signal can be interpreted to mean a state in which the interrupt request signal is updated.

The first through m-th interrupt holders 120_1, ..., and 120_m each receive the idle state 220 (n) ). Each of the first through m-th interrupt holders 120_1 through 120_m receives the first through m-th interrupt request signals nIRQ_I1 through nIRQ_Im, State 260 can be entered. For example, when the first to m-th interrupt request signals nIRQ_I1, ..., nIRQ_Im are received, when the interrupt arbiter 140 directly transmits the output enable signals AS1, ..., ASm Each of the first through m-th interrupt holders 120_1, ..., and 120_m may directly enter the assert state 260 (RA). However, when the first to the m-th interrupt request signals nIRQ_I1, ..., nIRQ_Im are received, the interrupt arbiter 140 sets the time interval with the previous interrupt request signal to the output enable signal Each of the first through m-th interrupt holders 120_1, ..., and 120_m may enter the wait state 240 (RNA). Each of the first to mth interrupt holders 120_1 to 120_m receives the output permission signals AS1 to ASm from the interrupt arbitrator 140 while staying in the wait state 240 (AR) to the assert state 260. [0054] FIG. Each of the first through m-th interrupt holders 120_1 through 120_m holds the first through the m-th interrupt request signals nIRQ_O1 through nIRQ_Om while staying in the assert state 260, (AL) to the idle state 220 when the output of the idle state 220 is completed. Each of the first through m-th interrupt holders 120_1, ..., and 120_m is implemented as a state machine 200 having a simple structure, so that it can be manufactured at a small size and operate at low power.

13 is a diagram showing a state machine of an interrupt arbiter provided in the interrupt spread device of FIG.

13, the state machine 300 of the interrupt arbiter 140 outputs any one of the first to the m-th interrupt request signals nIRQ_O1, ..., nIRQ_Om to the first to mth processors (NIRQ_O1, ..., nIRQ_Om) are output to the first to m-th processors, and an idle state 340 indicating that at least one of the first to the n-th interrupt request signals . ≪ / RTI > At this time, the idle state 320 may correspond to the default state of the interrupt arbiter 140. [ Thus, the idle state 320 means a state in which no interrupt is present, and the wait state 340 means a state in which some interrupt occurs and is transmitted to the processor, thereby waiting for the inrush current to disappear Can be interpreted.

Specifically, when the first through m-th interrupt holders 120_1 through 120_m do not transmit the output request signals RS1 through RSm, the interrupt arbiter 140 outputs the output request signals RS1 through RSm to the idle state 320 Stay. When one of the first to mth interrupt holders 120_1 to 120_m transmits the output request signals RS1 to RSm, the interrupt arbiter 140 receives the output request signals RS1 to RSm, (REQ), and output enable signals AS1, ..., ASm to the corresponding interrupt holders. Thereafter, the interrupt arbiter 140 may enter the idle state 320 after entering the wait state 340 by a predetermined interval. At this time, any one of the first through m-th interrupt holders 120_1, ..., and 120_m transmits the output request signals RS1 through RSm to the interrupt arbiter 140, , The interrupt arbiter 140 can not output the output request signals RS1, ..., RSm even if the other one of the first through m-th interrupt holders 120_1 through 120m transmits the output request signals RS1 through RSm. And does not transmit the output enable signals AS1, ..., ASm to the corresponding interrupt holders. Accordingly, the first to m-th interrupt request signals nIRQ_O1, ..., nIRQ_Om may be output to the first to m-th processors with a predetermined interval or more. In this manner, the interrupt arbiter 140 is also implemented as the state machine 300 of a simple structure, so that it can be manufactured at a small size and operate at low power.

14 is a timing chart showing an example of the operation of the interrupt spread device of FIG.

14, when the i-th interrupt request signal nIRQ_Ii is input to the i-th interrupt holder 120_i in the interrupt spread device 100, the i-th interrupt holder 120_i outputs an output request signal (RSi, req). At this time, the interrupt arbiter 140 can output the output enable signal ASi, ack directly to the i-th interrupt holder 120_i because the interrupt arbiter 140 has been in the idle state since there is no previous interrupt request signal. As a result, the i-th interrupt holder 120_i enters the assert state ASSERT from the idle state IDLE, and the interrupt arbiter 140 enters the wait state WAIT from the idle state IDLE, The i-th interrupt request signal nIRQ_Oi may be output to the i-th processor.

On the other hand, when the i-th interrupt request signal nIRQ_Ij is input to the j-th interrupt holder 120_j while the i-th interrupt holder 120_i is staying in the assert state ASSERT, the j-th interrupt holder 120_ And outputs the output request signal RSj, req to the arbiter 140. [ At this time, since the interrupt arbiter 140 remains in the wait state (WAIT), the output enable signal ASj, ack is not output to the jth interrupt holder 120_j. The time during which the interrupt arbiter 140 stays in the wait state WAIT is predetermined (for example, determined by a physical characteristic value), and the time can be adjusted using a circuit such as a counter or the like. Thus, the jth interrupt holder 120_j can enter the wait state (WAIT) instead of the assert state ASSERT in the idle state IDLE. Thereafter, the interrupt arbiter 140 enters the idle state (IDLE) in the wait state (WAIT) at the time when the i-th interrupt request signal nIRQ_Oi and the j-th interrupt request signal nIRQ_Oj have a predetermined interval, j output enable signal ASj, ack to the j interrupt holder 120_j. Therefore, the j-th interrupt holder 120_j can enter the assert state ASSERT in the wait state WAIT based on the output enable signal ASj, ack, and the j-th interrupt request signal nIRQ_Oj lt; / RTI > processor. As a result, the i-th interrupt request signal nIRQ_Oi and the j-th interrupt request signal nIRQ_Oj may be output to the i-th processor and the j-th processor, respectively, at predetermined intervals by the interrupt spread device 100. As described above, even if the interrupt spread device 100 generates a plurality of interrupts at a plurality of interrupt sources within a short time, each interrupt time interval between a plurality of interrupt request signals generated based on the interrupts is maintained at a predetermined interval (Or a plurality of cores of a multicore processor) in an inactive state can be prevented from continuously changing (i. E., Abruptly waking up) to an active state within a short time have.

15 is a block diagram illustrating a system on-chip according to one embodiment of the present invention.

15, the system on-chip 500 includes first to n-th interrupt sources 520_1, ..., and 520_n, an interrupt controller 540, an interrupt spread device 560, Processors 580_1, ..., 580_m. Generally, since the number of interrupt sources 520_1, ..., 520_n is greater than the number of processors 580_1, ..., 580_m in the system on-chip 500, But is not limited thereto. Each of the first through m-th processors 580_1, ..., 580_m may correspond to independent processors, while the first through m-th processors 580_1, ..., And may correspond to a plurality of cores of a multicore processor (e.g., a dual core processor, a quad core processor, etc.).

The first to nth interrupt sources 520_1, ..., and 520_n may generate first to nth interrupts INT_R1, ..., INT_Rn, respectively. The first through n-th interrupt sources 520_1, ..., and 520_n are IPs that perform predetermined operations in a multiprocessor system (or a multicore system) For example, a video module, a sound module, a display module, a memory module, a communication module, a camera module, and the like. When the first to nth interrupt sources 520_1 to 520_n respectively generate the first to the nth interrupts INT_R1 to INT_Rn, the first to nth interrupts INT_R1,. The first through the m-th interrupt request signals nIRQ_I1 through nIRQ_Im are generated based on the first to mth interrupt request signals nIRQ_O1, ..., nIRQ_Om, May be input to the first to mth processors 580_1, ..., and 580_m at a predetermined interval or more. As a result, each of the first through m-th processors 580_1 through 580_m outputs the first through the n-th sources in response to the first through the m-th interrupt request signals nIRQ_O1 through nIRQ_Om, Can be performed.

The interrupt controller 540 generates first to m-th interrupts INT_R1 to INT_Rn based on the first to the n-th interrupts INT_R1 to INT_Rn generated in the first to nth interrupt sources 520_1 to 520_n. Interrupt request signals nIRQ_I1, ..., nIRQ_Im. In one embodiment, the interrupt controller 540 receives first through n-th interrupts INT_R1, ..., INT_Rn from the first through n-th interrupt sources 520_1 through 520_n, The first to mth processors 580_1, ..., and 580_m in which the first to nth interrupts INT_R1, ..., INT_Rn are respectively performed can be determined. That is, the interrupt controller 540 may allocate the first to the nth interrupts INT_R1, ..., INT_Rn to the first to m processors 580_1, ..., 580_m. In general, the number of first to mth processors 580_1, ..., 580_m in the system on-chip 500 is larger than the number of first to nth interrupt sources 520_1, ..., 520_n The interrupt controller 540 outputs the first to the n-th interrupts INT_R1 to INT_Rn to the first to the m processors 580_1 to 580_m in a temporal and / or spatial manner Can be properly allocated.

The interrupt spread device 560 outputs a time interval between adjacent interrupt request signals among the first to mth interrupt request signals nIRQ_I1, ..., nIRQ_Im inputted from the interrupt controller 540 at a predetermined interval or more Can be adjusted. When the first to the m-th processors 580_1 to 580_m are changed from the inactive state to the active state, the first to the m-th processors 580_1, 580_m) in which no inrush current is generated. In one embodiment, the interrupt spread device 560 receives the first to the m-th interrupt request signals nIRQ_I1, ..., nIRQ_Im and outputs the first to the mth interrupt request signals nIRQ_O1, first to mth interrupt holders for outputting first to mth interrupt request signals nIRQ_Om to the first to mth processors 580_1 to 580_m with a predetermined interval or more, , ..., nIRQ_Im) of the interrupt request signal is smaller than a preset interval, the interrupt arbiter may adjust the time interval to a predetermined interval. That is, the first to mth interrupt request signals (nIRQ_I1, ..., nIRQ_Im) are respectively received by the first to mth interrupt holders, and the first to mth interrupt holders are connected to the first to mth processors 580_1, ..., and 580_m, respectively. In one embodiment, the interrupt holders and the interrupt arbiter operate on one clock domain, and a request / acknowledge handshaking operation may be performed between the interrupt holders and the interrupt arbiter .

In detail, the interrupt spread device 560 controls each of the first to the m-th interrupt request signals (nIRQ_I1, ..., nIRQ_Im) k is an integer equal to or greater than 1) k-th interrupt request signal is greater than 0, the k-th interrupt request signal is transmitted until the k-th time interval becomes a predetermined interval Output can be delayed. In addition, the interrupt spreading device 560 may interrupt the k-th interrupt request signal according to the predetermined priority when the k-th time interval between the k-th interrupt request signal and the (k + 1) -th interrupt request signal is 0 And may delay one of the request signal and the (k + 1) -th interrupt request signal by a predetermined interval. Further, the interrupt spread device 560 outputs first to m-th interrupt request signals nIRQ_O1 (nIRQ_O1, ..., nIRQ_Im) different from the input order of the first to mth interrupt request signals , ..., nIRQ_Om). For example, even when the interrupt spread device 560 sequentially receives the k-th interrupt request signal, the (k + 1) -th interrupt request signal and the (k + 2) -th interrupt request signal, The interrupt request signal and the (k + 2) -th interrupt request signal on the basis of the predetermined priority.

In accordance with an embodiment, the interrupt spreading unit 560 includes first to mth processors 580_1, ..., and 580_m, a first group of processors in an active state and a second group of processors in an inactive state, And interrupt request signals assigned to the first group of processors in the active state among the first to m-th interrupt request signals nIRQ_I1, ..., nIRQ_Im are not adjusted at predetermined intervals , And the first to mth interrupt request signals (nIRQ_I1, ..., nIRQ_Im), which are active in the active state, of the interrupt request signals. As described above, the system on-chip 500 includes the interrupt spread device 560, so that the first through n-th interrupts INT_R1 (520_n) output from the first through n-th interrupt sources , NIRQ_Im) of the first to the m-th interrupt request signals (nIRQ_I1, ..., nIRQ_Im) generated based on the first to the m- It is possible to prevent the processors 580_1, ..., 580_m from continuously changing to the active state within a short time (i.e., sudden wake-up). As a result, the system on-chip 500 can prevent generation of an inrush current due to a sudden wake-up in a plurality of processors (or a plurality of cores of a multicore processor) .

16 is a diagram showing an example in which the interrupt spread device operates in the system on-chip of FIG.

16, the first through m-th interrupt holders 562_1, ..., and 562_m in the interrupt spread device 560 in the system on-chip 500 are connected to an interrupt arbiter (not shown) The first through the m-th interrupt request signals nIRQ_I1 through nIRQ_Im input to the first through the m-th interrupt holders 562_1 through to the mth interrupt holders 562_1 through to the mth interrupt holders 562_m, M processors 580_1, ..., and 580_m, respectively. However, for convenience of explanation, it is assumed that m is 4 in Fig.

When the first to n-th interrupt sources 520_1 to 520_n output the first to the nth interrupts INT_R1 to INT_Rn, the interrupt controller 540 controls the first to n- It is possible to generate the first to fourth interrupt request signals nIRQ_I1, ..., nIRQ_I4 based on the n-th interrupts INT_R1, ..., INT_Rn. 16, the first to fourth interrupt request signals nIRQ_I1, ..., nIRQ_I4 include a first interrupt request signal nIRQ_I1, a third interrupt request signal nIRQ_I3, (nIRQ_I2), and the fourth interrupt request signal (nIRQ_I4). At this time, the first interrupt holder 562_1 can output the first interrupt request signal nIRQ_O1 directly to the first processor 580_1 since there is no interrupt request signal prior to the first interrupt request signal nIRQ_I1. Since the time interval between the first interrupt request signal nIRQ_I1 and the third interrupt request signal nIRQ_I3 is smaller than the predetermined interval PS, the third interrupt request signal nIRQ_I3 is generated in the third interrupt holder 562_3. And outputs the third interrupt request signal nIRQ_O3 to the third processor 580_3 after delaying the first interrupt request signal nIRQ_O3 by the predetermined time DL1. Since the time interval between the third interrupt request signal nIRQ_I3 and the second interrupt request signal nIRQ_I2 is smaller than the predetermined interval PS, the second interrupt holder 562_2 outputs the second interrupt request signal nIRQ_I2, And outputs the second interrupt request signal nIRQ_O2 to the second processor 580_2 after delaying the first interrupt request signal nIRQ_O2 by a predetermined time DL2. Since the time interval between the second interrupt request signal nIRQ_I2 and the fourth interrupt request signal nIRQ_I4 is smaller than the predetermined interval PS, the fourth interrupt holder 562_4 outputs the fourth interrupt request signal nIRQ_I4, And outputs the fourth interrupt request signal nIRQ_O4 to the fourth processor 580_4 after delaying the fourth interrupt request signal nIRQ_O4 by a predetermined time DL3. As a result, the first to fourth processors 580_1, ..., 580_4 can receive the first to fourth interrupt request signals nIRQ_O1, ..., nIRQ_O4 with a predetermined interval PS , It is possible to prevent an inrush current due to sudden wake-up from occurring in the first to fourth processors 580_1, ..., 580_4.

17 is a diagram showing another example of the operation of the interrupt spread device in the system on-chip of FIG.

17, the first through m-th interrupt holders 562_1, ..., and 562_m in the interrupt spread device 560 in the system on-chip 500 are connected to an interrupt arbiter (not shown) The first through the m-th interrupt request signals nIRQ_I1 through nIRQ_Im input to the first through the m-th interrupt holders 562_1 through to the mth interrupt holders 562_1 through to the mth interrupt holders 562_m, M processors 580_1, ..., and 580_m, respectively. However, for convenience of explanation, it is assumed that m is 4 in Fig.

When the first to n-th interrupt sources 520_1 to 520_n output the first to the nth interrupts INT_R1 to INT_Rn, the interrupt controller 540 controls the first to n- It is possible to generate the first to fourth interrupt request signals nIRQ_I1, ..., nIRQ_I4 based on the n-th interrupts INT_R1, ..., INT_Rn. 17, the first to fourth interrupt request signals nIRQ_I1, ..., nIRQ_I4 include a first interrupt request signal nIRQ_I1, a second interrupt request signal nIRQ_I2, (nIRQ_I4), and the third interrupt request signal (nIRQ_I3). At this time, the first interrupt holder 562_1 can output the first interrupt request signal nIRQ_O1 directly to the first processor 580_1 since there is no interrupt request signal prior to the first interrupt request signal nIRQ_I1. Since the time interval between the first interrupt request signal nIRQ_I1 and the second interrupt request signal nIRQ_I2 is greater than the predetermined interval PS, the second interrupt holder 562_2 receives the second interrupt request signal nIRQ_O2, To the second processor 580_2. Since the time interval between the second interrupt request signal nIRQ_I2 and the fourth interrupt request signal nIRQ_I4 is smaller than the predetermined interval PS, the fourth interrupt holder 562_4 outputs the fourth interrupt request signal nIRQ_I4, And outputs the fourth interrupt request signal nIRQ_O4 to the fourth processor 580_4 after delaying the first interrupt request signal nIRQ_O4 by a predetermined time DL1. Since the time interval between the fourth interrupt request signal nIRQ_I4 and the third interrupt request signal nIRQ_I4 is smaller than the predetermined interval PS, the third interrupt holder 562_3 outputs the third interrupt request signal nIRQ_I3, And outputs the third interrupt request signal nIRQ_O3 to the third processor 580_3 after delaying the first interrupt request signal nIRQ_O3 by a predetermined time DL2. As a result, since the first to fourth processors 580_1, ..., 580_4 can receive the first to fourth interrupt request signals nIRQ_O1, ..., nIRQ_Om with a predetermined interval or more, It is possible to prevent an inrush current due to sudden wake-up from occurring in the first to fourth processors 580_1, ..., and 580_4.

FIG. 18 is a diagram showing another example in which the interrupt spread device operates in the system on-chip of FIG.

18, the first through m-th interrupt holders 562_1, ..., and 562_m in the interrupt spread device 560 in the system on-chip 500 are connected to an interrupt arbiter (not shown) The first through the m-th interrupt request signals nIRQ_I1 through nIRQ_Im input to the first through the m-th interrupt holders 562_1 through to the mth interrupt holders 562_1 through to the mth interrupt holders 562_m, M processors 580_1, ..., and 580_m, respectively. However, for convenience of explanation, it is assumed that m is 4 in Fig.

When the first to n-th interrupt sources 520_1 to 520_n output the first to the nth interrupts INT_R1 to INT_Rn, the interrupt controller 540 controls the first to n- It is possible to generate the first to fourth interrupt request signals nIRQ_I1, ..., nIRQ_I4 based on the n-th interrupts INT_R1, ..., INT_Rn. 18, after the first interrupt request signal nIRQ_I1 and the second interrupt request signal nIRQ_I2 are inputted simultaneously, the first to fourth interrupt request signals nIRQ_I1, ..., nIRQ_I4, The fourth interrupt request signal nIRQ_I4 and the third interrupt request signal nIRQ_I3 may be sequentially input. At this time, since the first interrupt request signal nIRQ_I1 and the second interrupt request signal nIRQ_I2 are input simultaneously, the first interrupt holder 562_1 receives the first interrupt request signal nIRQ_O2 having a higher priority than the second interrupt request signal nIRQ_O2 And can output the request signal nIRQ_O1 directly to the first processor 580_1. On the other hand, the second interrupt holder 562_2 delays the second interrupt request signal nIRQ_I2 having a lower priority than the first interrupt request signal nIRQ_I1 by a predetermined interval, nIRQ_O2) to the second processor 580_2. The fourth interrupt request signal nIRQ_I4 and the third interrupt request signal nIRQ_I3 are sequentially inputted based on the predetermined priority although the fourth interrupt request signal nIRQ_I4 and the third interrupt request signal nIRQ_I3 are sequentially input. Can be output in a non-sequential manner. For example, the third interrupt request signal nIRQ_03 having a higher priority may be output before the fourth interrupt request signal nIRQ_04 having a lower priority. That is, since the third interrupt holder 562_3 has the third interrupt request signal nIRQ_I3 because the time interval between the second interrupt request signal nIRQ_I2 and the third interrupt request signal nIRQ_I3 is less than the predetermined interval PS, And outputs the third interrupt request signal nIRQ_O3 to the third processor 580_3 after delaying the first interrupt request signal nIRQ_O3 by a predetermined time DL2. The fourth interrupt holder 562_4 may delay the fourth interrupt request signal nIRQ_I4 by a predetermined time DL3 and then output the fourth interrupt request signal nIRQ_O4 to the fourth processor 580_4 . As a result, the first to fourth processors 580_1, ..., 580_4 can receive the first to fourth interrupt request signals nIRQ_O1, ..., nIRQ_Om at predetermined intervals, It is possible to prevent an inrush current caused by sudden wake-up from occurring in the first to fourth processors 580_1, ..., 580_4.

FIG. 19 is a flowchart showing an example of a method for verifying whether any system on-chip is equipped with an interrupt spread device, and FIG. 20 is a flowchart for verifying whether or not any system on- Fig. 2 is a view for explaining an example of a method for performing the above method.

19 and 20, the verification method of FIG. 19 includes sequentially applying a plurality of interrupt request signals IAT corresponding to a plurality of interrupts to a plurality of processors at a first time interval ATP Step S510), the processors detect a second time interval (ETP) to be woken up (step S520), and it is determined whether the first time interval ATP has become 0 (step S530) . In this case, if the first time interval ATP does not become zero, the verification method of FIG. 19 may reduce the first time interval ATP (Step S540) and then perform the steps (Step S510, Step S520, and Step S530) may be repeated. On the other hand, when the first time interval ATP is 0, the verification method of FIG. 19 may determine whether the second time interval ETP has converged to a predetermined value (Step S550). As a result, when the second time interval ETP converges to a predetermined value, the verification method of FIG. 19 determines that the interrupt spread device and method according to the embodiments of the present invention are applied to an arbitrary system on-chip (Step S560), and if the second time interval ETP does not converge to a constant value and continuously decreases, the verification method of FIG. 19 may be applied to any system on-chip in embodiments of the present invention It is determined that the interrupt spreading apparatus and method are not applied (step S570). That is, the convergence of the second time interval ETP to a constant value means that even if the first time interval ATP between the plurality of interrupt request signals IAT becomes smaller than a predetermined value, (IAT) is being input to a plurality of processors with a second time interval (ETP) (i.e., a predetermined interval), so that any system on-chip can be provided with an interrupt spread It can be judged that the apparatus and method are applied. However, the verification method of FIG. 19 can be implemented in various ways according to the required conditions, as an example.

Fig. 21 is a flowchart showing another example of a method for verifying whether or not any system on-chip has an interrupt spread device.

Referring to FIG. 21, the verification method of FIG. 21 sequentially applies a plurality of interrupt request signals corresponding to a plurality of interrupts to a plurality of processors at a first time interval (step S610) (step S620), and it may be determined whether the first time interval is 0 (step S630). If the first time interval does not become 0, the verification method of FIG. 21 may reduce the first time interval (Step S640), and then perform the steps (Step S610, Step S620, Step S630) It can be repeated. On the other hand, if the first time interval is 0, the verification method of FIG. 21 can determine whether the voltage drop of the supply voltage has converged to a predetermined value (Step S650). As a result, when the voltage drop of the supply voltage converges to a predetermined value, the verification method of FIG. 21 determines that the interrupt spread device and method according to the embodiments of the present invention are applied to an arbitrary system on-chip S660). If the voltage drop of the supply voltage does not converge to a constant value but continuously increases, the method of verifying in FIG. 21 may be applied to any system on-chip, such as an interrupt spread device It is judged that the method is not applied (Step S670). That is, the convergence of the voltage drop of the supply voltage to a constant value means that even if the first time interval between the plurality of interrupt request signals becomes smaller than a predetermined value, a plurality of interrupt request signals Processors, it can be determined that an arbitrary system on-chip is applied to the interrupt spreading apparatus and method according to the embodiments of the present invention. The verification method of FIG. 21 is performed together with the verification method of FIG. 19, thereby making it possible to make a more accurate determination as to whether or not the interrupt spread apparatus and method according to the embodiments of the present invention are applicable.

FIG. 22 is a block diagram illustrating a multicore system according to an embodiment of the present invention, and FIG. 23 is a diagram illustrating an example in which the multicore system of FIG. 21 is implemented as a smartphone.

22 and 23, the multicore system 600 includes first to nth interrupt sources 610_1, ..., 610_n, an interrupt controller 620, an interrupt spread device 630, (RAM) device 650, a ROM (Read Only Memory) device 660, a storage device 670, a system bus 680, and the like can do. In this case, the multi-core processor 640 may include the first through m-th cores P1, ..., Pm. If m is 2, a dual core processor, m is 4, . ≪ / RTI > At this time, the multicore system 600 may correspond to the smartphone 700, but is not limited thereto. For example, the multi-core system 600 may be implemented with electronic devices such as smart pads, mobile devices such as mobile phones, and smart televisions. Further, the multicore system 600 should be interpreted not only as a system having a multicore processor with a plurality of cores, but also as a multiprocessor system having a plurality of processors with a single core.

The first to nth interrupt sources 610_1 to 610_n may generate first to nth interrupts INT_R1 to INT_Rn, respectively. In this case, the first to nth interrupt sources 610_1, ..., and 610_n are IPs 610_1, ..., and 610_n that perform a predetermined operation in the multicore system 600, For example, a video module, a sound module, a display module, a memory module, a communication module, a camera module, and the like. The interrupt controller 620 generates first to m-th interrupts INT_R1 to INT_Rn based on the first to n-th interrupts INT_R1 to INT_Rn output from the first to nth interrupt sources 610_1 to 610_n, Interrupt request signals nIRQ_I1, ..., nIRQ_Im. The interrupt spreading unit 630 is configured to interrupt a time interval between adjacent interrupt request signals among the first to mth interrupt request signals nIRQ_I1, ..., nIRQ_Im input from the interrupt controller 620 by at least a predetermined interval . The first to mth interrupt request signals nIRQ_O1 to nIRQ_Om are input to the first to mth cores P1 to Pm in the multicore processor 640, Respectively. To this end, the interrupt spread device 630 may include first to m-th interrupt holders and an interrupt arbiter for controlling the first to m-th interrupt holders. However, since this has been described above, a duplicate description thereof will be omitted.

Meanwhile, the multicore processor 640 may be connected to the system bus 680 via the bus interface 645 to transmit and receive data to and from other components. That is, the multi-core processor 640 is connected to the plurality of IP addresses 610_1, ..., 610_n (610_1, ..., 610_n) via a system bus 680 such as an address bus, a control bus, and a data bus ), The RAM device 650, the ROM device 660, the storage device 670, and the like. At this time, the storage device 670 may be a hard disk drive (HDD), a solid state drive (SSD), a RAID (Redundant Array of Independent Disk), or the like. In accordance with an embodiment, the multicore processor 640 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus. Meanwhile, although not shown in FIG. 21, the multicore system 600 may further include a non-volatile memory device and / or a volatile memory device. In this case, the nonvolatile memory device may be an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM) A volatile memory device may be implemented as a dynamic random access memory (DRAM), a nonvolatile memory device such as a dynamic random access memory (DRAM), a nonvolatile random access memory (NAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory Memory, an SRAM (Static Random Access Memory), a mobile DRAM, or the like.

As such, the multicore system 600 may have a system bus path for transmitting / receiving data and an interrupt path for processing interrupts, and the multicore processor 640 may have a system bus path 610_n through a bus path and an interrupt path to perform a predetermined operation and to cause the plurality of IPs 610_1, ..., 610_n to perform predetermined operations Interrupt processing can be performed. Meanwhile, the multicore system 600 may be implemented using various types of packages. For example, the package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC), plastic dual in-line packages (PDIP) (SMIC) chip, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat pack (MQFP), a thin quad flat pack (TQFP), a small outline integrated circuit (SOIC) Outline Package), Thin Small Outline Package (TSOP), Thin Quad Flat-Pack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) Stack Package) and the like can be used.

The present invention can be applied to a multiprocessor system having a plurality of processors (or multicore processors). For example, the present invention can be applied to a computer having a plurality of processors (or a multicore processor), a notebook computer, a mobile phone, a smart phone, a smart pad, a security system, and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims. It can be understood that it is possible.

100: Interrupt spread device 120: Interrupt holder
140: Interruption arbiter 500: System on-chip
520: Interrupt source 540: Interrupt controller
560: Interrupt spread device 580: Processor

Claims (26)

The interrupt spread device receiving a plurality of interrupt request signals;
The interrupt spread device determining whether each time interval between the interrupt request signals is less than a predetermined interval;
Adjusting the time interval to a predetermined interval if the time interval is shorter than the predetermined interval; And
And the interrupt spread device outputs the interrupt request signals to the plurality of processors, respectively,
Wherein the interrupt request signals are generated based on a plurality of interrupts output from a plurality of interrupt sources, the interrupt request signals are respectively assigned to the processors,
Wherein the predetermined interval is determined within a range in which an inrush current is not generated in the processors when the processors are changed from an inactive state to an active state. delete delete 2. The method of claim 1, wherein adjusting
When the kth time interval between the k-th adjacent interrupt request signal (where k is an integer equal to or greater than 1) and the (k + 1) -th interrupt request signal is greater than 0, until the kth time interval becomes the predetermined interval And delaying the output of the (k + 1) -th interrupt request signal. 5. The method of claim 4, wherein adjusting
Further comprising changing an output order of the interrupt request signals according to a predetermined priority. 6. The method of claim 5, wherein adjusting
And delaying one of the k-th interrupt request signal and the (k + 1) -th interrupt request signal by the predetermined interval according to the predetermined priority when the k-th time interval is 0 The interrupt spread method. The interrupt spread device receiving a plurality of interrupt request signals;
Classifying the plurality of processors to which the interrupt request signals are to be output respectively into processors that are in an active state and processors that are in an inactive state;
Outputting non-target interrupt request signals to be output to the active processors among the interrupt request signals to the processors in the active state, respectively;
Determining whether a time interval between target interrupt request signals to be output to the inactive processors among the interrupt request signals is less than a predetermined interval;
Adjusting the time interval to a predetermined interval if the time interval is shorter than the predetermined interval; And
And the interrupt spread device outputs the target interrupt request signals to the inactive processors, respectively,
The step of adjusting at the predetermined interval
If the kth time interval between adjacent kth (k is an integer greater than or equal to 1) target interrupt request signal and the (k + 1) th target interrupt request signal is greater than 0, the kth time interval may be the predetermined interval And delaying the output of the (k + 1) th interrupt request signal until the (k + 1) th interrupt request signal. delete 8. The method of claim 7, wherein adjusting
Further comprising changing an output order of the target interrupt request signals according to a predetermined priority. 10. The method of claim 9, wherein adjusting
And delaying one output of the k-th target interrupt request signal and the (k + 1) -th target interrupt request signal by the predetermined interval according to the predetermined priority when the k-th time interval is 0 And the interrupt spread method. (M is an integer equal to or greater than 2) interrupt request signals, and outputting the first to the m-th interrupt request signals to the first to the m-th processors, respectively, 1 to m < th > interrupt holders; And
And an interrupt arbiter for adjusting the time interval to a predetermined interval when a time interval between adjacent interrupt request signals among the first to mth interrupt request signals is smaller than the predetermined interval,
The first through the m-th interrupt request signals are generated based on a plurality of interrupts output from the plurality of interrupt sources, and the first through m-th interrupt request signals are respectively received And,
Wherein the first to mth interrupt holders are connected to the first to the m processors, respectively, and the first to the m-th interrupt request signals are provided to the first to the m processors, respectively, And outputs,
Wherein the predetermined interval is determined within a range in which an inrush current is not generated in the first to mth processors when the first to mth processors are changed from an inactive state to an active state, Interrupt spread device. delete delete delete The method of claim 11, wherein the first to m-th interrupt holders transmit the output request signal to the interrupt arbiter upon receiving the first to the m-th interrupt request signals, respectively, and receive an output enable signal from the interrupt arbitrator And outputs the first to the m-th interrupt request signals to the first to m-th processors, respectively. 16. The method of claim 15, wherein each of the first through m-th interrupt holders is in an idle state indicating that the first through the m-th interrupt request signals are not received, waiting for the output enable signal from the interrupt arbiter And an assert state indicating that the first to the m-th interrupt request signals are being output to the first to m-th processors, respectively, and a state machine And the interrupt spread device is implemented. The method of claim 15, wherein the interrupt arbiter sequentially outputs the output enable signal to the first through m-th interrupt holders when receiving the output request signal from the first through m-th interrupt holders, And the first to mth interrupt request signals are output to the first to the m processors at least over the predetermined interval. The method of claim 17, wherein the interrupt arbiter comprises: an idle state indicating that any one of the first through m-th interrupt request signals is not output to the first through m-th processors; And a wait state indicating that at least one of the signals is being output to the first through m-th processors. 12. The interrupt spread device of claim 11, wherein the interrupt arbiter changes the output order of the first through m-th interrupt request signals according to a predetermined priority. The apparatus of claim 11, wherein the interrupt arbiter classifies the first through m-th processors into a first group of processors in an active state and a second group of processors in an inactive state, The interrupt request signals allocated to the first group among the interrupt request signals are not adjusted at the predetermined intervals and the interrupt request signals allocated to the second group among the first to the m- Wherein the interrupt spread controller adjusts the interrupt interval by the predetermined interval. delete delete delete delete delete delete

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