JPH11149459A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a device compact and light in weight and to reduce power consumption while improving mount efficiency and preventing the power source of quick responsiveness from being used more than needed. SOLUTION: A control processor 10 is provided with a reset circuit 12 for asserting or de-asserting reset signals to data processors 20-1 to 20-4 and a reset interval monitoring circuit 11 for performing control so as to assert or de-assert the reset signals through the reset circuit 12 at fixed time intervals, and respective data processors 20-1 to 20-4 are provided with sleep mode control circuits 23-1 to 23-4 for controlling a change to or recovery from a power saving mode, sleep interva; monitoring circuits 22-1 to 22-4 for performing the change to or recovery from the power saving mode at every fixed time interval, and initializing circuits 21-1 to 21-4 for initializing the sleep interval monitoring circuits 22-1 to 22-4 based on the reset signals from the control processor 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multiprocessor system, and more particularly, to a reset control method in a multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, the operating frequency has been increased in order to realize higher performance of a processor, and accordingly, the power consumption of the processor has been increased.

[0003] In recent years, multiprocessor technology that generally improves processing performance by performing processing using a plurality of processors instead of performing processing using a single multiprocessor is generally used. As a result, the overall power consumption of the system has been further increased.

[0004] On the other hand, a processor is built in a portable device driven by a battery, as represented by a notebook personal computer or the like, and a processor with lower power consumption has been demanded. Also, from the viewpoint of environmental protection, the demand for low power consumption is increasing worldwide.

In order to satisfy the conflicting demands, recent processors have been provided with a sleep mode function which operates in a power saving mode when the operation of the processor is not required.

One of the problems in a multiprocessor system is that when resetting is performed simultaneously in all processors, the difference between the power consumption in the reset state and the power consumption in the reset release state is large, and the current of the difference is compensated for.
A large amount of current had to be supplied instantaneously.

Also, at the time of transition or return to the sleep mode as described above, similarly, it is necessary to instantaneously supplement the current by the difference in power consumption, so that a plurality of processors simultaneously operate as in a multiprocessor system. When a transition or return to the sleep mode is performed, a large amount of current is instantaneously supplied in proportion to the number of the processors.

In order to respond to such a rapid current change, it is necessary to use a power supply circuit having good responsiveness, but it is expensive and the power supply circuit is usually separated from the processor in terms of mounting. There is a limit to the improvement of responsiveness because it is often mounted in a place where it is not.

Therefore, usually, in order to supplement the response of the power supply,
By mounting a capacitor with good responsiveness near the processor, a difference in current change is supplied, and this is called a decoupling capacitor.

However, even in this decoupling capacitor, the package of the processor is BGA (Ball Grind).
d Arry), the mounting area has become smaller, and it has become difficult to mount a large amount of decoupling capacitors close to the processor.

JP-A-63-47812, JP-A-63-47812
Even in Japanese Patent Publication No. 2-78617 and Japanese Patent Publication No. 3-26843, there is no description about the problem in the multiprocessor and its solution even though the importance of the sleep mode and the power control are mentioned.

[0012]

In the conventional multiprocessor system as described above, the difference between the power consumption in the reset state and the power consumption in the reset release state and the difference between the power consumption in the sleep mode and the power consumption in the normal mode compensate for the difference in current. It is necessary to increase the number of decoupling capacitors in proportion to the number of processors in a multiprocessor. And a decoupling capacitor is required, which is a major problem in mounting.

[0013] Further, if the shift and release of the processors to the sleep mode are simultaneously performed in a large number of processors, a power supply and a large-capacity decoupling capacitor having a fast response are similarly required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and requires the decoupling capacitor by efficiently performing reset control and sleep mode control of a plurality of processors. It is possible to reduce the size to a minimum, thereby improving the mounting efficiency, avoiding the use of a power supply having a higher responsiveness than necessary, and reducing the size, weight, and power consumption of the device. An object is to provide a multiprocessor system.

[0015]

In order to achieve the above object, the present invention provides a multiprocessor comprising a plurality of data processors for performing specific data processing and a control processor for controlling the plurality of data processors. In the processor system, the control processor controls the control processor to assert or deassert reset signals for the plurality of data processors, and to perform the assertion or deassertion of the reset signal by the reset circuit at regular time intervals. Providing a reset interval monitoring circuit, and for each of the plurality of data processors,
A sleep mode control circuit that controls the transition or return to the power saving mode, a sleep interval monitoring circuit for performing the transition or return to the power saving mode at regular time intervals, and a reset signal from the control processor. An initialization circuit for initializing the sleep interval monitoring circuit is provided, and a reset signal of each data processor is asserted or deasserted at a fixed time interval, whereby a plurality of processors are simultaneously shifted to or released from a reset state. And by resetting the sleep interval monitoring circuit, which is a reference for entering and returning to the sleep mode, by the reset signal, a plurality of data processors are prevented from entering or returning to the sleep mode at the same time. To prevent simultaneous large current changes, It is that to realize a number of multiprocessor systems equipped only decoupling capacitors limited.

As a result, it is not necessary to use a power supply circuit having a higher response speed than necessary, and it is possible to suppress the mounting of a minimum decoupling capacitor. Low power consumption can be achieved.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a multiprocessor system according to the present invention.

In this embodiment, the number of data processors will be described as four, but the present invention is not limited to this.

Further, in the system of the present embodiment, the transition to and the return to the reset and the transition to and the return to the sleep mode are performed by only one processor within 128 microseconds based on the characteristics of the power supply circuit and the capacity of the decoupling capacitor. Suppose you can't. In each data processor, the transition to and return from the sleep mode is monitored every 1 millisecond, and the transition to the sleep mode is performed only when there is no data to be processed by the own processor.
Returning from the sleep mode to the normal mode is performed only when data for the own processor is generated.

In this embodiment, as shown in FIG. 1, four data processors 20-1 to 20-4 for performing specific data processing are provided.
And a control processor 1 connected to the data processors 20-1 to 20-4 via reset signal lines 30-1 to 30-4 and controlling the data processors 20-1 to 20-4. The control processor 1 asserts or deasserts a reset signal for each of the data processors 20-1 to 20-4, and asserts or deasserts the reset signal by the reset circuit 12 at regular time intervals. And a reset interval monitoring circuit 11 for controlling the
Also, the data processors 20-1 to 20-4 have sleep mode control circuits 23-1 to 23-3 that control transition to or return to a power saving mode (hereinafter, referred to as a sleep mode).
23-4, and a sleep interval monitoring circuit 22-1 for performing transition or return to the sleep mode at regular time intervals.
22-4 and initialization circuits 21-1 to 21-4 for initializing the sleep interval monitoring circuits 22-1 to 22-4 based on a reset signal from the control processor 10.

The operation when the power is turned on to the multiprocessor system configured as described above will be described below.

FIG. 2 is a timing chart for explaining the operation of the multiprocessor system shown in FIG.

When the power is turned on, first, the control processor 10 is activated, and all operating environments are prepared. During this time, all the data processors 20-1 to 20-
4 are asserted, that is, all the data processors 20-1 to 20-4 are asserted.
-4 is not activated and is kept in the reset state.

When all the environments are completed, the control processor 10 first deasserts only the reset signal line 30-1 for the data processor 20-1.

As a result, the data processor 20-1 is activated, and at the same time, the initialization of the sleep interval monitoring circuit 22-1 is performed by the initialization circuit 21-1.

In the present embodiment, the transition to the sleeve mode and the return to the sleeve mode are to be performed at intervals of 1 millisecond, so that a value of 1 millisecond is set to the sleep interval monitoring circuit 2.
2-1 is set.

Thereafter, in the data processor 20-1, the sleep interval monitoring circuit 22-1 determines whether or not there is data to be processed by its own processor every 1 millisecond. The mode control circuit 23-1 shifts to the sleep mode, and when data to be processed is generated, the sleep mode control circuit 23-1 returns from the sleep mode to the normal mode.

Next, in the control processor 10, the data processor 20-
128 microseconds after the reset signal for 1 is deasserted, the reset signal line 30-2 is deasserted, thereby resetting the data processor 20-2.

In the data processor 20-2 from which the reset has been released, the same control as that of the data processor 20-1 is performed.

What is important here is that the data processor 2
Since the reset release time is shifted by 128 microseconds between 0-1 and the data processor 20-2, as a result, both the operation in the sleep interval monitoring circuit 22-1 and the operation in the sleep interval monitoring circuit 22-2 are 128 microseconds.
This is a microsecond shift.

As a result, not only is the reset interval shifted by 128 seconds, but also the transition to and return from the sleep mode is shifted by 128 microseconds, so that the power supply circuit and the The restrictions imposed by the decoupling capacitor can be kept.

Similarly, for the data processors 20-3 and 20-4, the reset interval monitoring circuit 11
Since the reset is released at an interval of 8 microseconds, it is possible to prevent all the data processors from transitioning to the sleep mode within the same 128 microsecond interval.

[0034]

By controlling the reset signal of the multiprocessor by the control processor, the transition to and release from the reset state, and the transition to and from the sleep mode are efficiently performed, and can be supplemented by the capacity of the mounted decoupling capacitor. Since the configuration is such that the sleep mode transition and cancellation are not performed simultaneously by the above processors, a power supply circuit with a faster response than necessary becomes unnecessary, and the decoupling capacitor which required a large capacity is reduced to a minimum. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a multiprocessor system of the present invention.

FIG. 2 is a timing chart for explaining an operation of the multiprocessor system shown in FIG.

[Explanation of symbols]

 Reference Signs List 10 control processor 11 reset interval monitoring circuit 12 reset circuit 20-1 to 20-4 data processor 21-1 to 21-4 initialization circuit 22-1 to 22-4 sleep interval monitoring circuit 23-1 to 23-4 sleep mode Control circuit 30-1 to 30-4 Reset signal line

Claims (2)

[Claims] 1. A multiprocessor system comprising: a plurality of data processors for performing specific data processing; and a control processor for controlling the plurality of data processors, wherein the control processor is provided for the plurality of data processors. A multiprocessor system, comprising: a reset circuit for asserting or deasserting a reset signal; and a reset interval monitoring circuit for controlling the reset signal to be asserted or deasserted by the reset circuit at fixed time intervals. . 2. The multiprocessor system according to claim 1, wherein each of said plurality of data processors controls a transition or return to a power saving mode, and a transition or return to a power saving mode. A sleep interval monitoring circuit for performing the process at predetermined time intervals, and an initialization circuit for initializing the sleep interval monitoring circuit based on a reset signal from the control processor.